JPH04360582A - Semiconductor device - Google Patents

Abstract

PURPOSE:To easily control a threshold voltage and to reduce a resistance of a gate electrode by so laminating the electrode as to include a sub material layer having a low contact resistance and low contact resistance with a main material layer for constituting the gate electrode between the main material layers. CONSTITUTION:A gate electrode is formed of a three-layer structure having a first layer gate polycrystalline silicon 7/silicide film 6/second layer gate polycrystalline silicon 8, and a gate electrode material (main material layer) is used as the silicon 8 of a channel side. The film 6 of a sub material layer having lower resistance than those of the silicons 7, 8 of main material layers and low contact resistance with the main material layer, is inserted to the electrode. Accordingly, flatness and relationship between a channel and a work station can be maintained similarly to that of prior art, and a threshold voltage can be easily controlled. Further, a resistance of the electrode can be lowered.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to improvements in the structure of thin film field effect transistors used in SRAM memory cells.

0002

2. Description of the Related Art FIG. 2 shows a general thin film polycrystalline silicon transistor (Thin Film Transistor).
2 is a cross-sectional view of a type (lower gate type) in which the gate is formed under the channel layer (TFT). In the figure,
2 is a base insulating film made of a silicon oxide film, and 1 is a gate polycrystalline silicon serving as a gate electrode, which is formed on the base insulating film 2. 3 is a gate insulating film made of a silicon oxide film. 4 is a thin film polycrystalline silicon that forms the source/drain, 5 is a thin film polycrystalline silicon that becomes a channel,
It is formed with the gate insulating film 3 interposed therebetween, and serves as an active layer of the transistor.

[0003] In SRAMs, which are becoming increasingly highly integrated, pMOS is placed on nMOST in order to realize low standby current in a small area.
A memory cell (full CMOS type) in which thin film polycrystalline silicon transistors (pMOSTFT) are stacked is required.

[0004] Figure 2 shows a pMOSTFT suitable for that purpose.
The gate electrode layer of the pMOSTFT is made of polarized polycrystalline silicon 1, for example, N-type polycrystalline silicon.

[0005]

[Problems to be Solved by the Invention] Conventional semiconductor devices are constructed as described above, and polycrystalline silicon is used to control the threshold voltage, so there is a limit to how low the resistance of the gate electrode layer can be reduced. There was a problem. Furthermore, since the gate electrode layer has a polarity (for example, N-type), when this gate electrode is connected to a region of a different polarity (for example, P-type) of an element with another function, a ready-made PN junction will be formed. There was a problem.

The present invention was made to solve the above-mentioned problems, and it is easy to control the threshold voltage.
It is an object of the present invention to obtain a semiconductor device which has low resistance and does not require the formation of a ready-made PN junction.

[0007]

[Means for Solving the Problems] A semiconductor device according to the present invention includes a gate electrode having a sub-material layer having a low resistance and a low contact resistance with a main material layer constituting the gate electrode, between the main material layer. It is constructed by laminating layers so as to include. Further, the polarity of the main material layer is different between above and below the sub-material layer.

[0008]

[Operation] In the present invention, the gate electrode is constructed by laminating a main material layer having low resistance constituting the gate electrode and an auxiliary material layer having low contact resistance between the main material layers. Gate and channel work functions (
This makes it possible to reduce the resistance of the gate electrode while maintaining the same relationship (work function) as before. Furthermore, since the main material layer has different polarities above and below the sub-material layer, an ohmic-like connection is possible when connecting the gate electrode to a portion of another element having a different polarity.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a TFT according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same or equivalent parts, 6 is a silicide film (sub-material layer) using WSix, 7 is the first layer gate polycrystalline silicon film which is the main material layer, and 8 is the main material layer. The material layer is a second layer gate polycrystalline silicon film, and as shown in the figure, the gate electrode has a three-layer structure of first layer gate polycrystalline silicon 7/silicide film 6/second layer gate polycrystalline silicon 8. It becomes. The first layer gate polycrystalline silicon 7 is p-type, and the second layer gate polycrystalline silicon 8 is n-type, so that they have different polarities.

Next, an example of a method for manufacturing a TFT according to the present invention will be described. First, a first layer gate polycrystalline silicon 7 is deposited on the base insulating film 2 by the LPCVD method.
A p-type impurity is implanted into the layer gate polycrystalline silicon 7. Next, a silicide film (WSix) 6 is deposited by sputtering. Then, a second layer gate polycrystalline silicon 8 is deposited by the LPCVD method, and n-type impurities are implanted. Next, using a photoresist mask, the silicide film 6, first layer gate polycrystalline silicon 7, and second layer gate polycrystalline silicon 8 are etched, leaving a gate pattern. Next, a gate insulating film 3 is deposited by CVD at normal pressure. Then, thin film polycrystalline silicon 4 and 5 are deposited by the LPCVD method, and impurities are implanted into the thin film polycrystalline silicon 4 using a photoresist mask.
Form source/drain regions.

Since the operation of TFT is well known,
The explanation will be omitted here, and the operation and effect will be explained below. According to this embodiment, the gate electrode has a three-layer structure consisting of the first layer gate polycrystalline silicon 7/silicide film 6/second layer gate polycrystalline silicon 8, and the second layer gate electrode on the channel side
Since the same gate electrode material (main material layer) as the conventional one is used for the layer gate electrode polycrystalline silicon 8, the flatness and the work function relationship with the channel can be maintained as before, and the threshold voltage can be maintained as well. Control can also be easily performed in the same manner as before. In addition, a silicide film 6, which is a sub-material layer having a lower resistance than the first and second-layer gate polycrystalline silicon 7 and 8, which are the main material layers, and which has a low contact resistance with the main material layer, is inserted into the gate electrode. Therefore, the resistance of the gate electrode can be lowered.

Furthermore, when the first layer gate polycrystalline silicon 7, which is a gate electrode, is connected to an element having another function, when the connecting portion of the other side is p-type, in this embodiment, the first layer gate polycrystalline silicon 7 is connected to an element having another function. Since 7 is p-type, an ohmic-like connection is possible, and an existing PN junction can be prevented. For example, when the source/drain of the thin film transistor on the other side is p-type, if the first layer polycrystalline silicon 7 of the gate electrode is made p-type, a diode junction (PN junction) will not be formed between the two, and a p- It is possible to perform a p-type direct connection.

In the above embodiment, WSix was used for the silicide film 6 as the sub-material layer, but the material used for the silicide film 6 was the first and second layer gate polycrystalline silicon 7.
, 8, which allows ohmic-like connection and which has low resistance, may be used, and may be other silicide films or high-melting point metal films.

Further, in the above embodiment, in order to prevent the formation of a PN junction, the first layer gate polycrystalline silicon 7 and the second layer gate polycrystalline silicon 8 sandwiching the silicide film 6 are set to have different polarities. However, it goes without saying that the same polarity may be used when there is no problem with this PN junction.

Further, in the above embodiment, the gate electrode has a three-layer structure consisting of the first layer gate polycrystalline silicon 7/silicide film 6/second layer gate polycrystalline silicon 8, but it is possible to use a structure other than the three-layer structure. You can.

[0016]

As described above, according to the semiconductor device according to the present invention, the gate electrode is formed by forming the sub-material layer, which has a lower resistance than the main material layer and has a lower contact resistance with the main material layer, into the main material layer. Since the layered structure is made such that the main material layer is the same gate electrode material as conventional gate electrodes, it is formed on the channel side of the gate electrode, which improves the flatness of the device and the work function between the channel and the channel. While maintaining the same relationship as before, it is possible to easily control the threshold voltage, and
This has the effect of lowering the resistance of the gate electrode.

[0017] Furthermore, when the main material layer has different polarities between the layer above and the layer below the sub-material layer,
In other words, if the main material layer that connects the parts of the elements with other functions among the main material layers is made to have the same polarity as the parts of the elements with other functions that connect. , the formation of a PN junction can be prevented, and an ohmic-like connection can be achieved.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

[Brief explanation of symbols]

1 Gate polycrystalline silicon 2 Base insulating film 3 Gate insulating film 4 Thin film polycrystalline silicon (source/drain) 5
Thin film polycrystalline silicon (channel) 6 Silicide film (
WSix) 7 First layer gate polycrystalline silicon 8 Second layer gate polycrystalline silicon

Claims (4)

[Claims] 1. In a semiconductor device comprising a gate electrode formed on a base insulating film and an active layer formed on the gate electrode with a gate insulating film interposed therebetween, the gate electrode It has a lower resistance than the main material layer that makes it up,
A semiconductor device characterized in that the semiconductor device has a structure in which a sub-material layer having a low contact resistance with the main material layer is laminated between the main material layers. 2. The semiconductor device according to claim 1,
A semiconductor device characterized in that the main material layer has different polarities between a layer above the sub-material layer and a layer below the sub-material layer. 3. The semiconductor device according to claim 1,
A semiconductor device characterized in that the main material layer has the same polarity as a layer above the sub-material layer and a layer below the sub-material layer. 4. The semiconductor device according to claim 1,
A semiconductor device characterized in that the material of the main material layer is polycrystalline silicon, and the material of the sub-material layer is a high melting point metal or its silicide.