JPH02114532A - Semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize by directly connecting a high-concentration impurity diffusion region of a first conductive type, a first polycrystalline silicon layer of the first conductive type and a second polycrystalline silicon layer of a second conductive type formed on the surface of a semiconductor substrate. CONSTITUTION:A polyside wiring layer 5 has a double structure, wherein a first polycrystalline silicon layer 6 of the same conductive type (n-type) as that of a high-concentration impurity diffusion layer 2 and a high melting point metal layer 7 consisting of a high melting point metal material such as MOSi2 are laminated. Further, on this polyside wiring layer 5, an interlayer insulating film 8 covering this is formed and thereon a second polycrystalline silicon layer 9 of a second conductive type (p-type) is formed, while this silicon layer 9 is connected to the upper surface of the high melting point metal layer 7 through a contact hole formed in a prescribed position of the interlayer insulating film 8 for being conductive. Thereby, it becomes needless to be mutually connected by an aluminium wiring layer thus enabling a semiconductor device to be miniatualized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention mainly relates to semiconductor devices such as static RAM memory cells, and specifically relates to highly concentrated impurities of the first conductivity type formed on the surface of the semiconductor substrate. The present invention relates to an electrical connection structure between a diffusion region, a first polycrystalline silicon layer of a first conductivity type, and a second polycrystalline silicon layer of a second conductivity type.

[Conventional technology]

Conventionally, the most known semiconductor device of this type is one having a structure as shown in FIGS. 4 and 5. That is, in the first conventional example shown in FIG.
A first conductivity type (N type) high concentration impurity-enhanced PI1. fJ region 31, the first N-type polycrystalline silicon layer 33 located in the first layer on the field oxide film 32 formed on the surface of the semiconductor substrate 30, and the second layer on the field oxide film 32. Second conductivity type (P type)
and a second polycrystalline silicon layer 34 are interconnected by an aluminum 11 wiring layer 35. Note that reference numerals 36 and 37 in this figure indicate glabellar insulating films, and in predetermined positions of these glabellar insulating films 36 and 37, there are a high concentration impurity diffusion region 31 and a first polycrystalline silicon layer 3.
Openings (contact holes) are formed to connect each of the third and second polycrystalline silicon layers 34 and the aluminum wiring layer 35 to each other.

Further, in the second conventional example shown in FIG. directly connected through. The first polycrystalline silicon layer 33 and the second polycrystalline silicon layer 34 are connected to the aluminum wiring layer 35 through contact holes formed in the interlayer insulating film 36.37.
connected by. In this second conventional example, parts that are the same as or correspond to those in the first conventional example are given the same reference numerals, and their explanations are omitted.

[Problem to be solved by the invention]

Incidentally, in the semiconductor devices according to the first conventional example and the second conventional example described above, the electrical connection between at least the N-type first polycrystalline silicon layer 33 and the P-type second polycrystalline silicon layer 34 is made of aluminum. Since this is done through the wiring layer 35, it has been difficult to take sufficient measures to meet the growing demand for miniaturization of semiconductor devices in recent years. In particular, it has been extremely difficult to construct a highly integrated static RAM with a high resistance load or a complete CMO3 static memory cell in which a P-channel transistor is formed using a polycrystalline silicon layer.

The present invention was made to solve such inconveniences, and includes a first conductivity type high-4 degree impurity diffusion region formed on the surface of a semiconductor substrate, and a first conductivity type first polycrystalline impurity diffusion region. An object of the present invention is to provide a semiconductor device that can be miniaturized by directly connecting a silicon layer and a second polycrystalline silicon layer of a second conductivity type.

[Means to solve the problem]

In the semiconductor device according to the present invention, a first polycrystalline solicon layer and a refractory metal layer of the same conductivity type are laminated on a high concentration impurity diffusion region of the first conductivity type formed on the surface of a semiconductor substrate. a second polycide wiring layer of a second conductivity type that is electrically connected to the polycide wiring layer through a bloom formed on the glabellar insulating layer formed to cover the polycide wiring layer; It adopts a structure in which a crystalline silicon layer is formed.

[Effect]

According to the above configuration, the first
While the conductivity type high-4 degree impurity diffusion region and the first i conductivity type first polycrystalline silicon layer constituting the polycide wiring layer are directly connected, this first polycrystalline silicon layer and the second polycrystalline silicon layer are directly connected to each other. The conductivity type second polycrystalline silicon layer is tD>M through the high melting point metal layer of the polycide wiring layer which makes ohmic contact with the second polycrystalline silicon layer. Therefore, it is no longer necessary to use an aluminum interconnection layer as in the conventional example to connect the high 7-degree impurity expansion region, the first polycrystalline silicon layer, and the second polycrystalline silicon layer to each other.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device to which the present invention is applied, and the symbol l in this figure represents a semiconductor substrate;
2 is a first conductivity type (N type) high concentration impurity diffusion region formed on the surface thereof, 3 is a thick field oxide film formed on both sides of the impurity diffusion region 2, and 4 is a region continuous with the field oxide film 3. A thin gate oxide film is formed.

Further, reference numeral 5 denotes a polycide wiring layer, and this polycide wiring layer 5 includes a first polycrystalline silicon layer 6 of the same conductivity type (N type) as the high concentration impurity diffusion region 2, and a layer of MO3iz or W.
High melting point metal layer 7 made of a high melting point metal material such as Si2
It has a double layered structure. This polycide wiring layer 5 is formed to cover from one (left side in the figure) field oxide film 3 to the end of the other field oxide film 3 via the gate oxide film 4 and the high concentration impurity diffusion region 2. has been done.

Further, a glabellar insulating film 8 is formed on this polycide wiring layer 5 to cover it, and a second polycrystalline silicon layer 9 of a second conductivity type (P type) is formed on this glabellar insulating film B. ing. This second polycrystalline silicon layer 9 is
It is connected to the upper surface of the high melting point metal layer 7 located above the polycide wiring layer 6 through a contact hole formed at a predetermined position in the interlayer insulating film 8 for conduction.

Next, a manufacturing procedure for a semiconductor device having the structure shown in FIG. 1 will be explained.

First, a field oxide film 3 and a gate oxide film 4 are respectively formed on the surface of a prepared semiconductor substrate 1, and then contact holes are formed at predetermined positions in the gate oxide film 4. Then, by an implantation method and a diffusion method using these field oxide film 3 and gate oxide film 4 as masks, an N-type high concentration impurity diffusion region 2 is formed in a region corresponding to the contact hole on the surface of the semiconductor substrate 1.

Furthermore, a first polycrystalline silicon layer 6 is formed on the surface of the semiconductor substrate 1, that is, on the impurity diffusion region 2, the field oxide film 3, and the gate oxide film 4, by the CVD method. 6 is made to have the same conductivity type (N type) as the impurity diffusion region 2 by an implantation method. Next, on this first polycrystalline soric layer 6, M
After forming the polycide wiring layer 5 by forming the high melting point metal layer 7 made of O3iz, WSi2, etc.,
Gate electrodes and wiring are formed by patterning this polycide wiring layer 5 by photolithography. As a result, the impurity diffusion region 2 formed in the semiconductor substrate 1 and the gate electrode and wiring formed from the polycide wiring layer 5 are ohmic.

to form a contact and conduct.

Subsequently, an interlayer insulating film 8 is formed over the entire surface of the semiconductor substrate 1 by the CVD method, and then regions of the interlayer insulating film 8 corresponding to gate electrodes and wiring are removed by photolithography to form contact holes. Thereafter, a second polycrystalline silicon layer 9 is formed on this glabellar insulating film 8 by a CVD method, and the second polycrystalline silicon layer 9 is made into a P type by an implantation method. As a result, the gate electrode and wiring formed from the polycide wiring layer 5 and the second polycrystalline silicon layer 9 form an ohmic contact and are electrically connected. Therefore, at this point, the N-type impurity diffusion region 2 and the P-type second polycrystalline silicon layer 9 form an ohmic contact via the N-type polycide layer 5, and are electrically connected to each other. .

By the way, FIG. 2 is a sectional view showing a memory cell structure of a high resistance load type static RAM as another embodiment to which the present invention is applied. And P in this memory cell
The second polycrystalline silicon layer 9 is composed of a low concentration impurity region 9a serving as a high resistance region and a high concentration impurity region 9b. The electrode and the wiring and the second polycrystalline silicon layer 9 form an ohmink contact and are electrically connected.

Also, FIG. 3 is the same (complete CMO3 as another embodiment)
2 is a cross-sectional view showing a type static memory cell structure, in which a P-channel transistor is formed of a second polycrystalline silicon layer 9. FIG.

That is, the second polycrystalline silicon layer 9 functions as the drain region 10, source region 11, and channel region 12 of the P-channel transistor, and the polycide wiring layer 5 serves as the gate electrode. Note that at this time, the thickness of the interlayer insulating film 8 formed between the polycide VA layer 5 and the second polycrystalline silicon layer 9 is set to a thickness necessary as a gate insulating film of a P-channel transistor. Ru. Furthermore, a third polycrystalline silicon layer is formed on this second polycrystalline silicon film 9 via an interlayer insulating film (none of which is shown), and this third polycrystalline silicon layer is used as a P-channel transistor. Although it is possible to use the gate as a pole, in this case, the interlayer insulating film interposed between the second polycrystalline silicon layer 9 and the third polycrystalline silicon layer becomes the gate insulating film.

〔Effect of the invention〕

As explained above, according to the present invention, the first conductivity type high concentration impurity diffusion region formed on the surface of the semiconductor substrate and the first conductivity type first polycrystalline silicon layer constituting the polycide wiring layer are combined. A second polycrystalline silicon layer that is directly connected and has a second conductivity type is directly connected to the first polycrystalline silicon layer through a high melting point metal N of a polycide wiring layer that forms ohmic contact with the second polycrystalline silicon layer. will be done. Therefore, there is no need to connect the high concentration impurity diffusion region, the first polycrystalline silicon layer, and the second polycrystalline silicon layer to each other using an aluminum wiring layer as in the conventional example, and it is possible to miniaturize the semiconductor device. becomes. As a result, sufficient measures can be taken to meet the demand for miniaturization of semiconductor devices.

[Brief explanation of drawings]

1 to 3 show embodiments of the present invention, FIG. 1 is a sectional view showing the structure of a semiconductor device to which the present invention is applied, and FIG. 2 is a high resistance load type static device to which the present invention is applied. FIG. 3 is a cross-sectional view showing a memory cell structure of a RAM, and FIG. 3 is a cross-sectional view also showing a completely CMO3 static memory cell structure. 4 and 5 relate to conventional examples, FIG. 4 is a sectional view showing the structure of a semiconductor device as the first conventional example, and FIG. 5 is a sectional view showing the second conventional example. be. In the figure, 1 is a semiconductor substrate, 2 is a high concentration impurity diffusion region, 5 is a polycide wiring layer, 6 is a first polycrystalline silicon layer, 7 is a high melting point metal layer, 8 is an interlayer insulating layer, and 9 is a second polycrystalline silicon layer. It is a silicon layer.

Claims (1)

[Claims] (1) A polycide wiring layer in which a first polycrystalline silicon layer of the same conductivity type and a high melting point metal layer are stacked on a high concentration impurity diffusion region of the first conductivity type formed on the surface of a semiconductor substrate. A second polycrystalline silicon layer of a second conductivity type was formed on the interlayer insulating layer formed to cover the polycide wiring layer, and the second polycrystalline silicon layer was electrically connected to the polycide wiring layer through the opening formed therein. A semiconductor device characterized by: