JP3154130B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory suitable for application to a complete CMOS type static RAM.

[0002]

2. Description of the Related Art A stacked complete CMOS static RAM having a structure in which a load transistor composed of a thin film transistor (TFT) is stacked on a driver transistor,
In recent years, attention has been paid to low power consumption, good data retention characteristics, and high integration by stacking.

In such a stacked complete CMOS type static RAM, the gate electrode and the word line of the driver transistor are composed of a first polycide film (a composite film in which a refractory metal silicide film is laminated on a polycrystalline silicon (Si) film). ), And the gate electrode and the channel region of the load transistor composed of a TFT are formed by the second-layer polycrystalline Si film and the third-layer polycrystalline Si film, respectively, to increase the channel length of the load transistor. Have been proposed (IEICE Technical Report, vol.SD
M89-19, p.1, 1989).

[0004]

However, a stacked complete CMOS type static RAM disclosed in the above-mentioned document.
The contact portion of the gate electrode of one load transistor formed by the second-layer polycrystalline Si film with the gate electrode of the driver transistor formed by the first-layer polycide film; Since the contact portion of the drain region of the other load transistor formed of the third-layer polycrystalline Si film with respect to the electrode has an overlapping structure, disconnection of the wiring may occur at these contact portions. is there.

Further, a TF constituting a load transistor
In order to suppress the leakage current at the time of turning off the T, it is desired to increase the channel length of the TFT. However, depending on the arrangement of the load transistors in the memory cell of the above-mentioned conventional stacked complete CMOS static RAM, these may be reduced. There is a problem that the increase in the channel length of the load transistor is insufficient.

Regarding the increase in the channel length of the load transistor, the inventor of the present invention disclosed in Japanese Patent Application No. 2-290162 that the channel region of one of the load transistors and the drain region of the other of the pair of load transistors are connected to each other. , Each of these load transistors is formed of a semiconductor thin film so as to overlap with each other with a gate insulating film interposed therebetween, and the width of each semiconductor thin film is made larger in the drain region than in the channel region. RAM was proposed. According to this, the channel length of the load transistor can be made sufficiently large, whereby the leakage current when the load transistor is off can be greatly reduced.

However, in the stacked complete CMOS type static RAM proposed in Japanese Patent Application No. 2-290162, the drain region and the gate are provided on the contact portion of the drain region of one load transistor with respect to the gate electrode of the driver transistor. Since the channel region of the other load transistor is overlapped via the insulating film, the electric field concentration effect caused by the steep step at the contact portion causes
There is a concern that the gate breakdown voltage of the other load transistor may be degraded.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory capable of greatly reducing the leak current of a load transistor by increasing the channel length of a load transistor comprising a TFT. Another object of the present invention is to provide a semiconductor memory capable of preventing disconnection of wiring due to overlapping wiring contact portions and improving reliability.

Another object of the present invention is to provide a semiconductor memory capable of preventing deterioration of the gate breakdown voltage of a load transistor.

[0010]

To achieve the above object, the present invention provides a pair of first conductive type channel driver transistors (Q ₁ , Q ₂ ) and a pair of second conductive type channel load transistors (Q ₁ , Q ₂ ). Q ₃ , Q ₄ ) and a pair of access transistors (Q ₅ , Q ₆ ) form a memory cell, and a pair of first conductivity type channel driver transistors (Q ₁ , Q 4)
₂ ) In a semiconductor memory having a structure in which a pair of second-conductivity-type channel load transistors (Q ₃ , Q ₄ ) are stacked on a pair of second-conductivity-type channel load transistors (Q ₃ , Q ₄ ). One of the load transistors (Q ₃
Or Q ₄₎ of the channel region (19 or 22) and the other of the load transistor (Q ₄ or drain region (23 or 20 of the Q ₃₎₎ and the pair so as to overlap each other via the gate insulating film (21) The load transistors (Q ₃ , Q ₄ ) of the two-conductivity-type channel are each formed of a semiconductor thin film, and one of the driver transistors (Q ₁ , Q ₂ ) of the pair of first-conductivity-type channels is connected to one of the driver transistors (Q ₁ or Q ₁ ). Q ₂ ) to the other load transistor (Q ₄ or Q ₂ ) with respect to the gate electrode (G ₁ or G ₂ ).
₃ ) With the contact portion (C ₈ or C ₉ ) of the drain region (23 or 20) as a branch point, the drain region (23 or 20) and the channel region (22 or 20) of the other load transistor (Q ₄ or Q ₃ ). 19) and sail each other
It extends in the opposite direction .

[0011]

SUMMARY OF According to the semiconductor memory of this invention constructed as described above, one of the load transistors of the load transistor pair of the second conductivity type channel _{(Q 3, Q 4) (} Q 3 or Q ₄₎ Channel region (19 or 22)
And the drain region (23 or 20) of the other load transistor (Q ₄ or Q ₃ ) overlaps with each other via the gate insulating film (21) so that the load transistors (Q ₃ , Q _{3) 4} ) Since each is formed of a semiconductor thin film, the drain region of one load transistor can be used as it is as the gate electrode of the other load transistor. In this case, since the gate electrodes of the pair of load transistors (Q ₃ , Q ₄ ) are formed of different layers, there is no need to separate these gate electrodes from each other in the plane of the memory cell. For this reason, the channel length of these load transistors can be made sufficiently large, and the leakage current can be greatly reduced.

The contact point of the drain region of the other load transistor with respect to the gate electrode of one of the driver transistors (Q ₁ , Q ₂ ) of the pair of first conductivity type channels is taken as a branch point, Since the drain region and the channel region of the load transistor extend in directions substantially opposite to each other, the channel region of the other load transistor overlaps the contact portion of the drain region of one load transistor with respect to the gate electrode of the driver transistor. Can be prevented. As a result, it is possible to prevent the gate withstand voltage of the load transistor from deteriorating due to electric field concentration caused by the steep step at the contact portion.

Further, since a single contact portion is used for connecting the drain region of one load transistor, the gate electrode of the other load transistor, and the gate electrode of one driver transistor to each other, a wiring is provided at this contact portion. There is no risk of disconnection of steps.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals. First, the configuration of the memory cell of the complete CMOS static RAM will be described.

As shown in FIG. 6, the memory cell of the complete CMOS static RAM includes a flip-flop circuit including a pair of driver transistors Q ₁ and Q ₂ and a pair of load transistors Q ₃ and Q ₄ , and a memory. and a pair of access transistors Q _5, Q ₆ for exchanging data with the outside cells. WL indicates a word line, and BL and BL 'indicate bit lines. V _CC , V
_SS represents a power supply. FIG. 1 is a plan view of a stacked complete CMOS type static RAM according to a first embodiment of the present invention,
FIG. 2 is a sectional view taken along line 2-2 of FIG.

As shown in FIGS. 1 and 2, a stacked complete CMOS type static RAM according to the first embodiment is shown.
A semiconductor substrate 1 such as a p-type Si substrate
Field insulating film 2 such as a SiO ₂ film on the surface of
Are selectively formed, thereby separating elements. Below the field insulating film 2, for example, p
^{A +} type channel stop region 3 is formed. On the surface of the active region surrounded by the field insulating film 2, a gate insulating film 4 such as a SiO ₂ film is formed.

G ₁ and G ₂ denote gate electrodes of the driver transistors Q ₁ and Q ₂ , respectively, and WL and WL ′ denote word lines. These gate electrodes G ₁ , G ₂ and word line W
L, WL ', for example phosphorus n-type impurity and the first layer polycrystalline Si film doped for example n ⁺ -type high concentration, such as (P), the first layer of the n ⁺ -type For example, it is formed of a polycide film in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is laminated on a polycrystalline Si film.

On the other hand, in the active region surrounded by the field insulating film 2, for example, n ⁺ -type diffusion layers 5 to 11 constituting a source region or a drain region are formed. The gate electrode G ₁ and the diffusion layers 5 and 6 form a driver transistor Q composed of an n-channel MOS transistor.
₁ is formed. Similarly, the gate electrode G ₂ and the diffusion layers 7 and 8, the driver transistor Q ₂ to which an n-channel MOS transistor is formed. Also,
The word line WL and the diffusion layers 6 and 9 form an n-channel MO.
S access transistors Q ₅ consisting of transistors are formed by the word line WL and the diffusion layer 10, 11, n
Access transistor Q ₆ consisting channel MOS transistor is formed.

In this case, sidewall spacers 12 made of, for example, SiO ₂ are formed on the side walls of the gate electrodes G ₁ and G ₂ and the word lines WL and WL ′. And
The diffusion layers 5 to 11 include the side wall spacers 12.
For example, an n ⁻ -type low-impurity-concentration portion a is formed in a lower portion of the substrate. Therefore, the driver transistors Q ₁ and Q ₂
The access transistors Q ₅ and Q ₆ are connected to the LDD (ligh
tly doped drain) structure. However, these driver transistors Q ₁ , Q ₂ and access transistors Q ₅ , Q ₆ need not necessarily have an LDD structure.

C _{1 to} C ₃ are buried contacts (buried contacts).
contact). Then, the driver transistor one end of the gate electrode G ₁ of the Q ₁ is the driver transistor Q ₂ through a contact hole C ₁
It is in contact with the diffusion layer 7 and the other end diffusion layer 1 of the access transistor Q ₆ through the contact hole C ₂
0 is contacted. The gate electrode G ₂ of the driver transistor Q ₂ is, it is put in contact with the diffusion layer 6 of the driver transistor Q ₁ and the access transistor Q ₅ through the contact hole C _3.

Reference numeral 13 denotes an interlayer insulating film such as a phosphor silicate glass (PSG) film or a SiO ₂ film.
C ₄ and C ₅ indicate contact holes for buried contacts formed in the interlayer insulating film 13. Sign 1
Reference _numeral 4 denotes a ground power supply line for supplying the power supply voltage V _SS . The ground power supply line 14 includes, for example, an n ⁺ -type second-layer polycrystalline Si film in which an n-type impurity such as P is doped at a high concentration, or an n ⁺ -type second-layer polycrystal. It is formed of a polycide film or the like in which a high melting point metal silicide film is overlaid on a Si film. The ground power supply line 14, together are in contact with the diffusion layer 5 of the driver transistor Q ₁ through a contact hole C _4, it is put in contact with the diffusion layer 8 of the driver transistor Q ₂ through a contact hole C _5.

Reference numerals 15 and 16 indicate relay wiring. Like the ground power supply line 14, these relay wirings 15 and 16 are made of, for example, an n ⁺ -type second-layer polycrystalline Si film doped with an n-type impurity such as P at a high concentration, It is formed by a polycide film in which a refractory metal silicide film is superposed on a ⁺ -type second polycrystalline Si film. Here, the relay wiring 15 is put in contact with the diffusion layer 9 of the access transistor Q ₅ through the contact hole C ₆ for buried contact. The relay wiring 16 is put in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C ₇ for buried contact.

Reference numeral 17 denotes an interlayer insulating film such as a PSG film or a SiO ₂ film. Reference numeral 18 denotes a power supply voltage V
Indicates the power supply line for _CC supply. The power supply line 18 is formed of, for example, a p ⁺ -type third polycrystalline Si film and a fourth polycrystalline Si film in which a p-type impurity such as boron (B) is highly doped. Is done.

The reference numeral 19 for example, n-type channel region of the load transistor Q _3, 20 denotes a drain region, for example p ⁺ -type load transistor Q _3. Here, the drain region 20, also serves as a gate electrode of the load transistor Q _4. These channel region 19 and drain region 2
0 is formed, for example, by a third-layer polycrystalline Si film.

Reference numeral 21 denotes a gate insulating film such as a SiO ₂ film. Reference numeral 22 denotes an n-type channel region of the load transistor Q _4, 23 is the load transistor Q ₄
For example, a p ⁺ type drain region is shown. Here, the drain region 23, also serves as a gate electrode of the load transistor Q _3. The channel region 22 and the drain region 23 are formed of, for example, a fourth-layer polycrystalline Si film.

In this case, the channel region 19 of the load transistor Q ₃ formed by the third-layer polycrystalline Si film is used.
Is composed of a portion parallel to the bit lines BL and BL 'to be described later and a portion inclined with respect to the bit lines BL and BL', and has a bent shape as a whole. Similarly, the channel region 22 of the load transistor Q ₄ which is formed by the fourth layer polycrystalline Si film, inclined bit line BL, and a portion parallel to BL' and these bit line BL, and against BL' And has a bent shape as a whole.

The width of the drain region 20 of the load transistor Q ₃ is larger than the width of the channel region 19. Similarly, the width of the drain region 23 of the load transistor Q ₄ are, is greater than the width of the channel region 22. In this case, these drain regions 20, 23
Has a substantially rectangular shape. The drain region 23 which is used as a gate electrode of the load transistor Q ₃
Completely cover the channel region 19. On the other hand, the channel region 22 of the load transistor Q ₄ are, rests entirely on the drain region 20 to be used as the gate electrode of the load transistor Q _4.

C ₈ and C ₉ denote contact holes for buried contacts formed in the interlayer insulating films 13 and 17. Then, the load drain region 20 used as the gate electrode of the transistor Q ₄ are, the gate electrode G of the driver transistor Q ₂ through a contact hole C ₉
Contact ₂ Also, the load transistor Q ₃
The drain region 23 used as the gate electrode of the driver transistor Q ₁ through the contact hole C _8.
It is put in contact with the gate electrode G ₁ of the.

[0029] In this first embodiment, the load channel region 19 of the transistor Q ₃ and the drain region 20 which also serves as a gate electrode of the load transistor Q ₄ are, the contact hole C ₉ as a branch point, substantially opposite directions Extending. Similarly, the drain region 23 and channel region 22 of the load transistor Q ₄ also serves as a gate electrode of the load transistor Q ₃ are the contact hole C ₈ as a branching point, extend approximately in opposite directions.

Reference numeral 24 indicates an interlayer insulating film such as a PSG film. C _10, C ₁₁ represents a contact hole formed in the interlayer insulating film 24, the gate insulating film 21 and the interlayer insulating film 17. Here, the contact hole C ₁₀ is
It is formed on the access transistor Q _5. Also,
Contact holes C ₁₁ is formed on the access transistor of the memory cell adjacent using word line WL '. Then, for example, aluminum through a contact hole C ₁₀ (Al) bit lines are formed by wiring BL
Are in contact with the relay wiring 15. As already mentioned, since the relay wiring 15 is in contact with the diffusion layer 9 of the access transistor Q ₅ through the contact hole C _6, the bit lines BL diffusion layers of the access transistor Q ₅ through the relay wiring 15 9 Connected. Similarly, the bit line BL' are put in contact with the relay wiring 16 through a contact hole C _11, since the relay wiring 16 is in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C _7, the bit lines BL ′ Is connected to the diffusion layer 11 of the access transistor Q ₆ via the relay wiring 16. Note that these bit lines BL, BL extend in a direction perpendicular to the word lines WL.

Next, the stacked complete CMOS type static RA according to the first embodiment constructed as described above will be described.
An example of a method for manufacturing M will be described. As shown in FIGS. 1 and 2, first, the surface of a semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 2 to perform element isolation. At this time, for example, a p-type impurity such as B, which has been ion-implanted in the semiconductor substrate 1 in advance, diffuses, and a p ⁺ -type channel stop region 3 is formed below the field insulating film 2. Next, a gate insulating film 4 is formed on the surface of the active region surrounded by the field insulating film 2 by a thermal oxidation method. Then, a predetermined portion of the gate insulating film 4 and the field insulating film 2 is removed by etching to form contact holes C ₁ -C _3.

Next, for example, a first-layer polycrystalline Si film is formed on the entire surface by the CVD method, and an impurity such as P is doped into the polycrystalline Si film at a high concentration by a thermal diffusion method, an ion implantation method, or the like. After doping to lower the resistance, the polycrystalline Si film is patterned into a predetermined shape by etching to form gate electrodes G ₁ and G ₂ and word lines WL and WL ′.
Next, the gate electrodes G ₁ and G ₂ and the word line W
Using the L and WL 'as a mask, an n-type impurity such as P is ion-implanted into the semiconductor substrate 1 at a low concentration. Next, C
After forming, for example, an SiO ₂ film on the entire surface by the VD method, this SiO ₂ film is subjected to, for example, reactive ion etching (RI
The sidewall spacers 12 are formed on the side walls of the gate electrodes G ₁ and G ₂ and the word lines WL and WL ′ by etching in a direction perpendicular to the substrate surface by the method E).

Next, the side wall spacers 12,
Using the gate electrodes G ₁ and G ₂ and the word lines WL and WL ′ as a mask, n such as arsenic (As) is formed in the semiconductor substrate 1.
Type impurities are ion-implanted at a high concentration. Thereafter, a heat treatment for electrically activating the implanted impurities is performed. As a result, diffusion layers 5 to 11 having low impurity concentration portions a are formed below the sidewall spacers 12. Next, after an interlayer insulating film 13 is formed on the entire surface by the CVD method, predetermined portions of the interlayer insulating film 13 are removed by etching to form contact holes C ₄ , C ₅ , C ₆ , and C ₇ .

Next, a second-layer polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is doped with an impurity such as P at a high concentration to reduce the resistance. The ground power supply line 14 and the relay wirings 15 and 16 are formed by patterning the polycrystalline Si film into a predetermined shape by etching.

Next, the interlayer insulating film 1 is formed on the entire surface by the CVD method.
7 is formed. Next, a third-layer polycrystalline Si film is formed on the entire surface by a CVD method, and this polycrystalline Si film is doped with an n-type impurity such as P at a low concentration. covering the surface of the portion to be the channel region 19 of the load transistor Q ₃ after, for example, a resist pattern (not shown), a p-type impurity, such as a polycrystalline Si film using the resist pattern as a mask such as B Ion implantation at high concentration. After that, the resist pattern is removed. Next, the third polycrystalline Si film is patterned into a predetermined shape by etching, and the power supply voltage V
Wiring 18 for supplying _CC , n-type channel region 19 and p ⁺
A mold drain region 20 is formed.

Next, a gate insulating film 21 is formed on the entire surface by, for example, a CVD method. The gate insulating film 21
Can be formed by, for example, a thermal oxidation method.
Next, predetermined portions of the gate insulating film 21, the interlayer insulating film 17, and the interlayer insulating film 13 are removed by etching to form contact holes C ₈ and C ₉ . Next, a fourth-layer polycrystalline Si film is formed on the entire surface by a CVD method.
After doping in the n-type impurity such as P low concentration layer, the polycrystalline Si surface, for example, the resist pattern of the portion to be the channel region 22 of the load transistor Q ₄ after one of the film (not shown) And p-type impurities such as B are ion-implanted into the polycrystalline Si film at a high concentration using the resist pattern as a mask. After that, the resist pattern is removed. Next, the fourth-layer polycrystalline Si film is patterned into a predetermined shape by etching to form the wiring 18 for supplying the power supply voltage V _CC , the n-type channel region 22 and the p ⁺ -type drain region 23. .

Next, the interlayer insulating film 2 is formed on the entire surface by the CVD method.
4 is formed, the interlayer insulating film 24, the gate insulating film 2
1 and a predetermined portion of the interlayer insulating film 17 are removed by etching to form contact holes C ₁₀ and C ₁₁ . Next, after forming an Al film on the entire surface by, for example, a sputtering method,
The film is patterned into a predetermined shape by etching to form bit lines BL and BL ', thereby completing the intended stacked complete CMOS static RAM.

As described above, according to the first embodiment,
Load transistors Q ₃ and Q ₄ composed of p-channel TFTs
Are formed of the fourth-layer polycrystalline Si film and the third-layer polycrystalline Si film, respectively, so that there is no need to separate these gate electrodes from each other in the plane of the memory cell. As a result, the channel length of these load transistors Q ₃ and Q ₄ can be made sufficiently large, and the leakage current can be greatly reduced.

Further, the load transistor Q ₃ of the drain region 20 and the driver transistor Q gate electrode of the gate electrode G ₂ of the ₂ and the load transistor Q ₄ (drain region 23
Single is connected to each other at the contact portion, and the gate electrode G ₁ of the drain region 23 and the driver transistor to Q ₁ load transistor Q ₄ load transistor Q ₃ of the gate in the contact hole C ₉ and constituted) by since the electrode (constituted by the drain region 20) are interconnected by a single contact portion of the contact hole C _8, it is possible to prevent a disconnection of the wiring in these contact portions. Thereby, it is possible to improve the reliability and the yield of the stacked complete CMOS type static RAM.

Further, since no overlap contact portions of the drain region 20 of the load transistor Q ₃ to the gate electrode G ₂ of the driver transistor Q ₂ and the channel region 22 of the load transistor Q _4, a step is steep at the contact portion the deterioration of the gate breakdown voltage of the load transistor Q ₄ due to electric field concentration due to the sometimes can be prevented.

Furthermore, since it is not necessary to separate the channel regions 19 and 22 and the drain regions 20 and 23 of the load transistors Q ₃ and Q _{4 from} each other in the plane of the memory cell, it is necessary to increase the matching margin therebetween. Can be. Further, since the widths of the drain regions 20 and 23 are wider than those of the channel regions 19 and 22, the third polycrystalline Si film forming the load transistors Q ₃ and Q ₄ and the fourth
Failure due to misalignment between the polycrystalline Si films of the layers can be prevented.

Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view of a stacked complete CMOS type static RAM according to a second embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. The stacked complete CMOS static RAM according to the second embodiment is
The configuration is substantially the same as that of the first embodiment except that the following points are different.

[0043] First, the channel region 19 and drain region 20 of the load transistor Q ₃ are in the first embodiment is formed by a third layer of polycrystalline Si film, the channel region 22 and the drain region of the load transistor Q ₄ 23 is formed of a fourth-layer polycrystalline Si film, whereas in the second embodiment, the load transistor Q ₃
The channel region 19 and drain region 20 are formed by the fourth layer polycrystalline Si film, the channel region 22 and drain region 23 of the load transistor Q ₄ are formed by a third layer of polycrystalline Si film.

Second, the second embodiment differs from the first embodiment in the shape and layout of the ground power supply line 14, the power supply line 18, and the channel regions 19 and 22. Third, first
Drain region 2 of the load transistor Q ₄ in the embodiment with respect to the gate electrode G ₁ of the driver transistor Q ₁
Contact portion of the 0,23 whereas located on one end of the gate electrode G ₁ that is buried contact to the diffusion layer 10, in this second embodiment, the contact portion is a diffusion layer 7 are located on the other end portion of the gate electrode G ₁ that is buried contact.

Fourth, in the first embodiment, the bit line B
L and BL 'are connected to the diffusion layers 9 and 11 via the relay wirings 15 and 16, respectively. In the second embodiment, these bit lines BL and BL' are connected to the diffusion layers 9 and 11, respectively. , 11 directly.

The stacked complete CM according to the second embodiment
The method of manufacturing the OS-type static RAM is the same as that of the first embodiment, and a description thereof will be omitted. According to the second embodiment, the drain region 2 of the load transistor Q ₄ to the gate electrode G ₁ of the driver transistor Q ₁ as described above
By contact portion 3 is positioned on the other end portion of the gate electrode G ₁ that is buried contact to the diffusion layer 7, as compared with the first embodiment with respect to increased channel length of the load transistor Q ₄ In addition to the advantages, there are the same advantages as in the first embodiment.

Next, a third embodiment of the present invention will be described. This third embodiment is based on the technical report of
vol.SDM89-19, p.1, 1989, the above-described conventional stacked complete CMOS static RA.
The present invention is applied to M. FIG. 5 shows a stacked complete CMOS static RA according to the third embodiment.
It is a top view of M.

The complete stacked CM according to the third embodiment
In the OS type static RAM, the gate electrodes G ₁ and G ₂ of the driver transistors Q ₁ and Q ₂ and the word line WL are formed of, for example, a first-layer polycrystalline Si film or a polycide film, and the channel of the load transistor Q ₄ Area 2
2 and the drain region 23 are, for example, polycrystalline Si of the second layer.
Is formed by the membrane, the load transistor Q ₃ in the channel region 19 and drain region 20 are formed by, for example, the third layer polycrystalline Si film. Then, the load transistor Q ₃ in the channel region 19 and drain region 20 has substantially the same shape and layout as in the second embodiment as a whole. Similarly, the channel region 22 and drain region 23 of the load transistor Q ₄ are, has almost the same layout and shape as in the second embodiment as a whole. The third embodiment has many advantages similar to those of the first and second embodiments.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical concept of the present invention are possible. For example, in the above-described first and second embodiments, what is formed by the third-layer polycrystalline Si film is formed by the fourth-layer polycrystalline Si film, and the fourth-layer polycrystalline Si film is formed. What is formed of a crystalline Si film can be formed of a third-layer polycrystalline Si film. Similarly, in the third embodiment, what is formed by the second-layer polycrystalline Si film is formed by the third-layer polycrystalline Si film, and is formed by the third-layer polycrystalline Si film. Can be formed by the second layer polycrystalline Si film.

[0050]

As described above, according to the present invention,
Leakage current can be significantly reduced by increasing the channel length of the load transistor, wiring disconnection due to overlapping wiring contacts can be prevented, and deterioration of the gate withstand voltage of the load transistor can be prevented. can do.

[Brief description of the drawings]

FIG. 1 shows a stacked complete C according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a MOS static RAM.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

FIG. 3 shows a stacked complete C according to a second embodiment of the present invention.
FIG. 2 is a plan view showing a MOS static RAM.

FIG. 4 is a sectional view taken along line 4-4 in FIG. 3;

FIG. 5 shows a stacked complete C according to a third embodiment of the present invention.
FIG. 2 is a plan view showing a MOS static RAM.

FIG. 6 is a circuit diagram showing an equivalent circuit of a memory cell of a complete CMOS static RAM.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 4 and 21 a gate insulating film G _1, G ₂ gate electrode WL, WL 'word lines 5-11 diffusion layer C ₁ -C ₁₁ contact holes 15 and 16 relay wiring 13,17,24 interlayer insulating film 14 ground power supply line 18 supply line 19, 22 a channel region 20, 23 drain region Q _1, Q ₂ driver transistor Q _3, Q ₄ load transistors Q _5, Q ₆ access transistor BL, BL 'bit line

Claims (1)

(57) [Claims] 1. A memory cell is constituted by a flip-flop circuit constituted by a pair of driver transistors of a first conductivity type channel and a pair of load transistors of a second conductivity type channel, and a pair of access transistors.
In a semiconductor memory having a structure in which the pair of load transistors of the second conductivity type are stacked on the pair of driver transistors of the first conductivity type, one of the load transistors of the pair of second conductivity type channels is provided. The pair of second conductivity type load transistors are formed of a semiconductor thin film so that the channel region of the load transistor and the drain region of the other load transistor overlap with each other via a gate insulating film. With the contact point of the drain region of the other load transistor to the gate electrode of one of the driver transistors of the conductivity type channel as a branch point, the drain region and the channel region of the other load transistor are substantially mutually
A semiconductor memory extending in the opposite direction .