JPH0555500A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a thin semiconductor in a channel region from becoming improperly thin during the etching for forming an upper electrode of a TFT of a double gate structure for a load transistor of a stacked CMOS static RAM. CONSTITUTION:A load transistor Q4 has a gate electrode composed of lower and upper gate electrodes 17 and 18 that form a fin structure. A channel region 20 is formed between the upper and lower gate electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a method of manufacturing the same, and is particularly suitable for application to a complete CMOS static RAM.

[0002]

2. Description of the Related Art A stacked complete CMOS static RAM having a structure in which a load transistor composed of a thin film transistor (TFT) is stacked on a driver transistor is
In recent years, it has attracted attention because it has low power consumption, good data retention characteristics, and high integration by stacking.

FIG. 23 shows an example of a typical structure of the driver transistor and load transistor portions in such a stacked complete CMOS static RAM. Figure 2
3, reference numeral 101 is a p-type silicon (Si) substrate,
Reference numerals 102 and 103 denote n ⁺ type diffusion layers forming a source region or a drain region, and 104 denotes a gate electrode formed on a p type Si substrate 101 via a gate insulating film (not shown). These gate electrode 104 and diffusion layer 10
2, 103 form a driver transistor composed of an n-channel MOS transistor. Code 10
Reference numeral 5 is a gate electrode, 106 is a channel region made of a polycrystalline Si film formed on the gate electrode 105 via a gate insulating film (not shown), and 107 and 108 are p ⁺ type which form a source region or a drain region. Shows the diffusion layer of. The gate electrode 105 and the diffusion layers 107 and 108 form a load transistor composed of a p-channel TFT.

Recently, in order to improve the characteristics of the load transistor, as shown in FIG. 24, an attempt is made to configure the load transistor by a TFT having a so-called double-sided gate electrode structure in which a gate electrode 109 is also formed on the channel region 106. Has been done. T with such a double-sided gate electrode structure
According to the load transistor formed of FT, channels are formed on the upper surface and the lower surface of the channel region 106 in FIG. 24, so that the channel width is effectively increased and the drain current at the time of ON can be increased. In addition to increasing the on / off ratio of the load transistor (= drain current when on / drain current when off),
By performing ion implantation using the gate electrode 109 as a mask, various advantages are obtained such that the diffusion layers 107 and 108 forming the source region or the drain region can be formed in self-alignment with the gate electrode 109. be able to.

[0005]

However, the above-mentioned FIG.
The load transistor including the double-sided gate electrode structure TFT shown in (1) has the following problems. That is, FIG.
As shown in A, the upper gate electrode 109 has a resist pattern 110 having a shape corresponding to the gate electrode 109.
Is formed on a thin polycrystalline Si film having a film thickness of 100 to 500Å, and the polycrystalline Si film is patterned by reactive ion etching (RIE) using the resist pattern 110 as a mask. As shown in FIG. 25B, the thin polycrystalline Si film forming the channel region 106 is etched and the film thickness is reduced.

Therefore, an object of the present invention is that, when the load transistor is formed by a TFT having a double-sided gate electrode structure, the semiconductor thin film forming the channel region is etched and the film thickness is reduced when the upper gate electrode is formed. It is an object of the present invention to provide a semiconductor memory and a method for manufacturing the same that can solve the above problems.

[0007]

In order to achieve the above object, a first invention is a pair of second conductivity type composed of a pair of first conductivity type channel driver transistors (Q ₁ , Q ₂ ) and a thin film transistor. Channel load transistor (Q
₃ , Q ₄ ) and a pair of access transistors (Q ₅ , Q ₆ ) to form a memory cell, and a pair of first conductivity type channel driver transistors (Q ₁ , Q ₂ ). In a semiconductor memory having a structure in which a pair of second-conductivity-type load transistors (Q ₃ , Q ₄ ) are stacked on top of each other, the gate electrode of the load transistors (Q ₃ , Q ₄ ) is seen in a cross section in the channel width direction. Having a plurality of branch portions (17, 18), and a channel region (20) made of a semiconductor thin film is formed between the plurality of branch portions (17, 18) via a gate insulating film (19). Is.

The second invention comprises a pair of first-conductivity-type channel driver transistors (Q ₁ , Q ₂ ) and a pair of second-conductivity-type channel load transistors (Q ₃ , Q ₄ ). The flip-flop circuit and the pair of access transistors (Q ₅ , Q ₆ ) form a memory cell, and the pair of second conductive layers are provided on the pair of first conductive type channel driver transistors (Q ₁ , Q ₂ ). Type channel load transistors (Q ₃ , Q ₄ )
In a method of manufacturing a semiconductor memory having a structure in which
Forming the gate electrodes of the load transistors (Q ₃ , Q ₄ ) in a shape having a plurality of branch portions (17, 18) when viewed in a cross section in the channel width direction, and a plurality of branch portions (17, 18) of the gate electrodes. Between the above), a channel region (20) made of a semiconductor thin film is formed via the gate insulating film (19).

[0009]

According to the semiconductor memory and the method of manufacturing the semiconductor memory of the present invention configured as described above, a plurality of branch portions (1) of the gate electrodes of the load transistors (Q ₃ , Q ₄ ) are provided.
7 and 18), the branch region (18) above the channel region (20) when viewed from the semiconductor substrate side, that is, at the time of etching for forming the upper gate electrode, the channel region (20) is covered by the upper gate electrode. Is covered. Therefore, there is no problem that the semiconductor thin film forming the channel region (20) is etched and the film thickness is reduced.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are designated by the same reference numerals. First, the structure of the memory cell of the complete CMOS static RAM will be described.

As shown in FIG. 4, a memory cell of a complete CMOS static RAM comprises a flip-flop circuit composed of a pair of driver transistors Q ₁ and Q ₂ and a pair of load transistors Q ₃ and Q ₄ , and a memory. It is composed of a pair of access transistors Q ₅ and Q ₆ for exchanging data with the outside of the cell. WL indicates a word line, and BL and BL 'indicate bit lines. Also, V _CC , V
_SS represents a power supply. 1 is a plan view of a stacked complete CMOS static RAM according to a first embodiment of the present invention,
2 and 3 are cross-sectional views taken along lines 2-2 and 3-3 of FIG. 1, respectively.

As shown in FIGS. 1, 2 and 3, in the stacked complete CMOS static RAM according to the first embodiment, for example, silicon dioxide (SiO 2) is formed on the surface of a semiconductor substrate 1 such as a p-type Si substrate. ₂ ) A field insulating film 2 such as a film is selectively formed, whereby element isolation is performed. Below the field insulating film 2, for example, a p ⁺ type channel stop region 3 is formed. A gate insulating film 4 such as a SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 2.

G ₁ and G ₂ are the gate electrodes of the driver transistors Q ₁ and Q ₂ , and WL and WL 'are word lines. These gate electrodes G ₁ and G ₂ and word line W
L and WL ′ are, for example, an n ⁺ -type first-layer polycrystalline Si film that is heavily doped with an n-type impurity such as phosphorus (P), or this n ⁺ -type first-layer poly-Si film. It is formed of a polycide film or the like in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is stacked on the crystalline Si film.

On the other hand, in the active region surrounded by the field insulating film 2, for example, n ⁺ type diffusion layers 5 to 11 forming a source region or a drain region are formed. The gate electrode G ₁ and the diffusion layers 5 and 6 are used to form the driver transistor Q which is an n-channel MOS transistor.
₁ is formed. Similarly, the gate electrode G ₂ and the diffusion layers 7 and 8 form a driver transistor Q _{2 which} is an n-channel MOS transistor. Also,
An n-channel MO is formed by the word line WL and the diffusion layers 6 and 9.
An access transistor Q ₅ composed of an S transistor is formed, and n is formed by the word line WL and the diffusion layers 10 and 11.
An access transistor Q ₆ composed of a channel MOS transistor is formed. The driver transistors Q ₁ and Q ₂ and the access transistors Q ₅ and Q ₆ are
It is also possible to have a so-called LDD (lightly doped drain) structure.

C ₁ , C ₂ and C ₃ represent contact holes for buried contacts. Then, one end of the gate electrode G ₁ of the driver transistor Q ₁ is in contact with the diffusion layer 7 of the driver transistor Q ₂ through the contact hole C ₁ , and the other end of the gate electrode G ₁ is connected through the contact hole C _{2 to} the diffusion layer 10 of the access transistor Q _6. I am in contact with. The gate electrode G ₂ of the driver transistor Q ₂ are contact holes C
The diffusion layers 6 of the driver transistor Q ₁ and the access transistor Q ₅ are in contact with each other through ₃ .

Reference numeral 12 indicates an interlayer insulating film such as a phosphorus silicate glass (PSG) film or a SiO ₂ film.
Reference numeral 13 indicates a silicon nitride (Si ₃ N ₄ ) film. The Si ₃ N ₄ film 13 is formed on the lower gate electrode 17 as described later.
It is used as an etching stopper at the time of etching for forming a film and is also used as a part of the interlayer insulating film. Further, C ₄ and C ₅ represent contact holes for buried contacts formed in the interlayer insulating film 12 and the Si ₃ N ₄ film 13.

Reference numeral 14 indicates a ground power supply line for supplying the power supply voltage V _SS . The ground power supply line 14 is, for example, n such as P.
⁺ Second-layer polycrystalline Si film doped with a high-concentration type impurity, and a polycide film in which a refractory metal silicide film is stacked on the n ⁺ -type second polycrystalline Si film. It is formed by. The ground power line 14 is connected to the diffusion layer 5 of the driver transistor Q ₁ through the contact hole C _4.
Contact hole C ₅
Through to the diffusion layer 8 of the driver transistor Q ₂ .

Reference numerals 15 and 16 represent relay wirings. Similar to the ground power supply line 14, these relay wirings 15 and 16 are n ⁺ doped with a high concentration of an n-type impurity such as P.
Type second-layer polycrystalline Si film, a polycide film in which a refractory metal silicide film is laminated on the n ⁺ -type second-layer polycrystalline Si film, and the like. Here, relay wiring 1
5 is in contact with the diffusion layer 9 of the access transistor Q ₅ through a contact hole C ₆ for buried contact. The relay wiring 16 is in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C ₇ for buried contact.

Reference numeral 17 indicates the lower gate electrodes of the load transistors Q ₃ and Q ₄ . The lower gate electrode 17 is made of n ⁺ which is heavily doped with an n-type impurity such as P.
It is formed of a polycrystalline Si film of the second layer of the mold. In this case, the lower gate electrode 17 of the load transistor Q ₃ overlaps with the gate electrode G ₂ of the driver transistor Q ₂ , and the driver is through the contact hole C ₈ formed in the interlayer insulating film 12 and the Si ₃ N ₄ film 13. It is in contact with the diffusion layer 7 of the transistor Q ₂ . On the other hand, the lower gate electrode 17 of the load transistor Q ₄ overlaps with the gate electrode G ₁ of the driver transistor Q ₁ , and the driver transistor Q _{4 is} exposed through the contact hole C ₉ formed in the interlayer insulating film 12 and the Si ₃ N ₄ film 13. It is in contact with the diffusion layer 6 of Q ₁ .

Reference numeral 18 represents the upper gate electrodes of the load transistors Q ₃ and Q ₄ . The upper gate electrode 18 is made of n ⁺ which is heavily doped with an n-type impurity such as P.
It is formed of a polycrystalline Si film of the third layer of the mold. The upper gate electrode 18 has the same planar shape as the lower gate electrode 17. The upper gate electrode 18 of the load transistor Q ₃ is in contact with the lower gate electrode 17 on the contact hole C ₈ . On the other hand, the upper gate electrode 18 of the load transistor Q ₄ has a contact hole C ₉
It contacts the lower gate electrode 17 above.

In this case, the lower gate electrode 17 and the upper gate electrode 18 cause the load transistor Q ₃ ,
The gate electrode of Q ₄ is formed. These lower gate electrode 17 and upper gate electrode 18 form a so-called fin structure, branching with a contact portion at one end thereof as a branch point when viewed in a cross section in the channel width direction of the load transistors Q ₃ and Q ₄ . ing. Reference numeral 19 is, for example, SiO
₂ shows a gate insulating film such as a film. As the gate insulating film 19, the composite film of the SiO ₂ film and the Si ₃ N ₄ film (e.g., a three-layered film (ONO) film and SiO ₂ film and the Si ₃ N ₄ film and the SiO ₂ film) It is also possible to use. Reference numeral 20 indicates a channel region of the load transistors Q ₃ and Q ₄ . The channel region 20 is formed of, for example, a fourth-layer polycrystalline Si film. In this case, the channel region 20 is formed between the lower gate electrode 17 and the upper gate electrode 18.

Reference numeral 21 denotes a power supply line for supplying the power supply voltage V _CC . The power supply line 21 is formed of, for example, a p ⁺ -type fourth-layer polycrystalline Si film that is heavily doped with a p-type impurity such as boron (B). Code 2
Reference numerals 2 and 23 denote, for example, p ⁺ type diffusion layers forming the drain regions of the load transistors Q ₃ and Q ₄ , respectively. These diffusion layers 22 and 23 are formed of a polycrystalline Si film in the same layer as the fourth-layer polycrystalline Si film forming the channel region 20 and the power supply line 21. In this case, the diffusion layer 22 forming the drain region of the load transistor Q ₃ is in contact with the gate electrode G ₂ of the driver transistor Q ₂ through the contact hole C ₁₀ . On the other hand, the diffusion layer 23 forming the drain region of the load transistor Q ₄ has the driver transistor Q ₁ through the contact hole C _11.
Is in contact with the gate electrode G ₁ .

A lower gate electrode 17 and an upper gate electrode 18 contacting the diffusion layer 7 of the driver transistor Q ₂ through the contact hole C ₈ and a channel region 20 formed between the lower gate electrode 17 and the upper gate electrode 18. The load transistor Q ₃ formed of a p-channel TFT having a double-sided gate electrode structure is formed by the source region of the power supply line 21 and the drain region of the diffusion layer 22 adjacent to the channel region 20. Similarly, the lower gate electrode 17 and the upper gate electrode 18 contacting the diffusion layer 6 of the driver transistor Q ₁ through the contact hole C ₉ and the channel region 20 formed between the lower gate electrode 17 and the upper gate electrode 18. And a source region and diffusion layer 23 formed of the power supply line 21 in a portion adjacent to the channel region 20.
And a drain region formed of a load transistor Q ₄ formed of a p-channel TFT having a double-sided gate electrode structure.

Reference numeral 24 indicates an interlayer insulating film such as a PSG film. C ₁₂ and C ₁₃ are contact holes formed in the interlayer insulating film 24 and the gate insulating film 19. In this case, the contact hole C ₁₂ is formed on the access transistor Q ₅ . Further, the contact hole C ₁₃ is formed on the access transistor of the adjacent memory cell using the word line WL ′. And
Through the contact hole C ₁₂ , for example, aluminum (A
l) The bit line BL formed by the wiring is the relay wiring 15
I am in contact with. Since the relay wiring 15 is in contact with the diffusion layer 9 of the access transistor Q ₅ through the contact hole C ₆ as already described, the bit line BL is connected through the relay wiring 15 to the diffusion layer 9 of the access transistor Q _5. Will be connected to. Similarly, the bit line BL ′ is in contact with the relay wiring 16 through the contact hole C ₁₃ , and this relay wiring 16
Is in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C ₇ , the bit line BL ′ is connected to the diffusion layer 11 of the access transistor Q ₆ through the relay wiring 16. The bit lines BL and BL 'extend in the direction perpendicular to the word line WL.

Next, the stacked complete CMOS static RA according to the first embodiment configured as described above.
A method of manufacturing M will be described with reference to FIGS. 1, 2 and 5 to 13. Here, FIGS. 5 to 12 are sectional views taken along the same cutting plane as FIG. 2, and FIG. 13 is a sectional view taken along the same cutting plane as FIG.

As shown in FIGS. 1 and 5, first, the surface of the semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 2 for element isolation. At this time, p-type impurities such as B, which have been selectively ion-implanted into the semiconductor substrate 1 in advance, diffuse to form a p ⁺ -type channel stop region 3 below the field insulating film 2. To be done. Next, the gate insulating film 4 is formed on the surface of the active region surrounded by the field insulating film 2 by the thermal oxidation method. Next, predetermined portions of the gate insulating film 4 and the field insulating film 2 are removed by etching to remove the contact hole C.
_{1 to} C ₃ are formed.

Next, for example, a first-layer polycrystalline Si film is formed on the entire surface by the CVD method, and an n-type impurity such as P is formed on the polycrystalline Si film by a thermal diffusion method or an ion implantation method. After being heavily doped to reduce the resistance, the polycrystalline S
The i film is patterned into a predetermined shape by etching to form gate electrodes G ₁ and G ₂ and word lines WL and WL ′. These gate electrodes G ₁ , G ₂ and word lines WL,
When WL ′ is formed of a polycide film, after forming the refractory metal silicide film on the above-mentioned first-layer polycrystalline Si film doped with the n-type impurity, the refractory metal silicide film and the polycide film are formed. The crystalline Si film is patterned.

Next, an n-type impurity such as arsenic (As) is ion-implanted at a high concentration into the semiconductor substrate 1 using the gate electrodes G ₁ and G ₂ and the word lines WL and WL 'as masks. After that, a heat treatment for electrically activating the implanted impurities is performed. Thereby, the diffusion layers 5-11 are formed. Next, after the interlayer insulating film 12 is formed on the entire surface by the CVD method, the Si ₃ N ₄ film 13 is further formed on the interlayer insulating film 12 by the CVD method. After this, these S
Predetermined portions of the i ₃ N ₄ film 13, the interlayer insulating film 12, and the gate insulating film 4 are removed by etching to remove the contact holes C ₄ to.
Form C ₉ .

Then, a second-layer polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is heavily doped with an n-type impurity such as P to reduce the resistance. ,
The polycrystalline Si film is patterned into a predetermined shape by etching to form the ground power supply line 14, the relay wirings 15 and 16, and the lower gate electrode 17.

Next, as shown in FIG. 1 and FIG.
After forming, for example, a SiO ₂ film 31 on the entire surface by a method, a resist pattern 32 having openings at portions corresponding to the contact holes C ₈ and C ₉ is formed on the SiO ₂ film 31 by lithography. In the CVD for forming the SiO ₂ film 31, it is preferable to use tetraethoxysilane (T
EOS) is used as a source gas. Next, as shown in FIG. 7, the resist pattern 32 is used as a mask to form SiO 2.
_{2 The} film 31 is etched to form the opening 31a.

Next, the resist pattern 32 is removed.
Next, a third-layer polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is heavily doped with an n-type impurity such as P to reduce the resistance. Crystal S
The i film is patterned into a predetermined shape by etching,
As shown in FIGS. 1 and 8, the upper gate electrode 18 is formed. The upper gate electrode 18 is in contact with the lower gate electrode 17 through the opening 31a formed in the SiO ₂ film 31.

Next, as shown in FIG. 9, a SiO ₂ film 31 is formed.
Are removed by, for example, wet etching using buffered hydrofluoric acid. During this etching, Si ₃ N ₄
Since the film 13 acts as an etching stopper, this S
The interlayer insulating film 12 under the i ₃ N ₄ film 13 is prevented from being etched. Next, as shown in FIGS. 1 and 10, a gate insulating film 19 is formed on the surfaces of the lower gate electrode 17 and the upper gate electrode 18 by, for example, a thermal oxidation method.
During the thermal oxidation, the gate insulating film 19 is also formed on the surfaces of the ground power supply line 14 and the relay wirings 15 and 16.

Next, as shown in FIG. 11, a fourth-layer polycrystalline Si film 33 is formed on the entire surface by a low pressure CVD method.
In this case, the polycrystalline Si film 33 is formed so as to wrap around the portion between the lower gate electrode 17 and the upper gate electrode 18 having the fin structure. Next, as shown in FIGS. 1, 12, and 13, the power supply line 2 of the polycrystalline Si film 33 is used.
1 and the resist pattern 3 covering the surfaces of the load transistors Q ₃ and Q _{4 which} are to be the drain regions and overlapping both ends of the upper gate electrode 18 in the channel length direction.
4 is formed and the polycrystalline Si film 33 is etched using the resist pattern 34 as a mask to form the channel region 20 and the power supply line 21. The polycrystalline Si film having the shape of the drain region of the load transistors Q ₃ and Q ₄ is formed. The film 33 is formed, and the polycrystalline Si film 3 on the upper gate electrode 18 is further formed.
Remove 3.

Next, after removing the resist pattern 34, a resist pattern (not shown) having an opening in a portion corresponding to the polycrystalline silicon film 33 which becomes the drain regions of the power supply line 21 and the load transistors Q ₃ and Q _4. And using the resist pattern as a mask, p-type impurities such as boron (B) are added to the power source line 21 and the polycrystalline Si film 3 to be the drain regions of the load transistors Q ₃ and Q _4.
Ion implantation is performed at a high concentration. Next, after removing the resist pattern, a heat treatment for electrically activating the implanted impurities is performed if necessary. As a result, as shown in FIGS. 1, 2 and 3, the power supply line 21 made of the p ⁺ type polycrystalline Si film and the p ⁺ type diffusion layer 22 constituting the drain regions of the load transistors Q ₃ and Q ₄ are formed. , 23 are formed.

Next, the interlayer insulating film 2 is formed on the entire surface by the CVD method.
After forming 4, the predetermined portions of the interlayer insulating film 24 and the gate insulating film 19 are removed by etching to form contact holes C ₁₂ and C ₁₃ . Next, after forming an Al film on the entire surface by, for example, a sputtering method, the Al film is patterned into a predetermined shape by etching to form the bit lines BL, BL '.
To complete the desired stacked complete CMOS static RAM.

As described above, according to the first embodiment,
After forming the lower gate electrode 17 and the upper gate electrode 18 having a fin structure as a whole in a cross section in the channel width direction of the load transistors Q ₃ and Q _4, the lower gate electrode 17 and the upper gate electrode 17 are formed by the low pressure CVD method. 1
The fourth-layer polycrystalline Si film 33 is formed on the entire surface including the portion between
Then, the polycrystalline Si film 33 is patterned to form the channel region 20 between the lower gate electrode 17 and the upper gate electrode 18. Therefore, it is essential to solve the problem that the polycrystalline Si film forming the channel region is etched and the film thickness is reduced during etching for forming the upper gate electrode like the conventional double-sided gate electrode structure TFT. You can

The thickness of the polycrystalline Si film 33 for forming the channel region 20 is determined by the thickness of the SiO ₂ film 31 formed over the entire surface after the lower gate electrode 17 is formed. ₂ film 31 is C using TEOS
Since it can be formed by the VD method with good film thickness controllability, by controlling the film thickness of the SiO ₂ film 31, the film thickness of the polycrystalline Si film 33 is set to a desired film thickness with high accuracy. can do. Furthermore, the load transistors Q ₃ and Q ₄ are p-channel TFTs with double-sided gate electrode structure.
The load transistors Q ₃ and Q ₄ can have a large on / off ratio.

Next, a method of manufacturing a stacked complete CMOS static RAM according to the second embodiment of the present invention will be described with reference to FIGS. 1, 14 and 15. Here, FIGS. 14 and 15 are sectional views taken along the same cutting line as FIG. In the method of manufacturing a stacked complete CMOS static RAM according to the first embodiment described above, the lower gate electrode 17 and the third layer polycrystalline Si film are separately patterned to form the lower gate electrode 17 and Although the upper gate electrode 18 is formed,
In the second embodiment, these lower gate electrodes 1
7 and the upper gate electrode 18 are simultaneously formed by patterning once.

That is, in this second embodiment, as shown in FIGS. 1 and 14, after the contact holes C ₈ and C ₉ are formed in the Si ₃ N ₄ film 13 and the interlayer insulating film 12, the contact holes C ₈ and C ₉ are formed on the entire surface. A second-layer polycrystalline Si film 35 is formed, and the polycrystalline Si film 35 is doped with an n-type impurity at a high concentration to reduce the resistance. Next, after the SiO ₂ film 31 is formed on the entire surface, a predetermined portion of the SiO ₂ film 31 on the contact holes C ₈ and C ₉ is removed by etching to form the opening 31.
a is formed. Next, the third-layer polycrystalline Si film 3 is formed on the entire surface.
After forming 6, the polycrystalline Si film 36 is heavily doped with n-type impurities to reduce the resistance. After that, a resist pattern 37 having a shape corresponding to the lower gate electrode 17 and the upper gate electrode 18 is formed on the polycrystalline Si film 36.

Next, using the resist pattern 37 as a mask, the polycrystalline Si film 36, the SiO ₂ film 31 and the polycrystalline S film are formed.
The i film 35 is sequentially patterned by etching. Thereby, as shown in FIGS. 1 and 15, the lower gate electrode 17 and the upper gate electrode 18 are simultaneously formed by patterning once. Next, the resist pattern 3
After removing 7, the SiO ₂ film 31 is removed by etching. As a result, a state similar to that shown in FIG. 9 of the first embodiment is obtained. After that, the same steps as those in the first embodiment are performed,
Targeted Stacked Complete CMOS Static RA
Complete M.

As described above, according to the second embodiment,
Since the lower gate electrode 17 and the upper gate electrode 18 can be simultaneously formed by patterning once, the manufacturing process can be simplified accordingly.

Next, a method of manufacturing a stacked complete CMOS static RAM according to the third embodiment of the present invention will be described with reference to FIGS. 1 and 16-18. Here, FIGS. 16 to 18 are sectional views taken along the same cutting plane as FIG. In the method of manufacturing the stacked complete CMOS static RAM according to the first embodiment described above, during the etching for patterning the fourth-layer polycrystalline Si film 33, the third-layer multi-layer forming the upper gate electrode 18 is formed. Although the crystalline Si film may be etched and the film thickness may be reduced, the third embodiment eliminates such a fear.

That is, in the third embodiment, as shown in FIG. 16, after forming the third-layer polycrystalline Si film 36 in the same manner as shown in FIG. 14, the polycrystalline Si film 36 is further formed. A Si ₃ N ₄ film 38 is formed on top. And
A resist pattern 3 having a shape corresponding to the lower gate electrode 17 and the upper gate electrode 18 is formed on the Si ₃ N ₄ film 38.
9 is formed, and using this resist pattern 39 as a mask, the Si ₃ N ₄ film 38, the polycrystalline Si film 36, and the SiO ₂ film 31 are formed.
Then, the polycrystalline Si film 35 is sequentially patterned by etching. Thereby, as shown in FIGS. 1 and 17, the lower gate electrode 17 and the upper gate electrode 18 are simultaneously formed.

Next, after removing the resist pattern 39, the gate insulating film 1 is formed on the surfaces of the lower gate electrode 17 and the upper gate electrode 18 by a thermal oxidation method, as shown in FIG.
9 is formed. In this case, since the upper surface of the upper gate electrode 18 is covered with the Si ₃ N ₄ film 38 which is an oxidation resistant film, the upper surface of the upper gate electrode 18 is covered with the gate insulating film 1.
9 is not formed. After that, the fourth-layer polycrystalline S is formed on the entire surface.
The i film 33 is formed.

Next, the fourth-layer polycrystalline Si film 33 is patterned by etching. In this case, the upper surface of the third-layer polycrystalline Si film forming the upper gate electrode 18 is: Since the _third- layer polycrystalline Si film 33 is covered with the Si ₃ N ₄ film 38, the third-layer polycrystalline Si film forming the upper gate electrode 18 is etched during the etching of the fourth-layer polycrystalline Si film 33. Can be prevented from decreasing. After that, the same steps as in the first embodiment are carried out to complete the desired stacked complete CMOS static RAM.

Next, a method of manufacturing a stacked complete CMOS static RAM according to the fourth embodiment of the present invention will be described with reference to FIGS. 1 and 19 to 22. Here, FIGS. 19 to 22 are sectional views taken along the same cutting plane as FIG. 2. In the fourth embodiment, as shown in FIGS. 1 and 19, after forming the lower gate electrode 17 in the same manner as in the first embodiment, the gate electrodes G ₁ and G _{2 of the} driver transistors Q ₁ and Q ₂ are formed. A SiO ₂ film 31 having a predetermined shape is formed on the lower gate electrode 17 in the upper part of the.

Next, as shown in FIG. 20, after forming a third-layer polycrystalline Si film 36 on the entire surface, the polycrystalline Si film 36 is doped with an n-type impurity at a high concentration to reduce the resistance. To do.
Next, the lower gate electrode 17 is formed on the polycrystalline Si film 36.
After forming a resist pattern (not shown) having a shape corresponding to the upper gate electrode 18, the polycrystalline Si film 36 is patterned by etching using this resist pattern as a mask, and as shown in FIGS. The upper gate electrode 18 is formed. Next, after removing the SiO ₂ film 31 by etching, as shown in FIG. 22, a gate insulating film 19 is formed on the surfaces of the lower gate electrode 17 and the upper gate electrode 18 by a thermal oxidation method. In this case, the gate insulating film 19 is formed on the entire exposed surface of the lower gate electrode 17 and the upper gate electrode 18, including the inner surface of the cavity formed by removing the SiO ₂ film 31 by etching.

Next, low pressure CVD is carried out in the same manner as in the first embodiment.
A fourth-layer polycrystalline Si film is formed on the entire surface by the method. In this case, this polycrystalline Si film is also formed in the cavity between the lower gate electrode 17 and the upper gate electrode 18. Next, this polycrystalline Si film is patterned, and a necessary portion is doped with p-type impurities. As a result, the channel region 20 is formed in the cavity between the lower gate electrode 17 and the upper gate electrode 18, and the power supply line 21 and the diffusion layers 22 and 23 are formed. After that, the same process as in the first embodiment is performed to obtain the desired stacked complete CMO.
Complete an S-type static RAM.

As described above, according to the fourth embodiment,
By removing the SiO ₂ film 31 by etching, a channel region 20 is formed in the cavity formed between the lower gate electrode 17 and the upper gate electrode 18 via the gate insulating film 19.
Is formed. Therefore, when viewed in the channel length direction, the entire circumference of the channel region 20 is surrounded by the lower gate electrode 17 and the upper gate electrode 18. Therefore, in the load transistors Q ₃ and Q ₄ , channels are formed not only on the upper and lower surfaces of the channel region 20 in FIG. 22 but also on both side surfaces thereof. Therefore, as compared with the case of having a simple double-sided gate electrode structure, the load transistor Q
_Since the channel width of ₃ and Q ₄ can be increased,
The drain currents of the load transistors Q ₃ and Q ₄ when they are on can be increased by that amount, and the on / off ratio can be increased accordingly.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

[0051]

As described above, according to the present invention,
When the load transistor is composed of a TFT having a double-sided gate electrode structure, it is possible to solve the problem that the semiconductor thin film forming the channel region is etched and the film thickness is reduced when the upper gate electrode is formed.

[Brief description of drawings]

FIG. 1 is a stacked complete C according to a first embodiment of the present invention.
It is a top view which shows MOS type static RAM.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

3 is a sectional view taken along line 3-3 of FIG.

FIG. 4 is an equivalent circuit diagram of a memory cell of a complete CMOS static RAM.

FIG. 5: Stacked complete C according to the first embodiment of the present invention
FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MOS static RAM.

FIG. 6 is a stacked complete C according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MOS static RAM.

FIG. 7 is a stacked complete C according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MOS static RAM.

FIG. 8: Stacked complete C according to the first embodiment of the present invention
FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MOS static RAM.

FIG. 9: Stacked complete C according to the first embodiment of the present invention
FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MOS static RAM.

FIG. 10 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the stacked complete CMOS static RAM according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the stacked complete CMOS static RAM according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view for explaining the method of manufacturing a stacked complete CMOS static RAM according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the third embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the fourth embodiment of the present invention.

FIG. 20 is a cross sectional view for illustrating the method for manufacturing the stacked complete CMOS static RAM according to the fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the fourth embodiment of the present invention.

FIG. 22 is a cross-sectional view for explaining the method of manufacturing the stacked complete CMOS static RAM according to the fourth embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a schematic configuration of an example of a conventional stacked complete CMOS static RAM.

FIG. 24 is a sectional view showing a schematic configuration of another example of a conventional stacked complete CMOS static RAM.

FIG. 25 is a cross-sectional view for explaining a problem in the conventional method for manufacturing a stacked complete CMOS static RAM.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 4, 19 gate insulating film G ₁ , G ₂ gate electrode WL, WL ′ word line 5-11 n ⁺ type diffusion layer 12, 24 interlayer insulating film C ₁ -C ₁₃ contact hole 13, 38 Si ₃ N ₄ film 14 Ground power supply line 17 Lower gate electrode 18 Upper gate electrode 20 Channel region 21 Power supply line 22, 23 p ⁺ type diffusion layer 33, 35, 36 Polycrystalline Si film Q ₁ , Q ₂ Driver transistor Q ₃ , Q ₄ Load transistor Q ₅ , Q ₆ Access transistor BL, BL 'Bit line

Claims (2)

[Claims] 1. A memory cell is composed of a flip-flop circuit composed of a pair of first-conductivity-type channel driver transistors and a pair of second-conductivity-type channel load transistors formed of thin film transistors, and a pair of access transistors. In a semiconductor memory having a structure in which the pair of load transistors of the second conductivity type channel are stacked on the pair of driver transistors of the first conductivity type channel, the gate electrode of the load transistor is viewed in a cross section in the channel width direction. A semiconductor memory having a plurality of branch portions, wherein a channel region made of a semiconductor thin film is formed between the plurality of branch portions via a gate insulating film. 2. A memory cell is composed of a flip-flop circuit composed of a pair of driver transistors of a first conductivity type channel and a pair of load transistors of a second conductivity type channel composed of thin film transistors, and a pair of access transistors. In the method of manufacturing a semiconductor memory having a structure in which the pair of load transistors of the second conductivity type channel are stacked on the pair of driver transistors of the first conductivity type channel, the gate electrode of the load transistor is sectioned in the channel width direction. And a step of forming a channel region made of a semiconductor thin film between the plurality of branch portions of the gate electrode with a gate insulating film interposed therebetween. Manufacturing method of semiconductor memory.