JP2890797B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and is particularly suitable for application to a complete CMOS static RAM.

[Summary of the Invention]

The present invention relates to a semiconductor memory in which a memory cell is constituted by a flip-flop circuit constituted by a pair of driver transistors of a first conductivity type channel and a pair of load transistors of a second conduction type channel and a pair of access transistors. A pair of second-conductivity-type channel load transistors are formed of a semiconductor thin film so that the respective channel regions and drain regions of the pair of second-conductivity-type channel load transistors overlap with each other via a gate insulating film; and By increasing the width of each semiconductor thin film in the drain region compared to the channel region, the leakage current of the load transistor is greatly reduced, and defects due to misalignment of the semiconductor thin film forming the load transistor are reduced. Enabled to prevent it effectively Than it is.

[Conventional technology]

Thin film transistor (TFT) on driver transistor
In recent years, a stacked complete CMOS static RAM having a structure in which load transistors composed of stacked layers are stacked has been attracting attention because of its low power consumption, good data retention characteristics, and high integration by stacking.

As this stacked complete CMOS type static RAM,
A structure in which a load transistor composed of a TFT is stacked on the gate electrode of a driver transistor by sharing this gate electrode has been proposed (Nikkei Micro Devices, 19
September 88, pp.123-130).

On the other hand, a stacked complete CMOS static RAM in which the gate length of the load transistor is made larger than the channel length of the driver transistor by separately forming the gate electrode of the driver transistor and the gate electrode of the load transistor composed of TFT has also been proposed. Yes (IEDM, 1
988, pp. 48-59).

Note that the present inventor has disclosed in Japanese Patent Application No. 2-40666 that the pair of load transistors constituting a memory cell may overlap with each other via a gate insulating film so that the channel region and the drain region of the pair of load transistors overlap each other. Complete CMOS Type Static Formed with Semiconductor Thin Film
RAM is proposed.

[Problems to be solved by the invention]

TFT on driver transistor sharing gate electrode
In the above-mentioned conventional stacked complete CMOS type static RAM having a structure in which load transistors consisting of
Although the load transistor has an offset gate structure to suppress the leak current of the load transistor, the reduction of the leak current is not always sufficient.

On the other hand, in the above-described conventional stacked complete CMOS type static RAM in which the gate electrode of the driver transistor and the gate electrode of the load transistor are separately formed to increase the channel length of the load transistor, the necessary for reducing the leakage current. It is difficult to secure a channel length of 1.5 μm or more.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory capable of greatly reducing the leak current of a load transistor by increasing the channel length of a load transistor formed of a TFT.

Another object of the present invention is to provide a semiconductor memory capable of preventing a failure due to misalignment between semiconductor thin films forming a load transistor.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a pair of first
Driver transistor (Q ₁ , Q ₂ ) of the conduction type channel and a pair of load transistors (Q ₃ , Q ₄ ) of the second conduction type channel
In a semiconductor memory in which a memory cell is constituted by a flip-flop circuit constituted by the above and a pair of access transistors (Q ₅ , Q ₆ ), a load transistor (Q ₃ , Q ₄ ) of a pair of second conductivity type channels is provided. A pair of second-conductivity-type channel load transistors (Q ₃ , Q ₄ ) are arranged so that the respective channel regions (19, 22) and the drain regions (20, 23) overlap with each other via the gate insulating film (21). A drain region (20, 23) formed of a semiconductor thin film and having a width of each semiconductor thin film as compared with a channel region (19, 22) portion;
It is larger in the part.

In one embodiment of the present invention, the source regions of the pair of load transistors (Q ₃ , Q ₄ ) of the second conductivity type channel are connected to a power supply line (18) which is drawn out in opposite directions to sandwich the memory cell. Connected respectively.

[Action]

According to the semiconductor memory of the present invention configured as described above, each channel region (19, 22) and drain region (20, 23) of the pair of load transistors (Q ₃ , Q ₄ ) of the second conductivity type channel. ) Are formed of a semiconductor thin film such that the load transistors (Q ₃ , Q ₄ ) of the second conductivity type channel overlap with each other via the gate insulating film (21). The region becomes the gate electrode of the other load transistor as it is. For this reason, the gate length of the load transistors (Q ₃ , Q ₄ ), and thus the channel length, can be made sufficiently large, and the leakage current of the load transistors (Q ₃ , Q ₄ ) can be greatly reduced. .

In addition, the width of each semiconductor thin film is set in the channel region (1
Since the drain region (20, 23) is larger than that of the (9, 22) part, the gate electrode formed on the upper semiconductor thin film is completely formed on the channel region formed on the lower semiconductor thin film. For example, the load transistor (Q ₃ , Q ₄ ) may not be mounted, or the channel region formed in the upper semiconductor thin film may not completely ride on the gate electrode formed in the lower semiconductor thin film. Failure due to misalignment can be effectively prevented.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

First, the configuration of a memory cell of a complete CMOS static RAM will be described.

As shown in FIG. 3, the memory cell of the complete CMOS static RAM includes a flip-flop circuit including a pair of driver transistors Q ₁ and Q ₂ and a pair of load transistors Q ₃ and Q _4, and a memory cell outside the cell. And a pair of access transistors Q ₅ and Q ₆ for exchanging the data. WL indicates a word line, and BL and BL indicate bit lines. V _DD and V _SS represent power supplies.

FIG. 4 conceptually shows a configuration of a memory cell of a stacked complete CMOS type static RAM according to this embodiment, particularly, a load transistor portion. FIG. 5 is a sectional view taken along line VV in FIG.

4 and 5, reference numeral 101 denotes a semiconductor substrate, 1
02 power supply line of the power supply voltage V _DD for supplying, 103, for example n-type channel region of the load transistor Q _4, 104 denotes a drain region, for example p ⁺ -type load transistor Q _4. Here, the drain region 104 also serves as a gate electrode of the load transistor Q _3. Reference numeral 106, for example n-type channel region of the load transistor Q _3, 107 denotes a drain region, for example p ⁺ -type load transistor Q _3. Here, the drain region 107 also serves as a gate electrode of the load transistor Q _4.

As shown in FIGS. 4 and 5, in this embodiment, the drain region 107 used as a gate electrode of the load transistor Q ₄ are, off completely covers the channel region 103 of the load transistor Q _4. Also, load transistor Q ₃
The channel region 106 rests entirely on the drain region 104 used as a gate electrode of the load transistor Q _3.

Next, a specific structure of the stacked complete CMOS type static RAM according to this embodiment will be described.

FIG. 1 is a plan view of a stacked complete CMOS type static RAM according to this embodiment, and FIG. 2 is a sectional view taken along the line II-II of FIG.

As shown in FIGS. 1 and 2, in a stacked complete CMOS static RAM according to this embodiment, a field such as a SiO ₂ film is formed on the surface of a semiconductor substrate 1 such as a p-type silicon (Si) substrate. The insulating film 2 is selectively formed, thereby separating elements. Below this field insulating film 2, for example, ap ⁺ type channel stop region 3 is formed. On the surface of the active region surrounded by the field insulating film 2, a gate insulating film 4 such as a SiO ₂ film is formed.

G ₁ and G ₂ indicate gate electrodes of the driver transistors Q ₁ and Q ₂ , respectively, and WL and WL ′ indicate word lines. These gate electrodes G
₁ , G ₂ and word lines WL, WL 'are, for example, n ⁺ -type first doped with n-type impurities such as phosphorus (P) at a high concentration.
It is formed of a polycrystalline Si film as a layer or a polycide film in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is laminated on the n ⁺ type first polycrystalline Si film. You.

On the other hand, in the active region surrounded by the field insulating film 2, for example, n ⁺
Diffusion layers 5 to 11 are formed. By the gate electrode G ₁ and the diffusion layers 5 and 6, the driver transistor Q ₁ of n-channel MOS transistor is formed. Similarly, the gate electrode G ₂ and the diffusion layers 7 and 8 make the n-channel M
Driver transistor Q ₂ to which consisting OS transistor is formed. Also, the word line WL and the diffusion layers 6 and 9
Access transistor Q ₅ of n-channel MOS transistor is formed by the word line WL and the diffusion layers 10 and 11, the access transistor Q ₆ of n-channel MOS transistor is formed.

In this case, sidewall spacers 12 made of, for example, SiO ₂ are formed on the side walls of the gate electrodes G ₁ and G ₂ and the word lines WL and WL ′. In the diffusion layers 5 to 11, for example, an n ⁻ -type low impurity concentration portion a is formed below the side wall spacer 12. Therefore, the driver transistors Q ₁ and Q ₂ and the access transistors Q ₅ and Q ₆
(Lightly doped drain) structure.

C ₁ -C ₃ shows the contact holes for buried contact (buried contact). One end of the gate electrode G ₁ of the driver transistor Q ₁ is provided in contact with the diffusion layer 7 of the driver transistor Q ₂ through a contact hole C _1, the other end diffusion layers of the access transistor Q ₆ through the contact hole C ₂ 10 Contact. The gate electrode G ₂ of the driver transistor Q ₂ is, it is put in contact with the diffusion layer 6 of the driver transistor Q ₁ and the access transistor Q ₅ through the contact hole C _3.

Reference numeral 13 denotes, for example, a phosphor silicate glass (PSG) film or SiO
₂ shows an interlayer insulating film such as _two films. C ₄ and C ₅ indicate contact holes for buried contacts formed in the interlayer insulating film 13. Reference numeral 14 denotes a ground power supply line of the power supply voltage V _SS for supplying. The ground power supply line 14 is, for example, n
For example, an n ⁺ -type second-layer polycrystalline Si film doped with high-concentration type impurities, or a polycide in which a high-melting-point metal silicide film is stacked on this n ⁺ -type second-layer polycrystalline Si film It is formed by a film or the like. This ground power line 14 is
Together are in contact with the diffusion layer 5 of the driver transistor Q ₁ through C _4, it is put in contact with the diffusion layer 8 of the driver transistor Q ₂ through a contact hole C _5.

Reference numerals 15 and 16 indicate relay wiring. These relay wirings 15, 16
Similarly to the ground electrode line 14, for example, an n ⁺ -type second-layer polycrystalline Si film doped with an n-type impurity such as P at a high concentration, or an n ⁺ -type second-layer And a polycide film in which a refractory metal silicide film is overlaid on the polycrystalline Si film. Here, the relay wiring 15 is connected to the access transistor Q ₅ through the contact hole C ₆ for the buried contact.
In contact with the diffusion layer 9. Also, the relay wiring 16
It is put in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C ₇ for buried contact.

Reference numeral 17 indicates an interlayer insulating film such as a PSG film or a SiO ₂ film. Reference numeral 18 denotes a power supply line for supplying the power supply voltage _VDD . The power supply line 18 is formed of, for example, a p ⁺ -type third polycrystalline Si film and a fourth polycrystalline Si film in which a p-type impurity such as boron (B) is highly doped. Is done.

Reference numeral 19, for example n-type channel region of the load transistor Q _4, 20 denotes a drain region, for example p ⁺ -type load transistor Q _4. Here, the drain region 20, also serves as a gate electrode of the load transistor Q _3. These channel regions
The 19 and the drain region 20 are formed of, for example, a third layer polycrystalline Si film.

Reference numeral 21 indicates a gate insulating film such as a SiO ₂ film.
Reference numeral 22 denotes an n-type channel region of the load transistor Q _3, 23 denotes a drain region, for example p ⁺ -type load transistor Q _3. Here, the drain region 23, also serves as a gate electrode of the load transistor Q _4. These channel regions 22
The drain region 23 is formed of, for example, a fourth-layer polycrystalline Si film.

In this embodiment, third layer polycrystalline Si film for forming the load transistor Q ₄ are, the width at the portion of the drain region 20 than the portion of the channel region 19 is large. The drain region 23 which is used as a gate electrode of the load transistor Q ₄ are, it covers the channel region 19 completely. On the other hand, the fourth layer polycrystalline Si film for forming the load transistor Q ₃ are the width in the portion of the drain region 23 than the portion of the channel region 22 is large. The channel region 22 of the load transistor Q ₃ are the load transistor
On the drain region 20 to be used as the gate electrode of Q ₃ ride completely. Further, a drain region 20 used as the gate electrode of the load transistor Q _3, overlap each other at one end and the drain region 23 to be used as the gate electrode of the load transistor Q _4.

C ₈ and C ₉ indicate contact holes for buried contacts formed in the interlayer insulating films 13 and 17. The drain region 20 which is also the gate electrode of the load transistor Q ₃ are put in contact with the gate electrode G ₁ of the driver transistor Q ₁ through a contact hole C _8. The drain region 23 which is also the gate electrode of the load transistor Q ₄ are, is put in contact with the gate electrode G ₂ of the driver transistor Q ₂ through a contact hole C _9.

Reference numeral 24 indicates an interlayer insulating film such as a PSG film.
C _10, C ₁₁ represents a contact hole formed in the interlayer insulating film 24 and the interlayer insulating film 17. Here, the contact hole C ₁₀ is formed on the access transistor Q _5. Further, the contact hole C ₁₁ is formed on the access transistor of the memory cell adjacent using word line WL '. Then, for example, aluminum through a contact hole C ₁₀ (Al) bit lines BL formed by the wiring is in contact with the relay wiring 15. As already mentioned, since the relay wiring 15 is in contact with the diffusion layer 9 of the access transistor Q ₅ through the contact hole C _6, the bit lines BL diffusion layers of the access transistor Q ₅ through the relay wiring 15 9 Connected. Similarly, the bit line BL is in contact with the relay wiring 16 through a contact hole C _11, since the relay wiring 16 is in contact with the diffusion layer 11 of the access transistor Q ₆ through the contact hole C _7, the bit line BL is connected to the diffusion layer 11 of the access transistor Q ₆ through the relay wiring 16.
Connected. Note that these bit lines
BL, BL extend in a direction perpendicular to the word line WL.

Next, an example of a method of manufacturing the stacked complete CMOS type static RAM according to this embodiment configured as described above will be described.

As shown in FIGS. 1 and 2, first, the surface of a semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 2 to perform element isolation. At this time, a p-type impurity such as B, which has been ion-implanted in the semiconductor substrate 1 in advance, diffuses, and a p ⁺ -type channel stop region 3 is formed below the field insulating film 2. . Next, a gate insulating film 4 is formed on the surface of the active region surrounded by the field insulating film 2 by a thermal oxidation method. next,
A predetermined portion of the gate insulating film 4 and the field insulating film 2 is removed by etching to form contact holes C ₁ -C _3.

Next, for example, the first layer of polycrystalline Si
After forming a film, the polycrystalline Si film is doped with an impurity such as P at a high concentration by a thermal diffusion method or an ion implantation method to reduce the resistance, and then the polycrystalline Si film is formed into a predetermined shape by etching. By patterning, gate electrodes G ₁ and G ₂ and word lines WL and WL ′ are formed. Next, these gate electrodes G ₁ ,
G ₂ and the word lines WL, WL 'and the n-type impurity, such as in the semiconductor substrate 1 such as P is ion-implanted at a low concentration as a mask. Next, after forming, for example, an SiO ₂ film on the entire surface by the CVD method, this SiO ₂ film is subjected to, for example, reactive ion etching (RI
The sidewall spacers 12 are formed on the side walls of the gate electrodes G ₁ , G ₂ and the word lines WL, WL ′ by etching in a direction perpendicular to the substrate surface by the method E).

Next, the side wall spacer 12, the gate electrode
Semiconductor substrate 1 using G ₁ , G ₂ and word lines WL, WL ′ as masks
An n-type impurity such as arsenic (As) is ion-implanted therein at a high concentration. Thereafter, a heat treatment for electrically activating the implanted impurities is performed. As a result, diffusion layers 5 to 11 having the low impurity concentration portions a are formed below the sidewall spacers 12.

Next, after an interlayer insulating film 13 is formed on the entire surface by the CVD method, predetermined portions of the interlayer insulating film 13 are removed by etching to form contact holes C ₄ , C ₅ , C ₆ , and C ₇ .

Next, a second-layer polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is doped with an impurity such as P at a high concentration to reduce the resistance. The film is patterned into a predetermined shape by etching and the ground power line 14
Then, the relay wirings 15 and 16 are formed.

Next, after an interlayer insulating film 17 is formed on the entire surface by the CVD method, predetermined portions of the interlayer insulating film 17 and the interlayer insulating film 13 are removed by etching to form contact holes C ₈ and C ₉ .
Next, a third-layer polycrystalline Si film is formed on the entire surface by the CVD method, and this polycrystalline Si film is doped with an n-type impurity such as P at a low concentration. covering the surface of the portion to be the channel region 19 of the load transistor Q ₄ after, for example, a resist pattern (not shown), a p-type impurity, such as a polycrystalline Si film using the resist pattern as a mask such as B Ion implantation at high concentration. After that, the resist pattern is removed. Next, the third-layer polycrystalline Si film is patterned into a predetermined shape by etching to form a wiring 18 for supplying a power supply voltage V _DD , an n-type channel region 19 and a p ⁺ -type drain region 20. .

Next, the gate insulating film 21 is formed on the entire surface by, for example, a CVD method. The gate insulating film 21 can be formed by, for example, a thermal oxidation method. Next, a fourth-layer polycrystalline Si film is formed on the entire surface by a CVD method, and this polycrystalline Si film is doped with an n-type impurity such as P at a low concentration. After the load transistor Q ₃
Is covered with, for example, a resist pattern (not shown), and a p-type impurity such as B is ion-implanted into the polycrystalline Si film at a high concentration using the resist pattern as a mask. After that, the resist pattern is removed. Next, the fourth polycrystalline Si film is patterned into a predetermined shape by etching,
A wiring 18 for supplying _VDD , an n-type channel region 22 and ap ⁺ -type drain region 23 are formed.

Next, after an interlayer insulating film 24 is formed on the entire surface by the CVD method, predetermined portions of the interlayer insulating film 24 and the interlayer insulating film 17 are removed by etching to form contact holes C ₁₀ and C ₁₁ .

Next, after an Al film is formed on the entire surface by, for example, a sputtering method, the Al film is patterned into a predetermined shape by etching to form bit lines BL, BL, thereby completing the intended stacked complete CMOS static RAM.

As described above, according to this embodiment, the p-channel TFT
Since the load transistors and Q _3, Q ₄ of the channel region 19 and 22 and the drain region 20, 23 has a structure in which overlap with each other via the gate insulating film 21 made of, as in the prior art of the load transistors Q ₃ , as compared with the case of arranging side by side Q ₄ in plan view, the channel length of the load transistors Q _3, Q ₄ can be sufficiently large.

Specifically, for example, these load transistors Q ₃ , Q
₄ of the channel length, can be a driver transistor Q _3, 4 or more times the channel length of Q ₄ of n-channel MOS transistor. For example, driver transistors Q ₃ , Q
Assuming that the channel length of ₄ is 0.5 μm, the channel length of load transistors Q ₃ and Q ₄ can be 2 μm or more. As a result, it is possible to significantly reduce the leak current of these load transistors Q ₃ and Q ₄ . For example,
The polycrystalline Si film forming these load transistors Q ₃ and Q ₄ has a thickness of 500 mm, a channel width of 10 μm, and a channel length of 2 μm.
３3 μm, these load transistors Q ₃ , Q ₄
Can be reduced to about 10 ⁻¹¹ A. However, the gate voltage is 0 V and the drain voltage is −4 V.

Further, since the width of the drain regions 20 and 23 is wider than that of the channel regions 19 and 22, the third polycrystalline Si film and the fourth polycrystalline Si film forming the load transistors Q ₃ and Q ₄ are formed. A defect due to misalignment between films can be effectively prevented.

Further, since the drain regions 20 and 23 used as the gate electrodes of the load transistors Q ₃ and Q ₄ overlap each other, it is possible to improve the soft error resistance by the capacity of the overlapping portion.

Although the embodiments of the present invention have been specifically described above,
The invention is not limited to the embodiments described above,
Various modifications based on the technical concept of the present invention are possible.

For example, in the above embodiment, the case where the driver transistors Q ₁ , Q ₂ and the access transistors Q ₅ , Q ₆ have the LDD structure has been described, but these driver transistors Q ₁ , Q ₂ and the access transistor Q ₅ , Q ₆ is necessarily that there is no need to be the LDD structure is needless to say.

〔The invention's effect〕

As described above, according to the present invention, the pair of second conductivity type channels are arranged such that the respective channel regions and drain regions of the pair of second conductivity type load transistors overlap with each other via the gate insulating film. Since the load transistors are formed of semiconductor thin films, and the width of each semiconductor thin film is larger in the drain region than in the channel region, the leakage current of the load transistor can be significantly reduced. In addition, it is possible to effectively prevent a defect due to misalignment between the semiconductor thin films forming the load transistor.

[Brief description of the drawings]

FIG. 1 shows a stacked complete CMOS according to an embodiment of the present invention.
Plan view showing a type static RAM, FIG. 2 is II in FIG.
FIG. 3 is a circuit diagram showing an equivalent circuit of a memory cell of a complete CMOS static RAM, and FIG. 4 is a memory cell of a stacked complete CMOS static RAM according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line VV in FIG. Description of the key symbols in drawings 1: semiconductor substrate, 2: a field insulating film, G _1, G _2: gate electrode, WL, WL ': the word line, 5 to 11: diffusion layer, C ₁ -C _11: contact hole , 13, 17, 24: interlayer insulating film, 14: ground power line,
15, 16: relay wiring, 18: power supply line, 19, 22: channel area, 21:
A gate insulating film, 20, 23: drain region, Q _1, Q _2: driver transistor, Q _3, Q _4: load transistor, Q _5, Q _6: access transistor, BL, BL: Bit line.

Claims (1)

(57) [Claims] 1. A semiconductor memory in which a memory cell is constituted by a flip-flop circuit constituted by a pair of driver transistors of a first conductivity type channel and a pair of load transistors of a second conduction type channel and a pair of access transistors. A pair of second-conductivity-type channel load transistors are formed of a semiconductor thin film such that respective channel regions and drain regions of the pair of second-conductivity-type channel load transistors overlap with each other via a gate insulating film;
A semiconductor memory, wherein the width of each of the semiconductor thin films is larger in the drain region than in the channel region.