JPH043983A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve write characteristics and punch-through voltage while preventing the decrease in breakdown voltage by isolating a semiconductor region from the heavily doped area of a drain region. CONSTITUTION:An impurity introduced is diffused and electrically activated by annealing. As a result, lightly doped areas 6a, 6b, 7a, and 7b are formed under a side wall spacer 4, and a p-type semiconductor region 8 is formed between the lightly doped areas 6b and 7b and a p-type silicon substrate. The p-type semiconductor region 8, between the lightly doped areas 7b in a drain region and the p-type silicon substrate, is not directly in contract with the heavily doped areas in the drain region. If the impurity concentration in the p-type semiconductor region is increased, therefore, it is possible to prevent the decrease in the breakdown voltage between the semiconductor region 8 and the heavily doped areas in drain region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory having a floating gate type memory transistor.

[Summary of the invention]

The present invention has a floating gate type memory transistor, and a drain region of a second conductivity type of the memory transistor formed in a semiconductor substrate of a first conductivity type is composed of a high impurity concentration region and a low impurity concentration region. In a nonvolatile semiconductor memory in which a semiconductor region of a first conductivity type is formed between a low impurity concentration portion of a drain region and a semiconductor substrate, the semiconductor region is not in contact with a high impurity concentration portion of the drain region. This makes it possible to improve write characteristics and punch-through voltage while preventing a decrease in breakdown voltage.

[Conventional technology]

EFROM (elect) with a design rule of 1.0 μm or less
rically programmable and
Read 0nly Memory), write characteristics, soft write resistance, and GIS L (Gate I
unduced 5ubbreakdoTsn Leak
age) In order to satisfy the tolerance, so-called PLD (Profiled Light) as shown in Fig. 4 is used.
There is a tendency to use memory transistors of the tly Doped Drain type. As shown in FIG. 4, in this PLD type EFROM, a floating gate FC' is formed on, for example, a p-type silicon (St) substrate 101 via a gate insulating film 102, and a floating gate FC' is formed on a p-type silicon (St) substrate 101 via a gate insulating film 102. Control gates CG' are stacked. Reference numeral 104 indicates these floating gates FG.
A sidewall spacer 105 formed on the sidewalls of ' and control gate CG' indicates an insulating film. on the other hand,
In the P-type Si substrate 1, for example, an n-type source region 106 and a drain region 107 are formed in self-alignment with the floating gate FG' and the control gate CG'. These source regions 106 and drain regions 107 are provided with sidewall spacers 1.
For example, an n-type low impurity concentration region 106 in the lower part of 04.
a, 107a and, for example, an n-type low impurity concentration portion 106
b, 107b are formed. Between these low impurity concentration portions 106b, 107b and the p-type St substrate 101, for example, a p-type semiconductor region (p-bokeh) 10B is formed, respectively. In this case, this p-type semiconductor region 108 is in contact with the high impurity concentration portions of the source region 106 and drain region 107, respectively.

Such a PLD type EFROM is manufactured by the method shown in FIGS. 5A and 5B. That is,
As shown in FIG. 5A, first, a gate insulating film 102, a floating gate FG', an insulating film 103, and a control gate CG' are formed on a p-type Si substrate 101.
Using these as a mask, arsenic (As) is first ion-implanted into the p-type Si substrate 101 in a direction almost perpendicular to the substrate surface, followed by phosphorus (P) ion implantation, and then boron (B) ion implantation. do. As a result, a region 109 where As and P are ion-implanted at a low concentration, a region 110 where a P is ion-implanted at a low concentration, and a region 111 where a B is ion-implanted are connected to the floating gate FG'' and the control gate CG'. is formed in a self-consistent manner.

Next, as shown in FIG. 5B, after forming a sidewall spacer 104 and an insulating film 105, a p-type Si
For example, As ions are implanted at a high concentration into the substrate 101 from a direction substantially perpendicular to the substrate surface. By this, A
A region 111 into which s is ion-implanted at a high concentration is formed in a self-aligned manner with respect to the sidewall spacer 104.

Thereafter, annealing is performed for diffusion of implanted impurities and electrical activation. As a result, the desired PLD type EPROM is completed as shown in FIG.

[Problem to be solved by the invention]

In the conventional PLD type EPROM shown in FIG. When the impurity concentration of the region 108 is increased, breakdown is likely to occur between the p-type semiconductor region 108 and the high impurity concentration portion of the drain region 107 (and the breakdown voltage is lowered. This can be prevented. Therefore, this p-type semiconductor region 10
If the impurity concentration of the p-type semiconductor region 10 is kept low, it becomes difficult to improve the punch-through breakdown voltage.
Setting the impurity concentration of No. 8 was difficult.

Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory that can improve write characteristics and punch-through voltage while preventing a decrease in breakdown voltage.

[Means to solve the problem]

In order to achieve the above object, the present invention has a floating gate type memory transistor and has a second conductivity type drain region (7) of the memory transistor formed in a first conductivity type semiconductor substrate (1). ) consists of a high impurity concentration part and a low impurity concentration part (7a, 7b), and a first conductivity type is formed between the low impurity concentration part (7a, 7b) of the drain region (7) and the semiconductor substrate (1). In a nonvolatile semiconductor memory in which a semiconductor region (8) is formed, the semiconductor region (8) is not in contact with the high impurity concentration portion of the drain region (7).

[Effect]

According to the nonvolatile semiconductor memory of the present invention configured as described above, the semiconductor region (8) is not in contact with the high impurity concentration portion of the drain region (7).
Even if the impurity concentration of the semiconductor region (8) and the drain region (7) are increased, breakdown is unlikely to occur between the semiconductor region (8) and the high impurity concentration portion of the drain region (7). As a result, the semiconductor region (8)
By increasing the impurity concentration of the semiconductor region (8), it is possible to improve the write characteristics and the punch-through breakdown voltage while preventing a decrease in the breakdown voltage between the semiconductor region (8) and the high impurity concentration portion of the drain region (7). can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a PLD type EPROM according to an embodiment of the present invention.

As shown in FIG. 1, in this embodiment, for example, p
A gate insulating film 2, such as a 5iOz film, is formed on the surface of an active region surrounded by a field insulating film (not shown) for isolation between elements selectively formed on the surface of a type of Si substrate 1. There is. A floating gate FG is formed on this gate insulating film 2. This floating gate FC can be formed of a polycrystalline Si film doped with an impurity such as P, for example. A control gate CG is laminated on the floating gate FC via an insulating film (coupling insulating film) 3 such as a 5in2 film, for example. This control gate CG is formed by overlaying a polycrystalline St film doped with an impurity such as P, or a refractory metal silicide film such as a tungsten silicide (WSiz) film on a polycrystalline St peritoneum doped with this impurity. It can be formed using a polycide film or the like. Sidewall spacers 4 made of, for example, SiO□ are formed on the sidewalls of these floating gates FG and control gates CG. Reference numeral 5 indicates an insulating film such as a SiO□ film.

On the other hand, there is a floating gate F in the P-type Si substrate 1.
For example, an n-type source region 6 and drain region 7 are formed in self-alignment with respect to C and control gate CG. In these source regions 6 and drain regions 7, for example, n
Type low impurity concentration portions 6a, 7a and, for example, n-type low impurity concentration portions 6b, 7b are formed. These n-
For example, a p-type semiconductor region (p pocket) 8 is formed between the low impurity concentration portions 6b, 7b of the mold and the p-type Si substrate 1. In this case, this p-type semiconductor region 8 is not in direct contact with the high impurity concentration portion of the drain region 7.

Therefore, breakdown is less likely to occur between the p-type semiconductor region 8 and the high impurity concentration portion of the drain region 7. Note that the p-type semiconductor region 8 on the source region 6 side
can be omitted.

Next, the PLD according to this embodiment configured as described above
A method for manufacturing type EPROM will be explained.

As shown in FIG. 2A, first, a gate insulating film 2 is formed by thermal oxidation on the surface of an active region surrounded by a field insulating film (not shown) formed on the surface of a p-type St substrate 1. A first layer of polycrystalline Si film is formed on the entire surface by the CVD method, and this polycrystalline Si film is doped with an impurity such as P to lower the resistance. Next, an insulating film 3 is formed on this polycrystalline Si film by, for example, a thermal oxidation method. Next, a second layer of polycrystalline Si film is formed on the entire surface of this insulating film 3 by the CVD method, and then this polycrystalline Si film is doped with an impurity such as P to lower its resistance. Next, these second layer polycrystalline Si film, insulating film 3, third layer polycrystalline St film, and gate insulating film 2 are etched by, for example, reactive ion etching (
Etching is performed in a direction perpendicular to the substrate surface using the RIE method. Thereby, the floating gate f-FG and the control gate CG are formed in a self-aligned manner. In addition,
When the control gate CG is formed of a polycide film, etching may be performed in the same manner as described above after further forming a high melting point metal silicide film on the second layer polycrystalline Si film. Next, these control gates CG
and p-type Si using the floating gate FC as a mask.
For example, As ions are first implanted into the substrate 1 in a direction substantially perpendicular to the substrate surface at a low concentration, and then, for example, P ions are implanted at a low concentration. As a result, the region 9 into which ions of ^S and P are ion-implanted at a low concentration, and the region 10 into which ions into which P are ion-implanted at a low concentration are connected to the control gate C.
G and floating gate FG in a self-aligned manner.

Next, as shown in FIG. 2B, ions of, for example, B are obliquely implanted into the p-type St substrate l from a direction inclined by, for example, 30 to 60 degrees with respect to the substrate surface. This oblique ion implantation is usually performed while rotating the substrate with respect to the ion beam in order to improve the uniformity of the implanted amount. As a result, by this oblique ion implantation, regions 11 in which B ions are implanted are formed in the P-type Si substrate 1 in the lower portions of both ends of the floating gate FC.

Next, a 5iOz film, for example, is formed on the entire surface by CVD, and then this 5iOz film is etched in a direction perpendicular to the substrate surface by, for example, RIE. As a result, Fig. 2C
As shown in FIG. 2, sidewall spacers 4 are formed on the side walls of the floating gate FC and control gate CG. Next, an insulating film 5 is formed on the upper surface of the control gate CG and the surface of the p-type Si substrate 1 by, for example, thermal oxidation.
form. Next, these side wall spacers 4
Using the control gate CG and floating gate FG as masks, ions of, for example, As are implanted into the p-type Si substrate 1 at a high concentration from a direction substantially perpendicular to the substrate surface. As a result, a region 12 in which As is ion-implanted at a high concentration is formed in a self-aligned manner with respect to the sidewall spacer 4.

After that, annealing is performed for diffusion of the implanted impurity and electrical activation. As a result, as shown in FIG. 7b is formed, and a p-type semiconductor region 8 is formed between these low impurity concentration parts 6b, 7b and the p-type Si substrate 1.
is completed. In this case, this p-type semiconductor region 8 is
This p-type semiconductor region 8 is formed by shallowly forming a region 11 in which B is ion-implanted under both ends of the floating gate FG by diagonal B ion implantation. It is possible to have a structure that does not contact the high impurity concentration portion of the region 7.

As described above, according to this embodiment, the p-type semiconductor region 8 formed between the low impurity concentration portion 7b of the drain region 7 and the p-type Si substrate 1 is the high impurity concentration portion of the drain region 7. This p-type semiconductor region 8
Even if the impurity concentration is increased, the breakdown voltage between the p-type semiconductor region 8 and the high impurity concentration portion of the drain region 7 can be prevented from decreasing. That is, according to this embodiment, the p-type semiconductor region 8 and the drain region 7
By increasing the impurity concentration of this p-type semiconductor region 8, it is possible to improve the write characteristics and punch-through breakdown voltage while preventing a decrease in the breakdown breakdown voltage between the p-type semiconductor region 8 and the high impurity concentration portion.

By the way, when reducing the design rule in order to increase the integration of MO3IC that uses two types of power supply voltages (for example, +a = 5V and Vpp = 12°5V) such as EFROM, it is necessary to The problem is the thickness of the gate insulating film. In other words, due to its reliability, the strength of the electric field applied to the gate insulating film is 4MV/CI.
It is desirable to use it under conditions where the temperature is below 0. Therefore, for example, the thickness of the gate insulating film of a 5-inch type MOS transistor can be reduced by about 150 mm.
The thickness of the gate insulating film of a 2.5 V type MOS transistor can only be reduced by about 350 volts.As a result, MOS transistors using two types of power supply voltages
In this case, two types of gate insulating films having different thicknesses coexist. However, in this case, since the gate capacitance per unit area of the gate insulating film is different,
In order to obtain the same threshold voltage in MOS transistors whose gate insulating films have different thicknesses, these MOS
) It is necessary to change the impurity concentration in the channel region of the transistor. This means that the steps for adjusting the threshold voltage of the MOS transistor are doubled, resulting in an increase in the number of steps.

Next, a method for solving such problems will be explained.

Figure 3 shows an example of an EPROM that uses two types of power supply voltage.
This shows a MOSIC like . In FIG. 3, Ql represents, for example, a 5V type MOS) transistor, and Q2 represents, for example, a 12.5V type MOS) transistor. In this example, for example, SiO2 is deposited on the surface of the p-type Si substrate 21.
A field insulating film 22 like a □ film is formed to provide isolation between elements. A p-type channel stop region 23, for example, is formed under the field insulating film 22. For example, a gate insulating film 24 is formed on the surface of an active region surrounded by a field insulating film 22 in a portion of a 5V MOS transistor Q. Also, for example, 12.5V MO3I-ransistor Q
A gate insulating film 25 is formed on the surface of the active region surrounded by the field insulating film 22 at the portion 2 .

A gate electrode G1 is formed on the gate insulating film 24. Then, this gate electrode G, and the p-type Si substrate 1
For example, an n-type source region 26 and a drain region 27 are formed in the gate electrode G in a self-aligned manner with respect to the gate electrode G.
For example, a 5V type MOS transistor Q1 is formed. - On the other hand, a gate electrode G2 is formed on the gate insulating film 25. And this gate electrode G2
For example, an n° type source region 28 and a drain region 29 formed in the p type Si substrate 1 in a self-aligned manner with respect to the gate electrode G2 generate a voltage of, for example, 12°5V system.
OS) A transistor Q2 is formed.

In this example, the gate insulator M24 of, for example, a 5-type MOS transistor Q is formed of a 5iOz film. On the other hand, for example, a 12°5V MOS)
The gate insulating film 25 of the transistor Q2 is composed of a 5iCh film and an S
Composite film with is Na film, e.g. Si0g film and S
ON (OxideNitrid)
e) ONO (Oxide-Nitride-Ox
ide) is formed by a film.

For example, when the gate insulating film 24 of the 5V type MOS transistor Q1 is a SiO□ film with a thickness of 200, for example, when an ON film is used as the gate insulating film 25 of the 12.5V type MOS transistor Q2, for example, The thicknesses of the SiO□ film and the Si3N4 film of this ON film are 50 and 300, respectively.

In this case, since the dielectric constant of the Si, N4 film is about twice that of the SiO□ film, the conversion value of the ON film in terms of the SiO□ film is 0. Therefore, for example, a 5V system MOS) transistor Q1 and, for example, a 12.5V system MOS transistor Q
The gate capacitance per unit area is the same as that of 2. Therefore, even if the impurity concentrations of the channel regions of these MOS transistors Q, , Q, are the same, these MO3I
-Thresholds of transistors Q, , Q (direct voltages can be made the same. This makes it possible to simplify the manufacturing process.

Note that when an ONO film is used as the gate insulating film 25 of the MOS transistor Q2, the SiO□ of this ONO film is
Membrane equivalent planting value S transistor Q.

The thickness may be the same as that of the gate insulating film 24 made of SiO.

In addition, the above is, for example, a 5V MOS) transistor Q1.
For example, this is an example of a MOSIC in which a 12.5V type MOS) transistor Q2 is mixed, but it is a MOS in which two or more types of MOS) transistors that use different power supply voltages are mixed.
A similar approach can be applied to ICs.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, when performing oblique ion implantation of B in the process shown in FIG. 2, the substrate is rotated with respect to the ion beam, so the floating gate F
B ion implantation regions 11 are formed in the lower parts of both ends of G, but by performing oblique B ion implantation while fixing the tilt angle of the substrate with respect to the ion beam,
It is also possible to form this B ion implantation region 11 only in the lower part of the end of the floating gate FG of the seven drain regions. In this case, as a result, p-type semiconductor region 7 is formed only on the drain region 7 side.

〔Effect of the invention〕

As explained above, according to the present invention, the semiconductor region of the second conductivity type formed between the low impurity concentration portion of the drain region and the semiconductor substrate is not in contact with the high impurity concentration portion of the drain region. Even if the impurity concentration of this semiconductor region is increased, it is possible to prevent the breakdown voltage from decreasing between this semiconductor region and the high impurity concentration of the drain region.

This makes it possible to improve write characteristics and bunch-through breakdown voltage while preventing a decrease in breakdown voltage between the semiconductor region and the high impurity concentration of the drain region.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a PLD-type EFROM according to an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views for explaining a method for manufacturing a PLD-type EPROM according to an embodiment of the present invention in the order of steps. 3 is a cross-sectional view for explaining an example of the configuration of a gate insulating film in an MO3IC having two types of MOS transistors using different power supply voltages, and FIG. 4 is a cross-sectional view showing a conventional PLD type EPROM. FIGS. 5A and 5B are cross-sectional views for explaining a conventional PLD type EPROM manufacturing method in the order of steps. Explanation of main symbols in the drawings 1: p-type Si substrate, 2: gate insulating film, FG: floating gate, CG: control gate,
6: Source region, 7: Drain region, 6a, 1a:
n-type low impurity concentration portion, 6b, 7bin-type low impurity concentration portion, 8: p-type semiconductor region. Agent Patent Attorney Tadashi Sugiura Chikotsuto D-Luke-1 CG Implementation 1 Diagram 1 How to create diagrams Diagram 2 A Part 1 Diagram 3 Diagram 4 Enzo Manta! 4. Route method Diagram 2 C Rakuzo Mangoun Diagram 5 A Back road method Diagram 5 B

Claims (1)

[Claims] Having a floating gate type memory transistor,
The drain region of the second conductivity type of the memory transistor formed in the semiconductor substrate of the first conductivity type includes a high impurity concentration part and a low impurity concentration part, and the low impurity concentration part of the drain region and the semiconductor A nonvolatile semiconductor memory in which a semiconductor region of a first conductivity type is formed between a substrate and a substrate, wherein the semiconductor region is not in contact with the high impurity concentration portion of the drain region.