JPH03245567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a logic transistor in performance and degree of integration by a method wherein a high breakdown strength C-MOS transistor, memory cells, and a logic C-MOS transistor are mixedly mounted on the same substrate to constitute a semiconductor device, where the gate insulating film of the logic transistor is properly formed in thickness. CONSTITUTION:Gate insulating films used in an electrically erasable P-ROM are classified into three types in thickness, a tunnel insulating film in a memory cell 16, a 5V insulating film 17 in a logic transistor, and a high breakdown strength insulating film 18 in a memory cell. The films 16, 17, and 18 are so set in thickness to satisfy a formula, T16<T17<T18, where T16, T17, and T18 denote the thicknesses of the films 16, 17, and 18 respectively. The thickness of the film 16 is determined in accordance with a coupling ratio, and the easier rewriting becomes, the thinner the film 16 becomes. The film 18 is usually formed thicker than 450Angstrom . The thinner the film 17 becomes, the more it is enhanced in operational speed, a threshold value can be lessened in change due to a short channel effect, but a lower limit is determined basing on a voltage applied onto a gate insulating film. By this setup, a logic transistor can be improved in performance and degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to an electrically rewritable nonvolatile semiconductor memory device (EEFROM).

(Prior Art) EEPROM (electrical
ly erasable and programmable
bleROM) is known. EEPROM is EPR
Similar to OM, information is stored using charges stored in memory cells, but tunneling is used to move charges during writing and erasing, and a tunnel current passing through a thin tunnel insulating film on the substrate causes floating Electrons are exchanged with the gate.

FIG. 4(a) is a pattern plan view showing the structure of one memory cell of a conventional EEPROM, FIG. 4(b) is a cross-sectional view taken along line xx' in FIG. 4(a), FIG. 4(c) is a cross-sectional view taken along the line Y-Y' in FIG. 4(a), and FIG. 4(d) shows a large-scale logic circuit such as a gate array formed on the same substrate as the memory cell. FIG. 2 is a cross-sectional view showing a logic transistor included in the device.

In FIGS. 4(a) to (C), a cell representing one bit (unit of information) has a selection transistor 41 for preventing half selection and a storage transistor 42 for storing information.
It is composed of That is, a selection gate 46 and a floating gate 47 are formed adjacent to each other with a gate insulating film 45 interposed in an element region separated by an element isolation region 44 on a semiconductor substrate 43, and a control gate 49 is further formed with an interlayer insulating film 48 interposed therebetween. is formed.

Note that 50 is a diffusion layer of a conductivity type opposite to that of the substrate, and 51 is an aluminum wiring formed on an interlayer insulating film.

In the storage transistor 42, information is stored at a floating gate 47 that is electrically floating. By accumulating/depleting electrons in this floating gate 47, 0N10FF of the storage transistor is controlled.

In order to accumulate/deplete electrons in the floating gate 47, a region of the tunnel insulating film 52 where a part of the gate insulating film 45 is thin (for example, about 100 layers) is used. Due to the bias with layer 50,
A tunnel current flows through the tunnel insulating film 52. Thereby, transfer of electrons at the floating gate 47 is achieved.

On the other hand, in the logic transistors constituting the large-scale logic circuit shown in FIG. A diffusion region having a conductivity type opposite to that of the substrate is formed.

By the way, in the EEFROM that utilizes the above-mentioned tunneling phenomenon, the power required for writing and erasing cells is small, so a booster circuit (not shown) is built in to generate a high voltage in the element, and a single power supply (for example, 5V) is required. ).

In the above conventional example, a high voltage (approximately 20 µm) from the booster circuit is applied to the gate electrodes of the memory cells and selection transistors shown in FIGS. 4(a) to 4(c), and the gate electrodes of the memory cells and selection transistors shown in FIG. A normal power supply voltage (approximately 5V) is applied to the gate electrode of the logic transistor.

However, regardless of the voltage used, the gate insulating film has the same thickness h (except for the tunnel insulating film 52 region).
For example, it is made up of about 450 people. In other words, the gate insulating film used in conventional EEFROM is 100%
Except for the tunnel insulating film, which has a thickness of about 450 mm, all the transistors have a thickness of about 450 mm, regardless of whether they are high voltage type or 5V type transistors.

In such a configuration, the logic transistor is
Since the operating voltage is 5V, which is the power supply voltage, it operates with the same film thickness as the 450-meter high-voltage type Kate insulating film. Regarding this, the following problems arise.

The first problem is that the operating speed is slow.

Usually, as a simple means, the drain-source current 105 is determined to estimate the operating speed of a single transistor. There is a relationship where the greater the IDS, the greater the operating speed. The above 105 can be expressed by the following equation in the saturation region of commonly used transistors.

Here, μ is the intra-channel mobility, COX is the gate insulating film capacitance, W is the channel width, L is the channel length, and VGS
is the gate-source voltage, VT□ is the threshold value, dl is the insulating film thickness, ε0 is the permittivity of vacuum, ε1 is the dielectric constant of the insulating film, and S is the electrode area.

According to the above equation (1), IDS decreases as the insulating film thickness d1 increases. Therefore, the thicker the gate insulating film, the slower the operating speed of the transistor becomes.

Second, as miniaturization progresses in recent years, there is the problem of the short channel effect, which has become a new obstacle. An approximate expression for the short channel effect can be expressed by the following expression.

Here, ΔL=[(X j +Wj)2 We2]' 2-X
j However, ΔVTH is the VTR change due to the short channel effect, εS is the dielectric constant of silicon, q is the amount of charge, NA is the acceptor impurity concentration, ψB is the surface potential, CI
is the insulating film capacitance, Lt4t is the effective channel length, Xj is the junction depth, Wj is the junction depletion layer width, and Wc is the channel depletion layer width.

According to the above equation (2), as the insulating film thickness d1 increases, ΔVTH increases, the short channel effect becomes even greater, and this becomes a hindrance to integration.

(Problems to be Solved by the Invention) Conventionally, EEFROMs have been constructed with the same film thickness regardless of the voltage used, except for the gate insulating film of various transistors or the tunnel insulating film region.

This not only hinders the improvement in operating speed of circuits around memory cells and large-scale logic circuits that operate on a power supply voltage, but also has the drawback that the short channel effect increases, which hinders integration.

This invention was made in consideration of the above circumstances, and its purpose is to improve the performance and high integration of logic transistors that constitute memory cell peripheral circuits and large-scale logic circuits that operate at normal power supply voltages. The objective is to provide a semiconductor device that realizes the

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device of the present invention includes a first MOS transistor having a first gate insulating film having a first thickness and operating at a first power supply voltage. and a second gate insulating film having a second film thickness thinner than the first film thickness within a part of the first gate insulating film, and operates at the first power supply voltage. Second to do
a third MOS transistor having a third film thickness that is thinner than the first gate insulating film and thicker than the second gate insulating film.
and a third ~10S transistor which has a gate insulating film and operates at a second power supply voltage lower than the power supply voltage of M1.

(Function) In this invention, the film thickness of the gate insulating film of the logic transistor that constitutes the peripheral circuit of the EEPROM that operates on a 5V power supply and the large-scale logic circuit that is mounted on the same semiconductor substrate as the EEPROM is determined. , the film is thinner than the gate insulating film of cells and transistors to which high voltages for writing and erasing are applied. As a result, the drain current increases due to the new transistor formed with the gate insulating film, thereby achieving an improvement in operating speed. Furthermore, the amount of threshold chemotaxis due to the short channel effect can also be suppressed.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIGS. 1(a) to (c) show an EE according to an embodiment of the present invention.
FIG. 1(a) is a cross-sectional view showing the structure of each transistor constituting the FROM. FIG.
1(b) is a sectional view showing the structure of a memory cell transistor, and FIG. 1(c) is a sectional view showing the structure of a high-voltage transistor around a memory cell that operates at a normal power supply voltage ((V). FIG. 2 is a cross-sectional view showing the structure of one channel transistor of a logic CMOS transistor that constitutes a memory cell peripheral circuit and a large-scale logic circuit that operate at 5V.

These transistors shown in FIG. 1 are mounted together on the same semiconductor substrate l. As is well known, the diffusion region 12 having a conductivity type opposite to that of the substrate is connected to the gate electrode 13 (13-1 or I
3-2). Substrate and gate electrode 1
A gate insulating film is formed between the gate electrodes 13-1, and an interlayer insulating film 14 is formed between the gate electrodes 13-1 and 13-2. In addition, the broken line 15 in FIG. 1(C) is L D
The gate sidewall portion for the D (lightly doped drain) structure is shown.

In this invention, three gate insulating films used in the EEFROM include a tunnel insulating film I6 in a memory cell, a 5V insulating film 17 in a logic transistor, and a high voltage insulating film 18 in a memory cell and a high voltage transistor. It is broadly classified into different types of film thickness.

That is, the normal power supply voltage (5V) shown in FIG. 1(C)
The gate insulating film of a logic transistor that operates in
It is formed as a 5V insulating film 17 that is thinner than the high voltage insulating film 1B.

In this embodiment, the high voltage insulating film 18 has a thickness of about 450 people, while the 5V insulating film 17 has a thickness of 250 people. This greatly contributes to increasing the speed of 5V logic transistors.

Furthermore, the short channel effect is suppressed, and the degree of integration is improved.

Next, the relationship between the film thicknesses of the above three types of insulating films will be explained in detail.

First, the thinnest gate insulating film is the tunnel insulating film 16, which requires a high electric field for charge transfer.

The thickness of the tunnel insulating film 16 is often determined from a capacitive coupling ratio called a coupling ratio of a storage transistor. The capacitive coupling ratio corresponds to a parameter that indicates the ease/difficulty of writing when transferring charge to and from the floating gate, and the larger this ratio is, the easier it is to write.

The thicker the tunnel insulating film 16 is, the harder it is to rewrite, and the thinner it is, the more advantageous it is to rewrite. However, if it is made too thin, it will deteriorate the charge retention characteristics, which is the most important reliability item for EEFROM.
The upper and lower limits of film thickness are severely restricted. From this background, in reality, the film thickness A (
(Illustrated in Figure 1) should be spread out for about 100 people.

Next, the high voltage insulating film 18 to which a voltage of 20V is applied will be explained.

Usually, about 450 people use a wide film thickness. It takes about 4.4 MV/cm as an electric field. Especially if this film thickness is a concern in terms of electric field strength, there is no problem even if the film thickness is formed to a certain extent. Therefore, the film thickness C (FIGS. 1(a), (b), and f: shown) of the high-voltage insulating film 18 is constrained to require at least 450 people.

Next, the 5V insulating film 17 used at a power supply voltage of 5V will be explained.

As mentioned above, the film thickness B (shown in FIG. 1(c)) is 250
It's about the size of a person. In particular, the film thickness does not have to be the above, but as the film thickness increases, the reduction in operating speed and changes and variations in the threshold value due to the short channel effect become more noticeable. As the film thickness is made thinner, the opposite effect to the above phenomenon can be expected. The lower limit is determined by the electric field applied to the gate insulating film, but is 120
It is possible to spread the number of people.

As described above, the gate insulating film used in the EEF ROM is roughly divided into three different types: the tunnel insulating film J8, the 5V type insulating film 17, and the high voltage type insulating film 18. If the thickness of the tunnel insulating film is A, the thickness of the 5-type insulating film is B, and the thickness of the high voltage insulating film is C, then the relationship between the film thicknesses is A<B<C.・(3) It is.

In the above relationship, A<B is an absolute condition. This is because, as described above, the allowable range of the thickness of the tunnel insulating film 1B is extremely narrow due to its characteristics, and it cannot be formed thickly. On the other hand, 5V
The lower limit determined by the electric field of the system insulating film 17 is 120 people (4, 2
~1v/cm).

Next, it goes without saying that B<C in the above relationship is a necessary condition in this invention. This condition is necessary in order to solve the above-mentioned problems, increase the speed of operation, and fully demonstrate the performance of the device.

Furthermore, the design ratio is shown in the following equation in consideration of scaling.

A: B:'C=1: 2.1: 4.2
...(4) However, taking into account variations in the manufacturing process, the film thickness of each left side is ±2 relative to the value on the right side.
Allow a tolerance of 5%.

For example, if the thickness A of the tunnel insulating film 1B is 80 people, then from the above equation (2), the thickness B of the 5V insulating film 17 is 1
68±41 people, film thickness C of high voltage insulating film 18 is 336±
There will be 82 people. By setting the film thickness A to 80, it becomes possible to lower the boost voltage, which conventionally required 20V, to about 17V. However, in this case, it is also necessary to thin the interlayer insulating film 14 at the same time.

As described above, it is very important to design each transistor to bring out the best performance for various insulating film thicknesses, and to define the ratio in consideration of scaling.

FIGS. 2(a) to 2(c) are cross-sectional views of one embodiment sequentially showing the manufacturing process of each transistor in FIG. 1. From the left side of the figure, a high voltage region constituting the high voltage transistor, a memory cell region constituting the memory cell transistor, and a 5V region constituting the logic transistor are shown, all of which are formed together on the same substrate. Ru. Note that FIG. 2 shows one embodiment of the method in which the interlayer insulating film or the single-layer insulating film between the floating gate and the control gate is used.

After forming the element isolation insulating film 22 on the semiconductor substrate 21, the substrate is thermally oxidized to form a high-voltage gate insulating film 23 having a desired thickness (FIG. 2(a)).

Next, using photolithography technology, holes are opened only in the tunnel window region in the memory cell region until the substrate 21 is exposed. After forming the tunnel insulating film 24 by thermal oxidation, the first conductive film 25 is formed by LPCVD (low pressure CVD) or the like.

Subsequently, after heat treatment, the first conductive film 25 and gate insulating film 23 extending in the 5V region are etched away using photolithography again, and the surface of the substrate 21 in the element active region in the 5V region is exposed ( Figure 2(b)).

Next, the interlayer insulating film 2 in the memory cell area and high voltage area is
Gate insulating films 27 for the 6V and 5V regions are formed at the same time.

Since this gate insulating film 27 is grown from the substrate, the first
The film thickness is only about half that of the interlayer insulating film 26 on the conductive film 25 (polysilicon).

In this way, the gate insulating film 27 is formed with a desired thickness,
Subsequently, a second conductive film 28 is deposited and heat treated (second
Figure (C)).

Note that in the memory region, the first conductive film serves as a floating gate, and the second conductive film serves as a control gate. Further, the high voltage transistor is used later by shorting the first conductive film and the second conductive film or by removing the second conductive film.

FIGS. 3(a) to 3(c) are cross-sectional views of other embodiments showing the manufacturing steps of each transistor shown in FIG. 1 in sequence, similar to FIG. 2 above. Note that FIG. 3 shows an example method in which the interlayer insulating film between the floating gate and the control gate is composed of two or more insulating films having different dielectric constants. In this embodiment, the interlayer insulating film is an oxide film/
Consists of nitride film/oxide film.

After forming the element isolation insulating film 32 on the semiconductor substrate 31, the substrate is thermally oxidized to form a high-voltage gate insulating film 33 having a desired thickness (FIG. 3(a)).

Next, using photolithography technology, holes are opened until the substrate 31 is exposed only in the tunnel window region.

After forming the tunnel insulating film 34 by thermal oxidation, LPCV
The first conductive film 3 is formed by D method (low pressure chemical vapor deposition method) or the like.
form 5. Subsequently, after heat treatment, an oxide film, a nitride film, and an oxide film are sequentially formed as the interlayer insulating film 36 by thermal oxidation or CVD. Thereafter, using the photolithography technique again, the interlayer insulating film 36, the first conductive film 35, and the high voltage gate insulating film 34 consisting of the three layers extending in the 5V region are sequentially removed by etching. The surface of the substrate 31 in the element active region is exposed (see FIG. 3 (
b)).

Next, the gate insulating film 37 in the 5V region is formed to a desired thickness by thermal oxidation, and then the second conductive film 38 is deposited and heat treated (FIG. 3(C)).

By making the gate insulating film in the 5V region thinner than in the high-voltage region, the operation of logic transistors that constitute memory cell peripheral circuits and large-scale logic circuits that operate on a normal 5V power supply voltage is improved. At this time, the drain current increases and an improvement in operating speed is achieved. Further, there is an advantage that the short channel effect due to miniaturization can be suppressed, and high integration can be achieved.

[Effects of the Invention] As explained above, according to the method of the present invention, logic transistors constituting memory cell peripheral circuits and large-scale logic circuits are configured with an appropriate gate insulating film, thereby improving operating speed. can be done. Moreover, the degree of integration can be improved while suppressing the short channel effect. Therefore, a highly reliable semiconductor device can be provided.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are sectional views showing each transistor structure constituting an EEFROM according to an embodiment of the present invention, and FIGS. 2(a) to (c) are sectional views showing each transistor structure in FIG. 3(a) to (C) are sectional views of another embodiment sequentially showing the manufacturing process of each transistor in FIG. 1, and FIG. (a) is the conventional E E FROM
FIG. 4(b) is a pattern plan view showing the structure of one memory cell in FIG.
Figure (c) is a cross-sectional view taken along the Y-Y' line in figure (a), and Figure 4 (d) is a cross-sectional view showing a logic transistor that constitutes a large-scale logic circuit on the same substrate as the memory cell. It is a diagram. 11... Semiconductor substrate, 12... Diffusion region, 13-1
．． 13-2... Gate electrode, 14... Interlayer insulating film,
15-...Gate side wall part, 1B...Tunnel insulating film,
17...5V type insulating film, 18...High voltage type insulating film.

Claims (3)

[Claims] (1) A first MOS transistor having a first gate insulating film having a first thickness and operating at a first power supply voltage; a second MOS transistor having a second gate insulating film having a second thickness thinner than the first film thickness and operating at the first power supply voltage; a third MOS transistor having a third gate insulating film having a third thickness that is thinner than the second gate insulating film and operating at a second power supply voltage lower than the first power supply voltage; A semiconductor device characterized by comprising: (2) The second MOS type transistor is a cell transistor configured as a memory cell of a nonvolatile semiconductor storage device in which stored information can be electrically erased and written, and the first MOS type transistor is a cell transistor configured as a memory cell of a nonvolatile semiconductor storage device in which stored information can be electrically erased and written. 2. The semiconductor according to claim 1, wherein the semiconductor is a high-voltage transistor in the periphery of a cell, and the third MOS transistor is a logic transistor constituting a large-scale logic circuit in the periphery of the nonvolatile semiconductor memory device. Device. (3) When the second film thickness is A, the third film thickness is B, and the first film thickness is C, the proportional relationship is A:B:C=1:2.1:4.2. have,
3. The semiconductor device according to claim 2, wherein each term on the right side has a film thickness relationship of ±25%.