JPH03245567A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03245567A
JPH03245567A JP2042888A JP4288890A JPH03245567A JP H03245567 A JPH03245567 A JP H03245567A JP 2042888 A JP2042888 A JP 2042888A JP 4288890 A JP4288890 A JP 4288890A JP H03245567 A JPH03245567 A JP H03245567A
Authority
JP
Japan
Prior art keywords
film
insulating film
thickness
logic
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2042888A
Inventor
Masataka Takebuchi
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2042888A priority Critical patent/JPH03245567A/en
Publication of JPH03245567A publication Critical patent/JPH03245567A/en
Application status is Granted legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Abstract

PURPOSE: To enhance a logic transistor in performance and degree of integration by a method wherein a high breakdown strength C-MOS transistor, memory cells, and a logic C-MOS transistor are mixedly mounted on the same substrate to constitute a semiconductor device, where the gate insulating film of the logic transistor is properly formed in thickness.
CONSTITUTION: Gate insulating films used in an electrically erasable P-ROM are classified into three types in thickness, a tunnel insulating film in a memory cell 16, a 5V insulating film 17 in a logic transistor, and a high breakdown strength insulating film 18 in a memory cell. The films 16, 17, and 18 are so set in thickness to satisfy a formula, T16<T17<T18, where T16, T17, and T18 denote the thicknesses of the films 16, 17, and 18 respectively. The thickness of the film 16 is determined in accordance with a coupling ratio, and the easier rewriting becomes, the thinner the film 16 becomes. The film 18 is usually formed thicker than 450Å. The thinner the film 17 becomes, the more it is enhanced in operational speed, a threshold value can be lessened in change due to a short channel effect, but a lower limit is determined basing on a voltage applied onto a gate insulating film. By this setup, a logic transistor can be improved in performance and degree of integration.
COPYRIGHT: (C)1991,JPO&Japio
JP2042888A 1990-02-23 1990-02-23 Semiconductor device Granted JPH03245567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2042888A JPH03245567A (en) 1990-02-23 1990-02-23 Semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2042888A JPH03245567A (en) 1990-02-23 1990-02-23 Semiconductor device
US07/658,699 US5101248A (en) 1990-02-23 1991-02-21 Semiconductor device
KR91002887A KR940005900B1 (en) 1990-02-23 1991-02-22 Semiconductor device
EP19910102621 EP0443603A3 (en) 1990-02-23 1991-02-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03245567A true JPH03245567A (en) 1991-11-01

Family

ID=12648573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2042888A Granted JPH03245567A (en) 1990-02-23 1990-02-23 Semiconductor device

Country Status (4)

Country Link
US (1) US5101248A (en)
EP (1) EP0443603A3 (en)
JP (1) JPH03245567A (en)
KR (1) KR940005900B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151610A (en) * 2000-10-27 2002-05-24 Samsung Electronics Co Ltd Nonvolatile memory element and its manufacturing method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6048769A (en) * 1997-02-28 2000-04-11 Intel Corporation CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
JP4614481B2 (en) 1999-08-30 2011-01-19 ルネサスエレクトロニクス株式会社 The semiconductor integrated circuit device
EP1157419A1 (en) * 1999-12-21 2001-11-28 Philips Electronics N.V. Non-volatile memory cells and periphery

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245165A (en) * 1985-08-23 1987-02-27 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPH01119070A (en) * 1987-10-31 1989-05-11 Toshiba Corp Semiconductor device and manufacture thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120166A (en) * 1980-02-27 1981-09-21 Hitachi Ltd Semiconductor ic device and manufacture thereof
JPS57113278A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Manufactue of eprom device
JPS58197776A (en) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp Semiconductor memory storage
JPS5916371A (en) * 1982-07-19 1984-01-27 Nec Corp Nonvolatile semiconductor memory
JPS60226181A (en) * 1984-04-25 1985-11-11 Nec Corp Non-volatile semiconductor memory device
JPS6276668A (en) * 1985-09-30 1987-04-08 Toshiba Corp Semiconductor memory device
JPH07101713B2 (en) * 1988-06-07 1995-11-01 三菱電機株式会社 The method of manufacturing a semiconductor memory device
US5008721A (en) * 1988-07-15 1991-04-16 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245165A (en) * 1985-08-23 1987-02-27 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPH01119070A (en) * 1987-10-31 1989-05-11 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151610A (en) * 2000-10-27 2002-05-24 Samsung Electronics Co Ltd Nonvolatile memory element and its manufacturing method
JP4588276B2 (en) * 2000-10-27 2010-11-24 三星電子株式会社Samsung Electronics Co.,Ltd. Method of manufacturing a nonvolatile memory device

Also Published As

Publication number Publication date
KR920000144A (en) 1992-01-10
EP0443603A2 (en) 1991-08-28
EP0443603A3 (en) 1992-02-12
US5101248A (en) 1992-03-31
KR940005900B1 (en) 1994-06-24

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