JPS60226181A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS60226181A
JPS60226181A JP8311084A JP8311084A JPS60226181A JP S60226181 A JPS60226181 A JP S60226181A JP 8311084 A JP8311084 A JP 8311084A JP 8311084 A JP8311084 A JP 8311084A JP S60226181 A JPS60226181 A JP S60226181A
Authority
JP
Japan
Prior art keywords
insulating film
gate
oxide film
film
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8311084A
Other languages
Japanese (ja)
Inventor
Susumu Hasunuma
蓮沼 晋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8311084A priority Critical patent/JPS60226181A/en
Publication of JPS60226181A publication Critical patent/JPS60226181A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve the dielectric withstanding capability of an insulating film and to obtain excellent non-volatile semiconductor memory device leading to the production of high-reliability devices with a high acceptable rate by a method wherein the thin gate insulating film region just under a floating gate is provided not adjoining a field insulating film region. CONSTITUTION:On the surface of a P type semiconductor substrate 11, a field oxide film 12 and a thin oxide film 13 are formed and, through the latter, As ions are implanted for the formation of an N type buried layer 14. Next, the oxide film 13 is removed by using F or the like. A process follows wherein thermal oxidation, patterning of a resist, partial removal of the oxide films, and second thermal oxidation are accomplished for the formation of a relatively thin first insulating film 15 and a relatively thick second insulating film 16. The first, insulating film 15 is not in contact with the field oxide film 12. Next, a floating gate 17, gate oxide film 18, control gate 19 are built for the completion of the required memory device. In a device wherein the gate is a lamination of the two insulating films 15, 16 greatly different from each other in thickness, a current flows in the thinner insulating film 15 generating a stronger electric field. This results in a memory device with its insulation not to be easily broken down due to pinholes and other defects.

Description

【発明の詳細な説明】 (技術分野) 本発明は不揮発性半導体記憶装置に関し、特に絶縁膜を
介して導電層に電子の注入、引出しを行なう手段を有す
る不揮発性半導体記憶装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having means for injecting and extracting electrons into and out of a conductive layer through an insulating film.

(従来技術) 従来の不揮発性半導体記憶装置は、絶縁膜を介して導電
層に電子の注入、引出しを行なう手段を設けて情報の消
去、書込みを行なっていた。
(Prior Art) Conventional nonvolatile semiconductor memory devices erase and write information by providing means for injecting and extracting electrons into and out of a conductive layer through an insulating film.

第1図は従来の不揮発性半導体記憶装置の一例の断面図
である。p型半導体基板1にLOC08法を用いてフィ
ールド絶縁膜7.薄いゲート絶縁膜3を設ける。n型埋
込層2をゲート絶縁膜3の下に設ける。ゲート絶縁膜3
の上に浮遊ゲート4゜ゲート絶縁膜5.制御ゲート6を
順次重ねて形成する。
FIG. 1 is a cross-sectional view of an example of a conventional nonvolatile semiconductor memory device. A field insulating film 7 is formed on the p-type semiconductor substrate 1 using the LOC08 method. A thin gate insulating film 3 is provided. An n-type buried layer 2 is provided under the gate insulating film 3. Gate insulating film 3
floating gate 4° gate insulating film 5. The control gates 6 are formed by sequentially overlapping each other.

このような構造の記憶装置の埋込層2と制御ゲート6の
間に電圧を印加し、各電極(2−4−6)間の容量結合
によって薄いゲート絶縁膜3(例えば3iQ2膜)中に
高電界を印加し、ファウラー・ノルドハイA(Fowl
er−Nordheim))yネル電流を発生させるこ
とによって、浮遊ゲート4に電子を注入、又は浮遊ゲー
ト4から電子を引出し情報の消去、書込みを行なってい
る。
A voltage is applied between the buried layer 2 and the control gate 6 of the memory device having such a structure, and capacitive coupling between the electrodes (2-4-6) causes the thin gate insulating film 3 (for example, 3iQ2 film) to be A high electric field is applied and the Fowler-Nordhei A (Fowl)
By generating a channel current, electrons are injected into the floating gate 4 or electrons are extracted from the floating gate 4 to erase or write information.

しかるに、このように薄い絶縁膜(5iOz膜では10
0〜150A)では書込み、消去時に印加される高電界
に対してその絶縁破壊耐圧に十分な余裕がなく、またピ
ンホール、欠陥等に起因する絶縁破壊も起シ、装置全短
絡させ、良品率を底下させたり、あるいは良品を不良品
にしてしまうという欠点があった。
However, such a thin insulating film (5iOz film has a thickness of 10
0 to 150 A), there is not enough margin for dielectric breakdown voltage against the high electric field applied during writing and erasing, and dielectric breakdown due to pinholes, defects, etc. also occurs, causing the entire device to short-circuit and reducing the yield rate. This has the drawback of causing a decline in product quality or turning good products into defective ones.

(発明の目的) 本発明の目的は、上記欠点を除去し、少なくとも浮遊ゲ
ートの下なる薄いゲート絶縁膜領域をフィールド絶縁膜
領域と隣接しないように設けることによって、絶縁膜の
絶縁破壊耐性を高め、高信頼性の製品を高良品率で得ら
れる不揮発性半導体記憶装置を提供することにある。
(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to improve the dielectric breakdown resistance of the insulating film by providing at least a thin gate insulating film region under the floating gate so as not to be adjacent to the field insulating film region. The object of the present invention is to provide a nonvolatile semiconductor memory device that can provide a highly reliable product with a high yield rate.

(発明の構成) 本発明の不揮発性半導体記憶装置は、半導体基板の主表
面に設けられた第1の絶縁膜と、該第1の絶縁膜の少な
くとも一部と隣接し、かつ該隣接部における膜厚が前記
第1の絶縁膜よシも厚く、該第1の絶縁膜以外の膜と隣
接する隣接部分においては隣接相手の膜よりも膜厚の薄
い第2の絶縁膜と、該第2の絶縁膜の少なくとも一部と
前記第1の絶縁膜の少なくとも一部とを覆って設けられ
た導電膜と、前記第1の絶縁膜の下の前記半導体基板内
に設けられた拡散領域とを含んで構成される。
(Structure of the Invention) A nonvolatile semiconductor memory device of the present invention includes a first insulating film provided on the main surface of a semiconductor substrate, and a first insulating film that is adjacent to at least a portion of the first insulating film and that is located in the adjacent portion. a second insulating film which is thicker than the first insulating film, and which is thinner than the adjacent film in an adjacent portion adjacent to a film other than the first insulating film; a conductive film provided covering at least a portion of the insulating film and at least a portion of the first insulating film; and a diffusion region provided in the semiconductor substrate under the first insulating film. It consists of:

(実施例) 次に、本発明の実施例について、図面を用いて説明する
(Example) Next, an example of the present invention will be described using the drawings.

第2図(a)〜(C)は本発明の一実施例及びその製造
方法を説明するための工程順に示した断面図である。
FIGS. 2(a) to 2(C) are cross-sectional views showing an embodiment of the present invention and a manufacturing method thereof in order of steps.

まず、第2図(alに示すように、p型半導体基板11
の表面に通常のLOCO8法を用いてフィールド酸化膜
12と、例えば100^程度の薄い酸化膜13を形成す
る。この酸化膜13を通してヒ素を例えば50KeVで
1.0XIOcm 程度イオン注入してn型埋込み層1
4を形成する。
First, as shown in FIG. 2 (al), a p-type semiconductor substrate 11
A field oxide film 12 and a thin oxide film 13 of, for example, about 100^ are formed on the surface using the usual LOCO8 method. Through this oxide film 13, arsenic is ion-implanted at about 1.0XIOcm at 50KeV to form an n-type buried layer 1.
form 4.

次に、第2図[b)に示すように、酸化膜13をフッ酸
等で除去し、熱酸化、レジストのパターニング、一部酸
化膜の除去、熱酸化を行なうことによシ比較的膜厚の薄
い(例えば120A程度の)第1の絶縁膜15と膜厚の
厚い(例えば600^程度の)第2の絶縁膜16とを形
成する。ここで、第1の絶縁膜15はフィールド酸化膜
12と隣接していないことが重要である。
Next, as shown in FIG. 2 [b], the oxide film 13 is removed using hydrofluoric acid, etc., and then thermal oxidation, patterning of the resist, removal of a portion of the oxide film, and thermal oxidation are performed. A first insulating film 15 having a thin thickness (for example, about 120 Å) and a second insulating film 16 having a thick thickness (for example, about 600 Å) are formed. Here, it is important that the first insulating film 15 is not adjacent to the field oxide film 12.

次に、第2図(C1に示すように、従来の浮遊ゲート構
造と同様に浮遊ゲート17.ゲート酸化膜18゜制御ゲ
ート19を形成して本発明の一実施例の不揮発性半導体
記憶装置を得る。ファウラー・ノルドハイム型のトンネ
ル電流Iは電界Eによって次式のように表わされる。
Next, as shown in FIG. 2 (C1), a floating gate 17, a gate oxide film 18, and a control gate 19 are formed in the same way as in the conventional floating gate structure to complete a nonvolatile semiconductor memory device according to an embodiment of the present invention. The Fowler-Nordheim type tunneling current I is expressed by the electric field E as follows.

I=S−Kl −E −exp(−に2/E) (S 
:面積。
I=S-Kl -E -exp(-2/E) (S
:area.

Kl、に2 :定数) つまシ、トンネル電流は電界強度に強く依存し、第2図
(C)に示すように、ゲート酸化膜として膜厚が大きく
異なる二種の絶縁膜15.’16が存在すると、電流は
電界の強い、膜厚の薄い方の絶縁膜15中f:流れるよ
うになる。
(Kl, 2: constant) The tunnel current strongly depends on the electric field strength, and as shown in FIG. 2(C), two types of insulating films 15. When '16 exists, current flows through the thinner insulating film 15 where the electric field is stronger.

本願発明者は、上述の実施例のような手法を用い薄いゲ
ート酸化膜15とフィールド酸化膜12との間の領域の
絶縁膜の膜厚をゲート酸化膜15よシも厚くシ、即ち第
2の絶縁膜16を設けたものについて、従来の均一な膜
厚のものとの比較を行なった結果、ピンホール、欠陥等
に起因する絶縁破壊の極めて起こシ難い高信頼性、高歩
留シの記憶素子が得られるという結果を得た。
The inventor of the present application used a technique similar to the above-described embodiment to increase the thickness of the insulating film in the region between the thin gate oxide film 15 and the field oxide film 12 to be thicker than the gate oxide film 15, that is, the second As a result of comparing the insulating film 16 with the conventional insulating film 16 with a uniform thickness, it was found that the insulating film 16 has high reliability and high yield, with extremely low dielectric breakdown caused by pinholes, defects, etc. The result was that a memory element was obtained.

この起因を調べるため本願発明者は薄い酸化膜を有する
MOSダイオードを試作し、その絶縁破壊耐圧を調べた
In order to investigate the cause of this, the inventors of the present invention fabricated a prototype MOS diode having a thin oxide film, and investigated its dielectric breakdown voltage.

すなわち、第3図fa)は通常のLOCO8構造のダイ
オードで31は半導体基板、32はフィールド酸化膜、
33はゲート酸化膜に相当する薄い酸化膜で厚いフィー
ルド酸化膜32に接している。また37は電極である。
That is, FIG. 3fa) shows a diode with a normal LOCO8 structure, 31 is a semiconductor substrate, 32 is a field oxide film,
A thin oxide film 33 corresponds to a gate oxide film and is in contact with the thick field oxide film 32. Further, 37 is an electrode.

また第3図(b)は本発明の一実施例のゲート酸化膜と
同様構造の酸化換全持つLOCO8構造のダイオードで
ある。すなわち本構造ではLOCO8構造の縁端に薄い
酸化膜35が接しないように薄い酸化膜35に接して、
これより厚い酸化膜36が形成され、厚い酸化膜36は
他端で非常に厚いフィールド酸化膜に接している。
Further, FIG. 3(b) shows a diode having a LOCO8 structure having the same structure as the gate oxide film of one embodiment of the present invention. That is, in this structure, the thin oxide film 35 is in contact with the edge of the LOCO8 structure so that the thin oxide film 35 is not in contact with the edge of the LOCO8 structure.
A thicker oxide layer 36 is formed, and the thicker oxide layer 36 contacts a much thicker field oxide layer at the other end.

そして何れのMOSダイオードも薄い酸化膜部分の膜厚
9面積は等しく形成した。
All MOS diodes were formed to have the same film thickness and area of the thin oxide film portion.

この2種類のダイオードに電圧を加え、その絶縁破壊耐
圧を測定し、その耐圧分布を第4図(a)。
Voltage was applied to these two types of diodes, their dielectric breakdown voltages were measured, and the breakdown voltage distribution is shown in Figure 4 (a).

(blに示した。(shown in bl.

第4図fatは第3図fa)に示した従来のLOCO8
構造で作成したMOSダイオードの耐圧分布図であシ、
また第4図(b)は第3図(b)に示した本発明の一実
施例のゲート酸化膜構造を持つMOSダイオードの耐圧
分布図である。第4図(a)、 (b)から明らかなよ
うに従来構造のものは絶縁破壊耐圧は低いものが多くあ
られれその分布も広くなっている。これに対し本発明構
造のものは絶縁破壊耐圧の低下は殆んどなく、分布は狭
い範囲に集中している。
Figure 4 fat is the conventional LOCO8 shown in Figure 3 fa)
This is a breakdown voltage distribution diagram of a MOS diode created according to the structure.
Further, FIG. 4(b) is a breakdown voltage distribution diagram of a MOS diode having a gate oxide film structure according to an embodiment of the present invention shown in FIG. 3(b). As is clear from FIGS. 4(a) and 4(b), many of the conventional structures have low dielectric breakdown voltages, and their distribution is wide. On the other hand, in the structure of the present invention, there is almost no decrease in dielectric breakdown voltage, and the distribution is concentrated in a narrow range.

この結果より、LOCO8構造のフィールド縁端は欠陥
等が発生し易く、トンネル電流のように強電界音用いる
デバイスには信頼性的にも、歩留シ的にも避けるべき構
造であることがわかる。
From this result, it can be seen that the field edges of the LOCO8 structure are prone to defects, and should be avoided in terms of reliability and yield for devices that use strong electric field sounds such as tunnel currents. .

なお、上記実施例では、nチャ/ネル浮遊ゲート型の場
合について説明を行なったが、本発明はnチャンネルに
限定されるものでなく、また浮遊ゲート構造に限定され
るものではない。
In the above embodiments, the case of an n-channel/channel floating gate type was explained, but the present invention is not limited to an n-channel type, nor is it limited to a floating gate structure.

(発明の効果) 以上説明したとお)、本発明によれば、欠陥の多い、フ
ィールド酸化膜と隣接する部分のゲート酸化膜厚を厚く
することによシ、絶縁破壊耐圧の高いゲートy化膜構造
が得られ、装置の信頼性。
(Effects of the Invention) As explained above, according to the present invention, by increasing the thickness of the gate oxide film in the portion adjacent to the field oxide film, which has many defects, the gate oxide film has a high dielectric breakdown voltage. structure and reliability of the device.

耐久性を高めることができる。Durability can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の不揮発性半導体記憶装置の一例の断面図
、第2図(a)〜(C)は本発明の一実施例及びその製
造方法を説明するために工程順に示した断面図、第3図
(a)、 (blはゲート絶縁膜の絶縁破壊耐圧を調べ
るために試作した従来例及び本発明構造のMOSダイオ
ードの断面図、第4図ta>、 (b)は第3図(a)
、 (b)のMOSダイオードの絶縁破壊耐圧分布図で
ある− 1・・・・・半導体基板、2・・・・・埋込層、3・・
・・・・ゲート絶縁膜、4・・・・・・浮遊ゲート、5
・・・・・・ゲート絶縁膜、6・・・・・・制御ゲート
、7・・・・・フィールド絶縁膜、11・・・・・半導
体基板、12・・・・・・フィールド酸化膜、13・・
・・・酸化膜、14・・・・・埋込層、15・・・・第
1の絶縁膜、16・・・・・・第2の絶縁膜、17・・
・・・浮遊ゲート、18・・・・ゲート酸化膜、19・
・・・・制御ゲート、31 ・・・半導体基板、32・
・ フィールド絶縁膜、33・・・・・ゲート酸化膜、
35・・・・・・第1の絶縁膜、36・・・・・第2の
絶縁膜、37.38 ・電極。 工・、−τ ゛・、。 代理人 弁理士 内 原 ・(、・、・。 第1力 元?圀 第3に 7)4圀
FIG. 1 is a sectional view of an example of a conventional nonvolatile semiconductor memory device, and FIGS. 2(a) to 2(C) are sectional views shown in order of steps to explain an embodiment of the present invention and its manufacturing method. 3(a), (bl is a cross-sectional view of a conventional example and a MOS diode of the present invention structure prototyped to investigate the dielectric breakdown voltage of the gate insulating film, FIG. a)
, is a dielectric breakdown voltage distribution diagram of the MOS diode in (b) - 1... Semiconductor substrate, 2... Buried layer, 3...
...Gate insulating film, 4...Floating gate, 5
...Gate insulating film, 6...Control gate, 7...Field insulating film, 11...Semiconductor substrate, 12...Field oxide film, 13...
...Oxide film, 14...Buried layer, 15...First insulating film, 16...Second insulating film, 17...
...Floating gate, 18...Gate oxide film, 19.
... Control gate, 31 ... Semiconductor substrate, 32.
・Field insulating film, 33...gate oxide film,
35...First insulating film, 36...Second insulating film, 37.38 - Electrode. Engineering・, −τ ゛・,. Agent Patent Attorney Uchihara ・(、・、・. Daiichi Rikimoto? Kuni 3rd 7) 4 Kuni

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の主表面に設けられた第1の絶縁膜と、該第
1の絶縁膜の少なくとも一部と隣接し、かつ該隣接部に
おける膜厚が前記第1の絶縁膜よフも厚く、該第1の絶
縁膜以外の膜と隣接する隣接部分においては隣接相手の
膜よシも膜厚の薄い第2の絶縁膜と、該第2の絶縁膜の
少なくとも一部と前記第1の絶縁膜の少くとも一部とを
覆って設けられた導電膜と、前記第1の絶縁膜の下の前
記半導体基板内に設けられた拡散領域とを含むことを特
徴とする不揮発性半導体記憶装置。
a first insulating film provided on the main surface of the semiconductor substrate; the first insulating film is adjacent to at least a portion of the first insulating film, and the film thickness at the adjacent portion is thicker than the first insulating film; In an adjacent portion adjacent to a film other than the first insulating film, there is a second insulating film that is thinner than the adjacent film, at least a portion of the second insulating film, and the first insulating film. A nonvolatile semiconductor memory device comprising: a conductive film provided to cover at least a portion of the first insulating film; and a diffusion region provided in the semiconductor substrate under the first insulating film.
JP8311084A 1984-04-25 1984-04-25 Non-volatile semiconductor memory device Pending JPS60226181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8311084A JPS60226181A (en) 1984-04-25 1984-04-25 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8311084A JPS60226181A (en) 1984-04-25 1984-04-25 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS60226181A true JPS60226181A (en) 1985-11-11

Family

ID=13793058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8311084A Pending JPS60226181A (en) 1984-04-25 1984-04-25 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS60226181A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101248A (en) * 1990-02-23 1992-03-31 Kabushiki Kaisha Toshiba Semiconductor device
KR100522098B1 (en) * 2002-10-22 2005-10-18 주식회사 테라반도체 Flash EEPROM unit cell and memory array architecture including the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105374A (en) * 1979-02-07 1980-08-12 Nec Corp Nonvolatile semiconductor memory
JPS55128872A (en) * 1979-03-27 1980-10-06 Sanyo Electric Co Ltd Semiconductor memory
JPS58115865A (en) * 1981-12-28 1983-07-09 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン Electrically programmable and erasable memory cell

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55105374A (en) * 1979-02-07 1980-08-12 Nec Corp Nonvolatile semiconductor memory
JPS55128872A (en) * 1979-03-27 1980-10-06 Sanyo Electric Co Ltd Semiconductor memory
JPS58115865A (en) * 1981-12-28 1983-07-09 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン Electrically programmable and erasable memory cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101248A (en) * 1990-02-23 1992-03-31 Kabushiki Kaisha Toshiba Semiconductor device
KR100522098B1 (en) * 2002-10-22 2005-10-18 주식회사 테라반도체 Flash EEPROM unit cell and memory array architecture including the same

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