JPH0529587A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor memory which has a small damage to be applied to a gate insulating film and can increase the number of times of repetitions of writing and erasing information. CONSTITUTION:An E<2>P-ROM 20 is formed of a DSA structure. The E<2>P-ROM 20 has a floating gate 36 and a control gate 40. In the ROM 20, phosphorus, etc., is ion implanted in a channel region 50, for example, except a P<++> type layer for constituting an effective channel 32, it is always set to a depression state, and set to the same potential as that of a source region 28 or a drain region 30 to become an electron discharge passage at the time of erasing information.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an improvement of the flash-type E ² P-ROM.

[0002]

2. Description of the Related Art An E ² P-ROM is known as a nonvolatile memory device capable of erasing and rewriting information. Although various structures of E ² P-ROM are known, DSA (Double-diffu) as shown in FIG.
E ^{2 of} sed Self Aligned structure
P-ROMs have been developed.

In this E ² P-ROM, the source region 4 and the drain region 6 of the high-concentration N ⁺⁺ layer are formed in the surface layer of the P-type substrate 2, and the high-concentration P ⁺ is formed around the lower layer side of the drain region 6. The effective channel region 8 of the ⁺ layer is formed. Then, the substrate 2 located between these source region 4 and drain region 6
A floating gate 12 and a control gate 14 are laminated on the surface of the via a gate insulating film 10. In order to electrically erase the information stored in the E ² P-ROM, zero or a negative potential is applied to the control gate 14,
This is performed by applying a positive potential to the source region 4 and discharging the electrons stored in the floating gate 12 to the source region 4.

[0004]

Conventionally, electron emission for erasing information is carried out between a small region of the side diffusion (under the channel) s of the source region 4 and the control gate 12. There is. Area s
Is about 0.05 μm in the past. F through the gate insulating film 10 corresponding to this extremely small area s
Since a −N tunnel current flows, electrons are emitted, so that the region s of the gate insulating film 10 is damaged by the passage of electrons when erasing information. If the gate insulating film 10 is damaged, this E
² There is a problem that the number of times information is repeatedly written and erased in the P-ROM is reduced.

Further, in manufacturing such an E ² P-ROM, the lower edge portion of the floating gate 12 made of a polysilicon layer is also oxidized by passing through an oxidation process, and the edge portion 12a of the gate 12 is a bird's beak. There is also a problem that it becomes a shape and rises upward, and the F-N tunnel current effect in the region s varies or decreases. The present invention has been made in order to effectively solve the problems of the prior art, and the damage to the gate insulating film is small, and the number of times of writing and erasing information can be increased. And its manufacturing method.

[0006]

In order to achieve the above object, the present invention provides a DSA (Double-diffused Self Aliment).
A non-volatile semiconductor memory device is configured using a gned, double-diffused self-aligned structure. This memory device has a floating gate and a control gate. In the memory device of the present invention, for example P
P-type impurities such as phosphorus are ion-implanted into the channel region other than the ⁺⁺ layer and kept in a depletion state so as to have the same potential as the source region or the drain region which becomes the electron emission path during information erasing. .

[0007]

In such a non-volatile semiconductor memory device of the present invention, by providing the channel region in the depletion state, the utilization region of the FN tunnel current effect becomes longer and the concentration of the electric field is relieved. The damage given to the device is reduced, and the number of times of writing and erasing information is increased.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings. FIG. 1 shows an E ² P-RO according to an embodiment of the present invention.
2 is a schematic sectional view of the ROM of the embodiment, FIG. 3 to FIG. 8 are schematic sectional views showing a manufacturing example of the ROM of the embodiment, and FIG. 9 is another embodiment of the present invention. FIG. 3 is a circuit configuration diagram of an E ² P-ROM. As shown in FIG. 1, in an E ² P-ROM 20 according to an embodiment of the present invention, a P-type semiconductor substrate 22 is used.
A plurality of memory cells 26 separated by the field oxide region 24 are formed on the surface of the. Each memory cell 26
Basically adopts the DSA structure. That is, the E ² P-ROM 20 of this embodiment has the following configuration.

Each memory cell 26 includes a P-type semiconductor substrate 22.
A source region 28 and a drain region 30 of high concentration N ⁺⁺ are formed in the surface layer of the above, and an effective channel region 32 of high concentration P ⁺⁺ is formed around the lower layer side of the drain region 30. Then, these source region 28 and drain region 30
The floating gate 36 is laminated on the surface of the substrate 22 located between the first gate insulating film 34 and the control gate 40 via the second gate oxide insulating film 38. There is. In the source region 28, the metal wiring layer 44 stacked on the interlayer insulating film 42 is formed.
Are connected through the contact hole 45. The metal wiring layer 44 is made of, for example, aluminum metal and has a function as a ground wiring layer.
A metal wiring layer 46 is connected to the drain diffusion layer 30 through a contact hole 47. The metal wiring layer 46 is made of, for example, aluminum metal and has a function as a bit line wiring layer.

Metal wiring layers 44 and 46 and each memory cell 2
6 is covered with an overcoat film 48. The overcoat film 48 is made of plasma silicon nitride, silicon oxide, polyimide resin, or the like. In this embodiment,
An N-type impurity such as phosphorus P is ion-implanted into the channel region 50 other than the effective channel region 32 formed of the P ⁺⁺ layer to form a low concentration N ⁻ region, which is always in the depression state. The E ² P-ROM 20 of the present embodiment is a NOR type memory and has a circuit configuration as shown in FIG. 2, for example. The control gate 40 of each memory cell 26 functions as a word line, the source region of each memory cell 26 is commonly connected to the metal wiring layer 44 as a ground wiring layer, and the drain region of each memory cell 26 is a contact hole. The metal wiring layer 46 as a bit line is commonly connected via 47.

An example of manufacturing such an E ² P-ROM 20 will be described below. As shown in FIG. 3, a field oxide region 24 for element isolation and a first gate oxide insulating film 34 are formed on the surface of a semiconductor substrate 22 made of a P-type silicon substrate by means of thermal oxidation or the like. Then, as shown in FIG.
Ions are implanted into the portion to be the channel region 50 for controlling the threshold voltage Vth to form a low concentration N ⁻ region. Next, the floating gate 36 made of, for example, a polysilicon layer is formed on the gate insulating film 34 corresponding to the portion to be the channel region 50. An insulating film is laminated on the entire surface of the substrate 22 to form the second gate insulating film 38 on the floating gate 36. Then, a control gate 40 made of, for example, a polysilicon layer is stacked on the insulating film 38 corresponding to the floating gate 36.

Next, as shown in FIG. 6, the insulating film other than the vicinity of the control gate 40 is etched with a predetermined pattern, and either one of the source region and the drain region is masked with the resist film 52, and boron is used. An effective channel region 32 made of a high concentration P ^{+ +} layer is formed by ion-implanting a P-type impurity such as a source region or a drain region and performing annealing diffusion after removing the resist film 52. In this embodiment, the effective channel region 32 is formed in the portion that will be the drain region. Next, as shown in FIG. 7, N-type impurities are ion-implanted into the portions to be the source region 28 and the drain region 30, and an annealing diffusion process is performed to form a high-concentration N ⁺⁺ region. Next, as shown in FIG.
2 is deposited to cover the surfaces of the memory cell 26 and the substrate 22. The interlayer insulating film 42 is not particularly limited, but a plasma silicon nitride film, a silicon oxide film, or the like is used. Thereafter, as shown in FIG. 1, contact holes 45 and 47 are formed in the interlayer insulating film 42, and a metal such as aluminum is formed on the contact holes 45 and 47 in a predetermined pattern by vapor deposition or the like.
If the metal wiring layers 44 and 46 are formed, an overcoat film 48 is formed on the metal wiring layers 44 and 46, and heat treatment is performed, then E ² P of this embodiment is formed.
ROM 20 is obtained.

Information is written in the E ² P-ROM 20 of this embodiment by injecting electrons into the floating gate 36 by utilizing the hot electron effect by channel injection. Information is erased by setting the control gate 40 to zero or a negative potential and the source region 28 to a positive potential. that way,
The electrons in the floating gate 36 are extracted to the source region 28 by the FN tunnel current effect, and the erase operation is achieved. At this time, in this embodiment, since the channel region 50 composed of the N ⁻ region is formed, this channel region 50 can also be set to the same potential as the source region 28. Therefore, when erasing information, the region through which electrons pass is erased. This means that the channel region 50 has been expanded. This expansion reduces damage caused by electrons passing through a narrow area, and
The concentration of the electric field is eliminated, and the number of times information is written and erased is increased.

Incidentally, in the past, as shown in FIG. 10, electrons were emitted at the time of erasing information through the side diffusion region s of the N ⁺⁺ layer of the source region 4.
This s length is about 0.05 μm. In this embodiment,
When the gate length L = 0.35 μm, the electron emission path width at the time of erasing information increases by the width of the channel region 50.
It becomes 0.15 μm to 0.20 μm. That is, the electron emission path width is 3 to 4 times that of the conventional case, and the damage amount (per unit area) of the insulating film 34 is alleviated. As a result, the number of times information is written and erased is improved by one digit or more as compared with the conventional case. In addition, E ^{2 of the} present embodiment
In the P-ROM 20, a bird's beak portion is formed at the end portion of the floating gate 36, and even if the gap between the end portion of the floating gate 36 and the side diffusion region of the source region 28 becomes non-uniform, a uniform gap is maintained. Since electrons are emitted between the floating channel portion 50 and the floating gate 36, there is no problem that the FN tunnel current effect varies or decreases.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, the source region 28 and the drain region 30 may be configured in reverse, and the effective channel region may be formed in the lower layer around the source region 28. In that case, writing information
Control gate 3 using F-N tunnel current effect
For erasing information, electrons are injected into 6 and electrons are emitted from the control gate through the drain region. Further, the semiconductor memory device of the present invention can be a NAND memory having a circuit configuration as shown in FIG. In the NAND type memory, each memory cell 26 is connected in series, and select cells 60 having select gates 59 are connected at both ends. In case of the NAND type, be formed effective channel layer 32 composed of a P ⁺⁺ layer around the lower portion of the drain region 30, the effective channel layer 32 composed of a P ⁺⁺ layer around the lower portion of the source region 28 There is no problem even if it is formed. In addition, writing and erasing information is F
-Achieved using the N tunneling current effect.

[0016]

As described above, according to the present invention,
Since the depletion type channel region is formed,
Since this channel region can be set to the same potential as the source region or the drain region which becomes the electron emission region at the time of erasing information, the region through which the electrons pass at the time of erasing information is expanded to the channel region. This enlargement reduces the damage caused by the passage of electrons through a narrow area, eliminates the concentration of the electric field, and increases the number of times of writing and erasing information. Further, in the semiconductor memory device of the present invention, even if the bird's beak portion is formed at the end portion of the floating gate, stable electron emission can be achieved between the channel portion 50 and the floating gate 36, which are kept in a uniform gap. Since this is done, there is no problem that the FN tunnel current effect varies or decreases.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an E ² P-ROM according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a ROM of the same embodiment.

FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 4 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 5 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 6 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 7 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 8 is a schematic cross-sectional view showing one manufacturing process of the ROM of the embodiment.

FIG. 9 is a circuit configuration diagram of an E ² P-ROM according to another embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a conventional E ² P-ROM.

[Explanation of symbols]

20 E ² P-ROM 22 semiconductor substrate 28 source region 30 drain region 32 effective channel region 34 gate insulating film 36 floating gate 38 gate insulating film 40 control gate 44 metal wiring layer 46 metal wiring layer

Claims (2)

[Claims] 1. A source region and a drain region are formed on a surface layer of a semiconductor substrate at a predetermined interval, and a floating gate and a control are provided on a surface of a semiconductor substrate which is a channel region located between these regions via a gate insulating film. A non-volatile semiconductor memory device in which a gate is laminated, and an effective channel region is formed around the lower layer side of the source region or the drain region, wherein a channel region other than the effective channel region is a depletion type, A non-volatile semiconductor memory device characterized in that it has the same potential as a source region or a drain region which becomes an electron emission path during erasing. 2. A step of forming a first gate insulating film on the surface of a semiconductor substrate, and ion implantation for forming a depletion type channel region on the surface of the semiconductor substrate corresponding to a portion to be a channel region. A step of forming a floating gate on the gate insulating film corresponding to the channel region, a second gate insulating film formed on the floating gate, and a second gate insulating film corresponding to the floating gate A step of forming a control gate on the upper side of the gate, a step of performing ion implantation for forming an effective channel region on one of the surface layers of the semiconductor substrate located on both sides of the gate, and a step of forming the control gate on both sides of the gate. A step of performing ion implantation for forming a source region and a drain region on the surface layer of the semiconductor substrate, respectively. Method of manufacturing a volatile semiconductor memory.