JPH08204031A - Manufacture of nonvolatile semiconductor memory element - Google Patents

Abstract

PURPOSE: To obtain a nonvolatile semiconductor memory element in which the counter area of a control gate with a floating gate is increased and in which a gate coupling ratio is increased by a method wherein an insulating film is formed on the floating gate and the height of a sidewall formed on the side part of the floating gate is made high. CONSTITUTION: A first silicon film 3 which is used as a floating-gate material and a first insulating film 4 are formed on a semiconductor substrate 1 so as to be patterned to be a prescribed shape. A second silicon film 5 is formed on the whole face, it is etched back, a sidewall is formed, the insulating film 4 is removed by phosphoric acid, and a protruding part which is higher than the height of the silicon film 3 and which is composed of the silicon film 5 is formed on the side face part of the silicon film 3. Then, the insulating film 4 is removed, an ONO film 6 is formed on the whole face, and a polycide film 7 is formed additionally. Then, the polycide film 7, the ONO film 6 and the silicon films 3, 5 are patterned. Thereby, the counter area of a control gate with a floating gate is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a non-volatile semiconductor memory device, and more particularly, it is isolated for each bit by a first gate electrode (floating gate) and a second gate electrode.
Having a gate electrode (control gate) of
The present invention relates to a method of manufacturing a nonvolatile memory device having a structure.

[0002]

2. Description of the Related Art A conventional non-volatile MOS structure having a first gate (floating gate) and a second gate (control gate) which are isolated for each bit, with reference to FIGS. 3, 4 and 5. The manufacturing process of the memory device will be described. 3 is a plan view of a non-volatile memory element having a MOS structure having a first gate (floating gate) and a second gate (control gate) which are isolated for each bit, and FIG. 3 is a manufacturing process diagram of the cross section XX 'of the nonvolatile memory element having the structure shown in FIG. 3, and FIG.
It is a manufacturing process drawing of Y'section. 3 to 5,
Reference numeral 21 is a silicon substrate, 22 is a tunnel oxide film, 23 is a polysilicon film to be a floating gate, and 24 is ON.
O film, 7 and 25 are polycide films serving as control gates, 26 is a source region, 27 is a drain region, 11, 2
Reference numeral 8 indicates a field oxide film, and 12 indicates an active region.

First, a field oxide film 28 having a film thickness of about 300 nm is formed on a silicon substrate 21 into which P-type impurities are introduced by a known technique (FIGS. 4A and 5).
(A)).

Next, a tunnel oxide film 22 having a film thickness of about 8 to 13 nm is formed by a thermal oxidation method, and the tunnel oxide film 2 is formed.
100-300nm which becomes a floating gate on 2
A polysilicon film 23 of a certain degree is formed by a CVD method, phosphorus is doped into the polysilicon film 23 by ion implantation or the like, and activation is performed by heat treatment. At this time, the volume concentration of phosphorus is set to about 10 ¹⁹ to 10 ²⁰ / cm ³ (FIG. 4).
(B), FIG. 5 (b)).

Next, the polysilicon film 23 is formed on the active region 12 by using a known photolithography etching process.
Is formed in a direction parallel to (FIGS. 4C and 5C). After that, the ONO film 24 (having a film thickness of 13 to 25 n in terms of oxide film) is formed on the polysilicon film 23 by using a thermal oxidation method, a CVD method, or the like.
m) is formed, and then a polycide film 25 (tungsten silicide (WS) is formed as a control gate.
i) (film thickness 100 nm) / polysilicon (Poly-S
i) (film thickness 100 nm)) is formed (FIGS. 4D and 5D).

Next, the polycide film 25 and the ONO film 24 are etched into a predetermined shape in a direction perpendicular to the polysilicon film 23 by using a well-known photolithography etching process, and subsequently, the polycide film 25 and the ONO film are etched. Membrane 2
The polysilicon film 23 is etched by using 4 as a mask. In this step, the floating gate 23 is isolated bit by bit. After that, arsenic or the like is implanted by an ion implantation method or the like, and N
A diffusion region of ⁺ is formed on the surface of the activation region, and the source region 2
6 and the drain region 27 are formed (FIG. 4E, FIG.
(E)).

After that, a CVD oxide film or the like having a thickness of about 400 nm is deposited on the entire surface, a contact hole is opened by a known photolithography etching method, and a metal wiring is formed.

Data writing in the non-volatile memory element formed in the above steps is performed by injecting electrons into the floating gate by a method such as a hot electron injection method or an FN (Fowler-Nordheim) method, whereby a threshold voltage is obtained. Write by raising.

For example, data reading is performed by setting the control gate to 3V, the drain region to 3V, and the source region to 0V. For data writing, the control gate is 12V, the drain region is 5V, and the source region is 0V.
Then, writing is performed by increasing the threshold voltage by injecting electrons into the floating gate by the channel hot electron injection method. For erasing data, the control gate is -11V and the drain region is 0.
V and source regions are set to 6 V, electrons are extracted from the floating gate to the source regions by the FN tunnel phenomenon, and the threshold voltage is lowered to perform erasing.

[0010]

As described above, in the writing of the flash memory, hot electrons are generated by applying a positive high voltage to the drain region and the gate electrode, and these hot electrons are generated in the tunnel oxide film. This is performed by the phenomenon of jumping over the energy barrier and being injected into the floating gate. At this time, the writing speed is the electric field in the direction (vertical direction) perpendicular to the substrate surface applied to the tunnel oxide film generated by the gate voltage,
It is determined by the strength of the electric field in the direction parallel to the substrate surface (lateral direction) generated by the voltage of the drain region.

Therefore, in order to improve the writing speed, the electric fields in the vertical and horizontal directions may be strengthened. Of these, the vertical electric field, that is, the electric field applied to the tunnel oxide film, is the ratio of the capacitance between the floating gate and the channel portion to the capacitance between the floating gate and the control gate (gate coupling ratio). It is known to be decided by. Since the capacitance is proportional to the area of the electrodes facing each other and inversely proportional to the distance between the electrodes, the tunnel oxide film and the ONO film between the floating gate and the control gate must be used to increase the capacitance ratio. Is preferably as thin as possible, and it is preferable that the ratio of the facing area of the floating gate and the control gate to the facing area of the floating gate and the channel portion is increased.

However, the tunnel oxide film is currently 6-2.
It is very difficult to form an oxide film as thin as 0 nm and thinner. Similarly, regarding the film thickness of the ONO film, it is difficult to form a thin film. Further, the electrons accumulated in the floating gate by writing must be retained, but the surroundings of the floating gate are covered with an insulating film such as an oxide film or an ONO film, and the electrons in the floating gate are insulated by these insulating films. This prevents electrons from exiting the floating gate.

Therefore, if both the tunnel oxide film and the ONO film are made extremely thin, the insulating property of the floating gate is weakened, and it becomes difficult to retain electrons in the floating gate.

From the above, it is effective to increase the ratio of the facing area of the floating gate and the control gate to the area of the floating gate and the channel portion.

As means for increasing the gate coupling ratio (second prior art) to improve the writing speed,
As shown in FIG. 6, a method has been proposed in which a sidewall made of the same material as the floating gate is formed on the sidewall of the floating gate to increase the facing area between the control gate and the floating gate to improve the gate coupling ratio. (JP-A-2-2685).

In this method, the increasing facing area between the floating gate and the control gate is the area of the curved surface of the sidewall formed on the floating gate sidewall, and the increasing area is the height and width of the sidewall. Depends on That is, the area that can be increased is determined by the height of the floating gate (corresponding to the height of the sidewall) and the film thickness of the polycrystalline silicon deposited when forming the sidewall (corresponding to the width of the sidewall).

Therefore, when the memory cell size is reduced, it is ideal that the height of the floating gate is low and the width of the side wall is small. Therefore, the size of the side wall is small and the control gate and the floating gate are small. The effect of increasing the facing area with the gate is reduced. In FIG. 6, reference numeral 29 represents a polysilicon film.

As a third conventional technique, as shown in FIG. 7, a method has been proposed in which one protrusion is provided on the floating gate in order to increase the capacitance (Japanese Patent Laid-Open No. 4-364786). ). However, this manufacturing process has a problem that the alignment margin cannot be sufficiently obtained when the transistor is miniaturized and the gate length is shortened. Also, if the height of the protrusion is increased,
The control gate coverage is poor and disconnection is likely to occur.

Further, when the third prior art process is used, the photoetching process is required four times when patterning the floating gate. In FIG. 7, 30 is a silicon oxide film, 31 is a resist film, and 32 is a polysilicon film.

In view of the above problems, it is an object of the present invention to provide a method for manufacturing a non-volatile semiconductor memory device having a high gate coupling ratio.

[0021]

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention as set forth in claim 1, a first silicon film serving as a floating gate material is entirely formed on a semiconductor substrate through a tunnel oxide film. And a step of forming a first insulating film, a step of patterning the first silicon film and the first insulating film into a predetermined shape, and a second step over the entire surface.
Forming a side wall of the first silicon film by forming a side wall by etching back the side wall of the first side of the first silicon film from the surface of the first side silicon film. A step of forming a convex portion made of a second silicon film having a high height, and a step of forming a second insulating film on the entire surface and forming a conductive film to be a control gate material on the second insulating film. And a step of patterning the conductive layer, the second insulating film, and the first and second silicon films into a predetermined shape by photoetching.

A method of manufacturing a nonvolatile semiconductor memory device according to a second aspect of the present invention is characterized in that a silicon nitride film is used as the first insulating film. It is a method of manufacturing a memory device.

[0023]

With the above structure, the insulating film formed on the floating gate can increase the height of the sidewall formed on the side portion of the floating gate, thereby increasing the facing area between the control gate and the floating gate. Therefore, the gate coupling ratio can be increased.

Therefore, a high gate coupling ratio can be realized even in a fine cell, and the writing speed can be improved.

[0025]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a sectional view taken along line XX 'in FIG. 3 showing a manufacturing process of a nonvolatile memory device having a MOS structure having a floating gate and a control gate which are isolated for each bit according to an embodiment of the present invention. And FIG. 2 shows the same Y-
It is a Y'sectional view. 1 and 2, 1 is a silicon substrate, 2 is a tunnel oxide film, 3 is a first polysilicon film that serves as a floating gate, 4 is a silicon nitride film, and 5 is a protrusion provided on the sidewall of the floating gate 3. Is a second polysilicon film, 6 is an ONO film, 7 is a polycide film, 8 is a source region, 9 is a drain region, 11 is a field oxide film, and 12 is an active region. An embodiment of the present invention will be described in detail below with reference to FIGS. 1, 2 and 3.

First, a field oxide film 11 having a film thickness of about 300 nm is formed on a silicon substrate 1 into which a P-type impurity has been introduced by a known technique (FIGS. 1A and 2).
(A)).

Subsequently, a film thickness of 8 to 13 nm is formed on the active region.
A tunnel oxide film 2 having a thickness of about 1 nm is formed by a thermal oxidation method, and a first polysilicon film 3 to be a floating gate is deposited on the tunnel oxide film 2 by a CVD method so as to have a film thickness of about 100 nm, and is deposited thereon. A silicon nitride film is deposited by a CVD method so as to have a film thickness of about 50 nm (see FIG. 1).
(B), FIG. 2 (b)).

Next, a resist mask (not shown) is formed on the first polysilicon film 3 and the silicon nitride film 4 on the region to be the active region by photolithography,
The first polysilicon film 3 and the silicon nitride film 4 are selectively patterned by the RIE method (FIGS. 1C and 2).
(C), FIG. 3).

Next, a second polysilicon film 5 is deposited by the CVD method so as to have a film thickness of about 50 nm, and a sidewall is formed by etching back by the RIE method, and then the silicon nitride film 4 is phosphorus. Remove with acid etc. (Fig. 1
(D), FIG. 2 (d)). Since the silicon nitride film and the silicon oxide film have high selectivity with respect to phosphoric acid and the like,
When the silicon nitride film is etched, the field oxide film is not reduced. As a result, a convex portion made of the second polysilicon film 5 which is higher than the height of the first polysilicon film 3 is formed on the side portion of the first polysilicon film 3 which becomes the floating gate.

After that, the first gate becomes a floating gate.
The polysilicon film 3 is thermally oxidized to form a thin oxide film, and a silicon nitride film and an oxide film are deposited on the thin oxide film by a CVD method or the like to form an ONO film 6 (having a film thickness of 13 in terms of oxide film).
.About.25 nm) is formed, and the polycide film 7 (tungsten silicide (film thickness: about 100 n
m) / third polysilicon film (film thickness of about 100 nm)).

Next, a resist mask (not shown) is formed on the polycide film 7 serving as a control gate in a direction perpendicular to the active region 12 by a known photolithography / etching process, and the polycide film 7 and ONO are formed. The film 6 and the first and second polysilicon films 3 and 5 to be floating gates are selectively patterned by the RIE method or the like, and arsenic or the like is injected by the ion implantation method to make the N ⁺ diffusion region the active region surface. Then, the source region 8 and the drain region 9 are formed (FIGS. 1E and 2E).

After that, a contact hole is opened and a metal wiring is formed in the oxide film of about 400 nm formed on the entire surface by a known photolithography etching process.

Then, as in the prior art, for example, data reading is performed by setting the control gate to 3V, the drain region to 3V, and the source region to 0V. The data is written by setting the control gate to 12V, the drain region to 5V, the source region to 0V, and injecting electrons into the floating gate by the channel hot electron injection method to raise the threshold voltage. To erase data, set the control gate to -1.
1V, drain region 0V, source region 6V, F
Erasing is performed by drawing electrons from the floating gate to the source region by the N tunnel phenomenon and lowering the threshold voltage.

[0035]

As described above in detail, since the facing area between the control gate and the floating gate is increased by using the present invention, the ONO film and the tunnel oxide film having the conventional film thickness are used. Even in this case, the gate gap ring ratio can be set large.

Hereinafter, the comparison of the gate gap ratio between the present invention and the prior art will be specifically described. The height of the floating gate is 100 nm, the width of the control gate is 0.6 μm, and the length of the floating gate is 0.6 μm.
m, the same width is 0.6 μm, the width of the active region is 0.4 μm, O
The thickness of the NO film is 15 nm and the thickness of the tunnel oxide film is 10.
nm.

The gate Gappling ratio GR is GR = Cono / (Cono + Ct) = Sono.Tt
It can be expressed as d / (Sono.Ttd + Std.Tono). Incidentally, Cono is the capacitance between the control gate and the floating gate,
Is the opposed area between the control gate and the floating gate, Tono is the thickness of the ONO film, Ctd is the capacitance between the floating gate and the substrate, Std is the opposed area between the floating gate and the substrate, and Ttd is the tunnel oxide film. The film thickness is shown.

The facing area Std between the conventional floating gate and the substrate shown in FIGS. 4 and 5 is Std = 0.4 × 0.6 = 0.24 (μm ² ), and the conventional control gate is The area Sono between the floating gate and the floating gate is: Sono = 0.6 × 0.6 + 2 × 0.1 × 0.6 = 0.
It becomes 48 (μm ² ). Therefore, the gate gap ratio G of the conventional cell is
R becomes 0.57. Further, in the case of forming a floating gate as in JP-A-2-2685, for example, by depositing polycrystalline silicon of 50 nm and etching back to form a sidewall of polycrystalline silicon on the side wall of the floating gate, a control gate and a floating gate are formed. The facing area Sono is: Sono = 0.6 × 0.6 + 2 × 0.112 × 0.6 =
It becomes 0.494 (μm ² ). Therefore, the gate coupling ratio GR is about 0.5.
It becomes 8. Here, the bottom of the sidewall is 0.5
It is approximated to a right-angled triangle with μm and height of 0.1 μm.

On the other hand, as in the present invention, when a silicon nitride film of 50 nm is deposited on the floating gate to form a sidewall of polycrystalline silicon,
The facing area Sono between the control gate and the floating gate is: Sono = 0.6 × 0.6 + 2 × (0.158 + 0.0)
5) × 0.6 = 0.610 (μm ² )

Therefore, the gate coupling ratio GR becomes about 0.63, which is 1 as compared with the conventional method shown in FIGS.
It is possible to improve the gate coupling ratio by 0% and by about 9% as compared with the method described in JP-A-2-2685. Here, the film thickness of the silicon nitride film is set to 50 nm, but the gate coupling ratio can be further improved by setting this film thickness to be thick. From this, the vertical electric field at the time of writing can be increased, so that the writing speed can be improved.

Further, since the gate coupling ratio can be increased without changing the film thickness of the tunnel oxide film and the area where the floating gate and the substrate face each other, the ONO film of the ONO film can be formed if no particular improvement in the writing speed is required. Since the film thickness can be increased, the insulating property between the floating gate and the control gate is improved, and the data retention capability can be improved. For example, if the cell is designed so as to obtain the same writing speed as the conventional one, the gate coupling ratio may be about 0.57, which is the same as the conventional one. The cell formed according to the present invention has the same tunnel oxide film thickness as the conventional one.
When the thickness is 0 nm, the ONO film can be set as thick as about 19 nm. As described above, even if the thickness of the ONO film is increased, the data retention capacity can be improved without changing the writing speed.

By using the present invention, a sufficient alignment margin can be obtained even when the transistor is miniaturized and the gate length is shortened, and the number of photoetching steps until patterning of the floating gate is two. The number of steps can be reduced as compared with the steps shown in FIG.

Further, in the conventional method shown in FIGS. 4 and 5, it is necessary to overlap the floating region so as to cover the active region, and the margin of the design rule is required for that, but in the present invention, the floating region is required. Since it overlaps with the active region wider than the gate photoresist pattern by the side wall, a margin can be taken in the cell design.

By using the invention described in claim 2, when the insulating film (silicon nitride film) formed on the floating gate after the sidewall formation is etched, the film reduction of the field oxide film can be suppressed. .

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention, which is taken along the line XX ′ in FIG. 3.

FIG. 2 is a manufacturing process diagram of the nonvolatile semiconductor memory device of the embodiment of the present invention, taken along the line YY ′ in FIG. 3;

FIG. 3 is a layout diagram of a nonvolatile semiconductor memory device.

FIG. 4 is a manufacturing process diagram of a conventional nonvolatile semiconductor memory device, taken along the line XX ′ in FIG. 3;

FIG. 5 is a manufacturing process diagram of a conventional nonvolatile semiconductor memory device, taken along the line YY ′ in FIG. 3;

FIG. 6 is a cross-sectional configuration diagram of a second conventional nonvolatile semiconductor memory device.

FIG. 7 is a manufacturing process diagram of a third conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 1 silicon substrate 2 tunnel oxide film 3 first polysilicon film 4 silicon nitride film 5 second polysilicon film 6 ONO film 7 polycide film 8 source region 9 drain region 11 field oxide film 12 active region

Claims (2)

[Claims] 1. A step of forming a first silicon film and a first insulating film as a floating gate material on the entire surface of a semiconductor substrate via a tunnel oxide film, the first silicon film and the first silicon film. A step of patterning the insulating film into a predetermined shape; a step of forming a second silicon film on the entire surface and forming a sidewall by etching back; a step of removing the first insulating film; A pair of side surfaces of the silicon film having a height higher than the surface of the first silicon film;
A step of forming a convex portion made of a second silicon film, a step of forming a second insulating film on the entire surface, and forming a conductive film as a control gate material on the second insulating film; And a step of patterning the conductive film, the second insulating film, and the first and second silicon films into a predetermined shape. 2. The method for manufacturing a non-volatile semiconductor memory device according to claim 1, wherein a silicon nitride film is used as the first insulating film.