JPH0529480A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten an insulating film between a semiconductor element and aluminium wiring, which is connected to the element, and to obtain contact holes having a good form. CONSTITUTION:A covering PSG film 7 is formed between a semiconductor element and an aluminium wiring and opening parts 8 larger than contact holes 10 are respectively formed in contact hole formation regions. Then, after a BPSG film 9 is formed on the whole surface by a vapor growth method, the contact holes 10 are formed in this film 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of planarizing an interlayer insulating film and forming a contact hole.

[0002]

2. Description of the Related Art A conventional method of forming an interlayer insulating film in a semiconductor device manufacturing process will be described with reference to a MOSFET.

As shown in FIG. 2, a channel stopper 2, a field oxide film 3, an impurity diffusion layer 6, an oxide film 4 and a gate electrode 5 made of polycrystalline silicon or the like are formed on a silicon substrate 1. Next, an oxide film 12 and a boron-phosphorus glass film (hereinafter referred to as a BPSG film) 13 by a vapor phase growth (CVD) method are formed as an interlayer insulating film between the gate electrode 5 and the aluminum wiring. The BPSG film 13 is brought into a fluid state by the heat treatment, which makes it possible to improve the flatness. Especially recently, as a reaction gas during vapor phase growth,
Instead of silane-based gas, tetraethoxysilane (TEO
It has become possible to further improve the flatness by using the S) -based gas.

Further, in recent years, a method using a coatable phosphorus glass film (hereinafter referred to as a coated PSG film) has been used as a method for further improving the flatness. Compared with the conventional CVD method, this method enables almost complete flattening regardless of the step of the element.

Usually, this coated PSG film has a thickness of 150 after coating.
The film quality is improved by performing heat treatment stepwise from a low temperature of around ℃ to a high temperature of 800 to 900 ℃.

[0006]

In the method of forming an interlayer insulating film in the above-described conventional manufacturing process of a semiconductor device, first, in the method of using the BPSG film by the CVD method,
At the time of planarization by heat treatment, the BPSG film 13 is concentrated on the upper part of the gate electrode 5 due to the influence of surface tension, and as shown in FIG. Can't get

On the other hand, the coated PSG film enables almost complete flattening. However, this coated PSG film has a problem that the etching rate during wet etching is extremely higher than that of a film formed by the CVD method or the like. As a result, as shown in FIG. 3, when the contact hole 10 is formed on the thick PSG film 7 formed on the diffusion layer 6, wet etching is performed in order to secure step coverage of the aluminum wiring as in the usual method. However, in order to obtain sufficient coverage, a considerable amount of taper etching is required with respect to the depth.
There is a problem that an extremely large contact hole 10 is opened by wet etching on the gate electrode 5 having a small SG film thickness.

Further, it is very difficult to control the etching amount of the coated PSG film 7 during wet etching, and if etching proceeds too much, it also affects the breakdown voltage of the interlayer insulating film.

[0009]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a coatable insulating film on a semiconductor substrate on which a semiconductor element is formed and having steps, and the coatable insulating film in a contact hole forming region. A step of forming an opening larger than the contact hole in the film, a step of forming an insulating film on the entire surface including the opening by a vapor phase growth method to fill the opening, and a step of forming a contact hole in the insulating film by the vapor phase growth method. And a step of forming.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are sectional views of a semiconductor chip for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a channel stopper 2 and a field oxide film 3 are formed on a silicon substrate 1. Next, a gate electrode 5 is formed in the element formation region via the oxide film 4, and then an impurity diffusion layer 6 serving as a source / drain is formed by an ion implantation method or the like. Next, a coatable phosphorous glass film (coated PSG film) 7 having a thickness of about 400 nm is coated on the silicon substrate 1 on which the semiconductor element is thus formed, and heat treatment is performed stepwise at a temperature of 150 to 900 ° C. To do.

Next, as shown in FIG. 1B, a contact hole forming region which requires connection with a semiconductor element is opened by anisotropic etching by a normal patterning method. At this time, the size of the opening portion 8 is larger than that of the contact hole formed in a later step. Next, as an insulating film by the CVD method, for example, a BPSG film 9 of 500 n is formed on the entire surface.
It is formed to a thickness of about m and is flattened by heat treatment.
As a result, the opening 8 is also sufficiently filled with the BPSG film 9.

Next, if necessary, the surface of the BPSG film 9 is etched by an anisotropic etching method to further flatten it.

Next, as shown in FIG. 1C, the BPSG embedded in the opening 8 by a normal patterning method.
A contact hole 10 is opened in the film 9. At this time, in order to improve the step coverage of the aluminum wiring, it is etched for several minutes by, for example, a wet etching method using buffered hydrofluoric acid, and then completely opened by an anisotropic dry etching method. Since the portion etched by the wet etching method is the BPSG film by the CVD method,
It is easy to control the etching amount. Further, the same contact hole 10 can be formed on the diffusion layer 6 and the gate electrode 5 on the opposite side. Hereinafter, the aluminum wiring 11 is formed by a usual method to complete the MOSFET.

When forming the opening 8 in the coated PSG film 7, it is not necessary to form the opening completely up to the surface of the silicon substrate, but rather, when considering damage to the substrate and flattening, the opening is just formed on the gate electrode 5. The degree of completion is preferable.

In the above embodiment, the MOSFE
Although the case of T has been described, the present invention can be applied to a method of manufacturing another semiconductor device having a step.

[0017]

As described above, according to the present invention, by using the coatable insulating film as the interlayer insulating film, the insulating film between the semiconductor element and the aluminum wiring can be almost completely flattened. .. In addition, the contact hole formation region of this coatable insulating film is filled with an insulating film formed by vapor phase epitaxy,
By forming a contact hole in this insulating film, it is possible to easily form a contact hole having a good shape.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional method for manufacturing a semiconductor device.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 1 Silicon Substrate 2 Channel Stopper 3 Field Oxide Film 4 Oxide Film 5 Gate Electrode 6 Impurity Diffusion Layer 7 Coated PSG Film 8 Opening 9 BPSG 10 Contact Hole 11 Aluminum Wiring 12 CVD Oxide Film 13 BPSG Film

Claims (1)

Claim: What is claimed is: 1. A step of forming a coatable insulating film on a semiconductor substrate having a semiconductor element formed thereon and having a step, and an opening larger than a contact hole in the coatable insulating film in a contact hole formation region. And a step of forming an insulating film on the entire surface including the opening by vapor phase epitaxy to fill the opening,
And a step of forming a contact hole in the insulating film by the vapor phase epitaxy method.