JPS61222224A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61222224A JPS61222224A JP6439685A JP6439685A JPS61222224A JP S61222224 A JPS61222224 A JP S61222224A JP 6439685 A JP6439685 A JP 6439685A JP 6439685 A JP6439685 A JP 6439685A JP S61222224 A JPS61222224 A JP S61222224A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact hole
- substrate
- deposited
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 229910052723 transition metal Inorganic materials 0.000 claims description 4
- 150000003624 transition metals Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 89
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体基板上に被着された絶縁層に形成されたコンタク
ト孔内に導電層を埋め込む際に、まずコンタクト孔内に
前もって薄く導電層を敷き、この上に多結晶半導体層を
堆積させることにより、段差被覆のよい、多結晶半導体
層をドープするときに基板に形成された拡散領域が広が
ることが少ない、および多結晶半導体層堆積後の基板の
平坦化エツチング時にコンタクト孔内の基板が侵される
ことがないプロセスを提供する。[Detailed Description of the Invention] [Summary] When embedding a conductive layer into a contact hole formed in an insulating layer deposited on a semiconductor substrate, a thin conductive layer is first spread inside the contact hole, and then a conductive layer is placed on top of the conductive layer. By depositing a polycrystalline semiconductor layer, it is possible to achieve good step coverage, less spread of the diffusion region formed in the substrate when doping the polycrystalline semiconductor layer, and flattening of the substrate after the polycrystalline semiconductor layer is deposited. To provide a process in which a substrate in a contact hole is not sometimes attacked.
本発明はコンタクト孔に導電層を埋め込む方式のオーミ
ックコンタクト形成方法に関する。The present invention relates to a method for forming an ohmic contact in which a conductive layer is buried in a contact hole.
デバイスの高集積化、多層化にともない、電極窓等、コ
ンタクト孔内の配線層の段差被覆がデバイスの信頼性上
問題となる。その対策としてコンタクト孔内に何らかの
導電物質を埋め込み、基板を平坦化する方法が考えられ
ている。As devices become more highly integrated and multilayered, step coverage of wiring layers in contact holes, such as electrode windows, becomes a problem in terms of device reliability. As a countermeasure to this problem, a method has been considered in which a conductive material of some kind is buried in the contact hole to flatten the substrate.
この際、段差被覆がよく、プロセスが基板に影響を与え
ないことが必要である。At this time, it is necessary that the step coverage is good and that the process does not affect the substrate.
（従来の技術〕
第３図は従来例によるコンタクト孔埋込構造を示す基板
断面図である。(Prior Art) FIG. 3 is a sectional view of a substrate showing a contact hole filling structure according to a conventional example.
図において、１はｐ型珪素（Ｓｉ）基板、１）は基板１
に形成されたｎ型拡散層である。In the figure, 1 is a p-type silicon (Si) substrate, 1) is a substrate 1
This is an n-type diffusion layer formed in .
基板全面に絶縁層としてドープされた燐珪酸ガラス（Ｄ
ＰＳＧ）層２を被着し、コンタクト孔３を開口する。Doped phosphosilicate glass (D
PSG) layer 2 is applied and contact holes 3 are opened.
つぎに、導電層としてタングステン（−）層４を２００
０〜３０００人程度コンタクト孔３内に選択成長し、そ
の上に配線層としてアルミニウム（Ａｌ）Ｊｉｉ ６を
基板全面に被着し、パターニングして配線する。Next, a tungsten (-) layer 4 with a thickness of 200 mm is added as a conductive layer.
Approximately 0 to 3,000 contacts are selectively grown in the contact hole 3, and aluminum (Al) Jii 6 is deposited on the entire surface of the substrate as a wiring layer thereon and patterned to provide wiring.
この例の場合、一層４の選択成長は２０００〜３０００
人程度成長するのが限度で、コンタクト孔をすべて埋め
込むことは出来ないので、段差被覆の改善にはあまり有
効ではない。In this example, the selective growth of layer 4 is 2000-3000
The growth limit is about the size of a human being, and it is not possible to fill all the contact holes, so it is not very effective in improving step coverage.
第４図は他の従来例によるコンタクト孔埋込構造を示す
基板断面図である。FIG. 4 is a cross-sectional view of a substrate showing another conventional contact hole filling structure.
図において、１はｐ型Ｓｉ基板、１）はｎ型拡散層であ
る。In the figure, 1 is a p-type Si substrate, and 1) is an n-type diffusion layer.
基板全面に絶縁層としてＤＰＳＧ層２を被着し、コンタ
クト孔３を開口する。A DPSG layer 2 is deposited as an insulating layer over the entire surface of the substrate, and a contact hole 3 is opened.
つぎに埋込層として多結晶珪素（ポリＳｉ）層５を、コ
ンタクト孔３を覆って基板全面に気相成長（ＣＶ Ｄ）
法により堆積する。Next, a polycrystalline silicon (poly-Si) layer 5 is grown as a buried layer by vapor phase growth (CVD) over the entire surface of the substrate, covering the contact hole 3.
Deposited by method.
つぎに、基板の平坦化エツチングを行いコンタクト孔３
内にのみポリＳｉ層５を残す。Next, the contact hole 3 is etched to flatten the substrate.
The poly-Si layer 5 is left only inside.
平坦化エツチングはドライエツチングを用いて、ポリＳ
ｉ層５の表面よりエツチングしてゆき、ＤＰＳＧ層２を
露出させるまで行う。For flattening, dry etching is used to flatten polyS.
Etching is continued from the surface of the i-layer 5 until the DPSG layer 2 is exposed.
この場合は、ポリＳｉ層５に不純物をドープして高導電
化するときの熱処理により、基板１に形成されたｎ型拡
散層１）が広がり、高集積化を阻害する。In this case, the heat treatment when doping the poly-Si layer 5 with impurities to make it highly conductive spreads the n-type diffusion layer 1) formed on the substrate 1, which impedes high integration.
また、平坦化エツチングの際にコンタクト孔３内のポリ
Ｓｉ層５をオーバエツチングして基板ｌを露出させ、基
板１に損傷を与えることがある。Further, during planarization etching, the poly-Si layer 5 in the contact hole 3 may be overetched, exposing the substrate 1, which may cause damage to the substrate 1.
コンタクト孔内に導電層を埋め込み、その上に配線層を
形成する場合は、導電層を厚く被着出来ないため配線層
の段差被覆が悪くなり、デバイスの信頼性を阻害する。When a conductive layer is buried in a contact hole and a wiring layer is formed thereon, the conductive layer cannot be deposited thickly, resulting in poor step coverage of the wiring layer, which impairs the reliability of the device.
またＣＶＤ法により多結晶半導体層を厚く被着してコン
タクト孔を埋め込んだ場合は、埋込層へのドープの際の
熱処理により、半導体基板に悪影響をあたえるという欠
点を有する。Furthermore, when a contact hole is filled by depositing a thick polycrystalline semiconductor layer using the CVD method, there is a drawback that heat treatment during doping of the buried layer adversely affects the semiconductor substrate.
上記問題点の解決は、半導体基板（１）上に被着された
絶縁層（２）を開口して形成したコンタクト孔（３）内
に導電層（４）を該コンタクト孔（３）が埋まらないよ
うに被着し、該導電層（４）上に多結晶半導体層（５）
を堆積して、該コンタクト孔（３）内に該多結晶半導体
層（５）を埋め込む本発明による半導体装置の製造方法
により達成される。The solution to the above problem is to fill the contact hole (3) by filling the conductive layer (4) into the contact hole (3) formed by opening the insulating layer (2) deposited on the semiconductor substrate (1). a polycrystalline semiconductor layer (5) on the conductive layer (4);
This is achieved by the method of manufacturing a semiconductor device according to the present invention, which embeds the polycrystalline semiconductor layer (5) in the contact hole (3) by depositing the polycrystalline semiconductor layer (5).
前記導電層（４）に−等の高融点遷移金属を用いる場合
は、特に効果がある。It is particularly effective when a high melting point transition metal such as - is used for the conductive layer (4).
本発明は、あらかじめコンタクト孔内に薄り導電層を敷
いておき、その後ＣＶＤによりコンタクト孔内をポリＳ
ｉで埋めつくすため、コンタクト孔の段差被覆は改善さ
れる。In the present invention, a thin conductive layer is laid in advance in the contact hole, and then the inside of the contact hole is filled with polysilicon by CVD.
Since the contact hole is completely filled with i, the step coverage of the contact hole is improved.
また、埋め込むポリＳｉ層の厚さは導電層の厚さだけ小
さくなり、そのためドープの温度、時間が小さくてすみ
、また−等の高融点遷移金属層の存在により、不純物原
子の基板内拡散層への突き抜け、基板内拡散層の広がり
等が防止できる。In addition, the thickness of the poly-Si layer to be embedded is reduced by the thickness of the conductive layer, so the temperature and time for doping are small, and the presence of the high melting point transition metal layer, such as -, creates a diffusion layer for impurity atoms in the substrate. It is possible to prevent penetration of the substrate, spread of the diffusion layer within the substrate, etc.
第１図（１）〜（４）は本発明の一実施例によるコンタ
クト孔埋込方法を工程順に示す基板断面図である。FIGS. 1(1) to 1(4) are cross-sectional views of a substrate sequentially showing a contact hole filling method according to an embodiment of the present invention.
第１図（１）において、１はｐ型Ｓｉ基板、１）は基板
１に形成されたｎ型拡散層である。In FIG. 1(1), 1 is a p-type Si substrate, and 1) is an n-type diffusion layer formed on the substrate 1.
基板全面に絶縁層として叶ＳＧ層２を被着し、ｎ型拡散
層１）上にコンタクト孔３を開口する。A SG layer 2 is deposited as an insulating layer over the entire surface of the substrate, and a contact hole 3 is opened on the n-type diffusion layer 1).
つぎに、導電層として讐層４を２０００〜３０００人程
度コンタクト孔３内に選択成長する。Next, about 2,000 to 3,000 conductive layers 4 are selectively grown in the contact holes 3.
−の選択成長条件は、反応ガスとして六弗化タングステ
ン（ＷＦ、） 、キャリアガスとして水素（Ｈ２）を用
い、これらを０．３ Ｔｏｒｒに減圧して３ｏｏ〜３５
゜℃で熱分解して行う。The selective growth conditions for - are tungsten hexafluoride (WF) as a reaction gas and hydrogen (H2) as a carrier gas, and the pressure is reduced to 0.3 Torr to produce a
This is done by pyrolysis at ℃.
第１図（２）において、多結晶半導体層としてポリＳｉ
層５を、ＣＶＤ法によりコンタクト孔３内を埋め込んで
基板全面に堆積する。In FIG. 1(2), poly-Si is used as the polycrystalline semiconductor layer.
A layer 5 is deposited over the entire surface of the substrate by filling the inside of the contact hole 3 using the CVD method.
第１図（３）において、基板の平坦化エツチングを行い
コンタクト孔３内にのみポリＳｉ層５を残すようにする
。In FIG. 1(3), the substrate is flattened and etched so that the poly-Si layer 5 remains only in the contact hole 3.
平坦化エツチングはドライエツチングを用いて、ポリＳ
ｉ層５の表面よりエツチングしてゆき、ＤＰＳＧＪｉｉ
２の表面が露出するまで行う。For flattening, dry etching is used to flatten polyS.
It is etched from the surface of the i-layer 5, and the DPSGJii
Repeat until surface 2 is exposed.
ポリＳｉのドライエツチングは、リアクティブイオンエ
ツチング（ＲＩ Ｂ）法による。エツチングガスとして
四弗化炭素（ＣＦ４）を用い、これを約０、Ｉ Ｔｏｒ
ｒに減圧して、周波数１３．５６ＭＦｌｚの電力をウェ
ハあたり２０囲程度加えて行う。Dry etching of poly-Si is performed by reactive ion etching (RIB). Carbon tetrafluoride (CF4) was used as an etching gas, and the etching gas was heated to about 0, I Tor.
The pressure is reduced to r, and power with a frequency of 13.56 MFlz is applied for about 20 cycles per wafer.
第１図（４）において、配線層としてＡＩ層６を基板全
面に被着し、パターニングして配線する。In FIG. 1(4), an AI layer 6 as a wiring layer is deposited on the entire surface of the substrate, patterned, and wired.
第２図（１）〜（３）は本発明の他の実施例によるコン
タクト孔埋込方法を工程順に示す基板断面図である。FIGS. 2(1) to 2(3) are cross-sectional views of a substrate showing a contact hole filling method according to another embodiment of the present invention in order of steps.
第２図（１）において、１はｐ型Ｓｉ基板、１）は基板
１に形成された電界効果トランジスタ（ＦＥＴ）のソー
ス、ドレイン領域でｎ１型拡散層、１２はフィールド−
酸化膜で二酸化珪素（ＳｉＯ□）ｌｉ、 １３はゲート
酸化膜で５ｉＯｚ層、１３′はＳｉ０１層、１４はゲー
ト電極でポリＳｉ層である。In FIG. 2 (1), 1 is a p-type Si substrate, 1) is an n1-type diffusion layer in the source and drain regions of a field effect transistor (FET) formed on the substrate 1, and 12 is a field-type Si substrate.
The oxide film is silicon dioxide (SiO□)li, 13 is a gate oxide film, which is a 5iOz layer, 13' is a Si01 layer, and 14 is a gate electrode, which is a poly-Si layer.
つぎに、導電層として一層４を２０００〜３０００人程
度ソース、ドレイン領域のｎ＋型型数散層１）上選択成
長する。Next, about 2000 to 3000 layers of a conductive layer 4 are selectively grown on the n+ type scattered layer 1) in the source and drain regions.
第２図（２）において、基板全面に絶縁層としてＤＰＳ
Ｇ層２を被着する。In Figure 2 (2), DPS is used as an insulating layer on the entire surface of the substrate.
Apply G layer 2.
つぎに、コンタクト孔３を開口しｎ型拡散層１）上に被
着されたＷＩｉ４の表面を露出する。Next, the contact hole 3 is opened to expose the surface of the WIi 4 deposited on the n-type diffusion layer 1).
第２図（３）において、多結晶半導体層としてポリ５３
層５を、ＣＶＤ法によりコンタクト孔３内を埋め込んで
基板全面に堆積する。In FIG. 2 (3), poly 53 is used as a polycrystalline semiconductor layer.
A layer 5 is deposited over the entire surface of the substrate by filling the inside of the contact hole 3 using the CVD method.
つぎに、基板の平坦化エツチングを行いコンタクト孔３
内にのみポリＳｉ層５を残すようにする。Next, the contact hole 3 is etched to flatten the substrate.
The poly-Si layer 5 is left only inside.
つぎに、配線層としてＡＩ層６を基板全面に被着し、バ
ターニングして配線する。Next, an AI layer 6 as a wiring layer is deposited on the entire surface of the substrate and patterned to form wiring.
実施例においては、導電層として高融点遷移金属の内−
を用いたが、これの代わりにチタン（Ｔｉ）、タンタル
（Ｔａ）等を用いてもよい。In the examples, the conductive layer is made of high melting point transition metals.
was used, but titanium (Ti), tantalum (Ta), etc. may be used instead.
以上詳細に説明したように本発明によれば、まずコンタ
クト孔内に導電層を敷き、その上に多結晶半導体層を埋
め込むことにより、コンタクト孔上の配線層の段差被覆
を改善し、デバイスの信頼性を向上する。As explained in detail above, according to the present invention, first a conductive layer is laid in the contact hole, and a polycrystalline semiconductor layer is buried thereon, thereby improving the step coverage of the wiring layer over the contact hole and improving the device. Improve reliability.
この際、導電層の存在により、多結晶半導体層へのドー
プの際の熱処理は低温、短時間ですみ、半導体基板に悪
影響をあたえるという欠点は除外される。At this time, due to the presence of the conductive layer, the heat treatment for doping the polycrystalline semiconductor layer can be performed at a low temperature and in a short time, eliminating the disadvantage of adversely affecting the semiconductor substrate.
第１図（１）〜（４）は本発明の一実施例によるコンタ
クト孔埋込方法を工程順に示す基板断面図、第２図（１
）〜（３）は本発明の他の実施例によるコンタクト孔埋
込方法を工程順に示す基板断面図、第３図は従来例によ
るコンタクト孔埋込構造を示す基板断面図、
第４図は他の従来例によるコンタクト孔埋込構造を示す
基板断面図である。
図において、
１はｐ型Ｓｉ基板、
１）は基板１に形成されたｎ型拡散層、１２はフィール
ド酸化膜でＳｉＯ□層、１３はゲート酸化膜でＳｉｎ、
層、
１３′はＳｉｎ、層、
１４はゲート電極でポリＳｉ層、
２は絶縁層でＤＰＳＧ層、
３はコンタクト孔、
４は導電層で一層、
５は多結晶半導体層でポリＳｉ層、
６は配線層でＡ１層
ηｑげ３月１こよ−る埋込方法
率 １０
率２旧
峯４−１２ＪFIGS. 1 (1) to (4) are cross-sectional views of a substrate showing the contact hole filling method according to an embodiment of the present invention in order of steps, and FIG.
) to (3) are cross-sectional views of a substrate showing a contact hole filling method according to another embodiment of the present invention in the order of steps, FIG. 3 is a cross-sectional view of a substrate showing a contact hole filling structure according to a conventional example, and FIG. 4 is another example. FIG. 2 is a cross-sectional view of a substrate showing a contact hole filling structure according to a conventional example. In the figure, 1 is a p-type Si substrate, 1) is an n-type diffusion layer formed on the substrate 1, 12 is a field oxide film, which is an SiO□ layer, 13 is a gate oxide film, which is made of Si,
13' is a Sin layer, 14 is a gate electrode and is a poly-Si layer, 2 is an insulating layer and is a DPSG layer, 3 is a contact hole, 4 is a conductive layer and is a single layer, 5 is a polycrystalline semiconductor layer and is a poly-Si layer, 6 is the wiring layer and A1 layer ηq is buried in March 1.
Claims (2)
開口して形成したコンタクト孔（３）内に導電層（４）
を該コンタクト孔（３）が埋まらないように被着し、該
導電層（４）上に多結晶半導体層（５）を堆積して、該
コンタクト孔（３）内に該多結晶半導体層（５）を埋め
込む ことを特徴とする半導体装置の製造方法。(1) A conductive layer (4) is placed in a contact hole (3) formed by opening an insulating layer (2) deposited on a semiconductor substrate (1).
is applied so as not to fill the contact hole (3), a polycrystalline semiconductor layer (5) is deposited on the conductive layer (4), and the polycrystalline semiconductor layer (5) is deposited in the contact hole (3). 5) A method for manufacturing a semiconductor device, characterized by embedding.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the conductive layer (4) is made of a high melting point transition metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6439685A JPS61222224A (en) | 1985-03-28 | 1985-03-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6439685A JPS61222224A (en) | 1985-03-28 | 1985-03-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61222224A true JPS61222224A (en) | 1986-10-02 |
Family
ID=13257114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6439685A Pending JPS61222224A (en) | 1985-03-28 | 1985-03-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61222224A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62235774A (en) * | 1986-04-07 | 1987-10-15 | Matsushita Electronics Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6046024A (en) * | 1983-08-24 | 1985-03-12 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-03-28 JP JP6439685A patent/JPS61222224A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6046024A (en) * | 1983-08-24 | 1985-03-12 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62235774A (en) * | 1986-04-07 | 1987-10-15 | Matsushita Electronics Corp | Semiconductor device |
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