JPS6046024A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the improper contact due to the disconnection of wirings by locally forming previously a primary layer on the first conductive layer, laminating the second conductive layer on the primary layer, and integrating both to be homogeneous, thereby forming a layer to become a leading electrode. CONSTITUTION:A contacting hole 5 is opened by an RIE method or the like on the prescribed region of a field oxidized film 2 of an element region. Then, a privary layer 6 made of polycrystalline Si is formed in the hole 5 and on the film 2. Then, plasma etching is formed on the surface of the layer 6, and the primary layers 6a, 6b are allowed to remain only in the hole 5 and on the periphery of a stepwise portion 5. Then, the second conductive layer 7 is formed on the layers 6a, 6b and the film 2. At this time, a reverse sputter etching is, for example, performed to activate it, thereby securing the layer 7 made of aluminum or the like. Then, heat treatment is performed, the remaining layers 6a, 6b and the layer 7 are integrated to form an electrode layer 8 made of aluminum alloy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the formation of wiring layers in semiconductor devices, and particularly relates to a buried electrode structure.

[Technical background of the invention and its problems]

BACKGROUND ART Conventionally, as a means for forming an extraction electrode through a contact hole provided on a semiconductor substrate, a method for forming an extraction electrode is deposited without heating the semiconductor substrate. The purpose of heating the semiconductor substrate in this manner is to promote surface diffusion of the extraction electrode forming material, such as aluminum, and to sufficiently fill the contact hole with the material. The contact hole is usually R,1,E (
It is formed using reactive ion etching (reactive ion etching) technology to have an opening size of approximately 3 μm and a steep inner surface.

When this heat treatment is used in combination, when the contact hole is relatively thick, about 3 μm in diameter, it is possible to deposit the lead-out electrode forming portion with good step force coverage. However, when the size of the contact hole is less than 2 μm, the step coverage of the deposited layer becomes poor at the inner wall surface. Particularly, when the size of the contact hole is 1 μm or less, there is a problem in that it is not possible to deposit the member for forming the extraction electrode.

Furthermore, in the process of heat treatment to establish ohmic contact at the contact portion where the aluminum wiring and the silicon substrate are in direct contact, a phenomenon has occurred in which silicon diffuses into the aluminum.

Therefore, at the interface between silicon and aluminum,
A pit is formed on the silicon side, and aluminum gets into it. If the P-N junction is shallow with a planar structure, the depth of this bit reaches the junction surface, resulting in a system where the withstand voltage of the P-N junction deteriorates. However, there was a drawback that the reverse leakage current increased. In order to solve this drawback, Japanese Patent Laid-Open No. 147981/1983 discloses a method in which a wiring layer is formed by depositing polycrystalline silicon over the entire diameter of the contact hole, then depositing aluminum, and then turning the contact hole. but,
With this method, since polycrystalline silicon exists in the entire area directly under the aluminum layer, even after subsequent processing, only a portion of the silicon in the polycrystalline silicon melts into the aluminum, and the polycrystalline silicon layer and aluminum layer are combined. Only a portion of the contact surfaces of the layers are alloyed. Since contact with the substrate is made through the remaining polycrystalline silicon, it has the disadvantage that contact resistance cannot be reduced. Furthermore, in order to ensure the connection even if there is misalignment between the contact hole and the diffusion layer, impurities of the same conductivity type as the diffusion layer are introduced into the polycrystalline silicon. P channel and N
O[
Purpose of the Invention The present invention provides a method for manufacturing a semiconductor device, which prevents contact failures such as wire breakage and reliably extracts an extraction electrode from a fine contact hole, thereby producing a highly reliable semiconductor device at a high yield. Its purpose is to provide.

[Summary of the invention]

In the present invention, a base layer is locally formed on the first conductive layer in advance, and a second conductive layer is laminated on the base layer to make the two integrally homogeneous, thereby forming a layer that will become an extraction electrode. However, this is a method for manufacturing a semiconductor device that can obtain a highly reliable semiconductor device having a lead-out electrode that prevents poor contact due to disconnection or the like at a high yield of 9.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS.
This will be explained with reference to D).

First, a field oxide film 2 surrounding an element region is formed in a predetermined region of a semiconductor substrate 1. As shown in FIG. Next, a dirt oxide film is formed on the element region, and a predetermined number of four turns of dirt electrodes 3 are formed on the dirt oxide film. Next, an oxide film covering the dirt electrode 3 is formed on the element region and is oxidized integrally with the field oxide film 2. The field lH support 2 above the dirt electrode 3 has a stepped portion 4 raised by the thickness of the r-) electrode 3. For example, R. 1. E (Reactive Ion
A contact hole 5 having a diameter of about 1 μm is opened by the Itching method. Then, for example, reduced pressure C-V. D(
Chemical Vapor Depositio
n) Next, a base layer 6 made of polycrystalline silicon is formed in the contact hole 5 and on the field oxide film 2 (see FIG. 1(A)). Here, as the material of the base layer 6, a material that is alloyed or solid-solved with silicon or aluminum may be used. In addition to the reduced pressure C, V, and D methods, any means for forming the base layer 6 may be used as long as it can form a smooth base layer 6 within the fine contact hole 5 or in the steep stepped portion 4. Further, it is desirable to introduce, for example, a P-type impurity into the base layer 6 made of silicon or the like in order to facilitate alloying with a second conductive layer 7, which will be described later.

Next, a plasma etching process is performed on the surface of the base layer 6, so that the base layers 6a and 6b remain only in the contact hole 5 and around the stepped portion 4 (see FIG. 2B).

Next, a second conductive layer 7 made of, for example, aluminum and having a thickness of about 1 μm is formed on the remaining base layers 6a, 6b and field oxide film 2 (see FIG. 3C). At this time,
For example, it is desirable to carry out an activation treatment by reverse sputter etching to reliably fix the second conductive layer 7 made of aluminum or the like. When forming this second conductive layer 7, there is no need to perform any heat treatment. As the second insulation layer 7, other than aluminum, an aluminum alloy or the like may be used. The point is that the base layer 6 is formed by the heat treatment described below.
Any material may be used as long as it is integrally made of the same material as a and 6b. Then, for example, 450°
The base layer 6a that remained after being heat-treated with C for 30 minutes.

6b and the second conductive layer 7 are integrated to form an electrode layer 8 made of an aluminum alloy (see (D) in the same figure).

Thereafter, the electrode layer 8 is subjected to i9 turning treatment to obtain an extraction electrode having a predetermined shape. Here, the base layers 6a, 6b and the second
The heat treatment for integrating the conductive layer may be performed after forming the extraction electrode by patterning.

According to such a method of manufacturing a semiconductor device, the base layer 6a remaining in the contact hole 5 and the stepped portion 4 in advance,
Since the lead-out electrode is formed from the electrode layer 8 integrated with the electrode 6b, the resistance of the lead-out electrode can be significantly reduced compared to the conventional method, and the electrode forming layer 7 has good stepping force distribution to prevent contact failures due to breakage, disconnection, etc. The extraction electrode can be easily extracted from the fine contact hole 5. It also prevents aluminum from penetrating the substrate, which has been a problem in the past. Therefore, a highly reliable semiconductor device can be obtained. Furthermore, when forming the second conductive layer 7, heat treatment is not necessarily required, so workability can be improved, and since no equipment for heat treatment is required, manufacturing costs can be reduced. As a result, manufacturing yield can be increased.

In addition, as shown in FIG. 2, inside the contact hole 5,
A barrier layer 9 made of Ti or PT silicide may be formed to prevent the underlying layer 6a and the semiconductor substrate 1 from reacting.

Further, as shown in FIG. 3, an alloying promoting layer 10 made of titanium or the like is formed on the second conductive layer 7V3 so that alloying easily occurs between the base layer 6a and the second conductive layer 7. Good〇Next, an example will be described in which the method of the present invention is applied to manufacturing a semiconductor device consisting of a complementary MO8FET.

First, as shown in Figure 4 (4), for example, if the specific resistance is 7 to 8
Ω・I have a P-type diffusion layer 21 in my N-type semiconductor substrate 20, and a P-w formed in this semiconductor substrate 20.
A device having an N-type diffusion layer 23 in the ELL region 22 is prepared. These diffusion regions become, for example, source/drain regions forming an FET element. Here, the impurity concentration of these diffusion regions was set to about 1020 crn-'.

In addition, the P-type diffusion region is formed using a groin to a diffusion depth of approximately 0.5 μm, and the N-type diffusion region is formed using arsenic to a diffusion depth of approximately 0.3 μm.
It was formed to a diffusion depth of μm. Furthermore, polycrystalline silicon was used as the dart metal constituting these FET elements.

A 5in2/PSG (Phosph) base layer is formed on the exposed surface of the semiconductor substrate 20 by vapor phase growth.

5ilicate Glass) F12 J@membrane 24 was formed to a thickness of about 1 tone. Next, RIE (Reactive Ion Etchi) is applied to this 5in2/PSG film 24.
Contact holes 26, 27, and 28 communicating with the P channel 2, the N channel 23, and the wiring 25 are opened by selectively etching using the NG) method. Here, the contact holes 26 . . . 28 are set to have a size of about 1.2 μm full square. Further, the 5IO2/PSG film 24 is usually 95mm thick before opening the contact holes 26...28.
Melting treatment is performed at a high temperature of 0 to 1000°C. However, this melting temperature is set to be as low as possible and for a short time so as to make the bonding depth shallow in order to achieve finer ligatures. For this reason, the PSG IIa 24 is not sufficiently melted, and as shown in the figure, the stepped portions of the wiring 26 made of polycrystalline silicon tend to have an inverted chi 79 shape or a steep shape.

Next, the contact holes 26...28 are formed.
A W film 29 is formed on the entire exposed surface of the i O2/PSG film 24.
is formed to a thickness of about 1000× by sputtering (see figure (B)). Here, to form wB2<2g, a vapor phase growth method may be used in addition to the sputtering method. In the case of the vapor phase growth method, since the W film 29 can be selectively deposited on the exposed surface of the silicon substrate, the process can be simplified.

After forming the W film 29, as shown in FIG.
℃ heat treatment for about 30 minutes, contact hole 26,
A WS 12 film 30 was formed within 27.28. Then,
The unreacted W film 29 was removed by chemical treatment such as boiling in aqua regia.

Next, as shown in FIG. CD), a polycrystalline silicon film with a thickness of about 70,001 cm was deposited on the surface of the semiconductor substrate 20 containing PSGg24 by using silane gas (SiH2) at a substrate temperature of 600° C. as shown in FIG. 31 was formed. The deposition rate of polycrystalline silicon at this time is approximately 100 i/mi
It was n. Here, when the polycrystalline silicon film 31 is formed by the low pressure CVD method, it is possible to form the polycrystalline silicon film 31 very well, so it is easy to form the polycrystalline silicon film 31 even in the minute contact holes 26...28 and in the places with reverse tapers. It is capable of depositing crystalline silicon.

Next, the polycrystalline silicon film 31 is etched by exposing it to a plasma atmosphere containing, for example, fluorine gas as a main component (see the figure (see the odor)).

Through this etching process, the polycrystalline silicon film 3 is completely removed to a thickness of 7000×, and the SIO2/P SG film 2 is removed.
Polycrystalline silicon filling portions 32 . . . 35 were formed in the recesses of No. 4. Note that this etching process may be performed isotropically or anisotropically.

Next, as shown in the same figure (F), S
i 02 /P A second conductive layer is formed on the SG film 24.
The thickness of the T film 36 is approximately 1 mm using the magnetron snorting method.
A μ door was formed. Next, this was subjected to heat treatment for 30 minutes in a forming gas at 450°C.

Through this heat treatment, an alloying reaction of At-3t occurs between the At film 36 and the polycrystalline silicon filling portions 32...35, and Sl diffuses into the At film 36, and the region where Si was present is replaced with At was substituted and infiltrated, and the polycrystalline silicon filling portions 32 . . . 35 and the At film 36 were able to be homogenized as an At-8+ alloy film 37, as shown in FIG.

In this way, the aluminum penetrates into the Silkowka Al film 36 in the locally provided polycrystalline silicon filling portions 32...35, and the polycrystalline silicon and aluminum become homogeneous. Therefore, so-called alloy spikes do not occur, and the newly formed At-8+ alloy film 37 and semiconductor substrate 2
The contact with o will also be good. Further, the polycrystalline silicon filling portions 32...35 are filled with fine contact holes 26...
27 and then integrated into the At-3+ alloy film 37, it is possible to prevent contact failures such as wire breakage and to reliably form lead-out electrodes through the fine contact holes 26...27. As a result, semiconductor devices with high reliability can be obtained at a high yield.

Next, the polycrystalline silicon filling portions 32...35 and the At film 3
The alloy reaction of At-8+ that occurs between 6 and 6 will be explained.

As mentioned above, the diffusion rate (diffusion coefficient D) of St into the At film 36 at a temperature of 450° C. is 8×1O−9cIIL.
2/sec. Therefore, when heat treatment is performed at 450''C for 30 minutes, Si diffuses into the Al film 36 by a distance of V plane=V sieve 30 cm−=38 μm.

In other words, 1.44μηL embedded in the contact holes 26...28 of 1.2X1.2X1μm3
3, 5L40 is πx(38)2 as shown in Figure 5.
It can be diffused into At having a volume of 4, where μηL3=45341tm3. The concentration of St at that time is 0.0
It will be 3%.

On the other hand, FiJ f81 in another Al at 450℃
, as is clear from the so-called binary phase diagram, +0.48ifit
It is Chi. This value is the value in bulk, and generally thin B'
), the solid solubility limit increases. Also, the solid solubility limit mentioned above is shown in terms of electric current, but since the specific gravity of Al and Si is almost the same, it is safe to assume that the volume and volume are the same. . Well, 45
At 0''C, Si can form a solid solution in the At film 36 up to 0.48%, and the diffusion rate of Si in the At film is sufficiently fast, so that it is buried in the contact holes 26...28. ] is all diffused into the At film 36 and homogenized.The polycrystalline silicon buried in the contact holes 26...28 and the S of the semiconductor substrate 20
Since a barrier layer consisting of 3 layers of WS12 is formed at the interface between i and the polycrystalline silicon that constitutes the dirt metal, there is no effect even if these homogenization treatments are performed excessively. do not have. The reason why the substrate surface is sputter-etched with Ar ions in the same vacuum immediately before sputter-depositing the At film 30 is to remove oxides and adsorbed substances formed on the polysilicon surface. This is because if these inclusions exist between the polycrystalline silicon filling portions 32 . . . 35 and the At film 36, mutual diffusion of At-81 is inhibited. Moreover, the polycrystalline silicon filling part 32...
The polycrystalline silicon forming 35 may be undoped with impurities, but it is better if it is doped with impurities.
It becomes easier to be dispersed in the AtAt film.

In particular, it has been empirically confirmed that when poron is doped as an impurity, diffusion becomes even easier. Depending on the case, the polycrystalline silicon filling portions 32 . . . 35 may be formed of polycrystalline silicon doped with impurities such as poron.

In addition, the Si in the contact holes 26...28 is replaced by At.
If it remains without being completely replaced and diffused, there is a problem that the contact resistance between the diffusion regions such as the source and drain or the dirt metal and the wiring formed by the At film 36 becomes high, and that electromigration occurs. In other words, when At and Si, which have different electrical resistances, are in contact with each other and a DC current is passed through the contact at a high current density, the At film 3
A phenomenon of diffusion (electromigration) occurs in Al-8i, and in this case, vacancies are generated at the Al-8i interface. This increases contact resistance and eventually causes an open failure.

In order to avoid such problems, it is desirable that all the Si in the contact holes 26...28 be made homogeneous with %Al-13+ alloy. As a result, high reliability can be maintained over a long period of time.

〔Effect of the invention〕

As explained above, the main advantage of the present invention is that the underlying layer, that is, polycrystalline silicon, is locally formed on the first conductive layer. That is, in the conventional technique of forming polycrystalline silicon over the entire surface, polycrystalline silicon is present in excess of aluminum, so that the silicon in polycrystalline silicon does not entirely penetrate into aluminum. For this reason, aluminum has the advantage of not forming alloy spikes on the substrate, but on the other hand, the part where this wiring layer made of polycrystalline silicon and aluminum contacts the semiconductor substrate is only polycrystalline silicon, so it has good electrical properties. It is difficult to get in touch with them. According to the present invention, a base layer such as polycrystalline silicon is locally formed. Therefore, all of the silicon in the polycrystalline silicon penetrates into the subsequently formed second conductive layer, for example aluminum, and the polycrystalline silicon and aluminum become homogeneous. Therefore, the conventional problem of aloise/matric acid does not occur, and since the material is made homogeneous, the contact with the semiconductor substrate is also good. Furthermore, since the underlying layer is locally buried, even very fine contact holes can be filled. Furthermore, since the materials are then homogenized in one piece, contact failures such as wire breakage can be prevented, and lead-out electrodes can be reliably formed from fine contact holes. As a result, a semiconductor device with high reliability and high yield can be provided.

[Brief explanation of the drawing]

FIGS. 1(4) to 1(D) are explanatory diagrams showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. FIG. 3 is a cross-sectional view of a semiconductor device obtained by using the method of the present invention in combination with the step of forming a barrier layer and an alloying promoting layer. FIG. The figures (G) to (G) are explanatory diagrams showing the process order of an embodiment in which the method of the present invention is applied to the manufacture of a semiconductor device made of complementary MO8IT, and Fig. 5 shows the solid solubility limit of S+ in the contact hole. It is an explanatory diagram showing a field. 1... Semiconductor substrate, 2... Fee/Redo oxide film,
3... Dirt electrode, 4... Step portion, 5... Contact 7j=-le, 6... Base layer, 7... Second conductive layer, 8... Electric 4'Ez layer, 9... Barrier layer, 10...
・Alloying promotion layer, 20...semiconductor substrate %2no...P
Channel, 22...p-well region, 23-N channel 1. ? 4-pscll! J, 25... Wiring,
26.27.28...Contact hole, 29...
W film, 30...WS l 2 film, 31... Polycrystalline silicon film, 32.33.34.35... Polycrystalline silicon filling part, 36... At film, 37... At- 8 membrane alloy membrane. Applicant's agent, patent attorney Takehiko Suzue! Figure 1 (A) (B) Figure 1 (D)

Claims (6)

[Claims] (1) A step of locally forming a base layer on the first conductive layer, a step of forming a second conductive layer on the base layer, and a step of making the base layer homogeneous with the second conductive layer. 1. A method for manufacturing a semiconductor device, comprising the step of heating. (2) The step of locally forming a base layer on the first conductive layer includes forming an insulating layer having at least a recessed portion exposing the first conductive layer on the first conductive layer, and forming the base layer on the first conductive layer. A step of forming a base layer on the entire surface of the insulating layer including the exposed portion of the layer, removing a predetermined thickness of the base layer from the surface for 3 times to leave the base layer in the recess, and removing the remaining base layer. A patented method for manufacturing a semiconductor device characterized by: (3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the first conductive layer is a semiconductor substrate. (4) The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the material of the underlayer is made of silicon or an element that becomes homogeneous with aluminum. (5) The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the material of the second conductive layer is aluminum or an aluminum alloy. (6) The semiconductor device according to any one of claims 2 to 5, wherein a barrier layer for controlling reaction with the base layer and the second conductive layer is formed in the recess. Production method.