JPH0240913A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To secure the conductivity of a contact hole and to realize the highly reliable contact hole by a method wherein, after silicide layers and a poly Si layer are etched back to flatten the aperture of the contact hole, the surface of the poly Si layer, whose aperture is exposed, is covered with a high melting point metal layer or its silicide layer. CONSTITUTION:An interlayer insulating film 7 is adhered on a field insulating film 5 adhered on a semiconductor substrate 1 through an oxide film 6. A first- layer wiring part 8 which is used as a bit line is formed by patterning on an upper layer of this film 7 and is connected to a high-concentration diffused layer 4 in the substrate 1 through a contact hole 9. This hole 9 is filled with a poly Si layer 11 and silicide layers 10a and 10b, the layer 11 consisting of a non-conductive material is covered with the layers 10a and 10b consisting of a conductive material and the wiring part 8 is formed into a two-Iayer structure, which consists of a barrier metal layer 8a consisting of TiN or the like and an AI layer 8b laminated on the surface of the layer 8a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and in particular to a technology that is effective when applied to burying contact holes for electrically connecting between a semiconductor substrate and wiring. It is something.

[Conventional technology]

As semiconductor devices become more highly integrated, the diameters of contact holes that electrically connect semiconductor substrates (hereinafter referred to as substrates) and wiring, and through holes that electrically connect multilayer wiring have become smaller. Its aspect ratio is also increasing. As a result, a serious problem arises in that the stamp coverage and film quality of a conductive film such as Aβ deposited in a contact hole (through hole) deteriorates, and the reliability of wiring deteriorates.

As a countermeasure, technology has been put into practical use that improves the step coverage of the conductive film by processing the cross-sectional shape of the contact hole into a tapered or stepped shape. There is even less space to do so.

Therefore, tungsten (W) embedding technology using selective CVD and AI embedding technology using bias sputtering are attracting attention.

The technology for embedding W using the selective CVD method is described, for example, in "Semiconductor World, March 1988 issue," published by Press Journal Co., Ltd., pages 43 to 44.

Also, regarding AI embedding technology using bias sputtering method, please refer to "Semiconductor World, 1988.
There is a description on pages 77 to 83 of ``February 2010 issue''.

[Problem to be solved by the invention] However, the W embedding technology using the selective CVD method has the following problems:
This technology is currently under development and has unresolved problems, such as the problem of W digging into the substrate and the problem of selectivity with the underlying layer.

On the other hand, AI embedding technology using bias sputtering method is
When applied to a contact hole with a high aspect ratio, there is a limit to the embedding ability, and since argon (Ar) is turned into plasma by applying a negative bias to the substrate, Ar in the implanted AI peritoneum is likely to be taken in. As a result, there are problems such as an increase in the resistance value of the AI film and a deterioration of the film quality.

Furthermore, damage to the substrate caused by Ar ions is also a drawback of the bias sputtering method.

As described above, there are still many problems to be solved with the selective CVD method for W and the bias sputtering method for Al.
(Mbit) M OS/Dynamic RAM (D
When applied to the manufacturing process of VLSIs having contact hole diameters on the submicron order, such as RAM) and 16 megabits MOS-DRAM, there is a problem in terms of reliability.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a highly reliable contact hole filling technique.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a silicide layer having a thickness sufficiently thin relative to the diameter of the contact hole is formed on the bottom and side walls of the contact hole using the CVD method, and then the inside of the contact hole is filled with polysilicon using the CVD method. Next, the silicide and polysilicon are etched back to flatten the opening of the contact hole, and then the surface of the polysilicon exposed in the opening is covered with a high melting point metal or its silicide to fill the contact hole. This is a method of manufacturing a semiconductor device.

[Effect]

If the silicide film formed by the CVD method is sufficiently thin relative to the diameter of the contact hole, it can be deposited faithfully to the cross-sectional shape of the contact hole.

Further, since polysilicon produced by the CVD method has very good step coverage, even a contact hole with a minute diameter can be completely buried inside the contact hole.

Furthermore, after etching back the silicide and polysilicon to planarize the opening of the contact hole, the surface of the polysilicon exposed in the opening is coated with a high melting point metal or its silicide, thereby improving the conductivity of the contact hole. is ensured.

Through the above steps, highly reliable contact hole filling is achieved.

〔Example〕

FIGS. 1(a) to 1(e) are enlarged cross-sectional views of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a main part of a semiconductor substrate obtained by the present invention.

The semiconductor device of this embodiment is a MOS-DRAM having a large capacity of, for example, 4 megabits.

As shown in FIG. 2, a buried barrier layer 2 in which p-type impurities are diffused is formed on a substrate 1 made of a p-type Si single crystal having a resistance value of, for example, 10Ω·clllI, and an n A low concentration diffusion layer 3 and a high concentration diffusion layer 4 in which a type impurity is diffused are formed.

A field insulating film 5 made of Sin is formed on the main surface of the substrate l by the LOCO3 method (selective oxidation method).
In a transistor formation region (not shown) surrounded by the field insulating film 5, a gate electrode and source/drain electrodes constituting a MOS/FET are formed.

An oxide film 6 made of SiO2 is formed on the upper layer of the field insulating film 5 by a CVD method or a thermal oxidation method.
Furthermore, a first interlayer insulating film 7 is formed on the upper layer. This interlayer insulating film 7 is made of, for example, BPSG (Boro Phospho 5il) deposited by CVD method.
icate Glass) was glass-flowed and flattened.

A first layer wiring 8 constituting a bit line is patterned on the upper layer of the interlayer insulating film 7, and is electrically connected to the high concentration diffusion layer 4 of the substrate 1 via a contact hole 9.

The inner bottom and side walls of the contact hole 9 are coated with WS.
A thin silicide layer tO made of i, MoSix, etc.
A polysilicon (polycrystalline silicon) 11 is buried in the center of the contact hole 9 surrounded by the silicide layer 10a. Further, on the surface of this polysilicon 11, a thin silicide layer 10b made of PtSIX or the like is formed.

That is, this contact hole 9 is made of polysilicon 1.
1 and silicide layers 10a and 10b, and has a structure in which polysilicon 11 made of a non-conductive material is covered with silicide layers 10a and 10b made of a conductive material.

The first layer wiring 8 is a barrier metal 8a made of TiN or the like.
A, i! on the surface of It has a two-layer structure in which layers 8b are laminated.

This is a configuration for preventing direct contact between the Af layer 8b and the silicide layers toa and 10b of the contact hole 9, since an alloying reaction occurs and the contact resistance increases.

In addition, since the first layer wiring 8 is made into two layers, its reliability is also improved. Furthermore, the Aβ calendar 8 of the first layer wiring 8
For b, an A2 alloy to which alloying elements such as Cu and 81 are added is used in order to improve its electromigration resistance and stress migration resistance.

A second interlayer insulating film 12 is formed above the first layer wiring 8 . This interlayer insulating film 12 is made of SOG (Spin O
It consists of a three-layer structure sandwiching glass.

The upper layer of the interlayer insulating film 12 includes the A1 layer 8b of the first layer wiring 8.
A second wiring layer 13 made of an A1 alloy having the same composition is patterned and electrically connected to a word line or the like in a transistor formation region via a through hole (not shown).

A passivation film 14 is formed on the upper layer of the second layer wiring 13 . This Pason Vanillon film 14 has a two-layer structure of, for example, 5in2 deposited by CVD method and S 1 3N4 deposited by the same CVD method.

Next, a process of filling a contact hole 9 connecting the first layer wiring 8 and the high concentration diffusion layer 4 of the substrate 1 is shown in FIGS.
This will be explained using (e).

First, a photoresist pattern 15 is formed on the interlayer insulating film 7, and a contact hole 9 with a substantially vertical cross section is etched by anisotropic etching such as reactive ion etching (RIE).
form. The diameter of this contact hole 9 is, for example, about 0.8 μm.

Next, phosphorus ('P) and arsenic (AS) are added from above the substrate l.
By implanting n-type impurity ions such as, a high concentration diffusion layer 4 is formed in a part of the low concentration diffusion layer 3 exposed at the bottom of the contact hole 9 (FIG. 1(a)).

Next, after removing the photoresist pattern 15, CVD
A silicide film 16 is deposited on the surface of the substrate 1 using a method. Here, the tungsten silicide film is deposited using a mixed gas of W F s and 5iHs, but other 7
A lycide film may also be used. The thickness of this silicide film 16 is
It should be sufficiently thin compared to the diameter of contact hole 9 (
For example, about 300 nm). In this way, silicide l110a that is faithful to the cross-sectional shape of the contact hole 9 is formed on the bottom and side walls of the contact hole 9.

Next, after the substrate 1 is annealed to lower the resistance of the silicide film 16, polysilicon 11 is deposited on the surface of the substrate 1 using the CVD method. Polysilicon 1 deposited by CVD method
1 has very good step coverage, so by making the film thickness of polysilicon 11 sufficiently thick, the inside of contact hole 9 can be completely filled with polysilicon 11 (FIG. 1 (c)). .

Next, the silicide film 16 and polysilicon 11 are etched back to planarize the opening of the contact hole 9.

As a result, the silicide layer 10a is exposed at the periphery of the opening of the contact hole 9, and the polysilicon 11 is exposed at the center (FIG. 1(C)). Note that when flattening the opening of the contact hole 9, the polysilicon 1
The silicide film 16 may be etched back in advance before depositing the polysilicon 11, and then the deposited polysilicon 11 may be further etched back.

Next, a thin film made of a transition metal such as PT (platinum) is deposited on the surface of the substrate 1 using a sputtering method.
By performing annealing at 0 to 600[deg.] C., the surface of polysilicon 11 exposed at the opening of contact hole 9 is silicided with this transition metal. Thereafter, by dissolving and removing the transition metal thin film deposited on the surface of the substrate l using aqua regia or the like, PtSi is formed on the surface of the polysilicon 11.
A thin silicide layer 10b consisting of the following is formed (FIG. 1(d)).

After filling the contact hole 9 in this manner, the first layer wiring 8 having a two-layer structure in which the barrier metal 8a and the AJ layer 8b are laminated is patterned to connect the substrate l and the first layer wiring 8 to the contact hole. 10 (FIG. 1(e)).

As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.

For example, in the above embodiment, a silicide layer is formed on the surface of polysilicon exposed at the opening of the contact hole, but the invention is not limited to this. For example, a high melting point metal such as W is formed by selective CVD method. The conductivity of the surface of polysilicon may be ensured by adhering it to the exposed surface of polysilicon. Note that in this case, the first layer wiring does not necessarily have to have a two-layer structure of the barrier metal and the A1 layer.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a step of forming a contact hole by etching a predetermined location of an insulating film deposited on a substrate;
A step of forming a silicide layer with a thickness sufficiently thin relative to the diameter of the contact hole on the bottom and sidewalls of the contact hole using the CVD method, and filling polysilicon inside the contact hole using the CVD method. burying the contact hole, flattening the opening of the contact hole, and covering the surface of the polysilicon exposed at the opening of the contact hole with a high melting point metal or its silicide. By doing so, it is possible to improve the connection reliability between the first layer wiring and the substrate, which are electrically connected through the contact hole.

In addition, since a silicide layer is provided above the contact hole, even if misalignment occurs between the contact hole and the first layer wiring, the polysilicon buried in the contact hole will not be damaged. be.

[Brief explanation of the drawing]

1(a) to (e) are enlarged cross-sectional views of main parts of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows main parts of a semiconductor substrate obtained by the present invention. It is a front view. 1... Semiconductor substrate, 2... Buried/<IJ layer, 3
...Low concentration diffusion layer, 4...High concentration diffusion layer, 5...
Field insulating film, 6... Oxide film, 7゜12... Interlayer insulating film, 8... First layer wiring, 8a... Barrier metal, 8b... Ap layer, 9... Contact hole, 1
0a, lOb...Silicide layer, 11...Polyrincon, 13...Second layer arrangement! , 14... Pannvation film, 15... Photoresist pattern, 16...
rinside membrane. Agent Patent Attorney Dai Tsutsui Wakui Diagram

Claims (1)

[Claims] 1. Forming a contact hole by etching a predetermined portion of an insulating film deposited on a semiconductor substrate;
forming a silicide layer on the bottom and sidewalls of the contact hole by depositing silicide on the surface of the semiconductor substrate using a CVD method to a thickness sufficiently thin with respect to the diameter of the contact hole; burying the polysilicon inside the contact hole by depositing polysilicon on the surface of the semiconductor substrate using The method includes the steps of planarizing the opening of the contact hole by etching back, and covering the surface of the polysilicon exposed at the opening of the contact hole with a high melting point metal or its silicide. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first layer wiring electrically connected to the semiconductor substrate through the contact hole has a two-layer structure of barrier metal and aluminum.