JPH0410412A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable filling a contact hole of less than 1/2 microns by opening an insulator layer on the surface of a semiconductor substrate and by providing contact holes filled with polycrystalline silicon. CONSTITUTION:An SiO2 layer 2 which coats a semiconductor substrate 1 is penetrated by a contact hole 3 through reactive ion etching. The next step is deposition of the first polycrystalline silicon layer 4 to a thickness about half that of a contact hole 3 and diffusion of phosphorus or boron throughout the first polycrystalline silicon layer 4. Another step is deposition of the second polycrystalline silicon layer 5 to completely fill contact holes and diffusion of phosphorus or boron throughout the second polycrystalline silicon layer 5. The last step is annealing of a semiconductor device and etchback of the first and second polycrystalline silicon layers 4, 5 from the insulator surface using reactive ion etching with CCl2F2 gas and N2 gas.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the manufacture of semiconductors, and in particular, to the manufacturing of semiconductors, an opening is formed in an insulating layer separating two different first and second conductive layers. Regarding contact hole devices.

[Conventional technology]

The contact hole is filled with a third conductor that provides electrical connection between the first and second conductor layers. Conventional processing techniques for contact hole filling include sputter deposition of aluminum or aluminum alloy into the contact hole, or selective vapor deposition (CVD) of tungsten into the contact hole.

[Problem to be solved by the invention]

Conventional aluminum sputtering methods for contact holes smaller than 1/2 micron suffer from low contact hole coverage, which causes high contact resistance.
)give. Also, contact junction (co
A barrier layer of metal silicide or metal lidonide (eg, WSi or TiN) is required between the substrate and the aluminum layer to prevent aluminum spikes from entering the ntact junction.

On the other hand, selective vapor deposition of tungsten provides high contact hole coverage but results in silicon intrusion at the contact junction, increasing contact resistance and junction leakage current.

Further, a contact hole of 1/2 micron or less having a high aspect ratio cannot be filled using the conventional sub-lid method or selective vapor deposition method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that enable filling of contact holes of 1/2 micron or less.

[Failure to solve the problem]

The semiconductor device of the present invention includes: a semiconductor substrate; an insulator layer on the surface of the semiconductor substrate; and a contact hole opened in the insulator layer and filled with polycrystalline silicon.

The semiconductor manufacturing method of the present invention includes the steps of: opening a contact hole in an insulator layer; depositing a first undoped polycrystalline silicon layer in the contact hole; a step of depositing a second undoped polycrystalline silicon layer in the contact hole, a second impurity diffusion step into the second undoped polycrystalline silicon layer, an annealing step, and a surface of the insulator layer. The method includes a step of etching back polycrystalline silicon.

According to the present invention, the first and second undoped polycrystalline silicon layers are grown at about 510° C. using a low pressure vapor phase growth method.
It is preferred to deposit at a deposition temperature of .

[Effect]

The first undoped polycrystalline silicon layer deposited inside the contact hole is 1/2 the width of the contact hole.
/2 or less, thereby leaving two openings through which the impurity from the first impurity diffusion enters and diffuses into the undoped polycrystalline silicon at the bottom of the contact hole 1.

A second undoped polycrystalline silicon layer is then deposited to fill the contact holes. A second impurity diffusion is doped into the second undoped polycrystalline layer to further reduce the sheet resistance of the polysilicon layer. However, these impurities do not diffuse into the bottom of the contact hole.

The annealing removes impurities concentrated in the doped first polycrystalline silicon layer at the bottom of the contact hole.
The contact hole is filled with doped polycrystalline silicon by back-diffusing into the second undoped polycrystalline Si layer near the bottom of the contact hole.

Polycrystalline silicon deposited at 510°C has a smoother surface structure and lower sheet resistance after impurity diffusion compared to polycrystalline silicon deposited at a conventional temperature of 600°C.

〔Example〕

FIG. 1 is a cross-sectional view of a device at each step for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The structure of a semiconductor device and its manufacturing method will be explained with reference to FIG.

First, as shown in FIG. 1(a), a contact hole 3 is formed in the SiO□ layer 2 covering the semiconductor substrate 1 by reactive ion etching.

Next, as shown in FIG.
Deposit at a deposition temperature of 10"C.

Next, as shown in Figure 1(C), 85% phosphorus was added for 30 minutes.
Boron is diffused into the first polycrystalline silicon layer 4 at a temperature of 0°C (n-type polycrystalline silicon) or boron is
Diffusion into the first polycrystalline silicon N4 at a temperature of 75°C (P-type polycrystalline silicon).

Next, as shown in FIG. 1(d), the second polycrystalline silicon layer 5 is coated with 51 layers to completely fill the contact hole.
Deposit at a deposition temperature of 0°C.

Next, as shown in Figure 1(e), 85% phosphorus was added for 30 minutes.
Diffusion into the second polycrystalline silicon layer 5 (n-type polycrystalline silicon) or boron at a temperature of 0°C for 30 minutes.
It diffuses into the second polycrystalline silicon layer 5 at a temperature of 875°C (p-most polycrystalline silicon).

Next, as shown in FIG. 1(f), the semiconductor device is annealed at a temperature of 900° C. for 5 minutes.

Finally, as shown in FIG. 1(b), the first and second polycrystalline silicon layers 4 and 5 are etched from the insulator surface using reactive ion etching (RIE) using CCl2F2 gas and N2 gas. Etched back.

〔Effect of the invention〕

According to the present invention, contact holes having a width of 0.15 microns or more and a depth of 1 micron could be filled, resulting in a contact resistance of ~100 ohms.

As described above, according to the semiconductor device and manufacturing method of the present invention, it is possible to fill contact holes of 1/2 micron or less, which was difficult to fill using conventional techniques.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor device and its manufacturing method. 1...Semiconductor substrate 2...5in2 layer 3...Contact hole 4...First polycrystalline silicon layer 5...Second polycrystalline silicon layer

Claims (3)

[Claims] (1) A semiconductor device having a semiconductor substrate, an insulator layer on the surface of the semiconductor substrate, and a contact hole opened in the insulator layer and filled with polycrystalline silicon. (2) a step of opening a contact hole in the insulator layer; a step of depositing a first undoped polycrystalline silicon layer in the contact hole; and a first step of diffusing impurities into the first undoped polycrystalline silicon layer; depositing a second undoped polycrystalline silicon layer in the contact hole, a second impurity diffusion step into the second undoped polycrystalline silicon layer, an annealing step, and etching the polycrystalline silicon from the surface of the insulator layer. A method for manufacturing a semiconductor device, including a step of backing up. (3) In the method for manufacturing a semiconductor according to claim 2, the first
and a second undoped polycrystalline silicon layer is deposited at a deposition temperature of about 510° C. using a reduced pressure vapor deposition method.