USRE45232E1 - Method of forming a contact plug for a semiconductor device - Google Patents

Method of forming a contact plug for a semiconductor device Download PDF

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USRE45232E1
USRE45232E1 US13/568,920 US201213568920A USRE45232E US RE45232 E1 USRE45232 E1 US RE45232E1 US 201213568920 A US201213568920 A US 201213568920A US RE45232 E USRE45232 E US RE45232E
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semiconductor device
manufacturing
layer
forming
insulating layer
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Dae Hee Weon
Seok Kiu Lee
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Mosaid Technologies Inc
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Conversant Intellectual Property Management Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Definitions

  • the present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with an improved contact plug suitable for highly integrated semiconductor devices.
  • a contact hole is first formed and then, polycrystalline silicon is deposited therein. This method is performed by using a Chemical Mechanical Polishing (CMP) process.
  • CMP Chemical Mechanical Polishing
  • SEG selective epitaxial growth
  • a plug using SEG can solve the problems of gap-fill and of undesirable increase of contact resistance.
  • the surface of the nitride layer is exposed when the self-aligned contact (SAC) etch is applied to cell activation regions.
  • SAC self-aligned contact
  • the SEG has a different facet generation depending on the selectivity and the thermal stress of the pattern material.
  • the nitride materials have difficulty in achieving selectivity at a temperature below 850° C., as compared with oxide materials.
  • the growth speed is lowered in order to have selectivity, thereby increasing the thermal budget on device.
  • FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method of manufacturing semiconductor device.
  • a gate electrode structure 3 having a hard mask (not shown) made of a nitride layer, is formed on a silicon substrate 1 and then, a sidewall spacer 5 is formed on the side of the gate electrode 3 .
  • impurity junction regions are formed by impurities implanted in the silicon substrate 1 on the lower part of both sides of the sidewall spacer 5 .
  • an interlayer insulating layer 7 is deposited by using an oxide layer material on the silicon substrate 1 , including the gate electrode structure 3 and the sidewall spacer 5 , in order to prevent the generation of short-circuits between adjacent cells.
  • the interlayer insulating layer 7 is subjected to a landing plug contact mask formation process using a photolithography and patterning process to form a landing plug contact hole 9 , which exposes the impurity junction regions (not shown), that is, a plug formation area.
  • a polycrystalline silicon layer 11 is then deposited to fill the landing plug contact hole 9 on the upper part of the interlayer insulating layer 7 , including the landing plug contact hole 9 .
  • a CMP or etch back process is performed on the polycrystalline silicon layer 11 , thereby forming a contact plug 11 a in the contact hole 9 to be in electrical contact with the impurity junction regions (not shown).
  • the conventional method has several problems in forming a contact hole and a contact plug having a high aspect ratio, wherein the circuit line width is below 0.16 ⁇ m.
  • one problem in the conventional contact formation process is to have a sufficient plug formation area by using a landing plug contact mask. That is, in the etching process to form a landing plug contact through SAC by a nitride layer spacer of the nitride layer barrier, the problem is that it is difficult to have a sufficient landing plug contact hole area due to the etching grade necessarily generated to have the etching selectivity ratio between the nitride layer of the gate spacer and the oxide layer of the interlayer insulating layer.
  • FIG. 5 is a cross sectional view for showing the steps of a method of manufacturing a semiconductor device according to another embodiment of the conventional method.
  • an isolation layer 23 is formed to define the device formation region on a silicon substrate 21 and a gate oxide layer 25 .
  • a gate 27 and a hard mask 29 are stacked on the device formation region of the silicon substrate 21 , thereby obtaining a gate structure.
  • an insulating layer spacer 31 is formed on the upper part and side of the gate structure and at the same time, the silicon substrate 21 is exposed.
  • a selective episilicon layer is grown over the height of the gate on the surface of the exposed silicon substrate 21 , thereby forming a contact plug 33 .
  • an interlayer insulating layer (not shown) is formed to electrically insulate the contact plug and then, additional processes (not shown) are performed.
  • the allowable margin of the side is very low in the-episilicon growth process.
  • the distance between adjacent activation regions becomes shorter.
  • the adhering episilicon layers thereby grow to the side from the adjacent activation regions.
  • the silicon of the activation region is formed in the shape of a “T” in order to form the contact plug, as shown in FIG. 6 , part “A”.
  • the side growth of episilicon is actively generated in a curved line. That is, the episilicon is generated in a direction other than in the directions 100 and 110 .
  • FIGS. 7 and 8 are SEM photographs showing cells of direction 100 and cells slanting by 30°, respectively.
  • the episilicon layer of FIG. 8 has the longer distance between activation regions. Therefore, side growth is actively generated and short-circuits may be caused between the adjacent activation regions.
  • the object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an improved contact plug suitable for highly integrated semiconductor devices.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying the manufacturing process by applying episilicon growth during plug formation.
  • Yet another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a sufficient gap fill margin due to the low step in the deposition of the interlayer insulating layer and the margin due to the reduction of target in the contact etch processes.
  • Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a maximum allowable margin of side growth in the episilicon growth process.
  • the present invention comprises the steps of: forming an insulating layer on a silicon substrate; forming a contact hole on the insulating layer; forming a selective silicon layer in the contact hole; and selectively forming a conductive plug on the selective silicon layer.
  • FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method of manufacturing a semiconductor device.
  • FIG. 5 is a cross sectional view showing the steps of a method of manufacturing a semiconductor device according to another embodiment using a conventional method.
  • FIG. 6 is a plane view showing the steps of a method of manufacturing a semiconductor device according to another embodiment of the conventional method, wherein episilicon is grown toward the side.
  • FIGS. 7 and 8 are SEM photographs showing side growth of episilicon according to directions of activation regions in the conventional method.
  • FIGS. 9 to 13 are cross sectional views showing the steps of a method of manufacturing a semiconductor device according to the present invention.
  • an isolation layer (not shown) is first formed to define the device formation region and device isolation region on a silicon substrate 41 .
  • a gate insulating layer (not shown), a gate 43 and a hard mask 45 are formed on the device formation region of the silicon substrate 41 .
  • a nitride insulating layer (not shown) is deposited on the upper part of the silicon substrate 41 , including over the gate 43 .
  • An insulting layer spacer 47 is then formed by selectively removing the nitride insulating layer by using an anisotropic etch process so that the insulating layer spacer 47 remains on the upper part and side part of the gate 43 .
  • the gate 43 is made of one or more of polycrystalline silicons having a thickness of between 500 and 1500 ⁇ , or is made of tungsten having a thickness of between 500 and 1500 ⁇ .
  • the hard mask 45 and the insulating layer spacer 47 are formed as nitrides on the gate 43 , in order to prevent damage to each layer during the etch process to form the landing plug contact hole.
  • a first episilicon layer 49 is grown on the exposed surface of the silicon substrate 41 on the lower parts of both sides of the insulating layer spacers 47 by performing selective episilicon growth processes.
  • the first episilicon layer 49 is grown to a thickness of between 1500 and 2000 ⁇ by using a known LPCVD process or UHVCVD process.
  • the episilicon target is thereby lowered by the first episilicon layer 49 in the formation of the contact hole using SAC. Therefore, the allowable margin of growth is increased on the side of contact hole by slightly growing the episilicon layer.
  • the height of the activation regions is increased by between 1500 and 2000 ⁇ after the first episilicon layer 49 is formed. Therefore, the area of the activation region is increased to have a sufficient etching margin in the landing plug etch process in consideration of the angle in landing plug contact etch process.
  • the H bake process is performed at a temperature of between 800 and 1000° C. for between 1 and 5 minutes and then, SiH 2 Cl 2 gas and HCl gas are supplied at a rate of between 10 and 500 sccm at a pressure of between 5 and 300 Torr.
  • the H bake process is performed at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 20 mTorr and, Si 2 H 6 gas and Cl 2 gas are then supplied at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 100 Torr.
  • an interlayer insulating layer 51 is deposited on the resulting structure including the first episilicon layer 49 to a thickness of between 3000 and 7000 ⁇ .
  • the interlayer insulating layer 51 is deposited by employing BPSG according to a LPCVD or PECVD method or by employing an oxide layer according to a HDPCVD method.
  • a sensitive film (not shown) is applied on the interlayer insulating layer 51 and then, a sensitive film pattern for the landing plug contact mask (not shown) is formed by performing exposure and development processes using photolithography.
  • the interlayer insulating layer 51 is selectively removed by employing the sensitive film pattern for the landing plug contact mask (not shown) as a mask, thereby forming a landing plug contact hole 53 exposing the first episilicon layer 49 . Subsequently, the sensitive film pattern (not shown) is removed.
  • a second episilicon layer 55 is grown on the first episilicon layer 49 on the lower parts of the landing plug contact hole 53 .
  • the second episilicon layer 55 is grown by using the same methods as that of the first episilicon layer 49 .
  • a doped amorphous silicon, polycrystalline silicon, titanium or other conductive metal layer is employed, instead of the second episilicon layer 55 .
  • the polycrystalline silicon layer is formed by using a furnace or LPCVD of a single wafer.
  • a contact plug may be formed by performing planation on the polycrystalline silicon layer by CMP processes.
  • a contact is easily formed by having a sufficient processing margin in the formation of a fine contact plug. That is, it is possible to have a sufficiently allowable margin of side growth in the episilicon growth process and to have a gap fill margin generated by the low step in the deposition of the interlayer insulating layer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device with an improved contact plug suitable for highly integrated semiconductor devices.
2. Description of the Related Art
As is well known, it is essential to reduce the contact resistance in a circuit line width to below 0.16 μm.
According to a recent method of forming a silicon contact plug, a contact hole is first formed and then, polycrystalline silicon is deposited therein. This method is performed by using a Chemical Mechanical Polishing (CMP) process.
Generally, it is desirable to apply selective epitaxial growth (SEG) during the manufacturing process of semiconductor devices since it is possible to reduce cell size, simplify manufacturing processes and improve electrical properties by using SEG.
Therefore, a plug using SEG can solve the problems of gap-fill and of undesirable increase of contact resistance.
Furthermore, it is possible to simplify the manufacturing process by using SEG since it does not require performing CMP and silicon recess etching for plug isolation.
However, there are several problems in applying SEG during plug manufacture.
First, there is a problem with the selectivity of the pattern material, that is, a material to form a window for growing the SEG.
Also, the surface of the nitride layer is exposed when the self-aligned contact (SAC) etch is applied to cell activation regions. The SEG has a different facet generation depending on the selectivity and the thermal stress of the pattern material.
Generally, in a low pressure chemical vapor deposition (LPCVD) process, the nitride materials have difficulty in achieving selectivity at a temperature below 850° C., as compared with oxide materials.
Therefore, the growth speed is lowered in order to have selectivity, thereby increasing the thermal budget on device.
The conventional method for manufacturing a semiconductor device will be described in more detail with reference to accompanying drawings.
FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method of manufacturing semiconductor device.
Referring to FIG. 1, a gate electrode structure 3, having a hard mask (not shown) made of a nitride layer, is formed on a silicon substrate 1 and then, a sidewall spacer 5 is formed on the side of the gate electrode 3.
Although it is not shown in the drawings, impurity junction regions (not shown) are formed by impurities implanted in the silicon substrate 1 on the lower part of both sides of the sidewall spacer 5.
Subsequently, an interlayer insulating layer 7 is deposited by using an oxide layer material on the silicon substrate 1, including the gate electrode structure 3 and the sidewall spacer 5, in order to prevent the generation of short-circuits between adjacent cells.
Referring to FIG. 2, the interlayer insulating layer 7 is subjected to a landing plug contact mask formation process using a photolithography and patterning process to form a landing plug contact hole 9, which exposes the impurity junction regions (not shown), that is, a plug formation area.
Referring to FIG. 3, a polycrystalline silicon layer 11 is then deposited to fill the landing plug contact hole 9 on the upper part of the interlayer insulating layer 7, including the landing plug contact hole 9.
Referring to FIG. 4, a CMP or etch back process is performed on the polycrystalline silicon layer 11, thereby forming a contact plug 11a in the contact hole 9 to be in electrical contact with the impurity junction regions (not shown).
However, the conventional method has several problems in forming a contact hole and a contact plug having a high aspect ratio, wherein the circuit line width is below 0.16 μm.
In particular, one problem in the conventional contact formation process is to have a sufficient plug formation area by using a landing plug contact mask. That is, in the etching process to form a landing plug contact through SAC by a nitride layer spacer of the nitride layer barrier, the problem is that it is difficult to have a sufficient landing plug contact hole area due to the etching grade necessarily generated to have the etching selectivity ratio between the nitride layer of the gate spacer and the oxide layer of the interlayer insulating layer.
In order to solve the problem, SAC of selective single crystal silicon has been proposed as shown in FIG. 5.
FIG. 5 is a cross sectional view for showing the steps of a method of manufacturing a semiconductor device according to another embodiment of the conventional method.
Referring to FIG. 5, an isolation layer 23 is formed to define the device formation region on a silicon substrate 21 and a gate oxide layer 25. A gate 27 and a hard mask 29 are stacked on the device formation region of the silicon substrate 21, thereby obtaining a gate structure. Then, an insulating layer spacer 31 is formed on the upper part and side of the gate structure and at the same time, the silicon substrate 21 is exposed.
Then, a selective episilicon layer is grown over the height of the gate on the surface of the exposed silicon substrate 21, thereby forming a contact plug 33.
Afterwards, an interlayer insulating layer (not shown) is formed to electrically insulate the contact plug and then, additional processes (not shown) are performed.
However, this embodiment of the conventional method has several problems.
First, the allowable margin of the side is very low in the-episilicon growth process.
Therefore, as the device is formed having fine features, the distance between adjacent activation regions becomes shorter. The adhering episilicon layers thereby grow to the side from the adjacent activation regions.
In order to solve this problem, a method has been proposed whereby the episilicon layer is grown by using processes without side growth.
However, there are also several problems in applying the process without side growth.
When the episilicon is applied without side growth, the silicon of the activation region is formed in the shape of a “T” in order to form the contact plug, as shown in FIG. 6, part “A”. According to this method, the side growth of episilicon is actively generated in a curved line. That is, the episilicon is generated in a direction other than in the directions 100 and 110.
FIGS. 7 and 8 are SEM photographs showing cells of direction 100 and cells slanting by 30°, respectively.
Compared with FIG. 7, the episilicon layer of FIG. 8 has the longer distance between activation regions. Therefore, side growth is actively generated and short-circuits may be caused between the adjacent activation regions.
However, it is very difficult to form activation regions in the shape of a “T” since the distance between the adjacent activation regions becomes shorter by the protruding part of the “T” and it is also difficult to form the cell in the shape of a “T” by using a photolithography process.
Furthermore, it is also difficult to obtain episilicon growth in a curved line.
In order to solve the above problems, a method is proposed whereby a contact is formed by a protruding part of a bit line. However, this is also very difficult to successfully perform.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems of the conventional method. The object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an improved contact plug suitable for highly integrated semiconductor devices.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying the manufacturing process by applying episilicon growth during plug formation.
Yet another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a sufficient gap fill margin due to the low step in the deposition of the interlayer insulating layer and the margin due to the reduction of target in the contact etch processes.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of having a maximum allowable margin of side growth in the episilicon growth process.
In order to accomplish the above objects, the present invention comprises the steps of: forming an insulating layer on a silicon substrate; forming a contact hole on the insulating layer; forming a selective silicon layer in the contact hole; and selectively forming a conductive plug on the selective silicon layer.
The above objects, and other features and advantages of the present invention will become more apparent after a complete understanding of the following detailed description is achieved when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method of manufacturing a semiconductor device.
FIG. 5 is a cross sectional view showing the steps of a method of manufacturing a semiconductor device according to another embodiment using a conventional method.
FIG. 6 is a plane view showing the steps of a method of manufacturing a semiconductor device according to another embodiment of the conventional method, wherein episilicon is grown toward the side.
FIGS. 7 and 8 are SEM photographs showing side growth of episilicon according to directions of activation regions in the conventional method.
FIGS. 9 to 13 are cross sectional views showing the steps of a method of manufacturing a semiconductor device according to the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
Although not shown in the drawings, an isolation layer (not shown) is first formed to define the device formation region and device isolation region on a silicon substrate 41.
Then, as shown in FIG. 9, a gate insulating layer (not shown), a gate 43 and a hard mask 45 are formed on the device formation region of the silicon substrate 41. A nitride insulating layer (not shown) is deposited on the upper part of the silicon substrate 41, including over the gate 43. An insulting layer spacer 47 is then formed by selectively removing the nitride insulating layer by using an anisotropic etch process so that the insulating layer spacer 47 remains on the upper part and side part of the gate 43. The gate 43 is made of one or more of polycrystalline silicons having a thickness of between 500 and 1500 Å, or is made of tungsten having a thickness of between 500 and 1500 Å.
In the above process, the hard mask 45 and the insulating layer spacer 47 are formed as nitrides on the gate 43, in order to prevent damage to each layer during the etch process to form the landing plug contact hole.
Referring to FIG. 10, a first episilicon layer 49 is grown on the exposed surface of the silicon substrate 41 on the lower parts of both sides of the insulating layer spacers 47 by performing selective episilicon growth processes. The first episilicon layer 49 is grown to a thickness of between 1500 and 2000 Å by using a known LPCVD process or UHVCVD process. The episilicon target is thereby lowered by the first episilicon layer 49 in the formation of the contact hole using SAC. Therefore, the allowable margin of growth is increased on the side of contact hole by slightly growing the episilicon layer.
The height of the activation regions is increased by between 1500 and 2000 Å after the first episilicon layer 49 is formed. Therefore, the area of the activation region is increased to have a sufficient etching margin in the landing plug etch process in consideration of the angle in landing plug contact etch process.
When the first episilicon layer 49 is grown by a LPCVD process, the H bake process is performed at a temperature of between 800 and 1000° C. for between 1 and 5 minutes and then, SiH2Cl2 gas and HCl gas are supplied at a rate of between 10 and 500 sccm at a pressure of between 5 and 300 Torr.
When the first episilicon layer 49 is grown by a UHVCVD process, the H bake process is performed at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 20 mTorr and, Si2H6 gas and Cl2 gas are then supplied at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 100 Torr.
Referring to FIG. 11, an interlayer insulating layer 51 is deposited on the resulting structure including the first episilicon layer 49 to a thickness of between 3000 and 7000 Å. The interlayer insulating layer 51 is deposited by employing BPSG according to a LPCVD or PECVD method or by employing an oxide layer according to a HDPCVD method.
Although it is not shown in the drawings, a sensitive film (not shown) is applied on the interlayer insulating layer 51 and then, a sensitive film pattern for the landing plug contact mask (not shown) is formed by performing exposure and development processes using photolithography.
Referring to FIG. 12, the interlayer insulating layer 51 is selectively removed by employing the sensitive film pattern for the landing plug contact mask (not shown) as a mask, thereby forming a landing plug contact hole 53 exposing the first episilicon layer 49. Subsequently, the sensitive film pattern (not shown) is removed.
Referring to FIG. 13, a second episilicon layer 55 is grown on the first episilicon layer 49 on the lower parts of the landing plug contact hole 53. The second episilicon layer 55 is grown by using the same methods as that of the first episilicon layer 49. Alternatively, a doped amorphous silicon, polycrystalline silicon, titanium or other conductive metal layer is employed, instead of the second episilicon layer 55.
The polycrystalline silicon layer is formed by using a furnace or LPCVD of a single wafer. When the polycrystalline silicon layer is employed, a contact plug may be formed by performing planation on the polycrystalline silicon layer by CMP processes.
As described above, according to the present invention, a contact is easily formed by having a sufficient processing margin in the formation of a fine contact plug. That is, it is possible to have a sufficiently allowable margin of side growth in the episilicon growth process and to have a gap fill margin generated by the low step in the deposition of the interlayer insulating layer.
It is also possible to have a sufficient margin due to the reduction of target in etch processes to form the landing plug contact.
Although the preferred embodiment of this invention has been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.

Claims (26)

What is claimed is:
1. A method of manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a silicon substrate;
forming a contact hole on the insulating layer;
forming a selective silicon layer in the contact hole; and
forming a selective conductive plug on the selective silicon layer,
wherein the selective silicon layer is an episilicon layer formed in accordance with an UHVCVD process,
wherein, in applying the UHVCVD, SiH2Cl2 gas and Cl2 gas are supplied.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a gate on the silicon substrate prior to the step of forming the insulating layer.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the gate is formed by one or more of polycrystalline silicons having a thickness of between 500 and 1500 Å, or tungsten having a thickness of between 500 and 1500 Å.
4. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming a hard mask comprising nitride having a thickness of between 1000 and 3000 Å on the upper part of the gate.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the hard mask comprising nitride is formed in accordance with an LPCVD process or a PECVD process.
6. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming an insulating layer spacer comprising nitride having a thickness of between 100 and 500 Å on the side of the gate.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating layer spacer of nitride is formed in accordance with an LPCVD process or a PECVD process.
8. The method of manufacturing a semiconductor device according to claim 1, wherein the selective silicon layer is an episilicon layer.
9. The method of manufacturing a semiconductor device according to claim 8 1, wherein the episilicon layer is formed to a thickness of between 1500 and 2000 Å in accordance with an LPCVD process or an UHVCVD process.
10. The method of manufacturing a semiconductor device according to claim 9, wherein, in applying the LPCVD process, a H bake process is performed at a temperature of between 800 and 1000° C. for between 1 to 5 minutes.
11. The method of manufacturing a semiconductor device according to claim 9, wherein, in applying the LPCVD process, SiH2Cl2 gas and HCl gas are supplied at a rate between 10 and 500 sccm and at a pressure of between 5 and 300 Torr.
12. The method of manufacturing a semiconductor device according to claim 9, wherein, in applying the UHVCVD process, a H bake process is performed at a temperature of between 400 and 800° C. and at a pressure of between 0.1 mTorr and 20 mTorr.
13. The method of manufacturing a semiconductor device according to claim 9, wherein, in applying the UHVCVD, the SiH2Cl2 gas and Cl2 gas are supplied at a temperature of between 400 and 800° C. and a pressure of between 0.1 mTorr and 100 Torr.
14. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer is a BPSG oxide layer or an unmixed oxide layer, having a thickness of between 3000 and 7000 Å.
15. The method of manufacturing a semiconductor device according to claim 1, wherein the selectively conductive plug comprises a layer of a material selected from a group comprising episilicon, polycrystalline silicon, titanium, and conductive metals.
16. The method of manufacturing a semiconductor device according to claim 15, wherein the selectively conductive plug has a thickness of between 1000 and 3000 Å.
17. The method of claim 1, wherein the selectively conductive plug comprises a layer of titanium.
18. A method of manufacturing a semiconductor device comprising the steps of:
forming an insulating layer on a silicon substrate;
forming a contact hole on the insulating layer;
forming a selective silicon layer in the contact hole; and
forming a selective conductive plug on the selective silicon layer,
wherein the selective conductive plug comprises a layer of conductive metal; and
wherein the selective silicon layer is an episilicon layer formed in accordance with an UHVCVD process,
wherein, in applying the UHVCVD, SiH2Cl2 gas and Cl2 gas are supplied.
19. The method of manufacturing a semiconductor device according to claim 18, further comprising the step of forming a gate on the silicon substrate prior to the step of forming the insulating layer.
20. The method of manufacturing a semiconductor device according to claim 19, wherein the gate is formed by one or more of polycrystalline silicons having a thickness of between 500 and 1500 Å, or tungsten having a thickness of between 500 and 1500 Å.
21. The method of manufacturing a semiconductor device according to claim 19, further comprising the step of forming a hard mask comprising nitride having a thickness of between 1000 and 3000 Å on the upper part of the gate.
22. The method of manufacturing a semiconductor device according to claim 21, wherein the hard mask comprising nitride is formed in accordance with an LPCVD process or a PECVD process.
23. The method of manufacturing a semiconductor device according to claim 19, further comprising the step of forming an insulating layer spacer comprising nitride having a thickness of between 100 and 500 Å on the side of the gate.
24. The method of manufacturing a semiconductor device according to claim 23, wherein the insulating layer spacer of nitride is formed in accordance with an LPCVD process or a PECVD process.
25. The method of manufacturing a semiconductor device according to claim 18, wherein the episilicon layer is formed to a thickness of between 1500 and 2000 Å.
26. The method of manufacturing a semiconductor device according to claim 18, wherein the selectively conductive plug has a thickness of between 1000 and 3000 Å.
US13/568,920 2001-10-08 2012-08-07 Method of forming a contact plug for a semiconductor device Expired - Lifetime USRE45232E1 (en)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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KR100503519B1 (en) * 2003-01-22 2005-07-22 삼성전자주식회사 Semiconductor device and Method of manufacturing the same
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US7468311B2 (en) * 2003-09-30 2008-12-23 Tokyo Electron Limited Deposition of silicon-containing films from hexachlorodisilane
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JP4215787B2 (en) * 2005-09-15 2009-01-28 エルピーダメモリ株式会社 Semiconductor integrated circuit device and manufacturing method thereof
JP2007294618A (en) * 2006-04-24 2007-11-08 Elpida Memory Inc Method of manufacturing semiconductor device, and semiconductor device
JP4552926B2 (en) 2006-11-20 2010-09-29 エルピーダメモリ株式会社 Semiconductor device and manufacturing method of semiconductor device
US20120261772A1 (en) * 2011-04-15 2012-10-18 Haizhou Yin Semiconductor Device and Method for Manufacturing the Same

Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005450A (en) 1970-05-13 1977-01-25 Hitachi, Ltd. Insulated gate field effect transistor having drain region containing low impurity concentration layer
US4072545A (en) 1974-12-03 1978-02-07 International Business Machines Corp. Raised source and drain igfet device fabrication
JPS5982768A (en) 1982-11-02 1984-05-12 Nec Corp Manufacture of semiconductor device
JPS59165461A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Schottky junction type compound semiconductor field effect transistor
JPS59165464A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of schottky junction type compound semiconductor field effect transistor
JPS59165462A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of compound semiconductor field effect transistor
JPS59165465A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of schottky junction type compound semiconductor field effect transistor
JPS59165463A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of compound semiconductor field effect transistor
JPS59189677A (en) 1983-04-13 1984-10-27 Fujitsu Ltd Manufacture of semiconductor device
JPS616195A (en) 1984-06-21 1986-01-11 Matsushita Electric Ind Co Ltd Liquid phase epitaxial growth process
JPS61164355A (en) 1985-01-16 1986-07-25 Mitsubishi Electric Corp Fault informing device of elevator
JPH02130919A (en) 1988-11-11 1990-05-18 Nec Corp Forming method for semiconductor film
US4948745A (en) 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
US4966868A (en) * 1988-05-16 1990-10-30 Intel Corporation Process for selective contact hole filling including a silicide plug
US5004702A (en) 1987-10-19 1991-04-02 Kabushiki Kaisha Toshiba Preparation method of selective growth silicon layer doped with impurities
US5057899A (en) * 1989-08-29 1991-10-15 Kabushiki Kaisha Toshiba Semiconductor device with improved wiring contact portion
US5073516A (en) 1991-02-28 1991-12-17 Texas Instruments Incorporated Selective epitaxial growth process flow for semiconductor technologies
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5291058A (en) 1989-04-19 1994-03-01 Kabushiki Kaisha Toshiba Semiconductor device silicon via fill formed in multiple dielectric layers
US5321306A (en) 1989-05-10 1994-06-14 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor device
US5321285A (en) * 1990-05-07 1994-06-14 Micron Technology, Inc. Carrier injection dynamic random access memory having stacked depletion region in Mesa
US5434092A (en) 1991-12-31 1995-07-18 Purdue Research Foundation Method for fabricating a triple self-aligned bipolar junction transistor
US5444278A (en) 1992-01-18 1995-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US5455198A (en) * 1992-12-31 1995-10-03 Hyundai Electronics Industries Co., Ltd. Method for fabricating tungsten contact plug
US5475240A (en) * 1991-03-15 1995-12-12 Mitsubishi Denki Kabushiki Kaisha Contact structure of an interconnection layer for a semiconductor device and a multilayer interconnection SRAM
US5604368A (en) 1994-07-15 1997-02-18 International Business Machines Corporation Self-aligned double-gate MOSFET by selective lateral epitaxy
US5652180A (en) * 1993-06-28 1997-07-29 Kawasaki Steel Corporation Method of manufacturing semiconductor device with contact structure
US5804470A (en) 1996-10-23 1998-09-08 Advanced Micro Devices, Inc. Method of making a selective epitaxial growth circuit load element
US5854127A (en) * 1997-03-13 1998-12-29 Micron Technology, Inc. Method of forming a contact landing pad
US5895948A (en) 1996-09-27 1999-04-20 Nec Corporation Semiconductor device and fabrication process thereof
US5955759A (en) 1997-12-11 1999-09-21 International Business Machines Corporation Reduced parasitic resistance and capacitance field effect transistor
US6001729A (en) * 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
US6030894A (en) 1996-12-04 2000-02-29 Nec Corporation Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si
US6030891A (en) 1997-12-18 2000-02-29 Advanced Micro Devices, Inc. Vacuum baked HSQ gap fill layer for high integrity borderless vias
US6090691A (en) 1999-11-15 2000-07-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a raised source and drain without using selective epitaxial growth
US6150190A (en) 1999-05-27 2000-11-21 Motorola Inc. Method of formation of buried mirror semiconductive device
US6218237B1 (en) 1996-01-03 2001-04-17 Micron Technology, Inc. Method of forming a capacitor
US6271125B1 (en) * 1999-02-18 2001-08-07 Taiwan Semiconductor Manufacturing Company Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure
US6372630B1 (en) * 1997-04-18 2002-04-16 Nippon Steel Corporation Semiconductor device and fabrication method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130682A (en) * 1993-11-02 1995-05-19 Nippon Steel Corp Method of manufacturing semiconductor device
JP2875210B2 (en) 1996-06-21 1999-03-31 泰孝 山下 Wear-resistant block and simple identification method of its wear level
KR100289749B1 (en) * 1998-05-12 2001-05-15 윤종용 Method for forming conductive pad
KR100335124B1 (en) * 1999-10-18 2002-05-04 박종섭 Method for forming epitaxial layer of semiconductor device
KR20010068539A (en) * 2000-01-06 2001-07-23 윤종용 The method of forming self-aligned contact for semiconductor devices
KR20010080841A (en) * 2000-01-17 2001-08-25 Samsung Electronics Co Ltd Method for manufacturing semiconductor dram device

Patent Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005450A (en) 1970-05-13 1977-01-25 Hitachi, Ltd. Insulated gate field effect transistor having drain region containing low impurity concentration layer
US4072545A (en) 1974-12-03 1978-02-07 International Business Machines Corp. Raised source and drain igfet device fabrication
JPS5982768A (en) 1982-11-02 1984-05-12 Nec Corp Manufacture of semiconductor device
JPS59165465A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of schottky junction type compound semiconductor field effect transistor
JPS59165464A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of schottky junction type compound semiconductor field effect transistor
JPS59165462A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of compound semiconductor field effect transistor
JPS59165463A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Manufacture of compound semiconductor field effect transistor
JPS59165461A (en) 1983-03-10 1984-09-18 Oki Electric Ind Co Ltd Schottky junction type compound semiconductor field effect transistor
JPS59189677A (en) 1983-04-13 1984-10-27 Fujitsu Ltd Manufacture of semiconductor device
JPS616195A (en) 1984-06-21 1986-01-11 Matsushita Electric Ind Co Ltd Liquid phase epitaxial growth process
JPS61164355A (en) 1985-01-16 1986-07-25 Mitsubishi Electric Corp Fault informing device of elevator
US5004702A (en) 1987-10-19 1991-04-02 Kabushiki Kaisha Toshiba Preparation method of selective growth silicon layer doped with impurities
US4966868A (en) * 1988-05-16 1990-10-30 Intel Corporation Process for selective contact hole filling including a silicide plug
JPH02130919A (en) 1988-11-11 1990-05-18 Nec Corp Forming method for semiconductor film
US5291058A (en) 1989-04-19 1994-03-01 Kabushiki Kaisha Toshiba Semiconductor device silicon via fill formed in multiple dielectric layers
US5321306A (en) 1989-05-10 1994-06-14 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor device
US4948745A (en) 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
US5057899A (en) * 1989-08-29 1991-10-15 Kabushiki Kaisha Toshiba Semiconductor device with improved wiring contact portion
US5321285A (en) * 1990-05-07 1994-06-14 Micron Technology, Inc. Carrier injection dynamic random access memory having stacked depletion region in Mesa
US5073516A (en) 1991-02-28 1991-12-17 Texas Instruments Incorporated Selective epitaxial growth process flow for semiconductor technologies
US5475240A (en) * 1991-03-15 1995-12-12 Mitsubishi Denki Kabushiki Kaisha Contact structure of an interconnection layer for a semiconductor device and a multilayer interconnection SRAM
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5434092A (en) 1991-12-31 1995-07-18 Purdue Research Foundation Method for fabricating a triple self-aligned bipolar junction transistor
US5444278A (en) 1992-01-18 1995-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US5455198A (en) * 1992-12-31 1995-10-03 Hyundai Electronics Industries Co., Ltd. Method for fabricating tungsten contact plug
US5652180A (en) * 1993-06-28 1997-07-29 Kawasaki Steel Corporation Method of manufacturing semiconductor device with contact structure
US5604368A (en) 1994-07-15 1997-02-18 International Business Machines Corporation Self-aligned double-gate MOSFET by selective lateral epitaxy
US6001729A (en) * 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
US6218237B1 (en) 1996-01-03 2001-04-17 Micron Technology, Inc. Method of forming a capacitor
US5895948A (en) 1996-09-27 1999-04-20 Nec Corporation Semiconductor device and fabrication process thereof
US5804470A (en) 1996-10-23 1998-09-08 Advanced Micro Devices, Inc. Method of making a selective epitaxial growth circuit load element
US6030894A (en) 1996-12-04 2000-02-29 Nec Corporation Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si
US5854127A (en) * 1997-03-13 1998-12-29 Micron Technology, Inc. Method of forming a contact landing pad
US6372630B1 (en) * 1997-04-18 2002-04-16 Nippon Steel Corporation Semiconductor device and fabrication method thereof
US5955759A (en) 1997-12-11 1999-09-21 International Business Machines Corporation Reduced parasitic resistance and capacitance field effect transistor
US6030891A (en) 1997-12-18 2000-02-29 Advanced Micro Devices, Inc. Vacuum baked HSQ gap fill layer for high integrity borderless vias
US6271125B1 (en) * 1999-02-18 2001-08-07 Taiwan Semiconductor Manufacturing Company Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure
US6150190A (en) 1999-05-27 2000-11-21 Motorola Inc. Method of formation of buried mirror semiconductive device
US6090691A (en) 1999-11-15 2000-07-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a raised source and drain without using selective epitaxial growth

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Hsieh et al., "Silicon Homoepitaxy by Rapid Thermal Processing Chemical Vapor Deposition (RTPCVD)-A Review," J. Electrochem. Soc., vol. 138, No. 4, pp. 1188-1207 (1991).
Moon, et al., "A Deep-Submicrometer Raised/Drain LDD Structure Fabricated Using Hot-Wall Epitaxy", VLSITSA, pp. 117-121 (1991).

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US6472303B1 (en) 2002-10-29
JP2003124144A (en) 2003-04-25

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