KR20010080841A - Method for manufacturing semiconductor dram device - Google Patents

Method for manufacturing semiconductor dram device Download PDF

Info

Publication number
KR20010080841A
KR20010080841A KR1020000002035A KR20000002035A KR20010080841A KR 20010080841 A KR20010080841 A KR 20010080841A KR 1020000002035 A KR1020000002035 A KR 1020000002035A KR 20000002035 A KR20000002035 A KR 20000002035A KR 20010080841 A KR20010080841 A KR 20010080841A
Authority
KR
South Korea
Prior art keywords
electrode
bitline
source
drain
gate
Prior art date
Application number
KR1020000002035A
Other languages
Korean (ko)
Inventor
Yu Cheol Shin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR1020000002035A priority Critical patent/KR20010080841A/en
Publication of KR20010080841A publication Critical patent/KR20010080841A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing semiconductor devices is provided to reduce the height between a gate electrode and a bitline by forming a bitline immediately after a bitline contact plug simultaneously formed with a bitline contact pad is formed. CONSTITUTION: The method forms a gate pattern(106) in a semiconductor substrate(100) in which a device isolation film is formed to define an active region(104). A source/drain region(108) is formed in the active region exposed at both sides of the gate pattern by means of an ion implantation process. A gate spacer(110) is formed at both sides of the gate pattern. Source/drain electrodes(112a,112b) connected to the drain electrode(112b) are formed on the drain electrode. A storage electrode connected to the source electrode is formed on the source electrode.
KR1020000002035A 2000-01-17 2000-01-17 Method for manufacturing semiconductor dram device KR20010080841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000002035A KR20010080841A (en) 2000-01-17 2000-01-17 Method for manufacturing semiconductor dram device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000002035A KR20010080841A (en) 2000-01-17 2000-01-17 Method for manufacturing semiconductor dram device

Publications (1)

Publication Number Publication Date
KR20010080841A true KR20010080841A (en) 2001-08-25

Family

ID=19639071

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000002035A KR20010080841A (en) 2000-01-17 2000-01-17 Method for manufacturing semiconductor dram device

Country Status (1)

Country Link
KR (1) KR20010080841A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451504B1 (en) * 2001-10-08 2004-10-06 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100455725B1 (en) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100455724B1 (en) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100666377B1 (en) * 2005-08-02 2007-01-09 삼성전자주식회사 Pad structure, method of forming the pad structure, semiconductor device having the pad structure and method of manufacturing the semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451504B1 (en) * 2001-10-08 2004-10-06 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100455725B1 (en) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100455724B1 (en) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 Method for forming plug in semiconductor device
KR100666377B1 (en) * 2005-08-02 2007-01-09 삼성전자주식회사 Pad structure, method of forming the pad structure, semiconductor device having the pad structure and method of manufacturing the semiconductor device

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