TW341728B - Process for producing a DRAM with a planar surface and less lithography mask - Google Patents

Abstract

A process for producing a DRAM, which comprises: forming a field oxide layer, polysilicon wordline and transfer gate transistor on a silicon semiconductor substrate, the transfer gate transistor comprising a gate oxide layer, gate and source/drain; depositing a first dielectric layer and using a lithography technique and etching technique to etch the first dielectric layer on the source/drain to expose the source/drain to simultaneously form a cell contact on the source region and a bit line contact on the drain region; depositing a layer of first polysilicon; etching back the first polysilicon to etch off a portion of the first polysilicon; depositing a layer of metal silicide; depositing a second dielectric layer; using a lithography technique and etching technique to etch the second dielectric layer, metal silicide and first polysilicon to form a bit line structure, while simultaneously forming a first polysilicon plug or stud in the cell contact; depositing a third dielectric layer; using an etching technique to etch back the third dielectric layer to form a third dielectric layer spacer on the secondary side of the bit line structure; depositing a layer of second polysilicon; using a lithography technique and etching technique to etch the second polysilicon outside the cell contact region to form a bottom electrode of capacitor; forming a capacitor dielectric layer; depositing a layer of third polysilicon; using a lithography technique and etching technique to etch the third polysilicon and capacitor dielectric layer to form a bottom electrode of capacitor.