TW288164B - Method of fabricating dynamic random access memory with E-shape capacitor - Google Patents

Abstract

A method of fabricating dynamic random access memory(DRAM) comprises the steps of: (1) forming active area and field oxide on semiconductor substrate; (2) forming metal oxide semiconductor field effect transistor(MOSFET) containing gate oxide, gate electrode, spacer and source/drain; (3) depositing first dielectric and etching the above first dielectric to form bit line contact; (4) forming bit line; (5) depositing second dielectric and third dielectric to overlay the above bit line, and by chemical mechanical polishing planarizing the above third dielectric; (6) by lithography and etch technique on capacitor region etching the above first dielectric, second dielectric and third dielectric to form node contact, and subsequent capacitor storage node electrically contacts with MOSFET through the above node contact; (7) depositing one first polysilicon to fill the above node contact and contact with source; (8) by chemical mechanical polishing performing polishing treatment to the above first polysilicon and third dielectric, in which the above polishing treatment removes one portion of the above third dielectric and reserves polysilicon pillar in node contact; (9) by lithography and etch technique on capacitor region etching the above third dielectric of some thickness on two sides of the above polysilicon pillar, so as to form trench on two sides of the above polysilicon pillar 22A; (10) depositing one second polysilicon which does not fill the above trench; (11) depositing fourth dielectric which fill the above trench; (12) by chemical mechanical polishing performing polishing treatment to the above fourth dielectric, second polysilicon and third dielectric and stops below top surface of the above polysilicon pillar; (13) removing left portion of the above third dielectric and fourth dielectric, and the above left polysilicon pillar and second polysilicon constitutes capacitor storage node; (14) forming one very thin capacitor dielectric on the above storage node surface, then forming one third polysilicon, and by lithography and etch technique etching the above capacitor dielectric and third polysilicon to form capacitor top electrode.