TW369701B - Transistor integration by dual spacer and process for self-aligned contact - Google Patents

Transistor integration by dual spacer and process for self-aligned contact

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Publication number
TW369701B
TW369701B TW087106642A TW87106642A TW369701B TW 369701 B TW369701 B TW 369701B TW 087106642 A TW087106642 A TW 087106642A TW 87106642 A TW87106642 A TW 87106642A TW 369701 B TW369701 B TW 369701B
Authority
TW
Taiwan
Prior art keywords
nitride
spacer
shelter
doped area
mask
Prior art date
Application number
TW087106642A
Other languages
Chinese (zh)
Inventor
zhen-ming Huang
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW087106642A priority Critical patent/TW369701B/en
Application granted granted Critical
Publication of TW369701B publication Critical patent/TW369701B/en

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Abstract

A process for transistor integration by dual spacer and for self-aligned contact, characterized by the following steps: first provide a substrate with peripheral circuitry and memory unit and gate electrode and a silicon nitride shelter are respectively defined on its surface. Next using nitride shelter as mask, plant ions on both sides of the substrate to form a lightly doped area, then form a silicon nitride spacer on the side wall. Using nitride shelter and nitride spacer as mask for memory unit, plant ions on both sides of its substrate to form a densely doped area which is extended to the bottom of the lightly doped area. Form a silicon oxide spacer on the side wall of each nitride spacer, and plant ions on both sides of the periphery circuitry substrate using nitride shelter, nitride spacer and oxide spacer as mask to form another densely doped area which is extended to the bottom of the lightly doped area. Form an inter-layer oxide to cover the layers on top of the substrates in sequence, then define a contact pattern at the designated position using nitride shelter and nitride spacer as mask, and etch the inter-layer oxide and oxide spacer until the corresponding densely doped are surface is exposed to form a self-aligned contact.
TW087106642A 1998-04-29 1998-04-29 Transistor integration by dual spacer and process for self-aligned contact TW369701B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087106642A TW369701B (en) 1998-04-29 1998-04-29 Transistor integration by dual spacer and process for self-aligned contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087106642A TW369701B (en) 1998-04-29 1998-04-29 Transistor integration by dual spacer and process for self-aligned contact

Publications (1)

Publication Number Publication Date
TW369701B true TW369701B (en) 1999-09-11

Family

ID=57941439

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106642A TW369701B (en) 1998-04-29 1998-04-29 Transistor integration by dual spacer and process for self-aligned contact

Country Status (1)

Country Link
TW (1) TW369701B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI498973B (en) * 2009-01-30 2015-09-01 Samsung Electronics Co Ltd Method of fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI498973B (en) * 2009-01-30 2015-09-01 Samsung Electronics Co Ltd Method of fabricating semiconductor device

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