TW288199B - Process of fabricating lightly doped drain with inverse-T-shaped gate - Google Patents

Process of fabricating lightly doped drain with inverse-T-shaped gate

Info

Publication number
TW288199B
TW288199B TW85104100A TW85104100A TW288199B TW 288199 B TW288199 B TW 288199B TW 85104100 A TW85104100 A TW 85104100A TW 85104100 A TW85104100 A TW 85104100A TW 288199 B TW288199 B TW 288199B
Authority
TW
Taiwan
Prior art keywords
forming
insulator
amorphous silicon
stacked amorphous
lightly doped
Prior art date
Application number
TW85104100A
Other languages
Chinese (zh)
Inventor
Shye-Lin Wu
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW85104100A priority Critical patent/TW288199B/en
Application granted granted Critical
Publication of TW288199B publication Critical patent/TW288199B/en

Links

Abstract

A process of fabricating lightly doped drain with inverse-T-shaped gate comprises of the steps of: (1) forming one gate oxide on substrate; (2) forming at least two layers of stacked amorphous silicon on the gate oxide; (3) forming first insulator on top of the stacked amorphous silicon, in which the first insulator is formed by masking one photoresist; (4) forming lightly doped source/drain electrode with the photoresist as implantation mask; (5) removing partial stacked amorphous silicon where is not masked by the photoresist to make the bottom expose; (6) forming second insulator spacer on the stacked amorphous silicon sidewall; (7) forming heavily doped source/drain with first insulator and second insulator spacer as implantation mask; (8) removing the stacked amorphous silicon bottom and the gate oxide where is not masked by the spacer; (9) removing the first insulator and second insulator spacer; (10) forming third insulator spacer on the gate oxide and the stacked amorphous silicon sidewall; (11) forming metal silicide on the stacked amorphous silicon top and above partial heavily doped source/drain electrode.
TW85104100A 1996-04-09 1996-04-09 Process of fabricating lightly doped drain with inverse-T-shaped gate TW288199B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW85104100A TW288199B (en) 1996-04-09 1996-04-09 Process of fabricating lightly doped drain with inverse-T-shaped gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW85104100A TW288199B (en) 1996-04-09 1996-04-09 Process of fabricating lightly doped drain with inverse-T-shaped gate

Publications (1)

Publication Number Publication Date
TW288199B true TW288199B (en) 1996-10-11

Family

ID=51398115

Family Applications (1)

Application Number Title Priority Date Filing Date
TW85104100A TW288199B (en) 1996-04-09 1996-04-09 Process of fabricating lightly doped drain with inverse-T-shaped gate

Country Status (1)

Country Link
TW (1) TW288199B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239003B1 (en) * 1998-06-16 2001-05-29 Texas Instruments Incorporated Method of simultaneous fabrication of isolation and gate regions in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239003B1 (en) * 1998-06-16 2001-05-29 Texas Instruments Incorporated Method of simultaneous fabrication of isolation and gate regions in a semiconductor device

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