TW277157B - Fabrication process of notching free polycide gate - Google Patents

Abstract

A fabrication method of MOS with polycide gate with narrow line and space comprises: forming field oxide on one silicon semiconductor substrate, exposing one portion of silicon substrate prepared as active region; forming one gate oxide layer on the above silicon substrate; forming one polysilicon layer on the above field oxide and gate oxide surface; forming one metal silicide layer on the above polysilicon layer surface; forming one rough surfaced silicon on the above SiO2 surface; forming one SiO2 layer on the above rough surfaced silicon; by etching patterning the pattern of the above SiO2 layer, rough surfaced silicon layer, metal silicide layer and polysilicon layer to form gate of transistor; by ion implantation doping the area of silicon substrate where is not covered by the above transistor gate to be conductive material.