TW289160B - Method of fabricating lightly doped drain transistor with differential spacer - Google Patents

Abstract

A method of fabricating complementary metal oxide semiconductor field effect transistor(CMOSFET), in which space width of N-type MOSFET is shorter than the one of P-type MOSFET, comprises the steps of: (1) forming field oxide for separating active area as isolation device on silicon semiconductor substrate; (2) forming gate oxide, gate electrode, N- lightly doped source/drain and P- lightly doped source/drain of N-type MOSFET and P-type MOSFET; (3) depositing one dielectric, and by etching forming first spacer on sides of gate of the above N-type MOSFET and P-type MOSFET; (4) by lithography forming photoresist pattern overlaying the above N-type MOSFET area, and by ion implantation forming P+ source/drain; (5) by etching performing etching to the above first spacer, making first spacer become second spacer with width shorter than the first spacer's; (6) by lithography forming photoresist pattern overlaying the above P-type MOSFET area, by ion implantation forming N+ source/drain.