KR960009076A - MOS transistor manufacturing method for driver IC - Google Patents

MOS transistor manufacturing method for driver IC Download PDF

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KR960009076A
KR960009076A KR1019940019294A KR19940019294A KR960009076A KR 960009076 A KR960009076 A KR 960009076A KR 1019940019294 A KR1019940019294 A KR 1019940019294A KR 19940019294 A KR19940019294 A KR 19940019294A KR 960009076 A KR960009076 A KR 960009076A
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impurity
oxide film
regions
silicon nitride
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KR1019940019294A
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KR0129960B1 (en
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고윤학
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

드라이버 집적회로(Driver IC)모스 트랜지스터 제조방법이 개시되어 있다. 반도체 기판 상에 패드산화막, 폴리 실리콘층 및 실리콘질화막을 차례로 적층하고, 기판상의 제1내지 제6영역에 해당하는 폴리실리콘층이 노출되도록 실리콘질화막을 식각한 다음, 제1영역의 일부영역, 제2 내지 제5영역 및 제6영역의 일부영역의 제1 불순물영역을 형성하고, 제1영역 및 제6영역의 제1불순물 영역과 인접하는 잔여영역에 제2불순물 영역을 형성한다. 이어서, 제1내지 제6영역에 필드산화막을 형성하고, 실리콘질화막, 폴리실리콘층, 및 패드산화막을 제거한다. 한편, 상기 결과물 상에 산화막을 성장시키고, 산화막을 패터닝하여 게이트 산화막을 형성하고, 게이트 폴리실리콘층을 형성한 다음, 제3불순물 영역을 형성한다. 상기 제1영역 및 제6영역의 바깥쪽 영역에 제4불순물 영역을 형성한다.Disclosed is a method for manufacturing a driver IC MOS transistor. The pad oxide film, the polysilicon layer, and the silicon nitride film are sequentially stacked on the semiconductor substrate, and the silicon nitride film is etched to expose the polysilicon layer corresponding to the first to sixth regions on the substrate, and then the partial region and the first region of the first region The first impurity region is formed in the partial region of the second to fifth regions and the sixth region, and the second impurity region is formed in the remaining region adjacent to the first impurity region of the first region and the sixth region. Subsequently, a field oxide film is formed in the first to sixth regions, and the silicon nitride film, the polysilicon layer, and the pad oxide film are removed. Meanwhile, an oxide film is grown on the resultant, the oxide film is patterned to form a gate oxide film, a gate polysilicon layer is formed, and then a third impurity region is formed. A fourth impurity region is formed in an outer region of the first region and the sixth region.

본 발명에 따르면, 채널에서 드레인에 이르는 저농도의 고저항 영역내에 고농도의 불순물 영역으로된 섬을 형성하여 고저항 영역을 절반이상 줄임으로써 동작저함을 감소시킬수 있다.According to the present invention, the operation deterioration can be reduced by forming an island composed of a high concentration of impurity regions in a low concentration high resistance region from the channel to the drain and reducing the high resistance region by more than half.

Description

드라이버 집적회로(Driver IC)용 모스 트랜지스터 제조방법MOS transistor manufacturing method for driver IC

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5A도 내지 제8B도는 본 발명에 따른 드라이버 집적회로 제조에 사용되는 모스 트랜지스터의 제조방법을 설명하기 위한 공정의 단면도.5A to 8B are cross-sectional views for explaining the manufacturing method of a MOS transistor used for manufacturing a driver integrated circuit according to the present invention.

Claims (7)

반도체 기판상에 패드산화막, 폴리실리콘층, 및 실리콘질화막을 차례로 적층하는 단계; 기판상의 제1 내지 제6영역에 해당하는 상기 폴리실리콘층이 노출되도록 실리콘질화막을 식각하는 단계; 상기 제1영역의 일부영역, 제2 내지 제5영역, 및 제6영역의 일부 영역에 기판과 반대 도전형의 제1불순물을 이온주입하여 제1불순물 영역을 형성하는 단계; 상기 제1영역 및 제6영역의 제1불순물영역과 인접하는 잔여영역에 기판과 같은 도전형의 제2불순물을 이온주입하여 제2불순물 영역을 형성하는단계; 상기 실리콘질화막을 마스크로 사용하여 상기 제1 내지 제6영역에 필드산화막을 형성하는 단계; 상기 실리콘질화막, 폴리실리콘층, 및 패드산화막을 제거하는 단계; 상기 결과물 상에 산화막을 성장시키고, 제3영역에 형성된 필드산화막과 제4영역에 형성된 필드산화막 사이의 산화막을 남기도록 상기 산화막을 패터닝하여 게이트 산화막을 형성하는 단계; 게이트 산화막이 혀성된 상기 결과물 상에 폴리실리콘층을 형성한 다음, 상기 제2영역에 형성된 필드산화막의 일부와 제4영역에 형성된 필드산화막의 일부에 걸쳐 형성되도록 상기 폴리실리콘층을 패터닝하여 게이트 폴리실리콘층을 형성하는 단계; 상기 제1 및 제2영역 형성된 필드산화막 사이의 영역, 상기 제2 및 제3영역에 형성된 필드산화막 사이의 영역, 상기 제4 및 제5영역에 형성된 필드산화막 사이의 영역, 및 상기 제5 및 제6영역에 형성된 필드산화막 사이의 영역에 기판과 반대 도전형의 제3불순물을 이온주입하여 제3불순물영역을 형성하는 단계 및 상기 제1 영역 및 제6영역의 바깥쪽 영역에 제4불순물을 이온주입하여 제4불순물영역을 형성하는 단계를 구비하는 것을 특징으로 하는 모스 트랜지스터 제조방법.Sequentially depositing a pad oxide film, a polysilicon layer, and a silicon nitride film on a semiconductor substrate; Etching the silicon nitride film to expose the polysilicon layers corresponding to the first to sixth regions on the substrate; Forming a first impurity region by ion implanting a first impurity of a conductivity type opposite to the substrate in the partial region of the first region, the second to fifth region, and the partial region of the sixth region; Forming a second impurity region by ion implanting a second impurity of a conductivity type, such as a substrate, into a remaining region adjacent to the first impurity region of the first and sixth regions; Forming a field oxide film on the first to sixth regions using the silicon nitride film as a mask; Removing the silicon nitride film, the polysilicon layer, and the pad oxide film; Growing an oxide film on the resultant, and patterning the oxide film to leave an oxide film between the field oxide film formed in the third region and the field oxide film formed in the fourth region to form a gate oxide film; A polysilicon layer is formed on the resultant gate oxide film, and then the polysilicon layer is patterned to be formed over a portion of the field oxide film formed in the second region and a portion of the field oxide film formed in the fourth region. Forming a silicon layer; A region between the field oxide films formed in the first and second regions, a region between the field oxide films formed in the second and third regions, a region between the field oxide films formed in the fourth and fifth regions, and the fifth and fifth regions Forming a third impurity region by ion implanting a third impurity of a opposite conductivity type to the substrate in a region between the field oxide films formed in the sixth region and ionizing a fourth impurity in an outer region of the first and sixth regions And forming a fourth impurity region by implantation. 제1항에 있어서, 상기 제2영역 및 제3영역 사의 상기 실리콘질화막은 상기 제2영역으로 주입되어 형성되는 제1불순물 영역과 제3영역으로 주입되어 형성되는 제1불순물영역이 연결될 수 있는 크기로 형성하고, 상기 제4영역 및 제5영역 사이의 상기 실리콘질화막은 상기 제4영역으로 주입되어 형성되는 제1불순물영역과 제5영역으로 주입되어 형성되는 제1불순물 영역이 연결될 수 있는 크기로 형성하는 것을 특징으로 하는 모스 트랜지스터 제조방법.2. The size of claim 1, wherein the silicon nitride layer of the second region and the third region is connected to a first impurity region formed by being injected into the second region and a first impurity region formed by being injected into a third region. And the silicon nitride film between the fourth region and the fifth region is sized to connect the first impurity region formed by being injected into the fourth region and the first impurity region formed by being injected into the fifth region. The MOS transistor manufacturing method characterized by forming. 제1항에 있어서, 상기 제2영역에서 제3영역에 이르는 폭이 0.5∼1.0μm인 것을 특징으로 하는 모스 트랜지스터 제조방법The MOS transistor manufacturing method of claim 1, wherein the width from the second region to the third region is 0.5 to 1.0 μm. 제1항에 있어서, 상기 제2불순물의 농도는 상기 제1불순물의 농도보다 고농도인 것을 특징으로 하는 모스(MOS) 트랜지스터 제조방법.The method of claim 1, wherein the concentration of the second impurity is higher than that of the first impurity. 제1항에 있어서, 상기 제3불순물의 농도는 상기 제2불순물의 농도보다 고농도인 것을 특징으로 하는 모스(MOS) 트랜지스터 제조방법.The method of claim 1, wherein the concentration of the third impurity is higher than that of the second impurity. 제1항에 있어서 , 상기 제3불순물이 n형인 비소(As)인 경우, 상기 이온주입 조건은 40∼80(keV)의 주입에너지와 3.0E15∼1.0E16(ions/cm2)의 도즈량인 것을 특징으로 하는 모스(MOS) 트랜지스터 제조방법.The method of claim 1, wherein when the third impurity is arsenic (As) of the n-type, the ion implantation conditions are the implantation energy of 40 to 80 (keV) and the dose amount of 3.0E15 to 1.0E16 (ions / cm 2 ) MOS transistor manufacturing method characterized in that. 제1항에 있어서, 상기 제3불순물이 p형인 붕소(B)인 경우, 상기 이온 주입조건은 40∼80(keV)의 주입에너지와 2.0E15∼1.0E16(ions/cm2)의 도즈량인 것을 특징으로 하는 모스(MOS)트랜지스터 제조방법.According to claim 1, wherein the third impurity is boron (B) of the p-type, the ion implantation conditions are 40 to 80 (keV) of implantation energy and 2.0E15 ~ 1.0E16 (ions / cm 2 ) of the dose amount MOS transistor manufacturing method characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940019294A 1994-08-04 1994-08-04 Fabrication method of mosfet for driver-ic KR0129960B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100975159B1 (en) * 2008-04-02 2010-08-10 강광욱 Domino game tool

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100975159B1 (en) * 2008-04-02 2010-08-10 강광욱 Domino game tool

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