KR20010095475A - method for fabricating CMOS Transistor - Google Patents

Abstract

PURPOSE: A fabrication method of a CMOS(Complementary MOS) transistor is provided to reduce a parasitic capacitance and to improve an integration degree of the transistors by forming a contact plug on a polysilicon layer. CONSTITUTION: After forming an n-well(102) in a substrate(100), a field oxide(104) is formed at an isolation region of the substrate. After forming a gate electrode(108a) on an active region, LDD(Lightly Doped Drain) regions(110a,110b) are formed at an NMOS and a PMOS transistor regions(A,B), respectively. An insulating spacer(112) is formed at both sidewalls of the gate electrode(108a). After forming a second polysilicon film(114) on the resultant structure, the second polysilicon film(114) is then selectively etched. N-type impurities and p-type impurities are sequentially implanted into the NMOS and the PMOS transistor regions(A,B), respectively. An annealing is carried out, so that n+ source and drain regions(122a) and p+ source and drain regions(122b) are self-aligned.

Description

Method for fabricating CMOS Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by reducing parasitic capacitance formed between a source / drain region and a substrate, low power consumption and high speed can be realized, and the size of a transistor The present invention also relates to a method of manufacturing a CMOS transistor that can be reduced.

A CMOS transistor is a device in which an NMOS transistor and a PMOS transistor coexist in one substrate, and are typically manufactured through the following fifth step process, as can be seen from the process steps shown in FIGS. 1A to 1E. As an example, a method of fabricating a CMOS transistor having a single well will be described. In the process flowchart, a region indicated by reference numeral A denotes an NMOS transistor formation portion, and a region denoted by reference numeral B denotes a PMOS transistor formation portion.

As a first step, after preparing the p-type semiconductor substrate 1 as shown in FIG. 1A, n-well impurities are selectively implanted into the substrate 1 of the portion B in which the PMOS transistor is to be formed and the N well (3) is formed, and the field oxide film 5 is formed in the element isolation region on the substrate 1 by the LOCOS method to define the active region. Subsequently, the gate oxide film 7 and the polysilicon film 9 are sequentially formed on the entire surface of the resultant product.

As a second step, as shown in FIG. 1B, the polysilicon film 9 is selectively etched using a resist pattern (not shown) defining a gate electrode forming portion as a mask, thereby forming a polysilicon material in an active region on the substrate 1. The gate electrode 9a is formed. Subsequently, a resist pattern (not shown) is formed on the resultant region of the remaining region except for the NMOS transistor forming unit A, and a low concentration n-type impurity is ion-implanted onto the substrate using the mask as a mask, followed by the resist pattern. Remove it. As a result, the n-LDD (lightly doped drain) region 11a is selectively formed only in the substrate 1 on both edges of the gate electrode 9a placed on the NMOS transistor forming portion A side. Thereafter, a resist pattern (not shown) is formed on the resultant region of the remaining region except for the PMOS transistor forming unit B, and a low concentration p-type impurity is ion-implanted onto the substrate using the mask as a mask, followed by the resist pattern. Remove it. As a result, the p-LDD region 11b is selectively formed only in the substrate 1 on both edges of the gate electrode 9a placed on the PMOS transistor forming portion B side.

Thus, before forming the source / drain regions, the n-LDD region 11a and the p-LDD region 11b are respectively formed on both edges of the gate electrode 9a through a low concentration n-type and p-type impurity implantation process. The reason for this is to prevent deterioration of device characteristics due to hot carriers during transistor driving.

As a third step, as shown in FIG. 1C, after forming spacers 15 of insulating material on both sidewalls of the gate electrode 9a, the remaining regions except for the NMOS transistor forming unit A are formed by using a photolithography process. A resist pattern 19 is formed on the resulting product, and a high concentration of n-type impurity is implanted onto the substrate using this as a mask. As a result, an n + type source / drain region 17a is selectively formed only in the substrate 1 on both edges of the spacer 15 placed on the NMOS transistor forming portion A side.

As a fourth step, as shown in FIG. 1D, the resist pattern 19 is removed, and the resist pattern 21 is again formed on the resultant region except for the PMOS transistor forming unit B by using a photolithography process. Then, a high concentration p-type impurity is implanted onto the substrate using this as a mask. As a result, a p + type source / drain region 17b is selectively formed only in the substrate 1 on both edges of the spacer 15 placed on the PMOS transistor forming portion B side.

As a fifth step, as shown in FIG. 1E, after removing the resist pattern 21, an insulating film 23 is formed on the entire surface of the resultant product, and the planarization thereof is performed. Subsequently, the insulating film 23 is selectively etched to form contact holes h so that the surfaces of the n + type source and drain regions 17a and the p + type source and drain regions 17b are exposed, respectively, and the contact holes h are formed. The contact wiring 25 is formed in a predetermined portion on the insulating film 23 including the ().

However, when manufacturing a CMOS transistor based on the above process sequence, the following problem occurs in device design.

In the case of the CMOS transistor shown in FIG. 1E, since the contact holes h are formed directly on the source and drain regions 17a and 17b, the source and drain regions must be defined including the contact hole area in the device design. As a result, there is a limit not only in reducing the junction area between the source / drain regions 17a, 17b and the substrate (or well) but also in reducing the size of the transistor.

When the junction area between the source / drain region and the substrate is large, the parasitic capacitance value formed between them is also larger than that otherwise, and it is difficult to implement low power consumption and high speed when driving the device. It is becoming.

Accordingly, an object of the present invention is to provide a polysilicon film over an active region and a field thin film separately from a gate electrode when manufacturing a CMOS transistor, so that contact holes are formed on the polysilicon film on the field oxide film, and The drain region provides a method of manufacturing a CMOS transistor in which the process progress is changed to be formed by the outdiffusion of the doped impurities in the polysilicon film, thereby reducing parasitic capacitance and reducing the size of the transistor.

1A to 1D are process flowcharts showing a conventional CMOS transistor manufacturing method,

2A to 2F are process flowcharts showing a method of manufacturing a CMOS transistor according to the present invention.

In order to achieve the above object, in the present invention, the step of forming a field oxide film on the isolation region on the semiconductor substrate with n well; Forming a gate oxide film in an active region on the substrate; Forming a gate electrode on a predetermined portion on the gate oxide film; Forming an n-LDD region in the substrate on both edges of the gate electrode of the NMOS transistor forming portion, and forming a p-LDD region in the n well on both edges of the gate electrode of the PMOS transistor forming portion; Forming insulating spacers on both edges of the gate electrode to expose the active region on the substrate; Sequentially depositing a polysilicon film and a photoresist film that are not doped with impurities on the resultant, and then etching back the exposed surface of the gate electrode to remove the remaining photoresist film; Selectively etching a second polysilicon film on the field oxide film; Ion implanting a high concentration n-type impurity onto the resultant portion of the NMOS transistor forming portion, and ion implanting a high concentration p-type impurity onto the resultant portion of the PMOS transistor forming portion; And the heat treatment is carried out so that the polysilicon film of the NMOS transistor forming portion is doped with a high concentration n-type impurity, and the polysilicon film of the PMOS transistor forming portion is doped with a high concentration p-type impurity and at the same time an n + type source / drain is formed in the substrate of the NMOS transistor forming portion. There is provided a CMOS transistor fabrication method comprising forming a region and forming a p + type source / drain region in a substrate of a PMOS transistor forming portion.

When manufacturing a CMOS transistor based on the above-described process procedure, since contact holes are formed on the polysilicon film on the field oxide film instead of the source and drain regions, the size of the source and drain regions can be made smaller than before. The parasitic capacitance formed between the n + type source / drain region and the substrate and between the p + type source / drain region and the n well can be reduced, and the size of the transistor can be reduced.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2F illustrate a process flowchart showing a method of manufacturing a CMOS transistor proposed in the present invention. Referring to this, the manufacturing method will be described in a fifth step as follows. As an example, a method of manufacturing a CMOS transistor having a single well will be described. In the process flowchart, a region indicated by reference numeral A denotes an NMOS transistor formation portion, and a region denoted by reference numeral B denotes a PMOS transistor formation portion.

As a first step, after preparing the n-type semiconductor substrate 100 as shown in Figure 2a, n-type impurities are selectively implanted into the substrate 100 of the portion (B) where the PMOS transistor is to be formed to n well And forming a field oxide film 104 in the device isolation region on the substrate 100 by applying a locus process. Subsequently, the gate oxide layer 106 and the first polysilicon layer 108 which are not doped with impurities are sequentially formed on the resultant.

As a second step, as shown in FIG. 2B, the first polysilicon layer 108 is selectively etched using a resist pattern (not shown) defining a gate electrode forming portion as a mask to form an active region on the substrate 100. 1 form a polysilicon gate electrode 108a. Subsequently, a resist pattern (not shown) is formed on the resultant region of the remaining region except for the NMOS transistor forming unit A, and a low concentration n-type impurity is ion-implanted onto the substrate using the mask as a mask, followed by the resist pattern. Remove it. As a result, the n-LDD region 110a is selectively formed only in the substrate 100 on both edges of the gate electrode 108a placed on the NMOS transistor forming portion A side. Thereafter, a resist pattern (not shown) is formed on the resultant region of the remaining region except for the PMOS transistor forming unit B, and a low concentration p-type impurity is ion-implanted onto the substrate using the mask as a mask, followed by the resist pattern. Remove it. As a result, the p-LDD region 110b is selectively formed only in the substrate 100 on both edges of the gate electrode 108a placed on the PMOS transistor forming portion B side.

As a third step, as shown in FIG. 2C, an insulating film made of an oxide film is formed on the resultant, and anisotropic dry etching (RIE) is performed to expose the active region on the substrate 100 so that both sidewalls of the gate electrode 108a are exposed. Insulation spacers 112 are formed. Subsequently, the second polysilicon layer 114 and the photoresist layer 116 which are not doped with impurities are sequentially formed on the resultant, and then etched back to expose the surface of the gate electrode 108a to planarize the film. To achieve.

As a fourth step, as shown in FIG. 2D, the remaining photoresist film 116 is removed, and then a second polysilicon film on the field oxide film 104 is selectively etched to separate the source and drain regions to be formed. Subsequently, a resist pattern 118 is formed on the resultant region except for the NMOS transistor forming unit A by using a photolithography process, and as a mask, a high concentration n-type impurity is formed on the substrate using 1E15 to 1E16 ( After ion implantation at a dose of ions / cm ² , the resist pattern 118 is removed.

As a fifth step, as shown in FIG. 2E, a resist pattern 120 is formed on the resultant region except for the PMOS transistor forming unit B by using a photolithography process, and the resist pattern 120 is used as a mask on the substrate. As a result, a high concentration of p-type impurities are implanted at a dose of 1E15 to 1E16 (ions / cm ² ), and then the resist pattern 120 is removed.

As a sixth step, heat treatment is performed as shown in FIG. 2F to dope the gate electrode 108a and the second polysilicon film 114 of the NMOS transistor forming portion A with high concentration n-type impurities to form a PMOS transistor. The gate electrode 108a of the portion B and the second polysilicon film 114 are doped with a high concentration p-type impurity. In this process, the substrate 100 of the NMOS transistor forming unit A is self-aligned to the spacer 112 by outdiffusion of impurities doped in the second polysilicon film 114. aligned n < + > type source / drain regions 122a are formed, and in the n well 102 of the PMOS transistor forming portion B, the dopant is doped out in the second polysilicon film 114. A p + type source / drain region 122b which is self-aligned with the spacer 112 is formed. Subsequently, an insulating film 124 is formed on the resultant and planarized, and then the insulating film 124 is selectively etched to partially expose the surface of the polysilicon film 114 on the field oxide film 104 to form a contact hole h. Form. Thereafter, the contact wiring 126 is formed in a predetermined portion on the insulating film 124 including the contact hole h, thereby completing the process.

In this case, since the contact hole h is formed on the polysilicon film 114 instead of the silicon substrate, it is not necessary to consider the contact hole size when forming the source / drain regions 122a and 122b. As a result, the area of the source and drain regions can be made smaller than before.

As a result, the junction area between the source / drain region and the substrate (or the well) can be reduced than before, and thus, between the n + type source / drain region 122a and the substrate 100 and the p + type source / drain region 122b. ) And the parasitic capacitance formed between the n well 102 can be reduced compared to the conventional method, and the additional effect of reducing the size of the transistor can be obtained.

As described above, according to the present invention, by changing the structure of the CMOS transistor so as to reduce the junction area between the source and drain regions and the substrate, the contact plug is formed on the polysilicon film on the field oxide film rather than the source and drain regions. In addition, since parasitic capacitance can be reduced, low power consumption and high speed can be realized while driving a device, and the size of a transistor can be reduced.

Claims (2)

forming a field oxide film on a device isolation region on a semiconductor substrate having n wells; Forming a gate oxide film in an active region on the substrate; Forming a gate electrode on a predetermined portion on the gate oxide film; Forming an n-LDD region in the substrate on both edges of the gate electrode of the NMOS transistor forming portion, and forming a p-LDD region in the n well on both edges of the gate electrode of the PMOS transistor forming portion; Forming insulating spacers on both edges of the gate electrode to expose the active region on the substrate; Sequentially depositing a polysilicon film and a photoresist film that are not doped with impurities on the resultant, and then etching back the exposed surface of the gate electrode to remove the remaining photoresist film; Selectively etching a second polysilicon film on the field oxide film; Ion implanting a high concentration n-type impurity onto the resultant portion of the NMOS transistor forming portion, and ion implanting a high concentration p-type impurity onto the resultant portion of the PMOS transistor forming portion; And the heat treatment is carried out so that the polysilicon film of the NMOS transistor forming portion is doped with a high concentration n-type impurity, and the polysilicon film of the PMOS transistor forming portion is doped with a high concentration p-type impurity, and an n + type source / drain is formed in the substrate of the NMOS transistor forming portion. And forming a p + type source / drain region in the region and in the substrate of the PMOS transistor forming portion. The method of claim 1, wherein after the heat treatment step Forming an insulating film on the resultant and planarizing it; Forming a contact hole by etching the insulating film to expose the surface of the polysilicon film on the field oxide film; And forming a contact wiring on a predetermined portion of the insulating film including the contact hole.