JP2844641B2 - Silicon planarization method - Google Patents

Silicon planarization method

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Publication number
JP2844641B2
JP2844641B2 JP5534989A JP5534989A JP2844641B2 JP 2844641 B2 JP2844641 B2 JP 2844641B2 JP 5534989 A JP5534989 A JP 5534989A JP 5534989 A JP5534989 A JP 5534989A JP 2844641 B2 JP2844641 B2 JP 2844641B2
Authority
JP
Japan
Prior art keywords
silicon
film
oxide film
silicon oxide
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5534989A
Other languages
Japanese (ja)
Other versions
JPH02234439A (en
Inventor
一郎 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5534989A priority Critical patent/JP2844641B2/en
Publication of JPH02234439A publication Critical patent/JPH02234439A/en
Application granted granted Critical
Publication of JP2844641B2 publication Critical patent/JP2844641B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造工程におけるシリコンの平
坦化方法に関する。
Description: BACKGROUND OF THE INVENTION The present invention relates to a method for planarizing silicon in a manufacturing process of a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体集積回路の高集積化に伴い、半導体素子を製造
する工程が多様になってきた。特に、半導体としてシリ
コンを用いた半導体装置を製造するうえで半導体素子を
形成すべきシリコン表面に凹凸を生じることがある。凹
凸が生じたシリコン上に半導体素子を形成した場合には
半導体素子の特性劣化につながる。第2図に凹凸が生じ
たシリコン表面に半導体素子を形成したときの様子を示
す。図中、11は半導体基板、12は層間絶縁膜、13は単結
晶シリコン膜、14はゲート絶縁膜、15はゲート電極、16
はn型高濃度不純物拡散層である。
2. Description of the Related Art With the increase in the degree of integration of semiconductor integrated circuits, the steps for manufacturing semiconductor elements have become diversified. In particular, when manufacturing a semiconductor device using silicon as a semiconductor, irregularities may be formed on a silicon surface on which a semiconductor element is to be formed. When a semiconductor element is formed on silicon having unevenness, the characteristics of the semiconductor element deteriorate. FIG. 2 shows a state in which a semiconductor element is formed on a silicon surface having irregularities. In the figure, 11 is a semiconductor substrate, 12 is an interlayer insulating film, 13 is a single crystal silicon film, 14 is a gate insulating film, 15 is a gate electrode, 16
Is an n-type high concentration impurity diffusion layer.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

凹凸が生じたシリコン上に半導体素子を形成した場
合、半導体素子の特性劣化につながるため凹凸を平坦に
することが必要であるが、平坦化する方法の一つとして
凹凸が生じたシリコン上に高分子有機膜等を塗布して表
面を平坦化し、高分子有機膜とシリコンのエッチングレ
ートが等しくなる条件でエッチングを行い、シリコンを
平坦にする方法が考えられる。しかしながら、高分子有
機膜とシリコンのエッチングレートが等しくなる条件で
はシリコン表面の凹凸とは別にシリコンが表面荒れを起
こすので実用的ではない。
When a semiconductor element is formed on silicon having unevenness, it is necessary to flatten the unevenness because the characteristic of the semiconductor element is deteriorated. A method of applying a molecular organic film or the like to flatten the surface and performing etching under the condition that the etching rate of the polymer organic film is equal to that of silicon to flatten silicon is considered. However, it is not practical under the condition that the etching rate of the polymer organic film is equal to the etching rate of silicon, because the surface of silicon is roughened separately from the unevenness of the silicon surface.

本発明の目的は上記課題を解決したシリコンの平坦化
方法を提供することにある。
An object of the present invention is to provide a method for planarizing silicon which has solved the above-mentioned problems.

〔課題を解決するための手段〕[Means for solving the problem]

前記目的を達成するため、本発明によるシリコンの平
坦化方法においては、凹凸のあるシリコン表面にシリコ
ン酸化膜を形成し、その上に高分子有機材料を用いて表
面を平坦化した後、高分子有機膜とシリコン酸化膜との
エッチングレートが等しい条件でエッチングを行い、シ
リコン酸化膜の表面を平坦化した後、シリコン酸化膜と
シリコンとのエッチングレートが等しい条件でエッチン
グを行い、シリコン表面を平坦化するものである。
In order to achieve the above object, in the method of planarizing silicon according to the present invention, a silicon oxide film is formed on an uneven silicon surface, and the surface is planarized using a high-molecular organic material. After the etching is performed under the condition that the etching rates of the organic film and the silicon oxide film are equal and the surface of the silicon oxide film is flattened, the etching is performed under the condition that the etching rates of the silicon oxide film and the silicon are equal and the silicon surface is flattened. It becomes something.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面を用いて詳細に説明す
る。第1図は本発明のシリコン平坦化方法を用いて製造
した半導体素子の構造を示す模式的断面図である。
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic sectional view showing the structure of a semiconductor device manufactured by using the silicon planarization method of the present invention.

図において、シリコン基板1上に層間絶縁膜2と半導
体素子を形成する単結晶シリコン膜3を順次設け、単結
晶シリコン膜3上にゲート絶縁膜4とゲート電極5とが
形成されている。以下、図示の半導体素子について、そ
の製造方法を述べる。
In the figure, an interlayer insulating film 2 and a single crystal silicon film 3 for forming a semiconductor element are sequentially provided on a silicon substrate 1, and a gate insulating film 4 and a gate electrode 5 are formed on the single crystal silicon film 3. Hereinafter, a manufacturing method of the illustrated semiconductor device will be described.

第3図(a),(b)は本発明のシリコンの平坦化方
法を順を追って示した模式図である。第3図(a)にお
いて、シリコン基板21上にシリコン酸化膜からなる層間
絶縁膜22を形成し、続いて多結晶シリコン層をCVD法を
用いて形成し、ゾーンメルト法を用いてポリシリコンの
単結晶化を行うことによって単結晶シリコン膜23を形成
する。このときポリシリコンの単結晶化によってシリコ
ン表面に凹凸が生じる。次に、単結晶シリコン膜23上に
少なくともシリコン表面の凹凸以上の膜厚のシリコン酸
化膜24をCVD法によって形成した後、高分子有機膜25を
スピン塗布法によって形成し、リフローベークによって
表面の平坦化を行う。続いて高分子有機膜とシリコン酸
化膜の等速エッチングを用いて矢印26までエッチングを
行う。次に、層間絶縁膜22のシリコン酸化膜と単結晶シ
リコン膜23の等速エッチングを矢印27まで行うと、単結
晶シリコン膜23の平坦化が行われ、第3図(b)の構造
が得られる。第1図は、この単結晶シリコン膜上にゲー
ト絶縁膜4を形成し、ゲート電極5をパターン形成した
後、イオン注入法を用いてn型高濃度不純物拡散層6を
形成したものである。
3 (a) and 3 (b) are schematic views sequentially showing a method for planarizing silicon of the present invention. 3 (a), an interlayer insulating film 22 made of a silicon oxide film is formed on a silicon substrate 21, a polycrystalline silicon layer is formed by a CVD method, and a polysilicon layer is formed by a zone melt method. The single crystal silicon film 23 is formed by performing single crystallization. At this time, irregularities occur on the silicon surface due to single crystallization of polysilicon. Next, after forming a silicon oxide film 24 having a thickness equal to or greater than the roughness of the silicon surface on the single-crystal silicon film 23 by a CVD method, a polymer organic film 25 is formed by a spin coating method, and the surface is reflow-baked. Perform planarization. Subsequently, etching is performed up to the arrow 26 by using uniform etching of the polymer organic film and the silicon oxide film. Next, when the silicon oxide film of the interlayer insulating film 22 and the single crystal silicon film 23 are etched at a constant speed up to the arrow 27, the single crystal silicon film 23 is planarized, and the structure of FIG. 3B is obtained. Can be FIG. 1 shows a structure in which a gate insulating film 4 is formed on this single crystal silicon film, a gate electrode 5 is patterned, and then an n-type high-concentration impurity diffusion layer 6 is formed by ion implantation.

以上、実施例では多結晶シリコンをゾーンメルト法を
用いて単結晶化する際に生じた凹凸の平坦化を行った
が、半導体素子製造工程中に生じたシリコンの凹凸の平
坦化であれば、多結晶シリコンの単結晶化に際して発生
した凹凸に限らない。
As described above, in the example, the unevenness generated when the polycrystalline silicon was single-crystallized by using the zone melt method was flattened, but if the unevenness of the silicon generated during the semiconductor element manufacturing process was flattened, The present invention is not limited to the irregularities generated during the single crystallization of polycrystalline silicon.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、平坦なシリコン表面に
半導体素子を形成することができ、信頼性を向上できる
効果を有する。
As described above, according to the present invention, a semiconductor element can be formed on a flat silicon surface, and there is an effect that reliability can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明を用いて製造した半導体素子の断面図、
第2図は従来例を示す模式図、第3図(a),(b)は
本発明の製造工程を説明する模式図である。 1,21……シリコン基板、2,22……層間絶縁膜 3,23……単結晶シリコン膜、4……ゲート絶縁膜 24……シリコン酸化膜、5……ゲート電極 25……高分子有機膜 6……n型高濃度不純物拡散層 26……高分子有機材料とシリコン酸化膜の等速エッチン
グ終点(矢印) 27……シリコン酸化膜と単結晶シリコンの等速エッチン
グ終点(矢印)
FIG. 1 is a cross-sectional view of a semiconductor device manufactured using the present invention,
FIG. 2 is a schematic diagram showing a conventional example, and FIGS. 3 (a) and 3 (b) are schematic diagrams for explaining a manufacturing process of the present invention. 1,21 ... Silicon substrate, 2,22 ... Interlayer insulation film 3,23 ... Single crystal silicon film, 4 ... Gate insulation film 24 ... Silicon oxide film, 5 ... Gate electrode 25 ... Polymer organic Film 6: n-type high-concentration impurity diffusion layer 26: constant-speed etching end point of polymer organic material and silicon oxide film (arrow) 27: constant-speed etching end point of silicon oxide film and single crystal silicon (arrow)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】凹凸のあるシリコン表面にシリコン酸化膜
を形成し、その上に高分子有機材料を用いて表面を平坦
化した後、高分子有機膜とシリコン酸化膜とのエッチン
グレートが等しい条件でエッチングを行い、シリコン酸
化膜の表面を平坦化した後、シリコン酸化膜とシリコン
とのエッチングレートが等しい条件でエッチングを行
い、シリコン表面を平坦化することを特徴とするシリコ
ンの平坦化方法。
1. A method in which a silicon oxide film is formed on an uneven silicon surface, the surface is flattened using a polymer organic material, and then the etching rates of the polymer organic film and the silicon oxide film are equal. A flattening method for a silicon oxide film, wherein the surface of the silicon oxide film is flattened, and then the silicon oxide film is etched under the same etching rate as that of silicon to flatten the silicon surface.
JP5534989A 1989-03-07 1989-03-07 Silicon planarization method Expired - Lifetime JP2844641B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5534989A JP2844641B2 (en) 1989-03-07 1989-03-07 Silicon planarization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5534989A JP2844641B2 (en) 1989-03-07 1989-03-07 Silicon planarization method

Publications (2)

Publication Number Publication Date
JPH02234439A JPH02234439A (en) 1990-09-17
JP2844641B2 true JP2844641B2 (en) 1999-01-06

Family

ID=12996024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5534989A Expired - Lifetime JP2844641B2 (en) 1989-03-07 1989-03-07 Silicon planarization method

Country Status (1)

Country Link
JP (1) JP2844641B2 (en)

Also Published As

Publication number Publication date
JPH02234439A (en) 1990-09-17

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