JPH0242719A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0242719A JPH0242719A JP19211788A JP19211788A JPH0242719A JP H0242719 A JPH0242719 A JP H0242719A JP 19211788 A JP19211788 A JP 19211788A JP 19211788 A JP19211788 A JP 19211788A JP H0242719 A JPH0242719 A JP H0242719A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- silicon
- semiconductor device
- deposited
- solid phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 9
- 239000007790 solid phase Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000001994 activation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は信顧性の高い配線を有する半導体装置の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device having highly reliable wiring.
第２図は従来のＭＯ５型半導体素子の断面図であり、’
？ｌＯＳトランジスタの部分のみを示したものである。Figure 2 is a cross-sectional view of a conventional MO5 type semiconductor device.
? Only the lOS transistor portion is shown.
従来におけるこのＭＯ３型半導体素子の製造方法につい
て以下説明する。まず、半導体基板１０１の表面を通常
のＬＯＣＯ３法を用いて、フィールド酸化膜１０２とア
クティブ領域１０３とに分離する。このとき、フィール
ド酸化膜１０２の下部にはチャネルストップドーピング
を行なっておく。次に、アクティブ領域１０３の上部に
ゲート酸化膜１０４を形成した後、ゲート電極１０５を
堆積し、パターニングする０次に、ソース・ドレイン領
域１０６を得るべく、半導体基板１０１と逆導電形の不
純物をイオン注入しアニールによる活性化工程を経た後
、中間絶縁膜１０７の堆積を行ない、さらにコンタクト
孔１０８のパターニングを行なう、最後に、配線材料１
０９の堆積、パターニングを行ない、シンクを経て完成
する。なお、ここに述べた工程では、パッシベーション
膜の形成等は省略しである。A conventional method of manufacturing this MO3 type semiconductor device will be described below. First, the surface of a semiconductor substrate 101 is separated into a field oxide film 102 and an active region 103 using the usual LOCO3 method. At this time, channel stop doping is applied to the lower part of the field oxide film 102. Next, after forming a gate oxide film 104 on the top of the active region 103, a gate electrode 105 is deposited and patterned. Next, in order to obtain a source/drain region 106, impurities of the opposite conductivity type to the semiconductor substrate 101 are added. After ion implantation and an activation process by annealing, an intermediate insulating film 107 is deposited, and contact holes 108 are patterned.Finally, wiring material 1
09 is deposited, patterned, and completed through a sink. Note that in the steps described here, the formation of a passivation film and the like are omitted.
ところで、上記のように製造された半導体装置において
は、コンタクト孔１０８のアスペクト比はデバイスの微
細化に伴い、太き（なる、このような高アスペクト比を
有するコンタクト孔１０８には、通常のスパッタ法では
配線材料１０９が入り込み難く、このためカバレージが
悪（なり、最悪の場合には断線を生じる。そこで、最近
では、スパッタ中に半導体基板１０１に電圧を印加する
バイアススパッタ法が用いられており、このバイアスス
パッタ法によれば、半導体基板１０１にスパッタ中に電
圧を印加することによりスパッタ収率の角度依存性が生
じることあるいは電圧印加の条件によりスパッタ中の配
線材料１０９が半溶融状態となることにより、高アスペ
クト比のコンタクト孔１０８にも配線材料１０９が入り
込む。By the way, in the semiconductor device manufactured as described above, the aspect ratio of the contact hole 108 has become thicker (as the device becomes finer). With this method, it is difficult for the wiring material 109 to penetrate, resulting in poor coverage (and in the worst case, disconnection).Therefore, recently, a bias sputtering method has been used in which a voltage is applied to the semiconductor substrate 101 during sputtering. According to this bias sputtering method, applying a voltage to the semiconductor substrate 101 during sputtering causes angular dependence of the sputtering yield, or the wiring material 109 during sputtering becomes a semi-molten state depending on the voltage application conditions. As a result, the wiring material 109 also enters the contact hole 108 having a high aspect ratio.
しかしながら、上記のようにバイアススパッタ法を用い
た場合には、通常のスパッタ法で形成した配線金属に比
較して膜荒れが生じ易くなる。このため、パターニング
に際して合せ精度が著しく劣化するというカバレージ以
外の短所が生した。However, when bias sputtering is used as described above, film roughness is more likely to occur compared to wiring metal formed by normal sputtering. For this reason, a disadvantage other than coverage has arisen in that alignment accuracy is significantly degraded during patterning.
又、バイアススパッタ法により形成された膜は、スパッ
タターゲット形状の変化のため、再現性に乏しかった。Furthermore, films formed by bias sputtering had poor reproducibility due to changes in the shape of the sputtering target.
この発明は上記のような課題を解決するために成された
ものであり、高アスペクト比のコンタクト孔への配線に
おけるカバレージの悪化や膜荒れを防止するとともに再
現性に富み信頼性のある半導体装置の製造方法を得るこ
とを目的とする。This invention was made to solve the above-mentioned problems, and provides a semiconductor device that prevents deterioration of coverage and film roughness in wiring to contact holes with high aspect ratios, and is highly reproducible and reliable. The purpose is to obtain a manufacturing method for.
この発明に係る半導体装置の製造方法は、コンタクト孔
を含めた全面にパラジウム及び非晶質シリコンを堆積す
る工程と、熱処理を行ない、コンタクト孔における非晶
質シリコンをパラジウムシリコン膜を通して固相成長さ
せる工程と、熱処理の際にコンタクト孔以外で形成され
た多結晶シリコンを除去する工程と、上記固相成長部を
活性化した後上部に配線を形成する工程を備えたもので
ある。The method for manufacturing a semiconductor device according to the present invention includes a step of depositing palladium and amorphous silicon on the entire surface including the contact hole, and heat treatment to grow the amorphous silicon in the contact hole in a solid phase through a palladium silicon film. The method includes a step of removing polycrystalline silicon formed outside the contact hole during heat treatment, and a step of activating the solid phase growth portion and then forming wiring thereon.
この発明においては、全面にパラジウム及び非晶質シリ
コンが堆積された後熱処理が行なわれ、コンタクト孔に
おいてはこの際形成されたパラジウムシリコン膜を通し
て非晶質シリコンが固相成長し、コンタクト孔以外では
多結晶シリコンが形成される。この多結晶シリコンは除
去され、固相成長部では活性化の後配線が形成される。In this invention, heat treatment is performed after palladium and amorphous silicon are deposited on the entire surface, and amorphous silicon grows in a solid phase through the palladium silicon film formed at this time in the contact hole, and in other areas other than the contact hole. Polycrystalline silicon is formed. This polycrystalline silicon is removed, and wiring is formed in the solid phase growth portion after activation.
以下、この発明の実施例を図面とともに説明する。第１
図（ａｌ〜＋ｄｉはこの実施例によるＭＯ３型半導体素
子の製造工程を示す断面図である。まず、！ａ１図に示
すように、半導体基板２０１の表面を通常のＬＯＣＯ５
法を用いてフィールド酸化ＩＪｉ２０２とアクティブ領
域２０３とに分離する。このとき、フィールド酸化膜２
０２の下部には、予めチャネルストップドーピングを行
なっておく。次に、アクティブ領域２０３の上部にゲー
ト酸化膜２０４を形成した後、このゲート酸化膜２０４
上にゲート電極２０５を堆積し、パターニングする。次
に、ソース・ドレイン領域２０６を得るべく半導体基ｖ
ｉ、２０１と逆導電形の不純物をイオン注入し、アニー
ルにより活性化した後、全面に中間絶縁膜２０７の堆積
を行ない、この中間絶縁膜２０７にコンタクト孔２０Ｂ
のパターニングを行なう。Embodiments of the present invention will be described below with reference to the drawings. 1st
Figures (al to +di are cross-sectional views showing the manufacturing process of the MO3 type semiconductor device according to this embodiment. First, as shown in Figure !a1, the surface of the semiconductor substrate 201 is
The field oxidation IJi 202 and the active region 203 are separated using a method. At this time, field oxide film 2
Channel stop doping is performed on the lower part of 02 in advance. Next, after forming a gate oxide film 204 on the upper part of the active region 203, this gate oxide film 204
A gate electrode 205 is deposited thereon and patterned. Next, in order to obtain the source/drain regions 206, the semiconductor substrate v
After ion-implanting impurities of the opposite conductivity type to 201 and activating them by annealing, an intermediate insulating film 207 is deposited on the entire surface, and a contact hole 20B is formed in this intermediate insulating film 207.
Perform patterning.
次に、ｆｂ１図に示すように、全面にＰｄ２０９を約５
００〜２０００人堆積し、続いて非晶質５ｉ２１０を全
面に堆積する。非晶質５ｉ２１０の厚さはコンタクト孔
２０８の直径及びアスペクト比に大きく依存するが、コ
ンタクト孔２０８の直径の１７２以上の厚さ、例えばコ
ンタクト孔２０８が１μφの場合５０００Å以上の厚さ
となる。Next, as shown in figure fb1, about 50% of Pd209 was applied to the entire surface.
00 to 2000, and then amorphous 5i210 is deposited on the entire surface. Although the thickness of the amorphous 5i 210 largely depends on the diameter and aspect ratio of the contact hole 208, it is 172 or more of the diameter of the contact hole 208, for example, if the contact hole 208 is 1 μφ, the thickness is 5000 Å or more.
次に、２８０℃前後の温度で不活性ガス中で約３０分間
熱処理を行なうと、堆積したＰｄ２０９はＰｄｚＳｉ
に変化する。この後、５００〜６００℃の熱処理をさら
に加えると、堆積した非晶質５ｉ２１０はコンタクト孔
２０８内においてはＰｉＳｉ を通してエピタキシャル
成長してｔｏ１図に示すようにエピタキシャル成長層２
１１を形成し、フィールド酸化膜２０２上では多結晶５
ｉ２１２となる・又・この熱処理によってＰｄｚＳｉ
はＰｄｘＳｉｙ２１３という組成になる。ｘ、ｙは熱処
理温度によって異なってく る 。Next, when heat treatment is performed for about 30 minutes in an inert gas at a temperature of around 280°C, the deposited Pd209 becomes PdzSi.
Changes to After that, when heat treatment is further applied at 500 to 600°C, the deposited amorphous 5i 210 grows epitaxially through PiSi in the contact hole 208, and as shown in the TO1 diagram, the deposited amorphous 5i 210 grows epitaxially.
11 is formed, and polycrystalline 5 is formed on the field oxide film 202.
By this heat treatment, PdzSi becomes i212.
has a composition of PdxSiy213. x and y vary depending on the heat treatment temperature.
この後、ｆｄ１図に示すように、多結晶５ｉ２１２を選
択的に除去し、コンタクト孔２０８に成長したエピタキ
シャル成長層２１１にイオン注入によりソース・ドレイ
ン領域２０６と同じ極性を有する不純物をドープして活
性化する。続いてＡ１２１４を堆積してバターニングし
、ＭＯ３型半導体素子が完成する。After that, as shown in the fd1 diagram, the polycrystalline 5i 212 is selectively removed, and the epitaxial growth layer 211 grown in the contact hole 208 is doped with impurities having the same polarity as the source/drain region 206 by ion implantation and activated. do. Subsequently, A1214 is deposited and patterned to complete the MO3 type semiconductor device.
なお、上記実施例においてＰｄと非晶質Ｓｔを用いたの
は、熱処理の際に形成されるＰｄ２Ｓｉ を通してエピ
タキシャル成長層２１１が形成可能なためである。The reason why Pd and amorphous St are used in the above embodiment is that the epitaxial growth layer 211 can be formed through Pd2Si formed during heat treatment.
以上のようにこの発明によれば、コンタクト孔の開花後
パラジウムと非晶質シリコンを堆積し、熱処理によりコ
ンタクト孔においてのみシリコンを固相成長させ、その
他の部分に形成されたシリコンを除去するようにしてい
る。このため、コンタクト孔にのみシリコンが埋め込ま
れたことになり、アスペクト比が大きなコンバク孔であ
ってもその後の配線作業が容易となり、カバレージの悪
化は生じない。又、バイアスの印加を行なう必要がない
ために、膜荒れは生じず、再現性にも問題はなく、信転
性のある半導体装置が得られる。As described above, according to the present invention, palladium and amorphous silicon are deposited after the contact hole blooms, silicon is grown in solid phase only in the contact hole by heat treatment, and silicon formed in other parts is removed. I have to. Therefore, silicon is embedded only in the contact hole, and even if the contact hole has a large aspect ratio, the subsequent wiring work is easy and no deterioration in coverage occurs. Further, since there is no need to apply a bias, film roughness does not occur, there is no problem in reproducibility, and a semiconductor device with high reliability can be obtained.
第１図ｆａｔ〜＋ｄｌはこの発明による半導体装置の製
造方法を示す工程断面図、第２図は従来方法によるＭＯ
３型半導体素子の断面図である。
２０１・・・半導体基板、２０３・・・アクティブ領域
、２０８・・・コンタクト孔、２０９・・・Ｐｄ、２１
０・・・非晶質Ｓｉ、２１１・・・エピタキシャル成長
層、２１２・・・多結晶シリコン、２１４・・・ＡＩ。
本発明方法１こよる工程断面図
第１ 図
本発明方法（こよる工程断面図
第１図FIG. 1 fat to +dl is a process cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a MO by a conventional method.
FIG. 3 is a cross-sectional view of a type 3 semiconductor element. 201... Semiconductor substrate, 203... Active region, 208... Contact hole, 209... Pd, 21
0... Amorphous Si, 211... Epitaxial growth layer, 212... Polycrystalline silicon, 214... AI. Process sectional view of method 1 of the present invention Fig. 1 Cross-sectional view of the process of the present invention method 1
Claims (1)
膜にコンタクト孔を開孔する工程と、 （ｂ）コンタクト孔を含めた全面にパラジウムを堆積し
た後、非晶質シリコンを堆積する工程と、 （ｃ）熱処理を行ない、コンタクト孔における非晶質シ
リコンを熱処理により形成されたパラジウムシリコン膜
を通して半導体基板のアクティブ領域に対して固相成長
させる工程と、 （ｄ）上記熱処理の際にコンタクト孔以外で非晶質シリ
コンから形成された多結晶シリコンを除去する工程と、 （ｅ）上記固相成長部を活性化した後上部に配線を形成
する工程 を備えたことを特徴とする半導体装置の製造方法[Claims] (a) A step of forming a contact hole in an insulating film formed on an active region of a semiconductor substrate; (b) After depositing palladium on the entire surface including the contact hole, an amorphous (c) performing heat treatment to grow the amorphous silicon in the contact hole in a solid phase onto the active region of the semiconductor substrate through the palladium silicon film formed by the heat treatment; (d) the above step; A step of removing polycrystalline silicon formed from amorphous silicon other than the contact hole during heat treatment; and (e) a step of activating the solid phase growth part and then forming a wiring above it. Characteristic semiconductor device manufacturing method
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19211788A JPH0242719A (en) | 1988-08-02 | 1988-08-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19211788A JPH0242719A (en) | 1988-08-02 | 1988-08-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0242719A true JPH0242719A (en) | 1990-02-13 |
Family
ID=16285952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19211788A Pending JPH0242719A (en) | 1988-08-02 | 1988-08-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0242719A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5409853A (en) * | 1994-05-20 | 1995-04-25 | International Business Machines Corporation | Process of making silicided contacts for semiconductor devices |
| US5879997A (en) * | 1991-05-30 | 1999-03-09 | Lucent Technologies Inc. | Method for forming self aligned polysilicon contact |
| WO2007057796A1 (en) * | 2005-11-16 | 2007-05-24 | Nxp B.V. | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
-
1988
- 1988-08-02 JP JP19211788A patent/JPH0242719A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5879997A (en) * | 1991-05-30 | 1999-03-09 | Lucent Technologies Inc. | Method for forming self aligned polysilicon contact |
| US5409853A (en) * | 1994-05-20 | 1995-04-25 | International Business Machines Corporation | Process of making silicided contacts for semiconductor devices |
| WO2007057796A1 (en) * | 2005-11-16 | 2007-05-24 | Nxp B.V. | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
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