KR20000074449A - Thin film transistor and the method of fabricating the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film transistor(TFT) is provided to shorten the time for crystallization by simultaneously crystallizing intrinsic amorphous silicon and impurity amorphous silicon, and to reduce a manufacturing time by performing an activation while performing a crystallization to polycrystalline silicon. CONSTITUTION: A substrate is prepared. A gate electrode is formed in a predetermined position of the substrate. An insulating layer is evaporated on the gate electrode and an exposed substrate. Intrinsic amorphous silicon is evaporated on the insulating layer. Impurity silicon is formed on the intrinsic amorphous silicon. A catalyst metal is coated on the impurity amorphous silicon. A direct current voltage is applied across both ends of a predetermined position on the impurity amorphous silicon coated with the catalyst metal, so that the intrinsic amorphous silicon and impurity amorphous silicon are crystallized to intrinsic polycrystalline silicon and impurity polycrystalline silicon. Source/drain electrodes are formed on the impurity polycrystalline silicon. The impurity polycrystalline silicon positioned between the source/drain electrodes is etched by using the source/drain electrodes. A process for coating a metal is included after the evaporation process of the impurity amorphous silicon, and before the crystallization process.

Description

Thin film transistor and the method of fabrication the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display using a polycrystalline thin film transistor, which is a switching element using a channel made of polycrystalline silicon, and a manufacturing method thereof.

In general, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) is a predetermined method, that is, amorphous silicon by plasma vapor deposition (Plasma chemical vapor deposition) or LPCVD (Low pressure CVD) method of 500 Å thickness on an insulating substrate After the film was deposited, a method of crystallizing it was used. The crystallization method can be classified into three types as follows.

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, which supplies laser energy to a substrate on which amorphous silicon is deposited to make the amorphous silicon in a molten state, and then forms polycrystalline silicon by cooling.

The second method, solid crystallization, forms a buffer layer to a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then heats the furnace at a high temperature. As a method of obtaining polycrystalline silicon by heat treatment for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular, so that polycrystalline silicon and The gate insulating film to be connected is irregularly grown, which lowers the breakdown voltage of the device, and the grain size of the polycrystalline silicon is extremely uneven, which lowers the device's electrical characteristics and requires the use of an expensive quartz substrate. There is a problem.

The third method, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate. However, since metal residues are more likely to be present in the network inside the polycrystalline silicon, it is possible to ensure film quality reliability. However, attempts are being made to apply the MIC method newly to apply crystallized polycrystalline silicon to thin film transistors and switching elements of liquid crystal displays.

Hereinafter, a manufacturing process of a liquid crystal display using a conventional polycrystalline silicon thin film transistor will be described with reference to the accompanying drawings.

1A to 1E illustrate a process of fabricating a conventional polycrystalline silicon thin film transistor.

First, the drawing illustrated in FIG. 1A is a process of continuously depositing the first insulating material 2 and the amorphous silicon 4 on the substrate 1. The first insulating film 2 is for preventing the elution of the alkali material in the substrate 1 which may be generated in a later process.

After the amorphous silicon 4 is deposited, it is crystallized by a predetermined crystallization method. The crystallization method has been described above, the description will be described by a general laser crystallization method.

Thereafter, the step of patterning the polycrystalline silicon crystallized in the process of FIG. 1A into the island 8 of the active layer is shown in FIG. 1B.

The process illustrated in FIG. 1C is a step of forming a gate insulating film and a gate electrode, forming a gate insulating film 10 and a gate electrode 12 as a second insulating layer on the island 8. The island 8 may be divided into two regions, in which the first active region 14 is a pure silicon region, and the second active regions 16 and 17 are impurity regions. The second active regions 16 and 17 are located at both edges of the first active region 14.

In addition, the gate insulating layer 10 and the gate electrode 12 are formed on the first active region 14.

The gate electrode 12 and the gate insulating film 10 are formed in the same pattern to reduce the number of masks. After the gate electrode 12 is formed, ion doping is performed to form an ohmic contact layer in the second active region. In this case, the gate electrode 12 serves as an ion stopper to prevent the dopant from penetrating into the first active 14 region. The ions, depending on the type of dopant and the doping during changes the electrical properties of the silicon island (8), the dopant is a P- type semiconductor when doped with a Group III element such as B ₂ H _6, PH _3, such as a Group 5 When the element is doped, it acts as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device. The ion doping process is followed by a process of activating the dopant.

FIG. 1D illustrates the deposition and patterning of an interlayer insulator 18, which is a third insulating layer, over the entire surface of the gate electrode 12, the second active regions 16 and 17, and the first insulating layer 2. In the step, source / drain contact holes 16 'and 17' are formed in the second active regions 16 and 17, respectively.

The figure shown in FIG. 1E is a combination of several processes.

First, the source electrode 20 and the drain electrode 22 contacting the second active regions 16 and 17, respectively, are formed through the contact holes 16 ′ and 17 ′ formed in FIG. 1D.

Thereafter, the protective layer 26 is deposited and patterned on the electrodes 20 and 22 and the entire surface of the substrate to form a contact hole in the protective layer 26 on the drain electrode 22.

The transparent conductive electrode is deposited and patterned to form a pixel electrode 28 in electrical contact with the drain electrode 22 through a contact hole formed in the protective layer 26 on the drain electrode 22.

The manufacturing process of the liquid crystal display device manufactured by the conventional laser silicon crystallization method is as above-mentioned. In other words, a polycrystalline silicon thin film transistor type liquid crystal display device having a top gate coplanar structure is manufactured.

However, when a thin film transistor is manufactured by the above-described conventional method of manufacturing a polycrystalline silicon thin film transistor, the manufacturing process of an amorphous silicon thin film transistor liquid crystal display device which is generally used is deviated.

That is, the thin film transistor, which is a switching element generally used in a liquid crystal display, is formed in an inverted staggered structure in which a gate electrode is formed on a substrate. However, when the thin film transistor is formed by the above-described method, the gate electrode is used. Since the coplanar thin film transistor structure formed on the active layer is applied, additional production equipment such as changing the existing process sequence is required.

In addition, due to a problem that the dopants penetrate into the first active region, that is, the channel layer in the activation process of the dopant, there is a disadvantage that the electrical characteristics of the thin film transistor may be degraded.

In addition, the liquid crystal display device using the coplanar polycrystalline silicon thin film transistor has a disadvantage in that an activation process is added, and thus, it is more complicated than the conventional liquid crystal display device using amorphous silicon.

Therefore, an object of the present invention is to use a manufacturing process of an existing liquid crystal display device as it is in a liquid crystal display device employing a polycrystalline silicon thin film transistor.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device, in which an activation process is unnecessary.

In addition, when polycrystalline silicon is formed by the MIC method in the crystallization method, an object of the present invention is to prevent a decrease in electrical characteristics due to metal contamination in the channel region of the polycrystalline silicon thin film transistor.

1A to 1E are process drawings showing a manufacturing process of a liquid crystal display device using a polycrystalline silicon thin film transistor according to the prior art.

2A to 2E are process charts showing a manufacturing process of the liquid crystal display device according to the first embodiment of the present invention.

3A to 3G are process drawings showing the manufacturing process of the liquid crystal display device according to the second embodiment of the present invention.

4A to 4B are process diagrams showing another process of the second embodiment of the present invention.

5 is a diagram showing current-voltage characteristics of a thin film transistor fabricated according to embodiments of the present invention.

<Description of the symbols for the main parts of the drawings>

50 gate electrode 52 insulating film

54: Pure Amorphous Silicon 56: Impurity Amorphous Silicon

56 amorphous silicon 60 source electrode

62 drain electrode 64 protective film

68 pixel electrode 86 etching prevention film

6: DC high voltage power supply

In order to achieve the above object, the present invention includes the steps of providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film on the gate electrode and the exposed substrate; Depositing pure amorphous silicon on the insulating film; Forming impurity silicon on the pure amorphous silicon; Coating a catalyst metal on the impurity amorphous silicon; Applying a direct current voltage to both ends of a predetermined position on the impurity amorphous silicon coated with the catalytic metal to crystallize the pure amorphous silicon and the impurity amorphous silicon into pure polycrystalline silicon and impurity polycrystalline silicon; Patterning the crystallized pure polycrystalline silicon and the impurity polycrystalline silicon into an island around the gate electrode; Forming a source and a drain electrode over the patterned island; A method of fabricating a thin film transistor including etching an impurity polycrystalline silicon positioned between the source and drain electrodes using the source and drain electrodes as a mask is disclosed.

In addition, the present invention comprises the steps of providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film on the gate electrode and the exposed substrate; Depositing pure amorphous silicon on the insulating film; Forming impurity silicon on the pure amorphous silicon; Coating a catalyst metal on the impurity amorphous silicon; Applying a direct current voltage to both ends of a predetermined position on the impurity amorphous silicon coated with the catalytic metal to crystallize the pure amorphous silicon and the impurity amorphous silicon into pure polycrystalline silicon and impurity polycrystalline silicon; Patterning the crystallized pure polycrystalline silicon and the impurity polycrystalline silicon into an island around the gate electrode; Forming a source and a drain electrode over the patterned island; Etching the impurity polycrystalline silicon positioned between the source and drain electrodes using the source and drain electrodes as a mask; Depositing a protective film over the entire surface of the source and drain electrodes and portions exposed by the source and drain electrodes, and patterning a portion of the drain electrode to be exposed; A method of manufacturing a liquid crystal display device including forming a pixel electrode in contact with the drain electrode through a contact hole formed on the passivation layer is disclosed.

In addition, the present invention comprises the steps of providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Continuously depositing an insulating film and pure amorphous silicon on the gate electrode and the exposed substrate; Forming an etch stop layer on the pure amorphous silicon on the gate electrode; Forming impurity amorphous silicon on the etch stop layer and pure amorphous silicon; Applying a DC voltage to both ends of a predetermined position on the impurity amorphous silicon to crystallize the pure amorphous silicon and the impurity amorphous silicon into pure polycrystalline silicon and impurity polycrystalline silicon; Coating a catalytic metal between depositing said pure amorphous silicon and applying said voltage; Patterning the crystallized pure polycrystalline silicon and the impurity polycrystalline silicon into an island around the gate electrode; A method of fabricating a thin film transistor including forming a source and a drain electrode on the patterned island is disclosed.

Hereinafter, with reference to the accompanying drawings and embodiments will be described the present invention in detail.

First embodiment

2A through 2E are diagrams illustrating a manufacturing process of a liquid crystal display device manufactured according to a first embodiment of the present invention.

When described in detail from the drawing shown in Figure 2a as follows.

First, the gate electrode 50 is formed at a predetermined position on the substrate 1, and then the insulating film 52, pure amorphous silicon 54 and impurity amorphous silicon 56 are continuously deposited to a predetermined thickness. The insulating film 52 may be a silicon nitride film (SiN _x ), TEOS (Tetra Ethoxy Silane), or the like, and preferably, a silicon oxide film (SiO ₂ ) is used.

In addition, the impurity amorphous silicon 56 is a gas containing elements of Groups 3 to 5 at the time of the pure amorphous silicon deposition, after deposition of the pure amorphous silicon 54, that is, PH ₃ , to B ₂ H ₆ It is formed by adding a small amount.

Thereafter, a metal (not shown) treatment is performed on the impurity amorphous silicon 56. The metal treatment may be performed by a sputter, a vacuum evaporator, a metal solution, or the like.

Preferably, the metal material used for the metal treatment may be nickel (Ni), lead (Pb), cobalt (Co) and the like.

2b is the most essential part of the present invention. That is, the pure amorphous silicon 54 and the impurity amorphous silicon 56 continuously deposited in the process of FIG. 2A are crystallized.

The crystallization method used in the present invention is an advanced method in the conventional MIC (metal induced crystallization) method, in order to compensate for the disadvantage that takes a high temperature, a long heat treatment time when the crystallization by the MIC method, in the present invention By applying a high voltage 6 of direct current to the metallized thin film, the crystallization time and the temperature required for crystallization are lowered. The metal used for the metal treatment is also called a catalytic metal.

Hereinafter, the crystallization method according to the present invention is referred to as a field applied metal induced crystallization method (Field Enhanced MIC: FE-MIC).

In addition, conventionally, when fabricating a thin film transistor using polycrystalline silicon, a coplanar structure having a very complicated structure was selected. However, in the present invention, the thin film transistor is a reverse staggered type which is very simple in structure and easy to manufacture. Produced.

That is, the pure amorphous silicon 54 and the impurity amorphous silicon 56 are simultaneously crystallized by the FE-MIC method to form pure polycrystalline silicon 54 'and impurity polycrystalline silicon 56'.

FIG. 2C is a step of patterning the polycrystalline silicon 54 '. 56' formed in FIG. 2B with an island 58. Referring to FIG. The island 58 is configured to cover the gate electrode 50.

FIG. 2D illustrates forming electrodes on the islands 58 to form source and drain electrodes 60 and 62. After the source and drain electrodes 60 and 62 are formed, the impurity polycrystal existing between the source electrode 60 and the drain electrode 62 (A) using the source and drain electrodes 60 and 62 as a mask. Silicon 57 is removed. This is to prevent leakage current flowing between the source electrode 60 and the drain electrode 62. As described above, the structure of the thin film transistor which etches the back channel portion A is commonly referred to as a back channel etching TFT (BCE TFT).

In the above-described FIG. 2D process, the inverted staggered polycrystalline silicon thin film transistor is completed.

2E is a cross-sectional view illustrating a liquid crystal display device to which the thin film transistor is applied. After the deposition of the passivation layer 64 over the entire surface of the thin film transistor and the substrate formed in FIG. 2D, a contact hole 65 is formed to expose a portion of the drain electrode 62. The pixel electrode 68 is formed to contact the drain electrode 62 through the contact hole 65.

When the thin film transistor and the liquid crystal display are manufactured by the above-described method, since the pure amorphous silicon and the impurity amorphous silicon can be simultaneously crystallized, the manufacturing process is simple.

In addition, by applying an inverted staggered thin film transistor to a liquid crystal display, there is an advantage that the existing production equipment can be used as it is.

Second embodiment

As described above in the first embodiment, the back channel etch thin film transistor (hereinafter referred to as a BCE TFT) in the thin film transistor continuously deposits an insulating film, amorphous silicon, and impurity amorphous silicon, thereby minimizing air pollution. When etching the back channel, the structure, or the portion of the channel where the current actually flows, is likely to be overetched.

Therefore, the above-described first embodiment of the present invention describes a liquid crystal display device using a BCE TFT having an inverted staggered structure, but in the second embodiment of the present invention, an etch-stopper TFT: Hereinafter, a liquid crystal display device to which an ES TFT is applied will be described in detail.

3A to 3H are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to a second exemplary embodiment of the present invention.

3A forms a gate electrode 80 on the substrate 1 and subsequently forms an insulating film 82 and pure amorphous silicon 84.

3B and 3C, after the etch stop layer 86 is formed on the pure amorphous silicon 84, the pure amorphous silicon 84 is subjected to metal treatment.

Next, as shown in FIG. 3D, impurity amorphous silicon is deposited on the metal-treated pure amorphous silicon 84 and the etch stop layer 86, and then a DC high voltage 6 is applied to the impurity amorphous silicon 88. ) Crystallized by application to the surface.

The metal treatment process is typically performed after the formation of the etch stop layer 86 on the pure amorphous silicon 84, but may be performed before the formation of the etch stop layer 86 or after the formation of the impurity amorphous silicon 88. In other words, the metal treatment may be performed in a process between the pure amorphous silicon deposition process and the impurity amorphous silicon deposition process, followed by a voltage application process.

At this time, the impurity amorphous silicon 88 can be coped with by ion doping.

FIG. 4A is a view illustrating a process of ion doping after the formation of the etch stop layer 86 shown in FIG. 3C. Here, the etch stop layer 86 of FIG. 3C functions as an anti-doping layer in FIG. 4A.

4B illustrates a process of applying a voltage after the ion doping process, and crystallization is performed in the above process.

That is, the above-described impurity amorphous silicon 88 and the ion doping process have a difference in process, but in terms of their function, they function as ohmic contacts between the electrode to be formed and the semiconductor layer.

3E is a step of forming the thin film transistor S after patterning the polycrystalline silicon crystallized in the crystallization process (FIGS. 3D and 4B) with an island.

That is, the source electrode 90 and the drain electrode 92 are formed, respectively, after forming islands in which the pure polycrystalline silicon formed in the crystallization process is the active layer 84 'and the impurity polycrystalline silicon is formed in the ohmic contact layer 88'. do. Thereafter, the thin film transistor is formed by removing the impurity polycrystalline silicon existing on the etch stop layer 86.

3F to 3G illustrate a process of manufacturing a liquid crystal display after forming the thin film transistor S. Referring to FIG.

That is, FIG. 3F illustrates a step of depositing a passivation layer 94 on the thin film transistor S and forming a contact hole to expose a portion of the drain electrode 92.

Thereafter, as illustrated in FIG. 3G, a transparent conductive electrode is deposited and patterned to form the pixel electrode 96 contacting the drain electrode 92 through a contact hole formed in the upper passivation layer 94 of the drain electrode 92. By doing so, a liquid crystal display device is formed.

5 is a diagram showing current-voltage characteristics of a polycrystalline silicon thin film transistor of FE-MIC fabricated according to an embodiment of the present invention.

As shown in FIG. 5, when the thin film transistor is formed by crystallization of the FE-MIC method, switching on / off is clearly distinguished.

That is, it can be concluded that the inverted staggered polycrystalline thin film transistor can be applied to the liquid crystal display.

When the thin film transistor and the thin film transistor according to the embodiments of the present invention are applied to a liquid crystal display, the following features are provided.

First, since pure amorphous silicon and impurity amorphous silicon can be crystallized at the same time, there is an advantage that the crystallization time can be shortened.

Second, since the activation is made at the same time as the crystallization to polycrystalline silicon, there is an advantage that the process time is shortened.

Third, when the inverted staggered polycrystalline silicon thin film transistor is applied to the liquid crystal display device, there is an advantage that it can be manufactured using the process equipment of the existing amorphous silicon thin film transistor liquid crystal display device without additional production equipment.

Claims (17)

Providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film on the gate electrode and the exposed substrate; Depositing pure amorphous silicon on the insulating film; Forming impurity silicon on the pure amorphous silicon; Coating a catalyst metal on the impurity amorphous silicon; Applying a direct current voltage to both ends of a predetermined position on the impurity amorphous silicon coated with the catalytic metal to crystallize the pure amorphous silicon and the impurity amorphous silicon into pure polycrystalline silicon and impurity polycrystalline silicon; Forming a source and a drain electrode on the impurity polycrystalline silicon; Etching the impurity polycrystalline silicon positioned between the source and drain electrodes using the source and drain electrodes as a mask Thin film transistor manufacturing method comprising a. The method according to claim 1, The insulating film is a thin film transistor manufacturing method, characterized in that the material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), TEOS (Tetra Ethoxy Silane). The method according to claim 1, The impurity amorphous silicon is formed by adding a PH ₃ gas during the deposition of the pure amorphous silicon, a thin film transistor manufacturing method, characterized in that the N-type semiconductor. The method according to claim 1, The impurity amorphous silicon is formed by adding a B ₂ H ₆ gas during the deposition of the pure amorphous silicon, a thin film transistor manufacturing method, characterized in that the P-type semiconductor. The method according to claim 1, The catalyst metal is a thin film transistor manufacturing method, characterized in that the material selected from the group consisting of nickel (Ni), lead (Pb), cobalt (Co). The method according to claim 1, And patterning the crystallized pure polycrystalline silicon and the impurity polycrystalline silicon into islands around the gate electrode. The thin film transistor manufactured by the manufacturing method of Claims 1-6. Providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film and pure amorphous silicon on the gate electrode and the exposed substrate; Forming an etch stop layer on the pure amorphous silicon on the gate electrode; Forming impurity amorphous silicon on the etch stop layer and pure amorphous silicon; Applying a DC voltage to both ends of a predetermined position on the impurity amorphous silicon to crystallize the pure amorphous silicon and the impurity amorphous silicon into pure polycrystalline silicon and impurity polycrystalline silicon; Coating a catalytic metal between depositing said pure amorphous silicon and applying said voltage; Patterning the crystallized pure polycrystalline silicon and the impurity polycrystalline silicon into an island around the gate electrode; Forming a source and a drain electrode on the patterned island Thin film transistor manufacturing method comprising a. The method according to claim 8, The insulating film is a thin film transistor manufacturing method, characterized in that the material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), TEOS (Tetra Ethoxy Silane). The method according to claim 8, The impurity amorphous silicon is a thin film transistor manufacturing method characterized in that the PH ₃ gas is added during the deposition of the pure amorphous silicon or formed by ion doping the pure amorphous silicon, N-type semiconductor. The method according to claim 8, The impurity amorphous silicon is formed by adding B ₂ H ₆ gas during the deposition of the pure amorphous silicon or ion-doped to the pure amorphous silicon, characterized in that the thin film transistor manufacturing method characterized in that the P-type semiconductor. The method according to claim 8, The coating of the catalytic metal may be performed after the deposition of the pure amorphous silicon. The method according to claim 8, The coating of the catalytic metal may be performed after the forming of the etch stop layer. The method according to claim 8, The coating of the catalytic metal may be after the step of forming the impurity amorphous silicon. The method according to claim 8, The catalyst metal is a thin film transistor manufacturing method, characterized in that the material selected from the group consisting of nickel (Ni), lead (Pb), cobalt (Co). The method according to claim 8, The etch stop layer is formed by depositing the insulating film, the pure amorphous silicon and the etch stop insulating film and then patterning the etch stop insulating film characterized in that the thin film transistor manufacturing method. The thin film transistor manufactured by the manufacturing method of Claims 8-16.