KR100958826B1 - Poly Crystalline Silicon Thin Film Transistor Having Bottom Gate Structure Using Metal Induced Lateral Crystallization and Method for Fabricating the Same - Google Patents

Abstract

The present invention utilizes MIC and MILC to amorphous the active region and source / drain region. The present invention relates to a polycrystalline silicon thin film transistor having a lower gate structure capable of shortening a process time and a process cost by simultaneously crystallizing a silicon layer and improving an interface characteristic between an active region and a gate insulating film, and a method of manufacturing the same.

The present invention is a gate insulating film, an amorphous silicon layer over a gate electrode formed on the substrate and a n ⁺ silicon layer, and then forming successively, n ⁺ by patterning the silicon layer and the amorphous silicon layer source region and a drain region n ⁺ silicon layer for And define the activation area. Subsequently, the first and second crystallization inducing metal films are formed at the positions where the source region and the drain region are to be formed and etched using them as an etching mask, thereby defining the source region and the drain region and forming an activation region having a channel region. do. Subsequently, the substrate is heat-treated to source and drain regions below the first and second crystallization induction metal films, the activation region is crystallized by MIC, and the channel region is crystallized by MILC.

Thin Film Transistors, Bottom Gate, MIC, MILC

Description

Poly Crystalline Silicon Thin Film Transistor Having Bottom Gate Structure Using Metal Induced Lateral Crystallization and Method for Fabricating the Same}

The present invention is a polycrystalline silicon thin film transistor and their relates to a method for producing, in particular, leads to a lower gate structure, a polysilicon thin film active region and the n ⁺ silicon layer in fabricating the transistor of metal crystallization having a bottom gate structure using a metal induced lateral crystallization Lower gate structure using metal-induced lateral crystallization that can shorten the manufacturing process time by crystallization using (MIC) and metal-induced lateral crystallization (MILC), and improve the interface characteristics between the active region and the gate insulating film It relates to a polycrystalline silicon thin film transistor having a and a method of manufacturing the same.

Thin film transistors used in display devices such as LCDs and OLEDs are generally activated by depositing silicon on transparent substrates such as glass and quartz, forming gate and gate electrodes, injecting dopants into source and drain regions, and then performing annealing treatment. After forming, the insulating layer is formed. An active layer forming a source region, a drain region, and a channel region of a thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method.

However, the silicon layer deposited directly on the substrate by a method such as CVD has a low electron mobility as an amorphous silicon film. As display devices using thin film transistors require fast operation speeds and are miniaturized, the degree of integration of the driving IC is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is formed simultaneously with the pixel TFTs by increasing the electron mobility of the silicon film, and individual pixels are It is necessary to increase the aperture ratio.

For this purpose, a technique is used in which an amorphous silicon layer is heat-treated to crystallize into a crystalline silicon layer having a polycrystalline structure having high electron mobility. Various methods have been proposed to crystallize an amorphous silicon layer of a thin film transistor into a crystalline silicon layer.

First, solid phase crystallization (SPC) is a method of annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of 600 ° C. or less, which is a deformation temperature of glass forming a substrate. Since the SPC method requires a long time for heat treatment, when the productivity is low and the area of the substrate is large, there is a problem that deformation of the substrate may occur during a long heat treatment process even at a temperature of 600 ° C. or less.

Excimer Laser Crystallization (ELC) is a method in which an excimer laser is injected into a silicon layer to instantaneously crystallize the silicon layer by generating a locally high temperature for a very short time. The ELC method has a technical difficulty in precisely controlling the scanning of the laser light, and since only one substrate can be processed at a time, there is a problem that productivity is lowered than when batch processing of several substrates at the same time in the blast furnace.

In order to overcome the disadvantages of the conventional silicon layer crystallization method, when a metal such as nickel, gold, aluminum, or the like is contacted with or injected into the silicon, the amorphous silicon changes into crystalline silicon even at a low temperature of about 200 ° C. The phenomenon in which is derived is used. This phenomenon is called metal induced crystallization (MIC). When a thin film transistor is manufactured using the MIC phenomenon, metal remains in the crystalline silicon constituting the active layer of the thin film transistor. A problem arises that causes current leakage.

Recently, the metal induced side crystallization (Metal Induced Lateral Crystallization) does not directly induce phase change of silicon, but the silicide generated by the reaction of metal and silicon continues to propagate to the side, leading to the crystallization of silicon sequentially. : A method of crystallizing a silicon layer using a MILC phenomenon has been proposed (see SW Lee & SK Joo, IEEE Electron Device Letter, 17 (4), p.160, (1996)).

Nickel and palladium are known as metals that cause the MILC phenomenon. In the case of crystallizing the silicon layer using the MILC phenomenon, the silicide interface including the metal moves to the side as the phase change of the silicon layer propagates, thereby forming the MILC shape. In the silicon layer crystallized using, there is almost no metal component used to induce crystallization, which does not affect the current leakage and other operating characteristics of the transistor activation layer. In addition, in the case of using the MILC phenomenon, the crystallization of silicon can be induced at a relatively low temperature of 300 ° C to 500 ° C, and thus, multiple substrates can be simultaneously crystallized without damaging the substrate by using a furnace.

The conventional method of crystallizing the silicon layer constituting the TFT by using the MIC and MILC phenomenon is to pattern the amorphous silicon layer formed on the insulating substrate by photolithography to form an active layer, and then form a gate insulating layer and a gate electrode on the active layer. do.

Subsequently, the entire substrate is doped with impurities using a gate electrode as a mask to form a source region, a channel region, and a drain region in the active layer, and then the entire substrate is partially formed in a partially formed MILC source metal layer in the source region and the drain region. The source and drain regions immediately below the metal layer remaining by annealing at a temperature of 300 ° C to 500 ° C are crystallized by MIC phenomenon and portions of the source and drain regions where the metal layer is not covered (metal-offset) and channel regions below the gate electrode. Silver induces crystallization by the MILC phenomenon induced from the remaining metal layer.

The thin film transistor manufacturing method of crystallizing a channel region by the MILC is generally used for manufacturing a polycrystalline silicon thin film transistor having a top gate structure. Currently, amorphous silicon thin film transistors used in AM-LCDs are mostly manufactured in a bottom gate structure due to degradation due to light in an active region. In addition, all manufacturing process technologies are focused on thin film transistors with a bottom gate structure.

A method of manufacturing a polycrystalline thin film transistor having a conventional lower gate structure is as follows.

First, a gate electrode is formed on a transparent insulating substrate, a gate insulating film is formed on the entire surface of the transparent insulating substrate on which the gate electrode is formed, amorphous silicon is deposited on the gate insulating film, and patterned into an active layer pattern, followed by primary laser annealing. Crystallized into polycrystalline silicon. Then, after the polycrystalline siliconized an active layer over n ⁺ silicon layer is formed by the n ⁺ silicon layer on the source and drain electrode pattern is patterned and again the second laser annealing in which crystallization of polycrystalline silicon, thin film by forming source and drain metal electrodes Produce a transistor.

In this case, since the laser annealing process is included more than once, there is a disadvantage that a lot of processing time is consumed. In addition, when the n ⁺ silicon layer is patterned into a source and drain electrode pattern and then crystallized into polycrystalline silicon by laser annealing like the amorphous silicon, the power control of the laser is fine due to the difference in thickness between the source and drain regions and the active layer region. If the power control is not made finely, the surface roughness may increase accordingly.

In addition, in general, polycrystalline silicon formed by laser annealing of amorphous silicon has a low crystallinity of lower silicon which forms an interface with a gate insulating film because crystal growth proceeds first on the surface. In this case, this tendency is aggravated as the thickness of amorphous silicon increases. In addition, in the case of laser irradiation, low energy is transferred to the gate insulating layer, which may increase oxygen or hydrogen defects.

Accordingly, the present invention has been made to solve the above problems, and its object is to produce metal-induced crystallization (MIC) and metal-induced side crystallization of the active region and n ⁺ silicon layer when fabricating a polycrystalline silicon thin film transistor having a lower gate structure. The present invention provides a polycrystalline silicon thin film transistor having a lower gate structure using MILC that can greatly reduce the crystallization process time by crystallizing at a time by using (MILC) and a process cost.

Another object of the present invention is to crystallize the active region and the n ⁺ silicon layer using MIC and MILC to increase the crystallinity of the underlying silicon forming the interface between the active region and the gate insulating film without affecting the gate insulating film. The present invention provides a polycrystalline silicon thin film transistor having a lower gate structure using MILC capable of improving interfacial properties, and a method of manufacturing the same.

It is still another object of the present invention to solve the problems of the manufacturing process of the polycrystalline thin film transistor having a lower gate structure caused by crystallizing the conventional active layer and the n ⁺ silicon layer by the laser annealing method twice and the characteristics of the manufactured thin film transistor. The present invention provides a method of manufacturing a polycrystalline silicon thin film transistor having a lower gate structure using MILC, which can be manufactured without significantly changing the existing process.

According to one aspect of the invention, the present invention comprises the steps of forming a gate electrode on the transparent insulating substrate; A gate insulating film over the transparent insulating substrate having the gate electrode formed thereon, an amorphous silicon layer to be used to form an activation region on the gate insulating layer, and ions to be used to form a source region and a drain region to be formed on the amorphous silicon layer. continuously forming n ⁺ silicon layers; Sequentially patterning the n ⁺ silicon layer and the amorphous silicon layer to define an n ⁺ silicon layer and an activation region for a source region and a drain region; Forming first and second crystallization inducing metal films at positions where the source region and the drain region of the n ⁺ silicon layer are to be formed, respectively; By using the first and second crystallization induction metal film as an etching mask, the exposed n ⁺ silicon layer and the upper portion of the center portion of the active region are sequentially etched to define a source region and a drain region by separating the n ⁺ silicon layer. And forming an activation region having a channel region at the center thereof. The substrate is heat-treated to crystallize by MIC a source region and a drain region formed of n ⁺ silicon under the first and second crystallization induction metal layers, and an activation region composed of amorphous silicon positioned under the source and drain regions. Crystallizing by MILC a channel region made of amorphous silicon located between the source and drain regions; Forming a source electrode and a drain electrode on the crystallized source region and the drain region, respectively; And depositing an interlayer insulating film on the substrate, etching a portion of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode.

According to another feature of the invention, the present invention comprises the steps of forming a gate electrode on the transparent insulating substrate; A gate insulating film over the transparent insulating substrate having the gate electrode formed thereon, an amorphous silicon layer to be used to form an activation region on the gate insulating layer, and ions to be used to form a source region and a drain region to be formed on the amorphous silicon layer. continuously forming n ⁺ silicon layers; Forming a crystallization inducing metal film on the n ⁺ silicon layer; Forming a metal film to be used to form a source electrode and a drain electrode on the crystallization inducing metal film; Forming a photoresist layer on the metal layer, and then forming a first etching mask for forming an activation region with respect to the amorphous silicon layer using an exposure slitting mask; The electrode forming metal film and the crystallization inducing metal film sequentially exposed using the first etching mask are etched and removed, and the n ⁺ silicon layer and the amorphous silicon layer are etched to activate the n ⁺ silicon layer for the source region and the drain region. Forming a region; Processing the first etch mask to form a second etch mask for forming source and drain electrodes; Etching the electrode forming metal film and the crystallization inducing metal film by using the second etching mask to form first and second crystallization inducing metal films separated from the source electrode and the drain electrode; Using the etched structure as a mask, the exposed n ⁺ silicon layer and a portion of the upper portion of the center portion of the active region are sequentially etched to separate the n ⁺ silicon layer to define a source region and a drain region, and to simultaneously form a channel in the center portion. Forming an activation region having a region; The substrate is heat-treated to crystallize by MIC a source region and a drain region formed of n ⁺ silicon under the first and second crystallization induction metal layers, and an activation region composed of amorphous silicon positioned under the source and drain regions. Crystallizing by MILC a channel region made of amorphous silicon located between the source and drain regions; Depositing an interlayer insulating film on the substrate and etching a portion of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode. To provide.

According to another feature of the invention, the present invention comprises the steps of forming a gate electrode on the transparent insulating substrate; Forming a gate insulating film over the transparent insulating substrate on which the gate electrode is formed, an amorphous silicon layer to be used to form an activation region on the gate insulating film, and a crystallization inducing metal film on the amorphous silicon layer; Forming an n ⁺ silicon layer doped with ions to be used to form a source region and a drain region on the crystallization inducing metal film; Forming a metal film to be used to form a source electrode and a drain electrode on the n ⁺ silicon layer; Forming a photoresist layer on the metal layer, and then forming a first etching mask for forming the activation region using an exposure slitting mask; Etching the electrode forming metal layer, the n ⁺ silicon layer, the crystallization inducing metal layer, and the amorphous silicon layer sequentially exposed using the first etching mask to form the n ⁺ silicon layer and the active region for the source region and the drain region. Steps; Processing the first etch mask to form a second etch mask for forming source and drain electrodes; The second etching mask is sequentially etched to form an electrode forming metal film, an n ⁺ silicon layer, a crystallization inducing metal film, and an upper portion of the center portion of the active region, thereby separating the source electrode and the drain electrode from the n ⁺ silicon layer. Forming an activation region having a source region and a drain region, first and second crystallization inducing metal films separated from each other, and a channel region in a central portion thereof; Heat treating the substrate to crystallize a source region and a drain region made of n ⁺ silicon and an activation region made of amorphous silicon by MIC, and to crystallize the source region and the drain region of the first and second crystallization induction metal layers. Crystallizing, by MILC, a channel region comprised of amorphous silicon positioned therebetween; And depositing an interlayer insulating film on the substrate, etching a part of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode.

The method of manufacturing the polycrystalline silicon thin film transistor may further include removing the first and second crystallization inducing metal layers before forming the source electrode and the drain electrode.

In addition, the step of forming the first and second crystallization-inducing metal film at a location where the source region and the drain region of the n ⁺ silicon layer are to be formed at intervals, the photoresist is applied to the entire surface of the substrate, the source region and the drain Forming an opening corresponding to the region; Forming a crystallization inducing metal film on the entire surface of the substrate; Removing the photoresist by a lift-off method to leave the first and second crystallization inducing metal films at positions where the source region and the drain region of the n ⁺ silicon layer are to be formed, respectively.

According to another feature of the invention, the present invention is a transparent insulating substrate; A gate electrode having an island shape on the transparent insulating substrate; A gate insulating film formed on an upper surface of the transparent insulating substrate on which the gate electrode is formed; An activation region formed on the gate insulating film and formed of island shape and made of polycrystalline silicon; Source and drain regions formed at both ends of the activation region, each of which comprises a n ⁺ silicon layer doped with ions; The n ⁺ are formed in the source region and the drain region of the silicon layer, a source consisting of n ⁺ silicon is located on the lower side at the time of heat treatment region and a drain region, active region composed of amorphous silicon is located at the lower side of the source region and the drain region First and second crystallization-inducing metal films for crystallizing by MIC and for crystallizing, by MILC, a channel region made of amorphous silicon positioned between the source region and the drain region; A source electrode and a drain electrode formed on the first and second crystallization inducing metal films; An interlayer insulating film formed on the substrate; Provided is a polycrystalline silicon thin film transistor having a lower gate structure, the pixel electrode being connected to a drain electrode through a contact window of the interlayer insulating layer.

According to another feature of the invention, the present invention is a transparent insulating substrate; A gate electrode formed on the transparent insulating substrate and having an island shape; A gate insulating film formed on an upper surface of the transparent insulating substrate on which the gate electrode is formed; An activation region formed on the gate insulating film and formed in an island shape; A source region and a drain region formed on both ends of the activation region, respectively, and having an ion-doped n ⁺ silicon layer made of polycrystalline silicon; A polycrystalline silicon thin film transistor comprising a source electrode and a drain electrode formed on the source region and the drain region, wherein the polycrystalline A source region and a drain region made of silicon and an activation region located below the source region and the drain region are amorphous by MIC crystallization using the first and second crystallization inducing metal films formed on or under the source region and the drain region. Silicon is crystallized; The channel region of the activation region located between the source region and the drain region provides a polycrystalline silicon thin film transistor having a lower gate structure, in which amorphous silicon is crystallized by MILC crystallization.

In this case, the crystallization induction metal film is made of any one selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt It is preferably formed to a thickness of 1 to 20 nm by any one of, sputtering, heat evaporation, PECVD, solution coating.

As described above, in the present invention, when manufacturing a polycrystalline thin film transistor having a bottom gate structure, amorphous of the active region and the source / drain region using MIC and MILC. By simultaneously crystallizing the silicon layer, the process time can be shortened and the interfacial characteristics can be improved by increasing the crystallinity of the lower silicon forming the interface between the active region and the gate insulating film without affecting the gate insulating film. Can be.

Hereinafter, with reference to the accompanying drawings will be described a specific embodiment of the present invention.

1 to 9 are process cross-sectional views illustrating a process of manufacturing a thin film transistor having a lower gate structure using MIC and MILC phenomenon according to the first embodiment of the present invention.

First, as shown in FIG. 1, a metal film, for example, MoW, Al, or Al alloy for preventing heel lock is formed on a transparent substrate 11, preferably a glass substrate on which a buffer layer (not shown) is formed. Deposition and patterning to form the gate electrode 12.

Thereafter, on the gate electrode 12, a gate insulating film 13, an amorphous silicon layer 14 to be used to form an activation region, and an n ⁺ silicon layer 15 doped with ions to be used to form a source region and a drain region. E). For example, the three thin films, that is, the gate insulating film 13, the amorphous silicon layer 14, and the n ⁺ silicon layer 15 are 700 to 4000 kPa and 600 to 400, respectively, without breaking the vacuum of the PECVD vacuum chamber. 2000 Å, 500 ~ 1000 Å thickness continuously deposited. The gate insulating layer 13 may use a silicon oxide film or a silicon nitride film.

Subsequently, a crystallization inducing metal film 16 is deposited on the n ⁺ silicon layer 15 to a thickness of 1 to 20 nm, for example 5 nm, by any one of methods such as sputtering, heat evaporation, PECVD, and solution coating. . At this time, the material of the crystallization induction metal film 16 that can be applied is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt, etc. Mainly used.

In this case, even when the crystallization-inducing metal film 16 is formed first and the n ⁺ silicon layer 14 is formed later, the amorphous silicon layer 14 and the n ⁺ silicon layer 15 are crystalline silicon, as described later. There is no difference in crystallization with. Thereafter, a conductive material, for example, a metal film 17, to be used to form the source electrode and the drain electrode is deposited on the crystallization inducing metal film 16.

Thereafter, a photoresist (PR) layer 21 is deposited on the metal layer 17 as shown in FIG. 2, and exposed using a slitting mask 20 for exposure as shown in FIG. 3. do. The slits mask 20 for exposure is formed with two slits 20a and 20b spaced apart from each other at the center thereof, and the outer side of the slits mask 20 is an amorphous silicon layer 14 and an n ⁺ silicon layer 15 as shown in FIG. Is sized to form an etch mask 22 to be patterned to define the active region and to define the source and drain regions.

When the exposure is performed, as shown in FIG. 3, the light incident through the two slits 20a and 20b is exposed wider than the width of the two slits 20a and 20b by diffuse reflection and cross linking. do. In Fig. 3, reference numerals 21a and 21b indicate portions of the photoresist to which exposure has been made.

Thereafter, when the photoresist layer 21 is developed in a developer, the exposed photoresist portions 21a and 21b are removed to obtain a first etching mask 22 for etching an active region formed of a photoresist as shown in FIG.

Thereafter, the electrode forming metal film 17 and the crystallization inducing metal film 16 which are sequentially exposed using the first etching mask 22 are removed by a wet etching method, and then the n ⁺ silicon layer 15 and the amorphous layer are amorphous. By removing the silicon layer 14 by wet or dry etching, the n ⁺ silicon layer 15a and the activation region 14a for the source and drain regions are obtained.

Subsequently, as shown in FIG. 5, the first etching mask 22 made of photoresist is subjected to O ₂ ashing or soaked in a developer until the electrode forming metal film 17 in the center is exposed. The etching process is performed while maintaining the profile of the exposed portion, thereby obtaining a second etching mask 23 for forming source and drain electrodes.

Thereafter, as shown in FIG. 6, when the electrode forming metal film 17 and the crystallization inducing metal film 16 are first etched by the wet etching method using the second etching mask 23, the exposed electrode forming metal is etched. The film 17 and the crystallization inducing metal film 16 are removed so that the source electrode 17a and the drain electrode 17b are defined and the first and second crystallization inducing metal films 16a and 16b separated from each other at the same time are obtained. do.

Then, by using the above etching the structure as a mask dry etching, for example, when sequentially etched so that the upper part of the removal of the n ⁺ silicon layer (15a) and the active area (14a) exposed by the plasma etching n ⁺ silicon layer 15a is separated to define the source region 15b and the drain region 15c, and the activation region 14a having the channel region 14b in the center is obtained.

Then, as shown in Fig carrying out the heat treatment at 300 ℃ to 500 ℃ for 1 hour to 5 hours. 7, the first and second crystallization-inducing source consisting of n ⁺ silicon in an amorphous state in a lower portion of the metal film (16a, 16b) The region 15b and the drain region 15c, and the activation region 14a made of amorphous silicon positioned below the source region 15b and the drain region 15c are crystallized by MIC, and the source region 15b And the channel region 14b made of amorphous silicon located inside the drain region 15c is crystallized by MILC.

Subsequently, as shown in FIG. 8, the residual photoresist is removed and the interlayer insulating film 71 is deposited. Next, a portion of the interlayer insulating layer 71 is etched to form a contact window 71a for the drain electrode 17b, and the pixel electrode 81 is formed as shown in FIG. 9.

As described above, the thin film transistor manufacturing process having the lower gate structure according to the first embodiment of the present invention can be applied without greatly changing the existing process.

In addition, the crystallization time is long and the crystallization time is long due to the crystallization of the active layer and the n ⁺ silicon layer by two laser annealing methods. However, in the present invention, the active region 14a and the source region ( 15b) and the n ⁺ silicon layer for the drain region 15c are crystallized at once using metal induction crystallization (MIC) and metal induction lateral crystallization (MILC) to significantly shorten the crystallization process time and reduce processing costs. It becomes possible.

In the present invention, the activation region 14a and the n ⁺ silicon layer are crystallized using MIC and MILC, that is, the crystallization is performed by the solid phase crystallization method, so that the gate insulating layer 13 is not directly heated. Will not affect.

Furthermore, in the crystallization method of the present invention, the interfacial characteristics can be improved by increasing the crystallinity of the lower silicon forming the interface between the activation region 14a and the gate insulating film 13.

Hereinafter, a process of manufacturing a crystalline silicon thin film transistor having a lower gate structure according to a second preferred embodiment of the present invention will be described with reference to FIGS. 10 to 18.

In the description of the second embodiment, the same element numbers are assigned to the same elements as the first embodiment, and detailed description thereof is omitted.

First, as shown in FIG. 10, a metal film, for example, MoW, Al, or an Al alloy for preventing hillock, is formed on a transparent substrate 11, preferably a glass substrate on which a buffer layer (not shown) is formed. Deposition and patterning to form the gate electrode 12.

Thereafter, on the gate electrode 12, the gate insulating film 13, the amorphous silicon layer 14 to be used to form the activation region, and the n ⁺ silicon in the amorphous state doped with ions to be used to form the source region and the drain region. Layer 15 is deposited. For example, the three thin films, that is, the gate insulating film 13, the amorphous silicon layer 14, and the n ⁺ silicon layer 15 are 700 to 4000 kPa and 600 to 400, respectively, without breaking the vacuum of the PECVD vacuum chamber. 2000 Å, 500 ~ 1000 Å thickness continuously deposited. The gate insulating layer 13 may use a silicon oxide film or a silicon nitride film.

Then, also active area mask, such as 11 for the (not shown), source by removing the n ⁺ silicon layer 15 and the amorphous silicon layer 14 in a wet or dry etched using region and a drain region n ⁺ silicon layer 15a and the activation area 14a are defined.

Next, as shown in FIG. 12, the photoresist 24 is coated on the entire surface of the substrate 11, and a pair of openings 24a corresponding to the source region and the drain region are formed.

Thereafter, as shown in FIG. 13, the crystallization-inducing metal film 16 is deposited on the entire surface of the substrate 11 at a thickness of 1 to 20 nm, for example, 5 nm, by any one of sputtering, heat evaporation, PECVD, and solution coating. do. At this time, the material of the crystallization induction metal film 16 that can be applied is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt, etc. Mainly used.

Thereafter, when the photoresist 24 is removed by a lift-off method, the first and second crystallization inducing metal films 16a and 16b separated from each other are obtained as shown in FIG.

Subsequently, the first and second crystallization induced metal films 16a and 16b separated from each other as shown in FIG. 15 are used as an etching mask to define the source region and the drain region, and are exposed by dry etching, for example, plasma etching. When sequentially etching so that a portion of the upper layer of the n ⁺ silicon layer 15a and the activation region 14a is removed, the n ⁺ silicon layer 15a is separated to define the source region 15b and the drain region 15c. An activation region 14a having a channel region 14b in the center portion is obtained.

Subsequently, when heat treatment is performed at 300 ° C. to 500 ° C. for 1 to 5 hours, as shown in FIG. 16, a source region 15b made of n ⁺ silicon positioned under the first and second crystallization inducing metal films 16a and 16b. ) And the drain region 15c, and the activation region 14a made of amorphous silicon positioned below the source region 15b and the drain region 15c are crystallized by MIC, and the source region 15b and the drain region The channel region 14b made of amorphous silicon located inside 15c is crystallized by MILC.

Subsequently, as shown in FIG. 16, the first and second crystallization inducing metal films 16a and 16b are removed, and a conductive material, for example, a metal film, to be used to form the source electrode and the drain electrode is deposited, and then patterned, respectively. The source electrode 17a and the drain electrode 17b are formed on the source region 15b and the drain region 15c made of n ⁺ silicon.

In this case, it is also possible to form the source electrode 17a and the drain electrode 17b without removing the first and second crystallization induction metal films 16a and 16b.

Thereafter, as shown in FIG. 17, the interlayer insulating film 71 is deposited, and then a portion of the interlayer insulating film 71 is etched to form a contact window 71a for the drain electrode 17b. Likewise, the pixel electrode 81 is formed.

As described above, the thin film transistor manufacturing process having the lower gate structure according to the second embodiment of the present invention can also be applied without significantly changing the existing manufacturing process.

In addition, in the present invention, the n ⁺ silicon layer for the activation region 14a, the source region 15b, and the drain region 15c is crystallized at once by using metal induced crystallization (MIC) and metal induced side crystallization (MILC). As a result, the crystallization process time can be greatly shortened, thereby reducing the processing cost. Since the heat is not directly applied to the gate insulating layer 13 when the crystallization is performed, the gate insulating layer 13 is not affected. The interfacial characteristics can be improved by increasing the crystallinity of the lower silicon forming the interface between the gate insulating films 13.

The polycrystalline silicon thin film transistor of the present invention and a manufacturing method thereof are applied to the production of a polycrystalline silicon thin film transistor having a bottom gate structure to display a display such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and the like. Applicable to thin film transistors (TFTs) used in devices, in particular, thin film transistors in which an active layer forming a source, a drain, and a channel of the thin film transistors are made of crystalline silicon, and a fabrication thereof. Applicable to the method.

1 to 9 are process cross-sectional views illustrating a process of manufacturing a crystalline silicon thin film transistor having a lower gate structure according to a first embodiment of the present invention;

10 to 18 are cross-sectional views illustrating a process of manufacturing a crystalline silicon thin film transistor having a lower gate structure according to a second preferred embodiment of the present invention.

* Explanation of Signs of Major Parts in Drawings *

11: transparent insulating substrate 12: gate electrode

13: gate insulating film 14: amorphous silicon layer

14a: active area 14b: channel area

15,15a: n ⁺ silicon layer 16: crystallization induced metal film

16a: first crystallization induced metal film 16b: second crystallization induced metal film

17: metal film 17a: source electrode

17b: drain electrode 20: slit mask

20a, 20b: Slit 21a, 21b: Exposed PR portion

22: first etching mask 23: second etching mask

24: photoresist 24a: opening

71: interlayer insulating film 71a: contact window

81: pixel electrode

Claims (9)

Forming a gate electrode on the transparent insulating substrate; A gate insulating film over the transparent insulating substrate having the gate electrode formed thereon, an amorphous silicon layer to be used to form an activation region on the gate insulating layer, and ions to be used to form a source region and a drain region to be formed on the amorphous silicon layer. continuously forming n ⁺ silicon layers; Sequentially patterning the n ⁺ silicon layer and the amorphous silicon layer to define an n ⁺ silicon layer and an activation region for a source region and a drain region; Forming first and second crystallization inducing metal films at positions where the source region and the drain region of the n ⁺ silicon layer are to be formed, respectively; By using the first and second crystallization induction metal film as an etching mask, the exposed n ⁺ silicon layer and the upper portion of the center portion of the active region are sequentially etched to define a source region and a drain region by separating the n ⁺ silicon layer. And forming an activation region having a channel region at the center thereof. The substrate is heat-treated to perform metal-induced crystallization (MIC) on a source region and a drain region consisting of n ⁺ silicon under the first and second crystallization inducing metal layers, and an activation region consisting of amorphous silicon positioned under the source region and the drain region. Crystallizing), and crystallizing a channel region made of amorphous silicon located between the source region and the drain region by metal induced lateral crystallization (MILC); Forming a source electrode and a drain electrode on the crystallized source region and the drain region, respectively; Depositing an interlayer insulating film on the substrate, etching a portion of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode. Forming a gate electrode on the transparent insulating substrate; A gate insulating film over the transparent insulating substrate having the gate electrode formed thereon, an amorphous silicon layer to be used to form an activation region on the gate insulating layer, and ions to be used to form a source region and a drain region to be formed on the amorphous silicon layer. continuously forming n ⁺ silicon layers; Forming a crystallization inducing metal film on the n ⁺ silicon layer; Forming a metal film to be used to form a source electrode and a drain electrode on the crystallization inducing metal film; Forming a photoresist layer on the metal layer, and then forming a first etching mask for forming an activation region with respect to the amorphous silicon layer using an exposure slitting mask; The electrode forming metal film and the crystallization inducing metal film sequentially exposed using the first etching mask are etched and removed, and the n ⁺ silicon layer and the amorphous silicon layer are etched to activate the n ⁺ silicon layer for the source region and the drain region. Forming a region; Processing the first etch mask to form a second etch mask for forming source and drain electrodes; Etching the electrode forming metal film and the crystallization inducing metal film by using the second etching mask to form first and second crystallization inducing metal films separated from the source electrode and the drain electrode; Using the etched structure as a mask, the exposed n ⁺ silicon layer and a portion of the upper portion of the center portion of the active region are sequentially etched to separate the n ⁺ silicon layer to define a source region and a drain region, and to simultaneously form a channel in the center portion. Forming an activation region having a region; The substrate is heat-treated to perform metal-induced crystallization (MIC) on a source region and a drain region consisting of n ⁺ silicon under the first and second crystallization inducing metal layers, and an activation region consisting of amorphous silicon positioned under the source region and the drain region. Crystallizing), and crystallizing a channel region made of amorphous silicon located between the source region and the drain region by metal induced lateral crystallization (MILC); Depositing an interlayer insulating film on the substrate and etching a portion of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode. . Forming a gate electrode on the transparent insulating substrate; Forming a gate insulating film over the transparent insulating substrate on which the gate electrode is formed, an amorphous silicon layer to be used to form an activation region on the gate insulating film, and a crystallization inducing metal film on the amorphous silicon layer; Forming an n ⁺ silicon layer doped with ions to be used to form a source region and a drain region on the crystallization inducing metal film; Forming a metal film to be used to form a source electrode and a drain electrode on the n ⁺ silicon layer; Forming a photoresist layer on the metal layer, and then forming a first etching mask for forming the activation region using an exposure slitting mask; Etching the electrode forming metal layer, the n ⁺ silicon layer, the crystallization inducing metal layer, and the amorphous silicon layer sequentially exposed using the first etching mask to form the n ⁺ silicon layer and the active region for the source region and the drain region. Steps; Processing the first etch mask to form a second etch mask for forming source and drain electrodes; The second etching mask is sequentially etched to form an electrode forming metal film, an n ⁺ silicon layer, a crystallization inducing metal film, and an upper portion of the center portion of the active region, thereby separating the source electrode and the drain electrode from the n ⁺ silicon layer. Forming an activation region having a source region and a drain region, first and second crystallization inducing metal films separated from each other, and a channel region in a central portion thereof; Heat treating the substrate to crystallize a source region and a drain region made of n ⁺ silicon and an activation region made of amorphous silicon by metal induced crystallization (MIC); Crystallizing a channel region made of amorphous silicon located between the source region and the drain region by metal induced lateral crystallization (MILC); Depositing an interlayer insulating film on the substrate, etching a portion of the interlayer insulating film to form a contact window for the drain electrode, and then forming a pixel electrode. 2. The method of claim 1, further comprising removing the first and second crystallization inducing metal layers before forming the source electrode and the drain electrode. The method according to any one of claims 1 to 3, wherein the crystallization induction metal film is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd And Pt, which is formed of any one selected from the group consisting of 1 to 20 nm thick by any one of sputtering, heat evaporation, PECVD, and solution coating. The method of claim 1, wherein the first and second crystallization inducing metal films are formed at positions where the source region and the drain region of the n ⁺ silicon layer are to be formed, respectively. Applying a photoresist to the entire surface of the substrate and forming openings corresponding to the source region and the drain region; Forming a crystallization inducing metal film on the entire surface of the substrate; Removing the photoresist by a lift-off method to leave the first and second crystallization inducing metal films at positions where the source region and the drain region of the n ⁺ silicon layer are to be formed, respectively. Method of manufacturing polycrystalline silicon thin film transistor. A transparent insulating substrate; A gate electrode having an island shape on the transparent insulating substrate; A gate insulating film formed on an upper surface of the transparent insulating substrate on which the gate electrode is formed; An activation region formed on the gate insulating film and formed of island shape and made of polycrystalline silicon; A source region and a drain region formed at both ends of the activation region, each of which comprises a n ⁺ silicon layer doped with ions; The n ⁺ are formed in the source region and the drain region of the silicon layer, a source consisting of n ⁺ silicon is located on the lower side at the time of heat treatment region and a drain region, active region composed of amorphous silicon is located at the lower side of the source region and the drain region First and second crystallization-inducing metal films for crystallizing by metal induced crystallization (MIC) and for crystallizing a channel region made of amorphous silicon located between the source and drain regions by metal induced side crystallization (MILC); ; A source electrode and a drain electrode formed on the first and second crystallization inducing metal films; An interlayer insulating film formed on the substrate; And a pixel electrode connected to the drain electrode through the contact window of the interlayer insulating film. A transparent insulating substrate; A gate electrode formed on the transparent insulating substrate and having an island shape; A gate insulating film formed on an upper surface of the transparent insulating substrate on which the gate electrode is formed; An activation region formed on the gate insulating film and formed in an island shape; A source region and a drain region formed on both ends of the activation region, respectively, and having an ion-doped n ⁺ silicon layer made of polycrystalline silicon; In a polycrystalline silicon thin film transistor comprising a source electrode and a drain electrode formed on the source region and the drain region, The polycrystalline The source and drain regions made of silicon, and the activation regions located below the source and drain regions, include metal-induced crystallization (MIC) using first and second crystallization-inducing metal films formed above or below the source and drain regions. Amorphous silicon is crystallized by; The channel region of the activation region located between the source region and the drain region is a polycrystalline silicon thin film transistor having a lower gate structure, characterized in that the amorphous silicon crystallized by metal induced lateral crystallization (MILC). The method of claim 7 or 8, wherein the crystallization induction metal film is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt A polycrystalline silicon thin film transistor having a lower gate structure, characterized in that it is made of any one selected from the group.

Images