CN112420747B - Array substrate and preparation method thereof - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides an array substrate and a preparation method thereof, wherein the preparation method of the array substrate comprises the following steps: sequentially preparing a grid electrode, a grid insulating layer and an active layer on a substrate, wherein the active layer comprises a channel region and a source electrode contact region and a drain electrode contact region which are respectively positioned at two sides of the channel region; preparing a crystallization inducing film on the active layer, and patterning the crystallization inducing film to form a crystallization inducing line at least positioned in the source contact region and the drain contact region, wherein the crystallization inducing line is perpendicular to a connection line direction between the source contact region and the drain contact region; and applying a horizontal electric field between two adjacent crystallization inducing lines, and simultaneously performing an annealing process on the active layer to induce the crystallization of the active layer so as to convert the active layer from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. The method and the device can solve the problem that the uniformity of laser annealing crystallization of the oxide semiconductor on a large generation line is poor, and the performance of an oxide semiconductor device is influenced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Oxide thin film transistor technology is considered to be a promising alternative to amorphous silicon thin film transistor technology, and is the mainstream technology of the next generation display driving backplane. Compared with the amorphous silicon thin film transistor technology, the existing oxide thin film transistor technology has the characteristics of higher mobility, good large-area uniformity and lower production cost. However, the mobility of the oxide thin film transistor technology is still insufficient compared with the low temperature polysilicon thin film transistor technology. Therefore, high mobility oxide thin film transistor technology is becoming a direction of great attention. In addition, the stability of oxide thin film transistors has been a major problem that plagues their widespread use. The oxide thin film transistor has a large number of deep gap state oxygen vacancies, which easily causes poor illumination stability of the device.
The crystallization of the oxide semiconductor can improve the illumination stability and mobility of the device. The generation line generation number of the display screen is defined according to the size of the glass substrate used for producing the display screen, and the larger the size of the glass substrate is, the higher the generation line generation number is. At present, the crystallization mode using laser annealing can support the production of 6 generations of lines to the maximum, and there are problems of poor crystallization uniformity and the like on large generation lines (such as 8.5 generations, 10 generations, 10.5 generations and the like), thereby affecting the performance of the oxide semiconductor device.
Therefore, the prior art has defects which need to be solved urgently.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which can solve the problems that the uniformity of laser annealing crystallization on an oxide semiconductor on a large generation line is poor and the performance of an oxide semiconductor device is influenced.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the application provides an array substrate, includes:
a substrate;
a gate disposed on the substrate;
a gate insulating layer disposed on the gate electrode;
the active layer is arranged on the grid insulating layer corresponding to the grid electrode and comprises a channel region and a source electrode contact region and a drain electrode contact region which are respectively positioned at two sides of the channel region;
a crystallization inducing layer disposed on the active layer, the crystallization inducing layer including at least a crystallization inducing line located at the source contact region and the drain contact region;
wherein the crystallization inducing line is wired perpendicular to a wiring direction between the source contact region and the drain contact region, and the active layer is a crystalline oxide semiconductor layer.
In the array substrate of the present application, the crystallization inducing layer further includes at least one crystallization inducing line located in the channel region, and the at least one crystallization inducing line located in the channel region is disposed in parallel with the crystallization inducing lines of the source contact region and the drain contact region.
In the array substrate of the present application, the material of the crystallization inducing layer is one or more alloys of nickel, tantalum, and tungsten metal materials.
In the array substrate of the present application, a crystal orientation direction of a portion of the active layer corresponding to between two adjacent crystallization inducing lines is parallel to a line direction between the source contact region and the drain contact region.
In the array substrate of the present application, the array substrate further includes a source electrode and a drain electrode disposed on the active layer, the source electrode contacts the source electrode contact region, the drain electrode contacts the drain electrode contact region, wherein a portion of the source electrode/drain electrode corresponding to the crystallization inducing line passes through the crystallization inducing line and contacts the source electrode contact region/drain electrode contact region.
The application also provides a preparation method of the array substrate, which comprises the following steps:
the method comprises the following steps that S1, a grid electrode, a grid insulation layer and an active layer are sequentially prepared on a substrate, wherein the active layer comprises a channel region, and a source electrode contact region and a drain electrode contact region which are respectively positioned on two sides of the channel region;
step S2, preparing a crystallization inducing film on the active layer, and patterning the crystallization inducing film to form a crystallization inducing line at least located in the source contact region and the drain contact region, wherein the crystallization inducing line is perpendicular to a connecting line direction between the source contact region and the drain contact region;
and S3, applying a horizontal electric field between two adjacent crystallization inducing lines, and simultaneously performing an annealing process on the active layer to induce the active layer to crystallize, so that the active layer is converted from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer.
In the production method of the present application, the intensity of the horizontal electric field applied between two adjacent ones of the crystallization-inducing lines is 1V/m to 10V/m.
In the production method of the present application, the patterning of the crystallization-inducing film in step S2 further includes the steps of:
forming at least one crystallization inducing line in the channel region; wherein at least one of the crystallization inducing lines in the channel region is disposed in parallel with the crystallization inducing lines in the source contact region and the drain contact region.
In the manufacturing method of the present application, an electric field direction of the horizontal electric field is parallel to a wiring direction between the source contact region and the drain contact region.
In the manufacturing method of the present application, a crystal orientation direction of a portion of the active layer corresponding to between two adjacent crystallization-inducing lines is parallel to a line direction between the source contact region and the drain contact region.
The beneficial effect of this application does: according to the array substrate and the preparation method thereof, parallel crystallization induction lines are formed in a source electrode contact region and a drain electrode contact region of an active layer, a horizontal electric field is applied between two adjacent crystallization induction lines, the direction of the electric field of the horizontal electric field is parallel to the direction of a connecting line between the source electrode contact region and the drain electrode contact region, and meanwhile, an annealing process is performed on the active layer to induce the active layer to perform transverse crystallization and longitudinal crystallization, so that the uniformity of crystallization is improved, and the active layer is changed from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. And further, the problem that the uniformity of laser annealing crystallization on the oxide semiconductor is poor on a large generation line, and the performance of the oxide semiconductor device is influenced is solved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2-7 are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," and the like are used in the orientation or positional relationship indicated in the drawings, which are based on the orientation or positional relationship shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore should not be considered as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. In this application, "/" means "or".
The present application may repeat reference numerals and/or reference letters in the various examples for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
At present, with the application of large-sized display panels in various fields of each row, the display requirements for the large-sized display panels are higher and higher. Among them, the oxide thin film transistor technology is applied to a display panel because of its high mobility, but a crystallization method using laser annealing has a problem of poor uniformity of crystallization for a large generation production line, thereby affecting the performance of an oxide semiconductor device.
Embodiments of the present application provide an array substrate and a method for manufacturing the same, which can improve uniformity of crystallization of an oxide semiconductor layer, thereby solving a problem that the uniformity of laser annealing crystallization of the oxide semiconductor layer on a large generation line is poor, which affects performance of an oxide semiconductor device.
Fig. 1 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure. Fig. 2 to fig. 7 are schematic views illustrating a manufacturing process of the array substrate according to an embodiment of the present disclosure. The preparation method comprises the following steps:
step S1, a grid electrode, a grid insulation layer and an active layer are sequentially prepared on a substrate, wherein the active layer comprises a channel region, and a source electrode contact region and a drain electrode contact region which are respectively positioned on two sides of the channel region.
As shown in fig. 2, a gate metal layer is deposited on the substrate 100, and in particular, the gate metal layer may be deposited on the substrate 100 by sputtering or thermal evaporation to a thickness of about 500 a to about 4000 a. And patterning the gate metal layer to form a patterned gate 200.
Then, a gate insulating layer 300 and an oxide semiconductor film layer are sequentially formed on the gate electrode 200, and the oxide semiconductor film layer is patterned to form an active layer 400 disposed corresponding to the gate electrode 200. The active layer 400 includes a channel region 401, and a source contact region 402 and a drain contact region 403 respectively located at two sides of the channel region 401.
Wherein the gate electrode 200 may include a single layer or a plurality of layers formed of at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).
The gate insulating layer 300 may be made of an oxide, a nitride, or an oxynitride.
Specifically, the material of the oxide semiconductor film layer includes, but is not limited to, amorphous ITO, IGO, IGZO, HIZO, IZO, a-InZnO, znO, cdO, tiO 2 、Al 2 O 3 、SnO、Cu 2 O、NiO、CoO、FeO、Cr 2 O 3 、SnO 2 、Fe 2 O 3 、ZrO 2 、WO 3 、In 2 O 3 、Fe 3 O 4 At least one of (a).
Step S2, preparing a crystallization inducing film on the active layer, and patterning the crystallization inducing film to form a crystallization inducing line at least located in the source contact region and the drain contact region, wherein the crystallization inducing line is perpendicular to a direction of a connection line between the source contact region and the drain contact region.
As shown in fig. 3 and 4, specifically, a crystallization inducing film 500 is prepared on the active layer 400 in a whole layer, the crystallization inducing film 500 has a thickness of 20 a to 500 a, and the crystallization inducing film 500 is patterned to form a crystallization inducing line 501 at the source contact region 402 and the drain contact region 403. Wherein the crystallization inducing line 500 is perpendicular to a connection line direction between the source contact region 402 and the drain contact region 403, and the connection line direction between the source contact region 402 and the drain contact region 403 is shown by an arrow in the figure.
Specifically, the material of the crystallization inducing line 501 is one or more alloys of nickel, tantalum, and tungsten metal materials, but not limited thereto.
The crystallization inducing line 501 covers a portion of the source contact region 402 and the drain contact region 403, such as one-half, one-third, one-fourth, one-fifth, etc. of the area of the source contact region 402/the drain contact region 403.
In the present embodiment, the crystallization inducing line 501 is located at a position on a side of the source/drain contact regions 402/403 away from the channel region 401.
And S3, applying a horizontal electric field between two adjacent crystallization inducing lines, and simultaneously carrying out annealing process on the active layer to induce the active layer to crystallize to form the active layer of the polycrystalline material.
Specifically, the crystallization inducing line 501 may induce the crystallization of the active layer under the heat treatment condition of the annealing process; the uniformity of laser annealing crystallization of an oxide semiconductor on a large generation production line is poor; therefore, the present application simultaneously applies a horizontal electric field between two adjacent crystallization-inducing lines 501, and since the electric field greatly increases the mobility of the diffusions, the rate of metal-induced lateral crystallization can be increased.
Further, the intensity of the horizontal electric field applied between two adjacent crystallization-inducing lines 501 is 1V/m to 10V/m. The intensity of the horizontal electric field is in this range, the mobility of the diffuser is high, and the rate of lateral crystallization is fast.
The annealing temperature in the conventional annealing crystallization process is high, for example, 600 ℃, and other film layers and devices of the array substrate are easily damaged at such a high temperature. Under the auxiliary action of the electric field, the temperature of the annealing process can be reduced, and the crystallization time is shortened.
In the embodiment, the temperature of the annealing process can be reduced by 200-400 ℃, which greatly reduces the process temperature compared with the conventional laser annealing crystallization process.
Further, the electric field direction of the horizontal electric field of the present application is parallel to the wiring direction between the source contact region 402 and the drain contact region 403.
The active layer 400 is crystallized to form crystal grains, wherein the crystal orientation direction of the portion of the active layer 400 corresponding to the portion between two adjacent crystallization inducing lines 501 is parallel to the line direction between the source contact region 402 and the drain contact region 403. Therefore, the active layer 400 is made superior in mechanical properties parallel to the crystalline direction.
In the present application, the active layer 400 is longitudinally crystallized at a position corresponding to the crystallization inducing line 501, and the active layer 400 is transversely crystallized at a portion corresponding to a portion between two adjacent crystallization inducing lines 501, so that the uniformity of crystallization of the active layer 400 of an oxide semiconductor material can be improved, and the problem of poor uniformity of laser annealing crystallization of an oxide semiconductor on a large-generation production line can be avoided. In addition, the lateral crystallization enables the channel region 401 to introduce less metal residue, thereby avoiding the possibility of the source contact region 402 and the drain contact region 403 penetrating. In addition, a horizontal electric field is applied between two adjacent crystallization inducing lines 501, so that a crystallization front can be moved out of the channel region 401, thereby avoiding the problems of increased gate leakage and the like caused by more crystallization fronts in the channel region 401, and further improving the reliability of the device.
In one embodiment, the preparation method of the present application may further include the steps of:
in step S4, as shown in fig. 5, a source electrode 600 and a drain electrode 700 are formed on the active layer 400.
The source electrode 600 contacts the source contact region 402, and the drain electrode 700 contacts the drain contact region 403, wherein the portion of the source electrode 600/drain electrode 700 corresponding to the crystallization-inducing line 501 contacts the source contact region 402/drain contact region 403 through the crystallization-inducing line 501.
The source 600/drain 700 material may be Cu, al, ag, mo, cr, nd, ni, mn, ti, ta, W, and other metals and alloys of these metals. The source/drain electrodes 600/700 may have a single layer structure or a multi-layer structure such as Cu/Mo, ti/Cu/Ti, mo/Al/Mo, etc.
In step S5, as shown in fig. 6, a passivation layer 800 is formed on the source electrode 600 and the drain electrode 700.
Wherein the passivation layer 800 includes a single-layer or multi-layer structure of one or more of silicon oxide and silicon nitride.
In one embodiment, the patterning of the crystallization-inducing film in the step S2 further includes the steps of:
forming at least one crystallization inducing line in the channel region; wherein the at least one crystallization inducing line located in the channel region is disposed in parallel with the crystallization inducing lines of the source contact region and the drain contact region.
As shown in fig. 7, only one crystallization inducing line 501 is illustrated in the channel region 401, but it is not limited thereto, and two, three, etc. crystallization inducing lines may be further included in other embodiments. Since the crystallization inducing lines 501 are also correspondingly disposed in the channel region 401, the crystallization inducing lines 501 located in the channel region 401 may simultaneously form an electric field with the crystallization inducing lines 501 on both sides thereof when an electric field is applied. As such, the uniformity of crystallization of the active layer 400 of the oxide semiconductor material can be further ensured.
The present application also provides an array substrate prepared by the above preparation method, as shown in fig. 8, the array substrate includes: a substrate 100; a gate 200 disposed on the substrate 100; a gate insulating layer 300 disposed on the gate electrode 200; an active layer 400 disposed on the gate insulating layer 300 corresponding to the gate electrode 200, the active layer 400 including a channel region 401 and source and drain contact regions 402 and 403 respectively located at both sides of the channel region 401; a crystallization inducing layer disposed on the active layer 400, the crystallization inducing layer including at least a crystallization inducing line 501 located at the source contact region 402 and the drain contact region 403; wherein the crystallization inducing line 501 is wired perpendicular to a wiring direction between the source contact region 402 and the drain contact region 403, and the active layer 400 is a polycrystalline oxide semiconductor layer.
In this embodiment, the material of the crystallization inducing layer is one or more alloys of nickel, tantalum, and tungsten metal materials.
Wherein a grain orientation direction of a portion of the active layer corresponding to between two adjacent crystallization-inducing lines is parallel to a line direction between the source contact region and the drain contact region.
The array substrate further comprises a source electrode and a drain electrode which are arranged on the active layer, the source electrode is in contact with the source electrode contact region, the drain electrode is in contact with the drain electrode contact region, and the part of the source electrode/the drain electrode, corresponding to the crystallization inducing line, is in contact with the source electrode contact region/the drain electrode contact region through the crystallization inducing line.
In one embodiment, as shown in fig. 9, the crystallization inducing layer further includes at least one crystallization inducing line 502 located in the channel region 401, and the at least one crystallization inducing line located in the channel region is disposed in parallel with the crystallization inducing lines of the source contact region and the drain contact region.
According to the array substrate and the preparation method thereof, parallel crystallization induction lines are formed in a source electrode contact region and a drain electrode contact region of an active layer, a horizontal electric field is applied between two adjacent crystallization induction lines, the electric field direction of the horizontal electric field is parallel to the connecting line direction between the source electrode contact region and the drain electrode contact region, and meanwhile, an annealing process is performed on the active layer to induce the active layer to perform transverse crystallization and longitudinal crystallization, so that the uniformity of crystallization is improved, and the active layer is changed from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer. Further solves the problem that the uniformity of laser annealing crystallization on the oxide semiconductor is poor on a large generation line, and the performance of the oxide semiconductor device is influenced.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application is defined by the appended claims.
Claims (8)
1. An array substrate, comprising:
a substrate;
a gate disposed on the substrate;
a gate insulating layer disposed on the gate electrode;
the active layer is arranged on the gate insulating layer corresponding to the gate electrode and comprises a channel region and a source electrode contact region and a drain electrode contact region which are respectively positioned at two sides of the channel region;
a crystallization inducing layer disposed on the active layer, the crystallization inducing layer including at least a crystallization inducing line located at the source contact region and the drain contact region;
the crystallization inducing lines are arranged in a direction perpendicular to a connecting line between the source contact region and the drain contact region, and a horizontal electric field is applied between every two adjacent crystallization inducing lines; the active layer is a crystalline oxide semiconductor layer, the crystal orientation direction of the portion, corresponding to the position between two adjacent crystallization inducing lines, of the active layer is parallel to the direction of a connecting line between the source contact region and the drain contact region, and the crystal orientation direction of the portion, corresponding to the position of the crystallization inducing line, of the active layer is perpendicular to the direction of the connecting line between the source contact region and the drain contact region.
2. The array substrate of claim 1, wherein the crystallization inducing layer further comprises at least one crystallization inducing line in the channel region, and the at least one crystallization inducing line in the channel region is disposed in parallel with the crystallization inducing lines in the source contact region and the drain contact region.
3. The array substrate of claim 1, wherein the crystallization inducing layer is made of one or more alloys of nickel, tantalum, and tungsten.
4. The array substrate of claim 1, further comprising a source electrode and a drain electrode disposed on the active layer, wherein the source electrode is in contact with the source contact region, and the drain electrode is in contact with the drain contact region, wherein a portion of the source/drain electrode corresponding to the crystallization inducing line is in contact with the source/drain contact region through the crystallization inducing line.
5. The preparation method of the array substrate is characterized by comprising the following steps:
the method comprises the following steps that S1, a grid electrode, a grid insulation layer and an active layer are sequentially prepared on a substrate, wherein the active layer comprises a channel region, and a source electrode contact region and a drain electrode contact region which are respectively positioned on two sides of the channel region;
step S2, preparing a crystallization inducing film on the active layer, and patterning the crystallization inducing film to form a crystallization inducing line at least located in the source contact region and the drain contact region, wherein the crystallization inducing line is perpendicular to a connecting line direction between the source contact region and the drain contact region;
step S3, applying a horizontal electric field between two adjacent crystallization inducing lines, and simultaneously performing an annealing process on the active layer to induce the active layer to crystallize, so that the active layer is converted from an amorphous oxide semiconductor layer to a crystalline oxide semiconductor layer;
the crystal orientation direction of the part of the active layer corresponding to the position between two adjacent crystallization inducing lines is parallel to the direction of a connecting line between the source electrode contact region and the drain electrode contact region, and the crystal orientation direction of the active layer corresponding to the position of the crystallization inducing line is perpendicular to the direction of the connecting line between the source electrode contact region and the drain electrode contact region.
6. The production method according to claim 5, wherein the intensity of the horizontal electric field applied between adjacent two of the crystallization-inducing lines is 1V/m to 10V/m.
7. The production method according to claim 5, wherein the patterning of the crystallization-inducing film in step S2 further comprises the steps of:
forming at least one crystallization inducing line in the channel region; wherein at least one of the crystallization inducing lines in the channel region is disposed in parallel with the crystallization inducing lines in the source contact region and the drain contact region.
8. The manufacturing method according to claim 5, wherein an electric field direction of the horizontal electric field is parallel to a wiring direction between the source contact region and the drain contact region.
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| KR100958826B1 (en) * | 2007-10-24 | 2010-05-24 | 재단법인서울대학교산학협력재단 | Poly Crystalline Silicon Thin Film Transistor Having Bottom Gate Structure Using Metal Induced Lateral Crystallization and Method for Fabricating the Same |
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| KR101263726B1 (en) * | 2008-11-07 | 2013-05-13 | 엘지디스플레이 주식회사 | Array substrate including thin film transistor of polycrystalline silicon and method of fabricating the same |
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