JP2010278116A - Method of manufacturing semiconductor element substrate, the semiconductor element substrate and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide electrical characteristics demanded of semiconductor elements requiring different electric characteristics using two kinds of crystalline semiconductor films, by forming two kinds of crystalline semiconductor films, having different average crystal particle sizes and superior carrier mobility on the same substrate. <P>SOLUTION: The manufacturing method includes an amorphous film formation step for forming an amorphous semiconductor film 24 on a substrate 11; a first crystallizing step for forming a first crystalline semiconductor film 24A, by melting/solidifying a part of the amorphous semiconductor film 24 for crystallizing; a second crystallizing step for forming a second crystalline semiconductor film 24B; whose average crystal particle size is larger than that of the first crystalline semiconductor film 24A by solid phase growth of a remaining amorphous semiconductor film 24; and a recrystallization step, in which the first and second c crystalline semiconductor films 24B are melted and solidified for recrystallization, while such state having average crystal particle size of the first crystalline semiconductor film 24A being smaller than that of the second crystalline semiconductor film 24B is maintained. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element substrate, a semiconductor element substrate, and a display device.

  A semiconductor element substrate includes an electric circuit having an active element utilizing the electrical characteristics of a semiconductor, and is widely applied to, for example, audio equipment, communication equipment, home appliances, and the like. Among them, a semiconductor element substrate including a field effect transistor such as a thin film transistor (hereinafter referred to as TFT) or a MOS (Metal Oxide Semiconductor) transistor is an active matrix driving type liquid crystal display device or an organic electroluminescence display device. It is used as an active matrix substrate in a thin display device.

  As a method for manufacturing such a semiconductor element substrate, in recent years, an amorphous semiconductor film is formed on a substrate having an insulating surface such as a glass substrate, and the amorphous semiconductor film is crystallized, A technique for forming a crystalline semiconductor film (a semiconductor film having a crystal structure) has been widely studied. A crystalline semiconductor film has a very high carrier mobility compared to an amorphous semiconductor film. Therefore, a TFT formed using a crystalline semiconductor film is, for example, a full monolithic liquid crystal display device in which peripheral circuits such as a drive circuit are formed on the same substrate together with a plurality of pixels constituting a display region. It is used as a TFT of each pixel, a TFT of a driving circuit, etc., and enables high definition and high speed moving image display of a display device.

  As a crystallization method for forming a crystalline semiconductor film, a thermal annealing method using a furnace annealing furnace is known. In order to crystallize an amorphous semiconductor film by a thermal annealing method using this furnace annealing furnace, it is usually necessary to perform a heat treatment at a temperature of 600 ° C. or more for 10 hours or more. For this reason, the substrate material applicable to crystallization is limited to expensive quartz or the like. In order to increase the production efficiency of the semiconductor element substrate, it is necessary to increase the area of the substrate. In recent years, the use of a substrate having a side exceeding 1 m has been considered. It is very difficult to process a large area substrate.

  Therefore, as a method for enabling the crystallization temperature to be lowered and the processing time to be shortened, a method of forming a crystalline semiconductor film by performing a heat treatment after adding a catalytic element that promotes crystallization to an amorphous semiconductor film Is known (see, for example, Patent Document 1). Specifically, a small amount of an element such as nickel, palladium, or lead is added to the amorphous semiconductor film, and then a heat treatment is performed at 550 ° C. for 4 hours to form a crystalline semiconductor film.

  Further, a laser annealing method is known as a technique for imparting high energy only to a semiconductor film without significantly increasing the temperature of the substrate. As the laser annealing method, for example, a pulsed laser beam such as an excimer laser is formed in an optical system so that a square spot of several centimeters square or a linear shape having a length of 100 mm or more is formed on the irradiated surface. An example is a method in which annealing is performed by moving the object relative to the irradiation object. When the amorphous semiconductor film is crystallized by such a laser annealing method, it is possible to use not only glass with a relatively low strain point but also plastic as a substrate material.

  Further, a method combining the above crystallization methods, that is, after forming a crystalline semiconductor film by adding a catalyst element that promotes crystallization to the amorphous semiconductor film and performing a heat treatment, the crystalline semiconductor A method for improving the crystallinity of a film by a laser annealing method is known (for example, see Patent Document 2). A method of performing laser annealing twice to improve the crystallinity of the crystalline semiconductor film is also known (see, for example, Patent Document 3). According to these methods, it is possible to form a crystalline semiconductor film having relatively large crystal grains throughout, and the carrier mobility of the crystalline semiconductor film can be further increased.

JP 7-183540 A JP 2000-216089 A JP 2007-115786 A

  However, when a crystalline semiconductor film is formed by the method disclosed in Patent Documents 2 and 3 and each pixel and peripheral circuit are formed on the same substrate using the crystalline semiconductor film, for example, the TFT of the pixel As described above, the number of crystal grains in the channel region tends to vary greatly between TFTs having relatively small channel regions, that is, the number of crystal grain boundaries in the channel region tends to vary greatly. There is a case. In order to suppress such a variation in threshold voltage between TFTs, it is conceivable to reduce the crystal grain size of the crystalline semiconductor film. The carrier mobility also decreases for TFTs in peripheral circuits that require carrier mobility.

  Further, in the case where a photosensor such as a photodiode is formed on the same substrate together with a TFT using a crystalline semiconductor film formed by the method disclosed in Patent Documents 2 and 3, the off-leak current in the dark in the photosensor May become relatively large, and the ratio of current flowing between the on state and the off state (hereinafter referred to as on / off ratio) may decrease. In order to suppress such a decrease in the on / off ratio of the optical sensor, it is conceivable to reduce the crystal grain size of the crystalline semiconductor film. However, as described above, the carrier mobility in the TFT of the peripheral circuit decreases. End up.

  Therefore, in a semiconductor element substrate in which an optical sensor such as a photodiode is formed on the same substrate together with two types of TFTs and TFTs having channel regions of different sizes, all TFTs and photodiodes existing on the substrate It is difficult to obtain necessary and sufficient electrical characteristics for a semiconductor element. In addition, a display device including such a semiconductor element substrate as an active matrix substrate has a room for improvement because variations in luminance and color tend to be large and display is not stable.

  The present invention has been made in view of such various points. The object of the present invention is to provide two types of crystals on the same substrate, each having an average particle size of crystal grains different from each other and each having excellent carrier mobility. Forming a crystalline semiconductor film and using the two types of crystalline semiconductor films to obtain desired electrical characteristics for each semiconductor element that requires different electrical characteristics.

  The inventors of the present invention have studied various methods for forming two types of crystalline semiconductor films having different average grain sizes, and crystallize the semiconductor film during the process of forming the crystalline semiconductor film. Attention was focused on the process (hereinafter referred to as the crystallization process). In the method of performing crystallization of the semiconductor film a plurality of times during the crystallization process, after forming the first crystalline semiconductor film by crystallizing a part of the amorphous semiconductor film, the remaining amorphous By forming a second crystalline semiconductor film having a larger average grain size than that of the first crystalline semiconductor film by solid-phase growth of the semiconductor film, two types of crystalline materials having different average grain diameters of the crystal grains are formed. It has been found that a semiconductor film can be formed. Then, the first crystalline semiconductor film and the second crystalline semiconductor film are maintained while maintaining the average grain size of the first crystalline semiconductor film smaller than the average grain size of the crystal grains of the second crystalline semiconductor film. In the second crystalline semiconductor film crystallized by solid phase growth, the crystallinity of the first crystalline semiconductor film and the second crystalline semiconductor film is improved by melting and solidifying and recrystallizing. It has been found that it is possible to improve the crystallinity of the second crystalline semiconductor film by increasing the crystal defects of the second crystalline semiconductor film, thereby increasing the carrier mobility, and thus the above problem can be solved brilliantly. Has reached

  That is, in order to achieve the above-described object, the present invention provides a solid crystal growth of the remaining amorphous semiconductor film after a part of the amorphous semiconductor film is melted and solidified, whereby the average grain size of the crystal grains is increased. A first crystalline semiconductor film and a second crystalline semiconductor film that are different from each other are formed, and the first crystalline semiconductor film and the second crystalline semiconductor film are melted and solidified and recrystallized.

  In the present specification, the average grain size of crystal grains means the average size of crystal grains contained in the crystalline semiconductor film, and is based on the back diffusion electron diffraction image method (Electron Backscatter Diffracation Patterns method). , Hereinafter referred to as the EBSP method).

  Specifically, a method for manufacturing a semiconductor element substrate according to the present invention is a method for manufacturing a semiconductor element substrate having a semiconductor element on a substrate having an insulating surface, wherein an amorphous semiconductor film is formed on the substrate. An amorphous film forming step of forming a film; a first crystallization step of forming a first crystalline semiconductor film by melting and solidifying a part of the amorphous semiconductor film; and The remaining amorphous semiconductor film that has not been crystallized in one crystallization step is solid-phase grown to form a second crystalline semiconductor film having an average grain size larger than that of the first crystalline semiconductor film. A second crystallization step and the first crystalline semiconductor while maintaining an average grain size of the crystal grains in the first crystalline semiconductor film smaller than an average grain size of the crystal grains in the second crystalline semiconductor film; Melting and solidifying the film and the second crystalline semiconductor film Ri, characterized in that it comprises a recrystallization step of recrystallizing the first crystalline semiconductor film and the second crystalline semiconductor film.

  According to this manufacturing method, the amorphous semiconductor film is formed on the substrate in the amorphous film forming process, and a part of the amorphous semiconductor film is melted and solidified and crystallized in the first crystallization process. Then, after the first crystalline semiconductor film is formed, the remaining amorphous semiconductor film is solid-phase grown in the second crystallization step, so that the average grain size of the crystal grains is larger than that of the first crystalline semiconductor film. A two crystalline semiconductor film is formed. As a result, a first crystalline semiconductor film and a second crystalline semiconductor film having different average grain sizes are formed. Further, in the recrystallization step, the first crystalline semiconductor film is maintained while maintaining the average grain size of the crystal grains in the first crystalline semiconductor film smaller than the average grain diameter of the crystal grains in the second crystalline semiconductor film. The first crystalline semiconductor film and the second crystalline semiconductor film are recrystallized by melting and solidifying the second crystalline semiconductor film. Thereby, the crystallinity of the first crystalline semiconductor film and the second crystalline semiconductor film is improved and the carrier mobility is increased. Therefore, on the same substrate, the first crystalline semiconductor film and the second crystalline semiconductor film having different average grain diameters and having excellent carrier mobility are formed. The first crystalline semiconductor film and the second crystalline semiconductor film can be used to obtain desired electrical characteristics for each semiconductor element that requires different electrical characteristics.

  As described above, the method of manufacturing a semiconductor element substrate according to the present invention includes other steps as long as it includes the amorphous film forming step, the first crystallization step, the second crystallization step, and the recrystallization step as essential steps. Although it does not need to include the process, it is preferably configured as follows.

  The amorphous semiconductor film is preferably an amorphous silicon film.

  According to this manufacturing method, carrier mobility such as continuous grain silicon (hereinafter referred to as CG silicon) or polycrystalline silicon (polysilicon) is used as the first crystalline semiconductor film and the second crystalline semiconductor film. It is possible to form an excellent crystalline silicon film.

  Prior to the amorphous film formation step, heating for promoting heating of the amorphous semiconductor film by reflecting or absorbing a laser beam to a region where the first crystalline semiconductor film is formed It is preferable to further include a heating promotion layer forming step of forming an acceleration layer, and in the first crystallization step, a part of the amorphous semiconductor film is melted and solidified by laser beam irradiation.

  According to this manufacturing method, heating of the amorphous semiconductor film is promoted by reflecting or absorbing the laser beam to the region where the first crystalline semiconductor film is formed before the amorphous film forming step. When the amorphous semiconductor film is irradiated with the laser beam in the first crystallization step, the heating promoting layer reflects or absorbs the laser beam in the first crystallization step, so that the amorphous semiconductor film The portion on and near the heating promotion layer is heated more than the portion away from the heating promotion layer, and the temperature rises. This makes it possible to selectively melt and solidify only the portion on and near the heating promoting layer in the amorphous semiconductor film, so that the first crystalline semiconductor having different crystal grain sizes can be obtained. It is possible to reliably form the film and the second crystalline semiconductor film separately.

  Furthermore, in the first crystallization step, the amorphous semiconductor film may be irradiated with a laser beam under a condition that only the amorphous semiconductor film is crystallized on the heating promotion layer and in the vicinity of the heating promotion layer. preferable. For example, it is preferable that the amorphous semiconductor film is an amorphous silicon film, and in the first crystallization step, the amorphous semiconductor film is irradiated with a laser beam having a wavelength of 370 nm or more and 650 nm or less.

  According to this manufacturing method, only the portion of the amorphous semiconductor film that forms the first crystalline semiconductor film on and near the heating promotion layer is selectively melted and solidified to be crystallized. The film can be formed at a predetermined position. This makes it possible to form the first crystalline semiconductor film and the second crystalline semiconductor film in desired positions.

  In the first crystallization step, the amorphous semiconductor film is preferably irradiated with a pulsed or continuous wave solid laser beam.

  According to this manufacturing method, since the laser oscillator of the solid laser beam has a simple structure, no maintenance is required over a long period of time. As a result, the operating time can be extended and the running cost can be reduced. It becomes possible.

  In the first crystallization step, it is preferable to irradiate the amorphous semiconductor film with a second harmonic of a yttrium aluminum garnet laser (hereinafter referred to as a YAG laser).

  According to this manufacturing method, since the second harmonic of the YAG laser has a wavelength of 532 nm, it is possible to selectively melt and solidify only the portion of the amorphous semiconductor film on and near the heating promoting layer for crystallization. It becomes possible. In particular, when the amorphous semiconductor film is an amorphous silicon film, it is possible to efficiently absorb the second harmonic of the YAG laser in the amorphous semiconductor film, and the crystal of the amorphous semiconductor film Can be efficiently performed.

  In the first crystallization step, the amorphous semiconductor film is scanned while step-scanning a pulsed laser beam having a linear beam shape on the surface of the amorphous semiconductor film in the width direction of the laser beam. Is preferably irradiated. Here, the straight shape means a rectangular or elliptical and elongated shape. The width direction of the laser beam means the short side direction of the laser beam when the laser beam is rectangular, and the short axis direction of the laser beam when the laser beam is elliptical. The step scanning is a scanning method in which the irradiation position of the laser beam is moved by a predetermined width for each shot of the pulsed laser beam.

  According to this manufacturing method, the amorphous semiconductor film is efficiently and simply crystallized because the amorphous semiconductor film is irradiated with a linear laser beam while performing step scanning in the width direction. Therefore, it is particularly effective when the amorphous semiconductor film has a large area.

  In addition, in the first crystallization step, the amorphous semiconductor film is irradiated with a continuous wave laser beam while scanning the surface of the amorphous semiconductor film at a speed of 5 cm / s or more and 3 m / s or less. It is preferable to do.

  According to this manufacturing method, since the scanning speed of the laser beam is 5 cm / s or more, the amorphous semiconductor film is suppressed from being evaporated by receiving excessive energy. Since the scanning speed of the laser beam is 3 m / s or less, the scanning speed of the laser beam is not too high, and the amorphous semiconductor film can be reliably melted and solidified.

  In the heating promotion layer forming step, the heating promotion layer is preferably formed so that the film thickness is 50 nm or more and 500 nm or less, and the heating promotion layer is formed so that the film thickness is 50 nm or more and 300 nm or less. More preferably, it is formed.

  If the heating promotion layer is formed so that the film thickness is smaller than 50 nm, the laser beam is reflected or absorbed by the heating promotion layer when the amorphous semiconductor film is irradiated with the laser beam in the first crystallization step. This may be insufficient, and it may not be possible to selectively melt and solidify only the portion of the amorphous semiconductor film on and near the heating promoting layer. On the other hand, if the heating promotion layer is formed so that the film thickness is larger than 500 nm, the step between the region where the heating promotion layer is provided and the region where the heating promotion layer is not provided becomes relatively large. For this reason, the electrodes and wirings are likely to be disconnected due to the steps.

  On the other hand, when the heating promotion layer is formed so that the film thickness is 50 nm or more and 500 nm or less as in the manufacturing method described above, only the portion of the amorphous semiconductor film on and near the heating promotion layer is selectively used. Can be reliably melted and solidified, and the step between the region provided with the heating promoting layer and the region not provided with the heating promoting layer is relatively small. Etc. are prevented from breaking. Furthermore, when the heating promotion layer is formed so that the film thickness is 300 nm or less, disconnection of electrodes, wiring, and the like due to a step between the region where the heating promotion layer is provided and the region where the heating promotion layer is not provided. It is further suppressed.

  The heating promotion layer preferably contains at least one element of molybdenum and tungsten.

  According to this manufacturing method, since molybdenum and tungsten are high melting point materials, the heating promotion layer containing at least one element of molybdenum and tungsten is difficult to melt in all the steps including the first crystallization step. . As a result, the material of the heating promotion layer is prevented from diffusing into the first crystalline semiconductor film, so that deterioration of the electrical characteristics of the first crystalline semiconductor film due to the heating promotion layer is suppressed. The

  In the second crystallization step, a catalyst element that promotes crystallization of the amorphous semiconductor film is added to the remaining amorphous semiconductor film, and then the remaining amorphous semiconductor film is imparted with crystallization energy. It is preferable to perform solid phase growth selectively. Here, the catalytic element may be added only to the remaining amorphous semiconductor film that has not been crystallized in the first crystallization step, or may be added to the entire semiconductor film including the first crystalline semiconductor film. . Specifically, it can be simply added by applying a solution containing the catalyst element or vacuum depositing the catalyst element.

  According to this manufacturing method, crystallization of the remaining amorphous semiconductor film to which the catalytic element is added is promoted, and crystal grains having a relatively large average grain size grow due to the catalytic element. The carrier mobility of the semiconductor film can be reliably increased. Therefore, it is possible to improve the efficiency of the manufacturing process and improve the characteristics of the second crystalline semiconductor film.

Further, in the second crystallization step, the catalyst element is added so that the concentration on the surface of the amorphous semiconductor film is 1 × 10 ¹⁰ atoms / cm ² or more and 1 × 10 ¹² atoms / cm ² or less. It is preferable. Here, the concentration of the catalytic element on the surface of the amorphous semiconductor film can be easily measured by total reflection X-ray fluorescence analysis. The concentration of the catalytic element on the surface of the amorphous semiconductor film may be a result of measuring the concentration in a region having a depth of several nm (5 nm to 10 nm) from the surface of the amorphous semiconductor film.

If the catalytic element is added so that the concentration on the surface of the amorphous semiconductor film is less than 1 × 10 ¹⁰ atoms / cm ^2, the effect of promoting crystallization of the amorphous semiconductor film by the catalytic element is relatively small. Therefore, the time required to crystallize the amorphous semiconductor film becomes long, and the efficiency of the manufacturing process is lowered. On the other hand, when the catalytic element is added so that the concentration on the surface of the amorphous semiconductor film exceeds 1 × 10 ¹² atoms / cm ² , the catalytic element in the second crystalline semiconductor film becomes high in concentration and is attributed to the catalytic element. Since the density of the formed crystal grains becomes relatively high and the average grain diameter of the crystal grains becomes small, the carrier mobility of the second amorphous semiconductor film tends to be small. For this reason, when a TFT is formed using the second crystalline semiconductor film, sufficient transistor characteristics may not be obtained.

On the other hand, when the catalyst element is added so that the concentration on the surface of the amorphous semiconductor film is 1 × 10 ¹⁰ atoms / cm ² or more and 1 × 10 ¹² atoms / cm ² or less as in the above manufacturing method. Since the crystallization of the remaining amorphous semiconductor film is effectively promoted by the catalytic element, the manufacturing process can be performed efficiently. Furthermore, since the catalyst element in the second crystalline semiconductor film has a low concentration, the density of the crystal grains formed due to the catalyst element is relatively low, and the average grain size of the crystal grains is increased. The carrier mobility of the crystalline semiconductor film can be reliably increased. Therefore, it is possible to further improve the efficiency of the manufacturing process and improve the characteristics of the second crystalline semiconductor film. In the case where a TFT is formed using the second crystalline semiconductor film, desired transistor characteristics can be obtained.

  The catalytic element preferably contains at least one element selected from the group consisting of iron, cobalt, nickel, germanium, ruthenium, rhodium, palladium, osmium, iridium, platinum, copper and gold.

  According to this manufacturing method, it is possible to favorably promote the crystallization of the remaining amorphous semiconductor film to which the catalytic element is added.

  In the second crystallization step, the remaining amorphous semiconductor film may be solid-phase grown by heat-treating the amorphous semiconductor film in a heat treatment furnace.

  According to this manufacturing method, it is possible to easily form the second crystalline semiconductor film while simultaneously improving the efficiency of the manufacturing process and improving the characteristics of the second crystalline semiconductor film.

  In the second crystallization step, the amorphous semiconductor film is preferably heat-treated at a temperature of 500 ° C. or higher and 700 ° C. or lower.

  If the amorphous semiconductor film is heat-treated at a temperature lower than 500 ° C., the solid phase growth rate of the amorphous semiconductor film becomes relatively slow. On the other hand, when the amorphous semiconductor film is heat-treated at a temperature exceeding 700 ° C., in addition to the crystal grains that are solid-phase grown due to the catalytic element, a relatively small particle size of, for example, 0.2 μm or less that does not originate from the catalytic element. Since crystal grains grow, the carrier mobility of the second crystalline semiconductor film tends to decrease. For this reason, when a TFT is formed using the second crystalline semiconductor film, sufficient transistor characteristics may not be obtained.

  On the other hand, when the amorphous semiconductor film is heat-treated at a temperature of 500 ° C. or more and 700 ° C. or less as in the above manufacturing method, the solid-phase growth rate of the amorphous semiconductor film is increased favorably. Furthermore, the growth of crystal grains not caused by the catalytic element is suppressed, and the carrier mobility of the second crystalline semiconductor film can be reliably increased. Therefore, it is possible to easily form the second crystalline semiconductor film while improving the efficiency of the manufacturing process and improving the characteristics of the second crystalline semiconductor film. In the case where a TFT is formed using the second crystalline semiconductor film, desired transistor characteristics can be obtained.

  In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are irradiated with a laser beam under a condition for partially melting the first crystalline semiconductor film and the second crystalline semiconductor film. Thus, it is preferable to partially melt and solidify the first crystalline semiconductor film and the second crystalline semiconductor film. For example, the amorphous semiconductor film is an amorphous silicon film, and a laser beam having a wavelength of 126 nm or more and less than 370 nm is applied to the first crystalline semiconductor film and the second crystalline semiconductor film in the recrystallization process. Irradiation is preferred.

  According to this manufacturing method, the first crystalline semiconductor film and the second crystalline semiconductor film are partially melted and solidified without melting each part of the first crystalline semiconductor film and the second crystalline semiconductor film. The crystallinity can be improved without changing the average grain size and crystal orientation of the crystal grains of the first crystalline semiconductor film and the second crystalline semiconductor film.

  As described above, from the viewpoint of exerting the operational effects of the present invention more reliably, the first crystallization step and the recrystallization step use laser beams having different wavelengths depending on the material of the amorphous semiconductor film. It is preferable. Specifically, when the amorphous semiconductor film is an amorphous silicon film, in the first crystallization step, the amorphous semiconductor film is irradiated with a laser beam having a wavelength of 370 nm or more and 650 nm or less to perform recrystallization. In the step, the first crystalline semiconductor film and the second crystalline semiconductor film are preferably irradiated with a laser beam having a wavelength of 126 nm or more and less than 370 nm.

  In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are irradiated by irradiating the first crystalline semiconductor film and the second crystalline semiconductor film with a pulsed excimer laser beam. May be melted and solidified.

  In the recrystallization step, the first crystalline semiconductor film is scanned while step-scanning a pulsed laser beam having a linear beam shape on the surface of the amorphous semiconductor film in the width direction of the laser beam. It is preferable that the first crystalline semiconductor film and the second crystalline semiconductor film are melted and solidified by irradiating the second crystalline semiconductor film.

  According to this manufacturing method, the first crystalline semiconductor film and the second crystalline semiconductor film are efficiently and simply melted and solidified because the amorphous semiconductor film is irradiated while step-scanning the linear laser beam in the width direction. Thus, crystallinity can be improved.

  The semiconductor element substrate according to the present invention is manufactured by the method for manufacturing a semiconductor element substrate according to the present invention.

  According to this configuration, the first crystalline semiconductor film and the second crystalline semiconductor film formed by the method for manufacturing a semiconductor element substrate according to the present invention have different average grain sizes, and carrier movement Since the electrical characteristics such as degrees differ from each other, by forming a semiconductor element using one of the first crystalline semiconductor film and the second crystalline semiconductor film according to the required electrical characteristics, different electrical characteristics can be obtained. Desired electrical characteristics can be obtained for each semiconductor element that requires characteristics.

  The semiconductor element substrate having the above structure may include a first TFT having a semiconductor layer formed from the first crystalline semiconductor film and a second TFT having a semiconductor layer formed from the second crystalline semiconductor film. Good.

  According to this configuration, it is possible to obtain desired electrical characteristics for the first TFT and the second TFT that require different electrical characteristics.

  Moreover, you may provide the optical sensor which has a semiconductor layer formed from the said 1st crystalline semiconductor film, and the semiconductor element which has a semiconductor layer formed from the said 2nd crystalline semiconductor film.

  According to this configuration, the optical sensor has the semiconductor layer formed from the first crystalline semiconductor film, and the semiconductor element has the semiconductor layer formed from the second crystalline semiconductor film. In the optical sensor, it is possible to suppress the off-leak current in the dark and increase the on / off ratio without reducing the mobility.

  Further, in a semiconductor device manufactured by a method of manufacturing a semiconductor element substrate including a heating promotion layer forming step, an optical sensor having a semiconductor layer formed from the first crystalline semiconductor film, and the second crystalline semiconductor film It is preferable that the heating promotion layer has a light-shielding property.

  According to this configuration, in the optical sensor, it is possible to suppress the off-leak current in the dark and increase the on / off ratio without reducing the carrier mobility of the semiconductor element. Since it functions as a light-shielding film of the optical sensor by having the light-shielding property, it is not necessary to provide the light-shielding film of the optical sensor separately from the heating acceleration layer, and the manufacturing efficiency is increased.

  In addition, a display device according to the present invention includes the semiconductor element substrate according to the present invention.

  The semiconductor element substrate according to the present invention is also effective in a display device.

  The display device having the above structure includes a first TFT having a semiconductor layer formed from the first crystalline semiconductor film, and a second TFT having a semiconductor layer formed from the second crystalline semiconductor film. The semiconductor layer preferably has a relatively small channel region, and the semiconductor layer of the second TFT preferably has a relatively large channel region.

  According to this configuration, variations in electrical characteristics in the first TFT having a relatively small channel region and a decrease in carrier mobility in the second TFT having a relatively large channel region are suppressed. Therefore, the first TFT and the second TFT are suppressed. Is applied to a display device in accordance with the required electrical characteristics, whereby desired electrical characteristics can be obtained for each TFT of the display device that requires different electrical characteristics.

  And it has a display area constituted by a plurality of pixels, the first TFT is provided for each pixel, and the second TFT constitutes a peripheral circuit provided outside the display area. Is preferred.

  According to this configuration, variations in threshold voltage between the TFTs of the pixel are suppressed, and a decrease in carrier mobility in the TFTs of the peripheral circuit is suppressed. As a result, desired electrical characteristics can be obtained for the TFTs of the pixels that require different electrical characteristics and the TFTs of the peripheral circuits, so that a display device capable of stable display with little variation in luminance and color can be realized. It becomes possible.

  Further, it is preferable that the optical sensor includes a photosensor having a semiconductor layer formed from the first crystalline semiconductor film and a TFT having a semiconductor layer formed from the second crystalline semiconductor film.

  According to this configuration, since the optical sensor has a semiconductor layer formed from the first crystalline semiconductor film and the TFT has a semiconductor layer formed from the second crystalline semiconductor film, the carrier mobility of the TFT In the optical sensor, the on / off ratio can be increased by suppressing the off-leakage current in the dark without reducing the above.

  According to the present invention, the first amorphous semiconductor film having a different average grain size from each other by solid-phase growth of the remaining amorphous semiconductor film after melting and solidifying a part of the amorphous semiconductor film and The first crystalline semiconductor film and the second crystalline semiconductor film are formed by respectively forming the second crystalline semiconductor film and melting and solidifying the first crystalline semiconductor film and the second crystalline semiconductor film to recrystallize them. The crystallinity of the second crystalline semiconductor film, particularly the crystallinity of the second crystalline semiconductor film crystallized by solid phase growth, is improved, so that the average grain sizes of the crystal grains are different from each other on the same substrate, and each has excellent carrier mobility. A first crystalline semiconductor film and a second crystalline semiconductor film can be formed. The first crystalline semiconductor film and the second crystalline semiconductor film can be used to obtain desired electrical characteristics for each semiconductor element that requires different electrical characteristics. For example, in a full monolithic type liquid crystal display device, a TFT of each pixel is formed using a first crystalline semiconductor film, and a TFT of a peripheral circuit is formed using a second crystalline semiconductor film, respectively. It is possible to suppress variations in threshold voltage between them and a decrease in carrier mobility in the TFTs in the peripheral circuit. Further, by forming a photosensor such as a photodiode using the first crystalline semiconductor film, the on / off ratio of the photosensor can be increased while suppressing a decrease in carrier mobility in the TFT of the peripheral circuit. As a result, high performance and high image quality of the display device can be realized.

It is a top view which shows a liquid crystal display device roughly. It is a figure which shows schematically the II-II cross section of FIG. It is sectional drawing which shows schematically the TFT of the pixel in an active matrix substrate, and the TFT of a peripheral circuit. 6 is a cross-sectional view showing a state in which a molybdenum film is formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. FIG. 3 is a cross-sectional view showing a state where a heating promotion layer is formed in the method for manufacturing the active matrix substrate of Embodiment 1. 6 is a cross-sectional view showing a state in which a gate insulating film and an amorphous silicon film are formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. FIG. 6 is a plan view showing a state where an amorphous silicon film is irradiated with a laser beam in the manufacturing method of the active matrix substrate of Embodiments 1 and 2. 6 is a cross-sectional view showing a state in which a first crystalline silicon film is formed in the method for manufacturing an active matrix substrate of Embodiment 1. FIG. 4 is a cross-sectional view showing a state in which a catalytic element is added to a silicon film in the method for manufacturing an active matrix substrate of Embodiment 1. FIG. 6 is a cross-sectional view showing a state in which a second crystalline silicon film is formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. FIG. 5 is a plan view showing a state in which a laser beam is irradiated to a first crystalline silicon film and a second crystalline silicon film in the method for manufacturing an active matrix substrate of Embodiments 1 and 2. FIG. 3 is a plan view showing the shapes of a first crystalline silicon layer and a second crystalline silicon layer in the method for manufacturing an active matrix substrate of Embodiment 1. FIG. 3 is a cross-sectional view showing a state in which a first crystalline silicon layer and a second crystalline silicon layer are formed in the manufacturing method of the active matrix substrate of Embodiment 1. 5 is a cross-sectional view showing a state in which a gate insulating film is formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. 5 is a cross-sectional view showing a state in which an aluminum film is formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. 6 is a cross-sectional view showing a state in which a gate electrode is formed in the method for manufacturing the active matrix substrate of Embodiment 1. FIG. FIG. 3 is a cross-sectional view showing a state in which a source region and a drain region are formed in a first crystalline silicon film and a second crystalline silicon film in the manufacturing method of the active matrix substrate of Embodiment 1. 6 is a cross-sectional view showing a state in which contact holes are formed in an interlayer insulating film in the method for manufacturing an active matrix substrate of Embodiment 1. FIG. It is sectional drawing which shows a photodiode roughly. 10 is a cross-sectional view showing a state in which a base coat film and an amorphous silicon film are formed in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 10 is a cross-sectional view showing a state in which a first crystalline silicon film is formed in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 6 is a cross-sectional view showing a state in which nickel is added to a silicon film in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 10 is a cross-sectional view showing a state in which a first crystalline silicon layer constituting a photodiode is formed in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 10 is a cross-sectional view showing a state in which a gate insulating film is formed in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 6 is a cross-sectional view showing a state where an n-type impurity is implanted into a first crystalline silicon film in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 10 is a cross-sectional view showing a state where a p-type impurity is implanted into a first crystalline silicon film in the method for manufacturing an active matrix substrate of Embodiment 2. FIG. 10 is a cross-sectional view showing a state in which an intrinsic semiconductor region, an n-type semiconductor region, and a p-type semiconductor region are formed in a first crystalline silicon film in the method for manufacturing an active matrix substrate of Embodiment 2. 6 is a cross-sectional view showing a state in which contact holes are formed in an interlayer insulating film in the method for manufacturing an active matrix substrate of Embodiment 2. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 18 show Embodiment 1 of a semiconductor element substrate manufacturing method, a semiconductor element substrate, and a display device according to the present invention.

  FIG. 1 is a plan view schematically showing the liquid crystal display device 1. FIG. 2 is a sectional view schematically showing the liquid crystal display device 1 along the line II-II in FIG. FIG. 3 is a cross-sectional view schematically showing the TFTs 20A and 20B of the active matrix substrate 10 constituting the liquid crystal display device 1. As shown in FIG. 4 to 18 are views for explaining a method of manufacturing the active matrix substrate 10 of the present embodiment, as will be described later. In FIG. 3, the left side of the drawing shows the pixel TFT 20A, and the right side of the drawing shows the peripheral circuit TFT 20B. In FIG. 1, the polarizing plate 36 is not shown, and in FIG. 2, the driving circuit 21 is not shown.

  The semiconductor element substrate of this embodiment is used as an active matrix substrate that constitutes a liquid crystal display device.

<Liquid crystal display device>
The liquid crystal display device 1 is a full monolithic display device in which peripheral circuits such as drive circuits 21 and 22 are formed on the same substrate together with a plurality of pixels constituting the display region D as shown in FIG. 2, the active matrix substrate 10 which is a semiconductor element substrate, a counter substrate 30 disposed to face the active matrix substrate 10, and a liquid crystal layer provided between the active matrix substrate 10 and the counter substrate 30. 31 and a sealing material 32 provided so as to adhere the active matrix substrate 10 and the counter substrate 30 and to enclose the liquid crystal layer 31.

  The active matrix substrate 10 and the counter substrate 30 are formed, for example, in a rectangular shape, provided with alignment films 33 and 34 on the surface on the liquid crystal layer 31 side, and a polarizing plate 35 on the surface opposite to the liquid crystal layer 31. , 36 are provided. The liquid crystal layer 31 is made of a nematic liquid crystal material having electro-optical characteristics. For example, the sealing material 32 is formed in a rectangular frame shape so as to extend along each side of the counter substrate 30.

  Further, in the liquid crystal display device 1, a display region D in which an image display is performed is defined in a region where the active matrix substrate 10 and the counter substrate 30 overlap each other and inside the sealing material 32. Here, the display area D is configured by arranging a plurality of pixels, which are the minimum unit of an image, in a matrix. Further, in the liquid crystal display device 1, around the display region D, the frame region F on the four sides where the sealing material 32 is disposed, and one side of the active matrix substrate 10 (the lower side in FIG. 1) An exposed terminal region T is defined. A flexible printed circuit board (hereinafter referred to as FPC) 37 is connected to the terminal area T so that a signal for image display or the like is input from the external circuit to the display device 1 through the FPC 37. It is configured.

<Active matrix substrate>
Although not shown in the display region D, the active matrix substrate 10 includes a plurality of gate wirings provided in parallel to each other on a substrate having an insulating surface such as a glass substrate or a plastic substrate, An interlayer insulating film provided so as to cover the gate wiring, and a plurality of source wirings provided on the interlayer insulating film so as to extend in parallel to each other in a direction intersecting each gate wiring. Here, the gate wiring and the source wiring are provided in a lattice shape as a whole so as to partition each pixel. A plurality of pixel electrodes are provided in a matrix between the lattices of the gate wiring and the source wiring.

  The active matrix substrate 10 is provided with a TFT (hereinafter referred to as a pixel TFT) 20A which is a first TFT shown on the left side in FIG. 3 connected to the pixel electrode for each pixel. Further, as shown in FIG. 1, the active matrix substrate 10 includes peripheral circuits such as a gate drive circuit 21 in the right frame region F and a source drive circuit 22 in the lower frame region F in the figure as a monolithic circuit. Are provided, and a TFT (hereinafter referred to as a peripheral circuit TFT) 20B which is the second TFT shown on the right side in FIG.

  The pixel TFT 20A and the peripheral circuit TFT 20B are n-channel TFTs and are formed on the substrate 11 via a base coat film 13 provided for the purpose of preventing impurity diffusion, as shown in FIG. Further, as shown on the left side in FIG. 3, each pixel is provided with a heating promotion layer 12 between the substrate 11 and the base coat film 13 so as to include a region where the pixel TFT 20A is provided.

<Pixel TFT>
The pixel TFT 20A is an island-shaped first crystalline silicon layer 14A provided on the base coat film 13 and having a channel region 14c, a source region 14s, and a drain region 14d, and a gate insulating film 15 on the first crystalline silicon layer 14A. A gate electrode 16a provided via the gate electrode 16a, an interlayer insulating film 17 provided so as to cover the gate electrode 16a, and lead electrodes 19s and 19d drawn from the source region 14s and the drain region 14d on the interlayer insulating film 17, respectively. And.

  The first crystalline silicon layer 14A includes a channel region 14c that overlaps the gate electrode 16a, and a source region 14s and a drain region 14d that are provided on both sides of the channel region 14c. The first crystalline silicon layer 14A is made of polycrystalline silicon. An n-type impurity element such as phosphorus (P) is ion-implanted into the source region 14s and the drain region 14d. An LDD (Lightly Doped Drain) region into which an impurity element is ion-implanted at a low concentration may be formed between each of the source region 14s and the drain region 14d and the channel region 14c.

  The gate electrode 16a is connected to the gate wiring. Contact holes 18 reaching the source region 14s and the drain region 14d are formed in the gate insulating film 15 and the interlayer insulating film 17, respectively, and the lead electrodes 19s and 19d are connected to the source region 14s and the drain through the contact holes 18, respectively. Each is connected to the region 14d. The extraction electrode 19s on the source region 14s side is connected to the source wiring, while the extraction electrode 19d on the drain region 14d side is connected to the pixel electrode.

  The channel region 14c of the pixel TFT 20A is formed in a relatively small rectangular shape having a length of about 4 μm and a width of about 4 μm, for example. The average grain size of the crystal grains in the first crystalline silicon layer 14A is, for example, about 0.1 μm or more and 1.0 μm or less.

<Peripheral circuit TFT>
The peripheral circuit TFT 20B is configured in the same manner as the pixel TFT 20A, and has an island-shaped second crystalline silicon layer 14B having a channel region 14c, a source region 14s, and a drain region 14d provided on the base coat film 13, and the channel region 14c. Through a gate electrode 16b provided through a gate insulating film 15, an interlayer insulating film 17 provided so as to cover the gate electrode 16b, and a contact hole 18 formed in the gate insulating film 15 and the interlayer insulating film 17. In addition, lead electrodes 19 s and 19 d led out from the source region 14 s and the drain region 14 d onto the interlayer insulating film 17 are provided.

  The channel region 14c of the peripheral circuit TFT 20B is formed in a relatively large rectangular shape having a length of about 20 μm and a width of about 20 μm, for example. The crystalline silicon layer 14B is made of polycrystalline silicon having a relatively large average grain size such as CG silicon, and the average grain size of the crystal grains is, for example, 3.0 μm or more.

  Thus, the pixel TFT 20A and the peripheral circuit TFT 20B have the same structure except that the size of the channel region 14c and the average grain size of the crystal grains in the crystalline silicon layers 14A and 14B are different from each other. . In these pixel TFT 20A and peripheral circuit TFT 20B, electrons injected into the extraction electrode 19s on the source region 14s side are transferred to the drain region 14d through the channel region 14c, and current flows to the extraction electrode 19d on the drain region 14d side. Flowing.

  Although the case where the pixel TFT 20A and the peripheral circuit TFT 20B are n-channel TFTs has been described here, a p-channel TFT in which a p-type impurity element such as boron (B) is ion-implanted into the source region 14s and the drain region 14d. In that case, a current flows using holes as carriers.

<Counter substrate>
Although not shown, the counter substrate 30 is provided on a substrate having an insulating surface such as a glass substrate or a plastic substrate, and a black matrix provided in a lattice shape so as to correspond to the gate wiring and the source wiring, and the black matrix. A plurality of color filters including, for example, a red layer, a green layer, and a blue layer, which are provided so as to be periodically arranged between matrix lattices, and a common electrode provided so as to cover the black matrix and each color filter And a photo spacer provided in a columnar shape on the common electrode.

<Operation of liquid crystal display device>
In the liquid crystal display device 1 configured as described above, in each pixel, when the gate signal is sent from the gate drive circuit 21 to the gate electrode 16a through the gate wiring and the pixel TFT 20A is turned on, the source drive circuit 22 A source signal is sent to the extraction electrode 19s on the source region 14s side via the source wiring, and a predetermined charge is written to the pixel electrode via the extraction electrode 19d on the first crystalline silicon layer 14A and drain region 14d side. At this time, a potential difference is generated between each pixel electrode of the active matrix substrate 10 and the common electrode of the counter substrate 30, and a desired voltage is applied to the liquid crystal layer 31. In the liquid crystal display device 1, by changing the alignment state of the liquid crystal molecules for each pixel according to the magnitude of the voltage applied to the liquid crystal layer 31, a desired image is displayed by adjusting the light transmittance of the liquid crystal layer 31. The

-Manufacturing method-
Next, a method for manufacturing the active matrix substrate 10 and the liquid crystal display device 1 will be described.

  In order to manufacture the liquid crystal display device 1, first, the active matrix substrate 10 and the counter substrate 30 are respectively manufactured, and alignment films 33 and 34 are formed on both the substrates 10 and 30, respectively. Next, the active matrix substrate 10 and the counter substrate 30 are bonded to each other via a sealing material 32, and the liquid crystal layer 31 is sealed between the active matrix substrate 10 and the counter substrate 30 by the sealing material 32. Then, after polarizing plates 35 and 36 are attached to the active matrix substrate 10 and the counter substrate 30, respectively, the FPC 37 is connected. The manufacturing method according to the present invention is particularly characterized by the manufacturing method of the active matrix substrate 10, and will be described in detail below with reference to FIGS. 4 to 18 are views for explaining a method of manufacturing the active matrix substrate 10 and show a cross section of a portion where the pixel TFT 20A and the peripheral circuit TFT 20B are formed so as to correspond to FIG.

  It should be noted that the manufacturing of the active matrix substrate 10 such as the manufacturing of the counter substrate 30, the formation of the alignment films 33 and 34, the bonding of the active matrix substrate 10 and the counter substrate 30, the bonding of the polarizing plates 35 and 36, and the connection of the FPC 37. Since other methods can be performed using a known method, description thereof is omitted.

  The manufacturing method of the active matrix substrate 10 of the present embodiment includes a heating acceleration layer forming step, an amorphous film forming step, a first crystallization step, a second crystallization step, and a recrystallization step. included.

  First, a method for forming a crystalline semiconductor film for forming the pixel TFT 20A and the peripheral circuit TFT 20B will be described.

<Heating acceleration layer forming step>
As shown in FIG. 4, a molybdenum film 23 is formed by sputtering, for example, on a substrate 11 having an insulating surface such as a glass substrate or a plastic substrate. Subsequently, the molybdenum film 23 is patterned by photolithography to form a heating promotion layer 12 that reflects the laser beam so as to include a region for forming the pixel TFT 20A as shown in FIG. Instead of the molybdenum film 23, the heating promotion layer 12 may be formed from a tungsten film that absorbs a laser beam.

  Here, if the heating promotion layer 12 is formed so that the film thickness becomes smaller than 50 nm, when the amorphous silicon film is irradiated with a laser beam in the first crystallization process to be performed later, The reflection of the laser beam becomes insufficient, and there is a possibility that only the heating promotion layer 12 and its vicinity in the amorphous silicon film cannot be selectively melted and solidified. On the other hand, if the heating promotion layer 12 is formed so that the film thickness is larger than 500 nm, the step between the region where the heating promotion layer 12 is provided and the region where the heating promotion layer 12 is not provided becomes relatively large. Therefore, the stepped electrodes 19s and 19d to be formed later are easily cut off due to the step. For this reason, it is preferable to form the heating promotion layer 12 with a thickness of 50 nm or more and 500 nm or less. Further, it is more preferable that the lead electrodes 19s and 19d are formed to a thickness of 300 nm or less from the viewpoint of satisfactorily suppressing disconnection of the extraction electrodes 19s and 19d.

  Next, as shown in FIG. 6, a silicon dioxide film is formed on the substrate on which the heating acceleration layer 12 has been formed by a CVD (Chemical Vapor Deposition) method using TEOS (Tetra EthOxy Silane) as a source gas. Further, the base coat film 13 is formed to a thickness of about 100 nm, for example. In addition to the silicon dioxide film, a silicon nitride film, a silicon oxynitride film, or the like may be formed as the base coat film 13, or a laminate of these films may be formed.

<Amorphous film formation process>
On the substrate on which the base coat film 13 is formed, an amorphous silicon film 24 having a thickness of, for example, about 50 nm is formed as an amorphous semiconductor film by LPCVD (Low Pressure CVD) using SiH ₄ as a source gas. Film.

<First crystallization step>
As shown in FIG. 7, a pulsed laser beam having a linear beam shape on the surface of the amorphous silicon film 24 is formed on the amorphous silicon film 24 formed in the amorphous film forming process. 25 is irradiated while step-scanning in the width direction of the laser beam 25 (in the direction indicated by the arrow in the figure), so that the amorphous silicon film 24 is on the heating promotion layer 12 and in the vicinity of the heating promotion layer 12. Is melted and solidified to crystallize.

  The laser beam 25 preferably has an aspect ratio of 2 or more, more preferably 10 or more and 10,000 or less. If the laser beam is shaped in such a straight line, it is possible to ensure an energy density sufficient to anneal the amorphous silicon film 24 sufficiently. By irradiating the amorphous silicon film 24 while step-scanning such a linear laser beam 25 in the width direction, the amorphous silicon film 24 can be efficiently and simply crystallized. is there.

  Further, the laser beam 25 is preferably a laser beam under a condition for crystallizing only the amorphous silicon film 24 on the heating promotion layer 12 and in the vicinity of the heating promotion layer 12. The laser beam is preferably. Therefore, as the laser beam 25, for example, a second harmonic of a YAG laser is used. Since the second harmonic of the YAG laser has a wavelength of 532 nm, it is easily absorbed by the silicon film. When the amorphous silicon film 24 is irradiated with the second harmonic, the crystallization can be performed more efficiently. Also, the YAG laser beam is a solid-state laser beam, and its laser oscillator has a simple structure, so no maintenance is required over a long period of time. As a result, the operating time is long and the running cost is low. It is possible to

  By performing this first crystallization step, as shown in FIG. 8, the amorphous silicon film 24 on and around the heating promotion layer 12 is crystallized to form a first crystalline semiconductor film. A first crystalline silicon film 24A is formed. On the other hand, other regions in the amorphous silicon film 24 remain unchanged as the amorphous silicon film 24.

<Second crystallization step>
As shown in FIG. 9, the entire surface of the silicon film 24C including the first crystalline silicon film 24A formed in the first crystallization process is promoted to crystallize the amorphous silicon film 24 as shown in FIG. Nickel (Ni) 26 is added as a catalyst element by vapor deposition. In FIG. 9, the nickel 26 is shown in the form of a film, but actually the nickel 26 is scattered in a granular form on the surface of the silicon film 24C.

  In addition to nickel 26, catalyst elements include iron (Fe), cobalt (Co), germanium (Ge), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium ( Ir), platinum (Pt), copper (Cu), gold (Au), and the like. In this second crystallization step, instead of nickel 26, at least one element of these metals is replaced with the silicon film 24C. It is preferable to add to the above, and a compound of these metals or a simple metal and a metal compound may be added.

The surface concentration of nickel 26 can be measured by total reflection X-ray fluorescence analysis. Here, if nickel 26 is added so that the concentration on the surface of the amorphous silicon film 24 is less than 1 × 10 ¹⁰ atoms / cm ² , the crystallization of the amorphous silicon film 24 by the nickel 26 is promoted. Since the effect is relatively small, the time required to crystallize the amorphous silicon film 24 becomes long, and the efficiency of the manufacturing process decreases. On the other hand, when nickel 26 is added so that the concentration on the surface of the amorphous silicon film 24 exceeds 1 × 10 ¹² atoms / cm ² , the nickel 26 in the amorphous silicon film 24 is obtained when heat treatment described later is performed. Since the density of the crystal grains formed due to the nickel 26 becomes relatively high and the average grain diameter of the crystal grains becomes small, the carrier mobility of the crystalline silicon film formed thereby becomes high. It tends to be small. And when forming TFT using the crystalline silicon film | membrane, there exists a possibility that sufficient transistor characteristics may not be acquired. For this reason, the nickel 26 is preferably added so that the concentration on the surface of the amorphous silicon film 24 is 1 × 10 ¹⁰ atoms / cm ² or more and less than 1 × 10 ¹² atoms / cm ² .

  Next, the substrate in which nickel 26 is added to the silicon film 24C is carried into an electric furnace (heat treatment furnace), and the substrate (silicon film 24C) is heat-treated in the nitrogen atmosphere in the electric furnace. By this heat treatment, the nickel 26 on the surface of the amorphous silicon film 24 is diffused into the amorphous region, and the remaining amorphous silicon film not crystallized in the first crystallization process due to the diffused nickel 26. In 24, relatively large crystal grains are grown in solid phase.

  Here, if the amorphous silicon film 24 is heat-treated at a temperature lower than 500 ° C., the solid phase growth rate of the amorphous silicon film 24 becomes relatively slow. On the other hand, when the amorphous silicon film 24 is heat-treated at a temperature exceeding 700 ° C., in addition to the crystal grains that are solid-phase grown due to the nickel 26, a relatively small grain size of, for example, 0.2 μm or less that does not originate from the nickel 26. Therefore, when a TFT is formed using the crystalline silicon film thus formed, there is a possibility that sufficient transistor characteristics cannot be obtained. Therefore, it is preferable to heat treat the amorphous silicon film 24 at a temperature of 500 ° C. or higher and 700 ° C. or lower.

  By performing this second crystallization step, the remaining amorphous silicon film 24 that has not been crystallized in the first crystallization step is solid-phase grown, and as shown in FIG. 10, the first crystalline silicon film 24A A second crystalline silicon film 24B having an average grain size larger than that is formed. At this time, the average grain size of the first crystalline silicon film 24A is not affected and does not change.

<Recrystallization process>
For the first crystalline silicon film 24A and the second crystalline silicon film 24B, as shown in FIG. 11, a pulse oscillation laser beam in which the beam shape on the surface of each of the crystalline silicon films 24A and 24B is linear. 27 is irradiated while performing step scanning in the width direction of the laser beam 27 (direction indicated by an arrow in the figure). Thus, the first crystalline silicon film 24A and the first crystalline silicon film 24A and the first crystalline silicon film 24A are maintained while maintaining the average grain size of the first crystalline silicon film 24A smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. The two crystalline silicon films 24B are melted and solidified, and the respective crystalline silicon films 24A and 24B are recrystallized. Thus, the crystalline silicon films 24A and 24B can be efficiently and simply crystallized by irradiating the crystalline silicon films 24A and 24B while step-scanning the linear laser beam 27 in the width direction. Is possible.

  The laser beam 27 reliably maintains the state in which the average grain size of the crystal grains in the first crystalline silicon film 24A is smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. From the viewpoint of recrystallizing the film 24A and the second crystalline silicon film 24B, it is preferable that the laser beam has a condition for partially melting the first crystalline silicon film 24A and the second crystalline silicon film 24B. A laser beam having a wavelength of 126 nm or more and less than 370 nm is preferable. Therefore, as the laser beam 27, for example, a XeCl excimer laser beam having a wavelength of 308 nm is used.

  By performing this recrystallization step, melting proceeds from the surface of the first crystalline silicon film 24A and the second crystalline silicon film 24B, but the first crystal in a region of about several nm from the interface with the base coat film 13 is obtained. The crystalline silicon film 24A and the second crystalline silicon film 24B are not melted. Then, the first crystalline silicon film 24A and the second crystalline silicon film 24B are partially melted and solidified and recrystallized, whereby crystal grains in the first crystalline silicon film 24A and the second crystalline silicon film 24B are obtained. The crystallinity of each of the crystalline silicon films 24A and 24B is improved without changing the average particle diameter of the film.

  As described above, the first crystalline silicon film 24 </ b> A and the second crystalline silicon film 24 </ b> B having different average grain sizes and excellent carrier mobility can be formed on the same substrate 11. it can. Next, a method for forming the pixel TFT 20A and the peripheral circuit TFT 20B using the first crystalline silicon film 24A and the second crystalline silicon film 24B will be described.

  The first crystalline silicon film 24A and the second crystalline silicon film 24B are patterned by photolithography to form regions that become the channel region 14c, the source region 14s, and the drain region 14d, respectively, as shown in FIGS. The first crystalline silicon layer 14A ′ is formed from the first crystalline silicon film 24A, and the second crystalline silicon layer 14B ′ is formed from the second crystalline silicon film 24B. Here, the first crystalline silicon layer 14A ′ and the second crystalline silicon layer 14B ′ have the same outer shape as shown in FIG. 12, and are formed so that only the size of the region to be the channel region 14c is different. To do.

  Next, the first crystalline silicon layer is formed on the substrate on which the first crystalline silicon layer 14A ′ and the second crystalline silicon layer 14B ′ are formed by an APCVD (Atmospheric Pressure CVD) method using TEOS or the like as a source gas. By forming an oxide film such as a silicon dioxide film so as to cover 14A ′ and the second crystalline silicon layer 14B ′, as shown in FIG. 14, the gate insulating film 15 is formed to have a thickness of about 100 nm, for example. Examples of the gate insulating film 15 include a silicon nitride film and a silicon oxynitride film in addition to the silicon dioxide film, and a laminate of these films may be used.

  Subsequently, as shown in FIG. 15, an aluminum film 28 having a thickness of about 300 nm is formed on the substrate on which the gate insulating film 15 has been formed by sputtering, and then the aluminum film 28 is formed by photolithography. By patterning, gate electrodes 16a and 16b are formed as shown in FIG. At this time, a gate wiring is also formed from the aluminum film 28 at the same time. The gate electrodes 16a and 16b are made of a film of a refractory metal material such as tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti) instead of aluminum, or these refractory metal materials. It may be formed from a film of nitride or the like, or may be formed from a laminate in which these films are stacked.

  Further, as shown in FIG. 17, after the n-type impurity element such as phosphorus is ion-implanted into the first crystalline silicon layer 14A ′ and the second crystalline silicon layer 14B ′ using the gate electrodes 16a and 16b as a mask, By performing activation annealing in an electric furnace, in the first crystalline silicon layer 14A ′ and the second crystalline silicon layer 14B ′, a source region 14s, a drain region 14d, and a gate are formed in a region where the gate electrodes 16a and 16b do not overlap. Channel regions 14c are formed in regions where the electrodes 16a and 16b overlap. Here, the arrow in FIG. 17 indicates the direction in which phosphorus is injected. In this way, the first crystalline silicon layer 14A and the second crystalline silicon layer 14B are formed.

  Next, a silicon nitride film or the like is formed on the substrate in which the channel region 14c, the source region 14s, and the drain region 14d are formed in the crystalline silicon layers 14A and 14B by the APCVD method so as to cover the gate electrodes 16a and 16b. By forming the film, the interlayer insulating film 17 is formed to a thickness of about 500 nm, for example. Then, the interlayer insulating film 17 and the gate insulating film 15 are patterned by photolithography, and as shown in FIG. 18, contact holes 18 penetrating the interlayer insulating film 17 and the gate insulating film 15 over the source region 14s and the drain region 14d. Respectively.

  Further, after a titanium film, an aluminum film, and a titanium film are sequentially formed on the substrate having the contact hole 18 formed in the interlayer insulating film 17 and the gate insulating film 15 by a sputtering method, a metal laminate is formed. Extraction electrodes 19s and 19d are formed by patterning the metal laminate. Thus, ohmic contact is realized between the extraction electrodes 19s and 19d and the source region 14s and the drain region 14d through the contact hole 18. In this way, the pixel TFT 20A and the peripheral circuit TFT 20B shown in FIG. 3 are formed. At this time, a source wiring is simultaneously formed from the metal laminate. The lead electrodes 19s and 19d may be formed of a single metal film such as tungsten, titanium, and aluminum, for example, instead of the laminated body of the titanium film, the aluminum film, and the titanium film. You may form from metal laminated bodies other than the laminated body of a titanium film.

  Thereafter, a transparent conductive film such as an ITO (Indium Tin Oxide) film is formed on the substrate on which the extraction electrodes 19s and 19d are formed by sputtering, and the transparent conductive film is patterned by photolithography to form a pixel. An electrode is formed.

  The active matrix substrate 10 can be manufactured as described above.

-Example-
According to the manufacturing method of the present embodiment, the first crystalline silicon film 24A and the second crystalline silicon film 24B are formed under the following conditions, and the pixel TFT 20A and the second crystalline silicon are formed using the first crystalline silicon film 24A. 50 pieces of peripheral circuit TFTs 20B were produced using the film 24B. The pixel TFT 20A manufactured in this embodiment has a rectangular shape with a channel region 14c of 4 μm in length and 4 μm in width, and the peripheral circuit TFT 20B has a rectangular shape with a channel region 14c of 20 μm in length and 20 μm in width.

<Production method>
In the heating promotion layer forming step, the heating promotion layer 12 was formed on the glass substrate 11 to a thickness of about 150 nm. As the base coat film 13, a silicon dioxide film was formed to a thickness of 100 nm. Further, in the amorphous film forming step, the amorphous silicon film 24 was formed with a thickness of 50 nm.

  Next, in the first crystallization step, the pulsed YAG laser beam 25 is shaped so that the beam shape on the surface of the amorphous silicon film 24 becomes a rectangular linear shape having a length of 100 mm and a width of about 45 μm. The amorphous silicon film 24 was irradiated with the second harmonic of the YAG laser while performing step scanning so that the laser beam 25 was moved with a width of 2 μm for each pulse oscillation shot. At this time, the energy applied to the laser oscillator that outputs the second harmonic of the pulsed YAG laser was set to 30 W. As a result, the amorphous silicon film 24 in the region of 500 nm on and around the heating promoting layer 12 was melted, solidified and crystallized to form the first crystalline silicon film 24A.

Subsequently, in the second crystallization step, according to the total reflection X-ray fluorescence analysis, the concentration of the region from the surface of the silicon film 24C to a depth of about several nm (5 nm to 10 nm) is 5 × 10 ¹⁰ atoms / cm ^2. Nickel 26 was added to the silicon film 24C as a catalytic element so as to reach a degree. And the board | substrate was heat-processed over 1 hour at 600 degreeC in nitrogen atmosphere with the electric furnace.

Next, in the recrystallization step, pulse oscillation is performed so that the beam shape on the surface of the first crystalline silicon film 24A and the second crystalline silicon film 24B becomes a rectangular linear shape having a length of about 125 mm and a width of about 0.4 mm. The XeCl excimer laser beam 27 was shaped, and the first crystalline silicon film 24A and the second crystalline silicon film 24B were irradiated while step scanning so that the laser beam 27 was moved with a width of 20 μm for each pulse oscillation shot. . At this time, the output of the XeCl excimer laser beam 27 was set so that the energy density applied to the surfaces of the first crystalline silicon film 24A and the second crystalline silicon film 24B was 350 mJ / cm ² . As a result, the melting progressed from the surfaces of the first crystalline silicon film 24A and the second crystalline silicon film 24B, but the first crystalline silicon film 24A and the second crystalline material in the region of 5 nm from the interface with the base coat film 13 were obtained. The silicon film 24B was not melted.

  Then, the gate insulating film 15 was formed to a thickness of 100 nm, and the gate electrodes 16a and 16b were formed from an aluminum film to a thickness of 300 nm. Further, the source region 14s and the drain region 14d of the first crystalline silicon layer 14A and the second crystalline silicon layer 14B were formed by ion implantation of phosphorus. Further, the interlayer insulating film 17 is formed to a thickness of 500 nm, and the extraction electrodes 19 s and 19 d are formed from a metal laminated film in which a titanium film is laminated from the lower layer to a thickness of 100 nm, an aluminum film is laminated to a thickness of 300 nm, and a titanium film is laminated to a thickness of 100 nm. .

<Evaluation>
For the silicon film immediately after each of the first crystallization step, the second crystallization step, and the recrystallization step, the average grain size of the crystal grains was measured by the EBSP method. The average grain size of the crystal grains in the first crystalline silicon film 24A after the first crystallization step was about 0.3 μm. After the second crystallization step, the average grain size of the crystal grains in the second crystalline silicon film 24B is about 4.0 μm, and the average grain size of the crystal grains in the first crystalline silicon film 24A is about 0.3 μm. It did not change. Even after the recrystallization step, the average grain size of the crystal grains in the first crystalline silicon film 24A is about 0.3 μm, and the average grain size of the crystal grains in the second crystalline silicon film 24B is about 4. It was 0 μm.

Further, the obtained pixel TFT 20A and peripheral circuit TFT 20B were subjected to IV measurement using a TFT electrical characteristic measuring instrument, and the carrier mobility and the threshold voltage variation were measured. Regarding the pixel TFT 20A, the carrier mobility was 180 cm ² / V · s, and the dispersion of 50 threshold voltages was relatively small, 0.05V. On the other hand, for the peripheral circuit TFT 20B, the carrier mobility was 370 cm ² / V · s, and the variation of 50 threshold voltages was relatively large at 0.15 V.

  From the above, the first crystalline silicon film having a different average grain size from each other is obtained by solid-phase growth of the remaining amorphous silicon film 24 after melting and solidifying a part of the amorphous silicon film 24. 24A and the second crystalline silicon film 24B can be formed, and further, the first crystalline silicon film 24A and the second crystalline silicon film 24B are recrystallized by melting and solidifying, whereby the first crystalline silicon film 24A The crystallinity of the first crystalline silicon film 24A and the second crystalline silicon film 24B is improved while maintaining the average grain size of the crystal grains smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. You can see that

  Then, by forming the pixel TFT 20A using the first crystalline silicon film 24A and the peripheral circuit TFT 20B using the second crystalline silicon film 24B, variation in threshold voltage between the pixel TFTs 20A can be reduced and the pixel TFT 20A can be reduced. It can be seen that excellent carrier mobility can be obtained for both the peripheral circuit TFT 20B, and in particular, high carrier mobility can be obtained for the peripheral circuit TFT 20B.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, the amorphous silicon film 24 is formed on the substrate 11 in the amorphous film forming step, and the first crystalline silicon in the amorphous silicon film 24 is formed in the first crystallization step. After the first crystalline silicon film 24A is formed by melting and solidifying the region where the layer 14A is to be formed, the remaining amorphous silicon film 24 is solid-phase grown in the second crystallization step. A second crystalline silicon film 24B having an average grain size larger than that of one crystalline silicon film 24A is formed. As a result, the first crystalline silicon film 24A and the second crystalline silicon film 24B having different average grain sizes can be formed. Furthermore, in the recrystallization step, the first crystalline silicon film 24A is maintained in a state where the average grain size of the crystal grains is smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. By melting and solidifying the silicon film 24A and the second crystalline silicon film 24B, the first crystalline silicon film 24A and the second crystalline silicon film 24B are recrystallized. Thereby, the crystallinity of the first crystalline silicon film 24A and the second crystalline silicon film 24B can be improved, and the carrier mobility can be increased. In particular, crystallinity of the second crystalline silicon film 24B is improved by reducing crystal defects in the second crystalline silicon film 24B crystallized by solid phase growth, and carrier mobility can be increased. Therefore, on the same substrate 11, the first crystalline silicon film 24A and the second crystalline silicon film 24B, which have different average grain sizes and have excellent carrier mobility, can be formed.

  Since the pixel TFT 20A is formed using the first crystalline silicon film 24A and the peripheral circuit TFT 20B is formed using the second crystalline silicon film 24B, variation in threshold voltage between the pixel TFTs 20A can be suppressed, and the peripheral circuit TFT 20B can be suppressed. It is possible to suppress a decrease in carrier mobility. As a result, desired electrical characteristics can be obtained for the pixel TFT 20A and the peripheral circuit TFT 20B that require different electrical characteristics, and therefore, a display device 1 that can display stably with little variation in luminance and color can be realized. Can do.

<< Embodiment 2 of the Invention >>
19 to 28 show a second embodiment of the semiconductor element substrate and the manufacturing method thereof according to the present invention. In the following embodiments, the same portions as those in FIGS. 1 to 18 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 19 is a cross-sectional view schematically showing the photodiode 20C. 20 to 28 are views for explaining a method of manufacturing the active matrix substrate 10 of the present embodiment, as will be described later.

  The semiconductor element substrate of this embodiment is also used as an active matrix substrate constituting a liquid crystal display device. The active matrix substrate 10 is provided with a photodiode 20C shown in FIG. 19 as an optical sensor functioning as a touch sensor for each pixel or a predetermined number of pixel groups. Other configurations of the active matrix substrate 10 of the present embodiment are the same as those of the active matrix substrate 10 of the first embodiment.

  As shown in FIG. 19, the photodiode 20C has a PIN structure, and is formed on the base coat film 13 so as to overlap the heating acceleration layer 12 together with the pixel TFT 20A. The heating promotion layer 12 has a light shielding property and functions as a light shielding film of the photodiode 20C. As a result, in the method of manufacturing the active matrix substrate 10 to be described later, it is not necessary to provide the light shielding film of the photodiode 20C separately from the heating promotion layer 12, and the manufacturing efficiency is improved.

  The photodiode 20C includes an island-shaped first crystalline silicon layer 14C having an intrinsic semiconductor region 14i, an n-type semiconductor region 14n, and a p-type semiconductor region 14p provided on the base coat film 13, and a first crystalline silicon layer. A gate insulating film 15 and an interlayer insulating film 17 provided so as to cover 14C; and extraction electrodes 19n and 19p respectively extracted from the n-type semiconductor region 14n and the p-type semiconductor region 14p on the interlayer insulating film 17. Yes.

  The first crystalline silicon layer 14C includes an intrinsic semiconductor region 14i provided at the center, and an n-type semiconductor region 14n and a p-type semiconductor region 14p provided on both sides of the intrinsic semiconductor region 14i. The first crystalline silicon layer 14C is also made of polycrystalline silicon such as CG silicon similar to the first crystalline silicon layer 14A of the pixel TFT 20A. An n-type impurity element such as phosphorus is ion-implanted in the n-type semiconductor region 14n, while a p-type impurity element such as boron is ion-implanted in the p-type semiconductor region 14p.

  Contact holes 18 reaching the n-type semiconductor region 14n and the p-type semiconductor region 14p are formed in the gate insulating film 15 and the interlayer insulating film 17, and the lead electrodes 19n and 19p are connected to the contact holes 18 through the contact holes 18, respectively. The n-type semiconductor region 14n and the p-type semiconductor region 14p are connected to each other.

  The intrinsic semiconductor region 14i of the photodiode 20C is formed in a rectangular shape having a length of about 5 μm and a width of about 10 μm, for example. The average grain size of the crystal grains in the first crystalline silicon layer 14C is, for example, about 0.1 μm or more and 1.0 μm or less.

-Manufacturing method-
Next, a method for manufacturing the active matrix substrate 10 having the above configuration will be described with reference to FIGS. 20 to 28 are views for explaining the manufacturing method of the active matrix substrate 10 of the present embodiment, and show a cross section of a portion where the photodiode 20C is formed so as to correspond to FIG.

  The manufacturing method of the active matrix substrate 10 of the present embodiment also includes a heating promotion layer forming step, an amorphous film forming step, a first crystallization step, a second crystallization step, and a recrystallization step. It is out.

  First, a method for forming a crystalline semiconductor film for forming the photodiode 20C, the pixel TFT 20A, and the peripheral circuit TFT 20B will be described.

<Heating acceleration layer forming step>
As in the first embodiment, a molybdenum film 23 is formed to a thickness of, for example, about 150 nm on a substrate 11 having an insulating surface such as a glass substrate or a plastic substrate by sputtering, and then the molybdenum film 23 is formed. Patterning is performed by photolithography to form the heating promotion layer 12 in a region where the photodiode 20C is to be formed, as shown in FIG. At this time, the heating promotion layer 12 is also formed in the region where the pixel TFT 20A is formed. Note that the heating promotion layer 12 may be formed of a tungsten film instead of the molybdenum film 23.

  Next, a base coat film 13 is formed to a thickness of about 100 nm, for example, by forming a silicon dioxide film on the substrate on which the heating promotion layer 12 is formed by a CVD method using TEOS as a source gas. In addition to the silicon dioxide film, a silicon nitride film, a silicon oxynitride film, or the like may be formed as the base coat film 13, or a laminate of these films may be formed.

<Amorphous film formation process>
As in the first embodiment, an amorphous silicon film 24 is formed as an amorphous semiconductor film on the substrate on which the base coat film 13 is formed by LPCVD (Low Pressure CVD) using SiH ₄ as a source gas. For example, the film is formed with a thickness of about 50 nm.

<First crystallization step>
For the amorphous silicon film 24 formed in the amorphous film forming step, as shown in FIG. 7, a continuous oscillation laser beam whose beam shape on the surface of the amorphous silicon film 24 is linear. By irradiating 25 while scanning the laser beam 25 in the width direction, the amorphous silicon film 24 is melted, solidified and crystallized on the heating promotion layer 12 and in the vicinity of the heating promotion layer 12. Here, the laser beam 25 preferably has an aspect ratio of not less than 10 and not more than 10,000 from the viewpoint of securing an energy density sufficient to anneal the amorphous silicon film 24 sufficiently. As the laser beam 25, for example, from the viewpoint of efficiently crystallizing the amorphous silicon film 24, extending the operating time of the laser oscillator, and reducing the running cost, the second harmonic of a YAG laser, for example, is used. Use.

  Here, if the scanning speed of the laser beam 25 is lower than 5 cm / s, the amorphous silicon film 24 is evaporated by receiving excessive energy, and the amorphous silicon film 24 may not be crystallized well. is there. On the other hand, if the scanning speed of the laser beam 25 is faster than 3 m / s, the scanning speed of the laser beam 25 is too high, and there is a possibility that the amorphous silicon film 24 cannot be reliably melted and solidified. For this reason, the scanning speed of the laser beam 25 is preferably 5 cm / s or more and 3 m / s or less.

  By performing this first crystallization step, as shown in FIG. 21, the amorphous silicon film on and around the heating promotion layer 12 is crystallized to form the first crystal as the first crystalline semiconductor film. A porous silicon film 24A is formed. On the other hand, other regions in the amorphous silicon film 24 remain unchanged as the amorphous silicon film 24.

<Second crystallization step>
As in the first embodiment, the entire surface of the silicon film 24C including the first crystalline silicon film 24A formed in the first crystallization step is coated with nickel 26 as a catalytic element by a resistance heating method as shown in FIG. Is deposited and added. FIG. 22 also shows the nickel 26 in a film shape, but actually the nickel 26 is scattered in a granular form on the surface of the silicon film 24C. At this time, the nickel 26 effectively promotes the crystallization of the remaining amorphous silicon film 24 to efficiently perform the manufacturing process, and lowers the density of the formed crystal grains to reduce the average grain size. From the viewpoint of surely increasing the carrier mobility of the second crystalline silicon film 24B by increasing the diameter, the concentration on the surface of the amorphous silicon film 24 is 1 × 10 ¹⁰ atoms / cm ² or more and 1 × 10 ^12. It is preferable to add so as to be less than atoms / cm ² .

  Next, the substrate in which nickel 26 is added to the silicon film 24 </ b> C is heat-treated in a nitrogen atmosphere in an electric furnace to diffuse the nickel 26 in the amorphous silicon film 24, and the first is caused by the diffused nickel 26. The remaining amorphous silicon film 24 that has not been crystallized in the crystallization step is solid-phase grown to form a second crystalline silicon film 24B having larger crystal grains than the first crystalline silicon film 24A. The heat treatment at this time increases the solid-phase growth rate of the amorphous silicon film 24 satisfactorily and suppresses the growth of crystal grains that are not caused by the catalytic element 26, thereby causing the carrier mobility of the second crystalline silicon film 24B. From the viewpoint of reliably increasing the temperature, it is preferable to carry out at a temperature of 500 ° C. or higher and 700 ° C. or lower.

  By performing this second crystallization step, the remaining amorphous silicon film 24 that was not crystallized in the first crystallization step is solid-phase grown, and the average grain size of the crystal grains is larger than that of the first crystalline silicon film 24A. The second crystalline silicon film 24B having a large thickness is formed. At this time, the average grain size of the first crystalline silicon film 24A is not affected and does not change.

<Recrystallization process>
As in the first embodiment, the first crystalline silicon film 24A and the second crystalline silicon film 24B have linear beam shapes on the surfaces of the crystalline silicon films 24A and 24B as shown in FIG. The pulsed laser beam 27 is irradiated while step-scanning in the width direction of the laser beam 27. Thus, the first crystalline silicon film 24A and the first crystalline silicon film 24A and the first crystalline silicon film 24A are maintained while maintaining the average grain size of the first crystalline silicon film 24A smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. The two crystalline silicon films 24B are melted and solidified, and the respective crystalline silicon films 24A and 24B are recrystallized. As the laser beam 27, for example, an XeCl excimer laser beam having a wavelength of 308 nm is used from the viewpoint of partially melting the first crystalline silicon film 24A and the second crystalline silicon film 24B.

  By performing this recrystallization step, melting proceeds from the surface of the first crystalline silicon film 24A and the second crystalline silicon film 24B, but the first crystal in a region of about several nm from the interface with the base coat film 13 is obtained. The crystalline silicon film 24A and the second crystalline silicon film 24B are not melted. Then, the first crystalline silicon film 24A and the second crystalline silicon film 24B are partially melted and solidified and recrystallized, whereby crystal grains in the first crystalline silicon film 24A and the second crystalline silicon film 24B are obtained. The crystallinity of each of the crystalline silicon films 24A and 24B is improved without changing the average particle diameter of the film.

  As described above, the first crystalline silicon film 24 </ b> A and the second crystalline silicon film 24 </ b> B having different average grain sizes and excellent carrier mobility can be formed on the same substrate 11. it can. Next, a method for forming the photodiode 20C, the pixel TFT 20A, and the peripheral circuit TFT 20B using the first crystalline silicon film 24A and the second crystalline silicon film 24B will be described.

  The first crystalline silicon film 24A is patterned by photolithography, and as shown in FIG. 23, the first crystalline silicon layer has a region that becomes an intrinsic semiconductor region 14i, an n-type semiconductor region 14n, and a p-type semiconductor region 14p. 14C ′ is formed. At this time, the first crystalline silicon layer 14A 'of the pixel TFT 20A is formed from the first crystalline silicon film 24A, and the second crystalline silicon layer 14B' of the peripheral circuit TFT 20B is simultaneously formed from the second crystalline silicon film 24B.

  Next, the first crystalline silicon layer 14A ′ is formed on the substrate on which the first crystalline silicon layers 14A ′ and 14C ′ and the second crystalline silicon layer 14B ′ are formed by APCVD using TEOS or the like as a source gas. , 14C ′ and the second crystalline silicon layer 14B ′, a silicon dioxide film or the like is formed to form a gate insulating film 15 of about 100 nm, for example, as shown in FIG. Examples of the gate insulating film 15 include a silicon nitride film and a silicon oxynitride film in addition to the silicon dioxide film, and a laminate of these films may be used.

  Subsequently, although illustration is omitted, after an aluminum film 28 is formed to a thickness of, for example, about 300 nm on the substrate on which the gate insulating film 15 is formed by sputtering, the aluminum film 28 is patterned by photolithography. Thus, gate electrodes 16a and 16b are formed. At this time, a gate wiring is also formed from the aluminum film 28 at the same time. The gate electrodes 16a and 16b may be formed of a high melting point metal material such as tungsten, molybdenum, tantalum, and titanium, or a film of a nitride of these high melting point metal materials, instead of aluminum. You may form from the laminated body on which the film | membrane was laminated | stacked.

  Next, as shown in FIG. 25, the first crystalline silicon layer 14C ′ for forming the photodiode 20C has an opening in a region that becomes the n-type semiconductor region 14n, and a resist layer that covers the other regions. After forming 40, phosphorus is ion-implanted into a region to be the n-type semiconductor region 14n of the first crystalline silicon layer 14C ′ using the resist layer 40 as a mask. The arrows in FIG. 25 indicate the direction in which phosphorus is injected. At this time, the first crystalline silicon layer 14A ′ for forming the pixel TFT 20A and the second crystalline silicon layer 14B ′ for forming the peripheral circuit TFT 20B are also opened in the regions serving as the source region 14s and the drain region 14d. By forming the resist layer 40 so as to have phosphorous, phosphorus is ion-implanted also into each of the first crystalline silicon layer 14A ′ and the second crystalline silicon layer 14B ′ that will become the source region 14s and the drain region 14d. The Thereafter, the resist layer 40 is removed by ashing or the like.

  Further, as shown in FIG. 26, after forming a resist layer 41 so as to cover the other region with an opening in a region to be the p-type semiconductor region 14p of the first crystalline silicon layer 14C ′, the resist layer 41 is used as a mask and boron is ion-implanted into a region to be the p-type semiconductor region 14p of the first crystalline silicon layer 14C ′. The arrows in FIG. 26 indicate the direction in which boron is implanted. Thereafter, the resist layer 41 is removed by ashing or the like.

  Then, by performing activation annealing on the first crystalline silicon layer 14C ′ into which phosphorus and boron are implanted, as shown in FIG. 27, the intrinsic crystalline region 14i and the n-type semiconductor are formed on the first crystalline silicon layer 14C ′. Region 14n and p-type semiconductor region 14p are formed. Thus, the first crystalline silicon layer 14C of the photodiode 20C is formed. At this time, activation annealing of the first crystalline silicon layer 14A ′ for forming the pixel TFT 20A and the second crystalline silicon layer 14B ′ for forming the peripheral circuit TFT 20B is also performed, and the first crystalline silicon layer 14A By simultaneously forming the source region 14s and the drain region 14d in 'and the second crystalline silicon layer 14B', the first crystalline silicon layer 14A of the pixel TFT 20A and the second crystalline silicon layer 14B of the peripheral circuit TFT 20B are formed. The

  Next, the gate electrodes 16a and 16b (not shown) are covered by the APCVD method on the substrate in which the intrinsic semiconductor region 14i, the n-type semiconductor region 14n, and the p-type semiconductor region 14p are formed on the first crystalline silicon layer 14C. An interlayer insulating film 17 is formed to a thickness of, for example, about 500 nm by forming a silicon nitride film or the like.

  Subsequently, the interlayer insulating film 17 and the gate insulating film 15 are patterned by photolithography, and as shown in FIG. 28, the interlayer insulating film 17 and the gate insulating film 15 are formed on the n-type semiconductor region 14n and the p-type semiconductor region 14p. The contact holes 18 penetrating through are formed respectively. At this time, the contact holes 18 penetrating on the source region 14s and the drain region 14d of the first crystalline silicon layer 14A for forming the pixel TFT 20A and the second crystalline silicon layer 14B for forming the peripheral circuit TFT 20B are also simultaneously formed. An interlayer insulating film 17 and a gate insulating film 15 are formed.

  Further, after a titanium film, an aluminum film, and a titanium film are sequentially formed on the substrate having the contact hole 18 formed in the gate insulating film 15 and the interlayer insulating film 17 by sputtering, a metal laminate is formed. Extraction electrodes 19n and 19p are formed by patterning the metal laminate. Thus, ohmic contact is realized between the extraction electrodes 19n and 19p and the n-type semiconductor region 14n and the p-type semiconductor region 14p through the contact hole 18. In this way, the photodiode 20C having the PIN structure shown in FIG. 19 is formed. At this time, the source region 14s and the drain region 14d of the first crystalline silicon layer 14A for forming the pixel TFT 20A and the second crystalline silicon layer 14B for forming the peripheral circuit TFT 20B are connected via the contact holes 18. By simultaneously forming the extraction electrodes 19s and 19d, the pixel TFT 20A and the peripheral circuit TFT 20B are formed. A source wiring is also formed simultaneously from the metal laminate. The lead electrodes 19n and 19p may be formed of a single metal film such as tungsten, titanium, and aluminum, for example, instead of the titanium film, aluminum film, and titanium film stack. You may form from metal laminated bodies other than the laminated body of a titanium film.

  Thereafter, as in the first embodiment, a transparent conductive film such as an ITO film is formed by sputtering on the substrate on which the extraction electrodes 19n, 19p, 19s, and 19d are formed. A pixel electrode is formed by patterning by lithography.

  The active matrix substrate 10 can be manufactured as described above.

-Example-
In accordance with the manufacturing method of the present embodiment, the first crystalline silicon film 24A and the second crystalline silicon film 24B were formed under the following conditions, and the photodiode 20C was fabricated using the first crystalline silicon film 24A. Further, a photodiode and a peripheral circuit TFT 20B as a comparative example were manufactured using the second crystalline silicon film 24B. The photodiode 20C manufactured in this embodiment has a rectangular shape in which the intrinsic semiconductor region 14i is 5 μm long and 10 μm wide, and the peripheral circuit TFT 20B has a rectangular shape in which the channel region 14c is 20 μm long and 20 μm wide.

<Production method>
In the heating promotion layer forming step, the heating promotion layer 12 was formed on the glass substrate 11 to a thickness of about 150 nm. As the base coat film 13, a silicon dioxide film was formed to a thickness of 100 nm. Further, in the amorphous film forming step, the amorphous silicon film 24 was formed with a thickness of 50 nm.

  Next, in the first crystallization step, the continuous wave YAG laser beam 25 is shaped so that the beam shape on the surface of the amorphous silicon film 24 becomes a rectangular linear shape having a length of about 2 mm and a width of about 50 μm. The amorphous silicon film 24 was irradiated with the second harmonic of the YAG laser while scanning the laser beam 25 at a speed of 20 cm / s. Here, the energy applied to the laser oscillator that outputs the second harmonic of the continuous wave YAG laser was set to 1.2 W. As a result, the amorphous silicon film 24 in the region of 500 nm on and around the heating promoting layer 12 was melted, solidified and crystallized to form the first crystalline silicon film 24A.

Subsequently, in the second crystallization step, according to the total reflection fluorescent X-ray analysis, the concentration of the region from the surface of the silicon film 24C to a depth of about several nm (5 nm to 10 nm) is about 5 × 10 ¹⁰ atoms / cm ^2. As a catalyst element, nickel 26 was added to the silicon film 24C. And the board | substrate was heat-processed over 1 hour at 600 degreeC in nitrogen atmosphere with the electric furnace.

Next, in the recrystallization step, pulse oscillation is performed so that the beam shape on the surface of the first crystalline silicon film 24A and the second crystalline silicon film 24B becomes a rectangular linear shape having a length of about 215 mm and a width of about 0.4 mm. The XeCl excimer laser beam 27 was shaped, and the first crystalline silicon film 24A and the second crystalline silicon film 24B were irradiated while step scanning so that the laser beam 27 was moved with a width of 20 μm for each pulse oscillation shot. . At this time, the output of the XeCl excimer laser beam 27 was set so that the energy density applied to the surfaces of the first crystalline silicon film 24A and the second crystalline silicon film 24B was 350 mJ / cm ² . As a result, the melting progressed from the surfaces of the first crystalline silicon film 24A and the second crystalline silicon film 24B, but the first crystalline silicon film 24A and the second crystalline material in the region of 5 nm from the interface with the base coat film 13 were obtained. The silicon film 24B was not melted.

  Then, the n-type semiconductor region 14n of the first crystalline silicon layer 14C was formed by ion implantation of phosphorus, and the p-type semiconductor region 14p was formed by ion implantation of boron. Further, the interlayer insulating film 17 is formed to a thickness of 500 nm, and the extraction electrodes 19n and 19p are formed from a metal laminated film in which a titanium film is laminated from the lower layer to a thickness of 100 nm, an aluminum film is laminated to a thickness of 300 nm, and a titanium film is laminated to a thickness of 100 nm. .

<Evaluation>
For the silicon film immediately after each of the first crystallization step, the second crystallization step, and the recrystallization step, the average grain size of the crystal grains was measured by the EBSP method. The average grain size of the crystal grains in the first crystalline silicon film 24A after the first crystallization step was about 0.3 μm. After the second crystallization step, the average grain size of the crystal grains in the second crystalline silicon film 24B is about 4.0 μm, and the average grain size of the crystal grains in the first crystalline silicon film 24A is about 0.3 μm. It did not change. Even after the recrystallization step, the average grain size of the crystal grains in the first crystalline silicon film 24A is about 0.3 μm, and the average grain size of the crystal grains in the second crystalline silicon film 24B is about 4. It was 0 μm.

Furthermore, when the photodiode 20C of the obtained example and the photodiode of the comparative example were compared by measuring the ratio (on / off ratio) between the on-current in the light and the off-current in the dark, respectively. A large ON / OFF ratio of 5.4 times that of the photodiode of the comparative example was measured for the photodiode 20C. The carrier mobility of the peripheral circuit TFT 20B formed from the second crystalline silicon film was measured and found to be relatively high at 350 cm ² / V · s.

  From the above, the first crystalline silicon film having a different average grain size from each other is obtained by solid-phase growth of the remaining amorphous silicon film 24 after melting and solidifying a part of the amorphous silicon film 24. 24A and the second crystalline silicon film 24B can be formed, and further, the first crystalline silicon film 24A and the second crystalline silicon film 24B are melted and solidified and recrystallized, whereby the crystal in the first crystalline silicon film 24A is obtained. The crystallinity of the first crystalline silicon film 24A and the second crystalline silicon film 24B is improved while maintaining the state in which the average grain size is smaller than the average grain size of the crystal grains in the second crystalline silicon film 24B. I can see that

  Further, the photodiode 20C is formed using the first crystalline silicon film 24A, and the peripheral circuit TFT 20B is formed using the second crystalline silicon film 24B, thereby obtaining high carrier mobility in the peripheral circuit TFT 20B. It can be seen that the ON / OFF ratio of 20C can be increased.

-Effect of Embodiment 2-
Therefore, also according to the second embodiment, the first crystalline silicon film 24A and the first crystalline silicon film 24A having different average grain sizes are obtained by performing the amorphous film forming step, the first crystallization step, and the second crystallization step. A second crystalline silicon film 24B can be formed. Further, by performing the recrystallization step, the crystallinity of the first crystalline silicon film 24A and the second crystalline silicon film 24B, particularly the crystallinity of the second crystalline silicon film 24B is improved, and the carrier mobility is increased. be able to. Therefore, on the same substrate 11, the first crystalline silicon film 24A and the second crystalline silicon film 24B, which have different average grain sizes and have excellent carrier mobility, can be formed.

  As in the first embodiment, the threshold voltage varies between the pixel TFTs 20A formed using the first crystalline silicon film 24A and the carrier movement in the peripheral circuit TFT 20B formed using the second crystalline silicon film 24B. Degradation can be suppressed. As a result, desired electrical characteristics can be obtained for the pixel TFT 20A and the peripheral circuit TFT 20B that require different electrical characteristics, so that a display device that can display stably with little variation in luminance and color can be realized. it can.

  Furthermore, since the photodiode 20C is formed using the first crystalline silicon film 24A, the off-leakage current in the dark can be suppressed in the photodiode 20C while suppressing the decrease in the carrier mobility of the peripheral circuit TFT 20B. The off ratio can be increased.

  In each of the above embodiments, the liquid crystal display device 1 including the active matrix substrate 10 has been described as an example. However, the present invention is not limited to this and is applicable to other display devices such as an organic electroluminescence display device. can do. In addition to a display device, a semiconductor element substrate provided with a plurality of semiconductor elements that require different electrical characteristics on the same substrate and any device including the semiconductor element substrate can be applied.

  As described above, the present invention is useful for a method of manufacturing a semiconductor element substrate, a semiconductor element substrate, and a display device. In particular, each semiconductor element that requires different electrical characteristics on the same substrate has desired electrical characteristics. It is suitable for a semiconductor element substrate manufacturing method, a semiconductor element substrate, and a display device that are desired to be obtained.

D Display area 1 Liquid crystal display device (display device)
DESCRIPTION OF SYMBOLS 10 Active matrix substrate 11 Substrate 12 Heating promotion layer 14A 1st crystalline silicon layer (semiconductor layer)
14B Second crystalline silicon layer (semiconductor layer)
14C First crystalline silicon layer (semiconductor layer)
14c Channel region 20A Pixel TFT (first thin film transistor)
20B peripheral circuit TFT (second thin film transistor)
20C photodiode (light sensor)
21 Gate drive circuit (peripheral circuit)
22 Source drive circuit (peripheral circuit)
24 Amorphous silicon film (amorphous semiconductor film)
24A First crystalline silicon film (first crystalline semiconductor film)
24B Second crystalline silicon film (second crystalline semiconductor film)
25, 27 Laser beam 26 Nickel (catalytic element)

Claims (29)

A method of manufacturing a semiconductor element substrate comprising a semiconductor element on a substrate having an insulating surface,
An amorphous film forming step of forming an amorphous semiconductor film on the substrate;
A first crystallization step of forming a first crystalline semiconductor film by melting and solidifying a part of the amorphous semiconductor film;
The remaining amorphous semiconductor film that has not been crystallized in the first crystallization step is solid-phase grown to obtain a second crystalline semiconductor film having an average grain size larger than that of the first crystalline semiconductor film. A second crystallization step to be formed;
The first crystalline semiconductor film and the second crystalline semiconductor are maintained while maintaining an average grain size of the crystal grains in the first crystalline semiconductor film smaller than an average grain diameter of the crystal grains in the second crystalline semiconductor film. A method for manufacturing a semiconductor element substrate, comprising: a recrystallization step of recrystallizing the first crystalline semiconductor film and the second crystalline semiconductor film by melting and solidifying the film. In the manufacturing method of the semiconductor element substrate according to claim 1,
The method of manufacturing a semiconductor element substrate, wherein the amorphous semiconductor film is an amorphous silicon film. In the manufacturing method of the semiconductor element substrate according to claim 1,
Prior to the amorphous film forming step, a laser beam is reflected or absorbed in a region where the first crystalline semiconductor film is to be formed to promote heating of the first crystalline semiconductor film. It further includes a heating acceleration layer forming step of forming a heating acceleration layer,
In the first crystallization step, a part of the amorphous semiconductor film is melted and solidified by laser beam irradiation. In the manufacturing method of the semiconductor element substrate according to claim 3,
In the first crystallization step, the amorphous semiconductor film is irradiated with a laser beam under a condition that only the amorphous semiconductor film is crystallized on and in the vicinity of the heating promotion layer. A method for manufacturing a semiconductor element substrate. In the manufacturing method of the semiconductor element substrate according to claim 3 or 4,
The amorphous semiconductor film is an amorphous silicon film,
In the first crystallization step, the amorphous semiconductor film is irradiated with a laser beam having a wavelength of 370 nm or more and 650 nm or less. In the manufacturing method of the semiconductor element substrate according to any one of claims 3 to 5,
In the first crystallization step, the amorphous semiconductor film is irradiated with a pulsed or continuous oscillation solid-state laser beam. In the manufacturing method of the semiconductor element substrate according to claim 6,
In the first crystallization step, the amorphous semiconductor film is irradiated with a second harmonic of an yttrium aluminum garnet laser. In the manufacturing method of the semiconductor element substrate according to any one of claims 3 to 5,
In the first crystallization step, the amorphous semiconductor film is irradiated with a pulsed laser beam having a linear beam shape on the surface of the amorphous semiconductor film while performing step scanning in the width direction of the laser beam. A method of manufacturing a semiconductor element substrate. In the manufacturing method of the semiconductor element substrate according to any one of claims 3 to 5,
In the first crystallization step, the amorphous semiconductor film is irradiated with a continuous wave laser beam while scanning the surface of the amorphous semiconductor film at a speed of 5 cm / s or more and 3 m / s or less. A method for manufacturing a semiconductor element substrate. In the manufacturing method of the semiconductor element substrate according to any one of claims 3 to 9,
In the heating promotion layer forming step, the heating promotion layer is formed so that the film thickness is not less than 50 nm and not more than 500 nm. In the manufacturing method of the semiconductor element substrate according to any one of claims 3 to 10,
The method of manufacturing a semiconductor element substrate, wherein the heating promotion layer contains at least one element of molybdenum and tungsten. In the manufacturing method of the semiconductor element substrate according to any one of claims 1 to 11,
In the second crystallization step, a catalyst element that promotes crystallization of the amorphous semiconductor film is added to the remaining amorphous semiconductor film, and then the remaining amorphous semiconductor film is imparted with crystallization energy. A method of manufacturing a semiconductor device substrate, wherein solid phase growth is selectively performed by the method. In the manufacturing method of the semiconductor element substrate according to claim 12,
In the second crystallization step, the catalyst element is added so that the concentration on the surface of the amorphous semiconductor film is 1 × 10 ¹⁰ atoms / cm ² or more and 1 × 10 ¹² atoms / cm ² or less. A method of manufacturing a semiconductor element substrate. In the manufacturing method of the semiconductor element substrate according to claim 12 or 13,
The catalytic element includes at least one element selected from the group consisting of iron, cobalt, nickel, germanium, ruthenium, rhodium, palladium, osmium, iridium, platinum, copper and gold. Manufacturing method. In the manufacturing method of the semiconductor element substrate according to any one of claims 1 to 14,
In the second crystallization process, the remaining amorphous semiconductor film is solid-phase grown by heat-treating the amorphous semiconductor film in a heat treatment furnace. In the manufacturing method of the semiconductor element substrate according to claim 15,
In the second crystallization step, the amorphous semiconductor film is heat-treated at a temperature of 500 ° C. or higher and 700 ° C. or lower. In the manufacturing method of the semiconductor element substrate according to claim 1,
In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are irradiated with a laser beam under a condition for partially melting the first crystalline semiconductor film and the second crystalline semiconductor film. A method of manufacturing a semiconductor element substrate, wherein the first crystalline semiconductor film and the second crystalline semiconductor film are partially melted and solidified. In the manufacturing method of the semiconductor element substrate according to claim 17,
The amorphous semiconductor film is an amorphous silicon film,
In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are irradiated with a laser beam having a wavelength of 126 nm or more and less than 370 nm. In the manufacturing method of the semiconductor element substrate according to claim 1,
The amorphous semiconductor film is an amorphous silicon film,
In the first crystallization step, the amorphous semiconductor film is irradiated with a laser beam having a wavelength of 370 nm or more and 650 nm or less,
In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are irradiated with a laser beam having a wavelength of 126 nm or more and less than 370 nm. In the manufacturing method of the semiconductor element substrate according to any one of claims 1 to 19,
In the recrystallization step, the first crystalline semiconductor film and the second crystalline semiconductor film are melted by irradiating the first crystalline semiconductor film and the second crystalline semiconductor film with a pulsed excimer laser beam. A method for producing a semiconductor element substrate, comprising solidifying. In the manufacturing method of the semiconductor element substrate according to any one of claims 1 to 20,
In the recrystallization step, the first crystalline semiconductor film and the first crystalline semiconductor film are formed while step-scanning a pulsed laser beam having a linear beam shape on the surface of the amorphous semiconductor film in the width direction of the laser beam. A method for manufacturing a semiconductor element substrate, comprising: irradiating a two crystalline semiconductor film to melt and solidify the first crystalline semiconductor film and the second crystalline semiconductor film. A semiconductor element substrate manufactured by the method for manufacturing a semiconductor element substrate according to claim 1. The semiconductor element substrate according to claim 22,
A first thin film transistor having a semiconductor layer formed from the first crystalline semiconductor film;
And a second thin film transistor having a semiconductor layer formed from the second crystalline semiconductor film. The semiconductor element substrate according to claim 22,
An optical sensor having a semiconductor layer formed from the first crystalline semiconductor film;
And a semiconductor element having a semiconductor layer formed from the second crystalline semiconductor film. A semiconductor element substrate manufactured by the method for manufacturing a semiconductor element substrate according to any one of claims 3 to 11,
An optical sensor having a semiconductor layer formed from the first crystalline semiconductor film;
A semiconductor element having a semiconductor layer formed from the second crystalline semiconductor film,
The semiconductor element substrate, wherein the heating promotion layer has a light shielding property. A display device comprising the semiconductor element substrate according to claim 22. The display device according to claim 26.
A first thin film transistor having a semiconductor layer formed from the first crystalline semiconductor film;
A second thin film transistor having a semiconductor layer formed from the second crystalline semiconductor film,
The semiconductor layer of the first thin film transistor has a relatively small channel region;
A display device, wherein the semiconductor layer of the second thin film transistor has a relatively large channel region. The display device according to claim 27.
A display area composed of a plurality of pixels;
The first thin film transistor is provided for each pixel,
The display device, wherein the second thin film transistor constitutes a peripheral circuit provided outside the display region. The display device according to claim 26.
An optical sensor having a semiconductor layer formed from the first crystalline semiconductor film;
A display device comprising: a thin film transistor having a semiconductor layer formed from the second crystalline semiconductor film.

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