JP2013161963A - Thin film transistor, manufacturing method of thin film transistor and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor having a channel structure compatible with a large ON-state current and a small OFF-state current.SOLUTION: A thin film transistor (100) includes: a substrate (10); a gate electrode (12); a gate insulating layer (13); a first silicon layer (16) formed over the gate insulating layer (13) in a central area in a length direction of the gate above the gate electrode (12); a pair of second silicon layers (15) formed in both sides of the first silicon layer (16) over the gate insulating layer (13) above both sides of the gate electrode (12) in the length direction of the gate; and a pair of source and drain electrodes (19). The first silicon layer (16) is thicker than the second silicon layers (15). The first silicon layer (16) is constituted of crystalline silicon. The second silicon layers (15) are constituted of crystalline silicon or amorphous silicon, average grain size thereof is smaller than that in the first silicon layer (16).

Description

  The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and a display device. More specifically, the present invention relates to a thin film transistor including a channel layer made of a semiconductor having high crystallinity and a semiconductor having low crystallinity, a method for manufacturing such a thin film transistor, and a display device including such a thin film transistor.

  In recent years, in order to produce a display with higher added value, a display using an organic EL (EL) device has been actively developed, and is currently put into practical use as a mobile small display device. .

  A TFT array in which a plurality of thin film transistor (TFT) elements are arranged in a matrix is used for an active matrix display device of an organic EL display. The conventional liquid crystal display is a voltage-driven pixel circuit, whereas the organic EL device is a current-driven device. For this reason, TFTs for driving organic EL devices are required to have higher drive current and smaller threshold voltage variations than TFTs used in conventional liquid crystal displays. Therefore, for driving the organic EL device, a thin film transistor using, for example, polycrystalline silicon or microcrystalline silicon in which the channel layer is crystalline silicon is used.

  The crystalline silicon in the channel part is generally formed by a method in which the amorphous silicon is irradiated with laser light to instantaneously raise the temperature to melt and recrystallize (Patent Document 1).

JP 2007-115786 A

  Crystalline silicon TFTs have advantageous features such as high reliability, mobility, drive current, and excellent light resistance compared to amorphous silicon TFTs. Due to the narrower band gap than amorphous silicon, the crystalline silicon TFT has a problem that the off-current increases.

  The present invention has been made to solve such problems, and has an object to provide a thin film transistor having a channel structure that achieves both a large on-current and a small off-current, a method for manufacturing the thin film transistor, and a display device. To do.

  In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and a gate of the gate electrode. A first silicon layer formed on the gate insulating layer above the central portion in the length direction of the gate electrode; and the first silicon layer on the gate insulating layer above both ends in the gate length direction of the gate electrode. A pair of second silicon layers formed on both sides of the layer, and a pair of source / drain electrodes formed above each of the second silicon layers along the upper surface of the second silicon layer, The first silicon layer is thicker than each of the second silicon layers, the first silicon layer is made of crystalline silicon, and each of the second silicon layers is formed on the first silicon layer. Included It is composed of a crystalline silicon or amorphous silicon having an average particle size smaller than the average grain size of crystal grains that.

  In the thin film transistor of the present invention, an electric field is applied to both the first silicon layer and the second silicon layer during the on operation, and the channel resistance is reduced, so that the on current increases. Further, during the off operation, the second silicon layer relaxes the electric field at the drain end, so that the off current is reduced. Therefore, the thin film transistor of the present invention can provide a thin film transistor that has both a large on-state current and a small off-state current.

FIG. 1 is a cross-sectional view showing a configuration of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit of the display device according to the embodiment of the present invention. FIG. 3A is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3B is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3C is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3D is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3E is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3F is a cross-sectional view for explaining the method for manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3G is a cross-sectional view for explaining the method of manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 3H is a cross-sectional view for explaining the method for manufacturing the thin film transistor array according to the embodiment of the present invention. FIG. 4 is a diagram for explaining a method of calculating the amplitude reflectance and the amplitude transmittance. FIG. 5 is a cross-sectional view of a model structure of a thin film semiconductor device according to an embodiment of the present invention. FIG. 6 shows an optical film thickness / laser suitable as the first silicon layer and the second silicon layer for the amorphous silicon layer processed in the fifth step when the crystalline silicon layer region is formed by the laser annealing method. It is a figure for demonstrating that the range of a wavelength exists. FIG. 7 shows a range of actual film thicknesses suitable for the amorphous silicon layer processed in the fifth step as the first silicon layer and the second silicon layer when the crystalline silicon layer region is formed by laser annealing. It is a figure for demonstrating that there exists. FIG. 8 is a diagram showing the relationship between the laser beam absorption rate of the amorphous silicon layer processed in the fifth step and the energy density of the laser beam. FIG. 9A is a surface SEM image of the first region after irradiation with a laser in a preferred range. FIG. 9B is a surface SEM image of the first region after irradiation with a laser outside the preferred range. FIG. 10A is a cross-sectional view of a model structure of a thin film semiconductor device according to an embodiment of the present invention in the second embodiment. FIG. 10B is a cross-sectional view of the model structure of the thin film semiconductor device according to the embodiment of the present invention in the second embodiment. FIG. 11 shows that when the crystalline silicon layer region is formed by laser annealing in the second embodiment, the amorphous silicon layer processed in the fifth step is used as a first silicon layer and a second silicon layer, respectively. It is a figure for demonstrating that the range of the suitable optical film thickness / laser wavelength exists. FIG. 12 shows an example of a display device using the thin film transistor of the present invention.

  In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and a gate of the gate electrode. A first silicon layer formed on the gate insulating layer above the central portion in the length direction of the gate electrode; and the first silicon layer on the gate insulating layer above both ends in the gate length direction of the gate electrode. A pair of second silicon layers formed on both sides of the layer, and a pair of source / drain electrodes formed above each of the second silicon layers along the upper surface of the second silicon layer, The first silicon layer is thicker than each of the second silicon layers, the first silicon layer is made of crystalline silicon, and each of the second silicon layers is formed on the first silicon layer. Included It is composed of a crystalline silicon or amorphous silicon having an average particle size smaller than the average grain size of crystal grains that.

  The thin film transistor according to the aspect of the invention may further include a channel protective layer formed on the first silicon layer and the second silicon layer.

  According to this aspect, during the on operation, an electric field is applied to both the first silicon layer and the second silicon layer, and the channel resistance is reduced, so that the on current is improved. Further, during the off operation, the second silicon layer relaxes the electric field at the drain end, and the current path (back channel) is formed by the convex shape that the first silicon layer is thick and the second silicon layer is thin. Since it becomes longer, the off-current is reduced. Therefore, the thin film transistor of the present invention can achieve both a large on-state current and a small off-state current.

  In one embodiment of the thin film transistor according to the present invention, a portion of the first silicon layer that is not in contact with the second silicon layer is made of crystalline silicon having a crystal grain size smaller than the first average grain size. It is desirable that

  If it is this aspect, it will play the role of the electric field relaxation layer which is a hot carrier suppression area | region, and has the reduction effect of an off-current.

  In the thin film transistor according to the aspect of the invention, it is preferable that the first silicon layer includes crystalline silicon having a particle diameter of 50 nm or more.

  According to this embodiment, the channel resistance is reduced, and the on-current is increased.

  In the aspect of the thin film transistor according to the present invention, it is preferable that the second silicon layer includes microcrystalline silicon having a particle diameter of 10 nm or less.

  If it is this aspect, an off-current can be reduced because the said 2nd silicon layer plays the role of an electric field relaxation layer.

  In the aspect of the thin film transistor according to the present invention, it is preferable that the second silicon layer includes amorphous silicon.

  According to this aspect, when the gate operation is turned off, the channel resistance of the second silicon layer is particularly increased, and further, the off-current can be reduced because it plays the role of an electric field relaxation layer.

  In one embodiment of the thin film transistor according to the present invention, the gate insulating layer preferably has silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride.

  According to this aspect, the gate insulating layer can be formed with a stacked structure of silicon oxide and silicon nitride, or silicon oxide and silicon nitride.

  According to another aspect of the method for manufacturing a thin film transistor according to the present invention, a first step of preparing a substrate, a second step of forming a gate electrode on the substrate, and a first step of forming a gate insulating layer on the gate electrode. 3 steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, and a first step of positioning the amorphous silicon layer on a central portion of the gate electrode in the length direction of the gate. A fifth step in which the thickness of the region is processed into a convex shape that is thicker than the thickness of the second region located on both ends of the gate electrode in the length direction of the gate; By irradiating laser light from above the amorphous silicon layer, a first silicon layer made of crystalline silicon is formed from the first region of the amorphous silicon layer, and the amorphous silicon layer From the second region of the A sixth step of forming a second silicon layer composed of crystalline silicon or amorphous silicon having an average grain size smaller than the average grain size of crystal grains contained in the silicon layer; and formed on the first silicon layer A seventh step of forming a channel protective layer; an eighth step of forming a contact layer only along the upper surface of the end portion of the channel protective layer, the side surface of the channel protective layer, and the upper surface of the second silicon layer; And a ninth step of forming a source electrode formed above one of the contact layers and a drain electrode formed above the other of the contact layers.

  According to this aspect, the channel layer on the gate insulating layer above the gate electrode has a convex shape, and the convex thick film portion (the first silicon layer) is a high crystalline silicon layer, for example, a polycrystalline silicon layer. In addition, the convex-shaped thin film portion (the second silicon layer) can form a structure of a low crystalline silicon layer or an amorphous silicon layer, and the effect is that when the gate voltage is on, the first An electric field is applied to both the silicon layer and the second silicon layer, and the channel resistance can be lowered to ensure the on-current. In addition, when the gate voltage is off, the channel resistance of the second silicon layer is particularly increased, and further, the second silicon layer serves as an electric field relaxation layer serving as a hot carrier suppression region. There is. For these reasons, the thin film transistor of the present invention can achieve both a large on-state current and a small off-state current.

  In the aspect of the method for manufacturing a thin film transistor according to the present invention, it is preferable that the amorphous silicon layer is laser-annealed in the sixth step.

  According to this aspect, by irradiating the amorphous silicon layer with a laser, the amorphous silicon layer is melted and recrystallized on the substrate with a low thermal load, and high-quality crystalline silicon can be obtained.

  In the aspect of the method for manufacturing a thin film transistor according to the present invention, it is desirable that in the sixth step, the amorphous silicon layer is irradiated with a green laser having a laser wavelength of 473 nm to 561 nm.

  According to this aspect, the amorphous silicon layer can be melted and recrystallized more stably.

  In the aspect of the method for manufacturing a thin film transistor according to the present invention, in the sixth step, the laser light is generated by a laser light source operating in a continuous oscillation mode or a pseudo laser oscillation mode, and the amorphous silicon layer is formed on the amorphous silicon layer. Irradiation is desirable.

  According to this aspect, the first silicon layer can be held in a molten state by irradiating the laser beam in the continuous oscillation mode or the pseudo continuous oscillation mode.

Moreover, in one mode of the method for manufacturing a thin film transistor according to the present invention, the absorption rate (%) of the laser beam of the amorphous silicon layer formed in the fourth step is X, and the thin film transistor formed in the fourth step When the absorption rate of the laser beam of the amorphous silicon layer is 23.2%, the relative value when the energy density of the laser beam necessary to crystallize the amorphous silicon layer is 1. X is Y and Y is
Y ≦ 1.2 (Formula 1)
Y ≧ 42.9X− ^1.19 (Formula 2)
It is desirable that the numerical value satisfy the range specified in.

  According to this aspect, the regions of the first silicon layer and the second silicon layer can be stably formed by laser light irradiation.

Further, in one aspect of the thin film transistor manufacturing method according to the present invention, the value obtained by dividing the film thickness of the amorphous silicon layer formed in the fifth step by the wavelength of the laser beam is X, and is formed in the third step. When the value obtained by dividing the optical film thickness of the gate insulating layer by the wavelength of the laser, which is a value obtained by adding the refractive index of the gate insulating layer to the film thickness of the gate insulating layer, is Y. The first region of the above satisfies (Equation 3) or (Equation 4), and the second region satisfies (Equation 5) or (Equation 6).
0.32 ≦ X ≦ 0.47 and 0.33 ≦ Y ≦ 0.39 (Formula 3)
0.41 ≦ X ≦ 0.59 and 0.51 ≦ Y ≦ 0.69 (Formula 4)
0.20 ≦ X ≦ 0.28 and 0.33 ≦ Y ≦ 0.39 (Formula 5)
0.20 ≦ X ≦ 0.28 and 0.51 ≦ Y ≦ 0.69 (Formula 6)
It is desirable.

  According to this aspect, since the absorption rate of the laser light of the amorphous silicon layer is 40% or more in the first region and less than 20% in the second region, In the laser annealing process, a first silicon layer having high crystallinity, for example, a polycrystalline silicon layer, and a second silicon layer having low crystallinity, for example, a microcrystalline silicon layer or an amorphous silicon layer are formed in a self-aligned manner. can do.

  In the aspect of the thin film transistor manufacturing method according to the present invention, in the fourth step, the second region of the amorphous silicon layer may be formed to have a constant thickness regardless of the presence or absence of the gate electrode. desirable.

  According to this aspect, since only the first silicon layer can generate a high crystallinity, for example, a polycrystalline silicon layer, thermal damage to the substrate due to laser annealing can be suppressed only in necessary portions.

  Further, in one aspect of the method of manufacturing a thin film transistor according to the present invention, in the eighth step, the amorphous silicon layer is formed through the channel protective layer in which the pair of source / drain electrodes are formed in the seventh step. Preferably, it is formed on the second region.

  According to this aspect, it is possible to avoid problems with the electrode due to the protrusions in the first region, which is a highly crystalline silicon layer.

  One embodiment of the display device according to the present invention includes a display panel and the above-described thin film transistor, and the thin film transistor is a display device that drives the display panel.

  According to this aspect, since a large ON current and a small OFF current can be compatible in the thin film transistor, a high-quality display device can be realized.

(First embodiment)
Hereinafter, a thin film transistor manufacturing method, a thin film transistor, and a display device according to an embodiment of the present invention will be described with reference to the drawings. The present invention is specified based on the description of the scope of claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the claims are not necessarily required to achieve the object of the present invention, but are described as constituting more preferable embodiments. . Each figure is a schematic diagram and is not necessarily shown strictly.

  FIG. 1 is an example of a cross-sectional view illustrating a configuration of a thin film transistor 100 according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit of a pixel portion of the display device according to the embodiment of the present invention. The thin film transistor 100 shown in the cross-sectional view of FIG. 1 is used, for example, in the drive transistor in FIG.

  As shown in FIG. 1, a thin film transistor 100 according to this embodiment is a bottom-gate thin film transistor element. The thin film transistor 100 includes a substrate 10, an undercoat layer 11, a gate electrode 12, a gate insulating layer 13, a high crystalline first silicon layer 16, a pair of low crystalline second silicon layers 15, and a pair of contact layers 18. A pair of source / drain electrodes 19 is provided.

  The substrate 10 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass.

The undercoat layer 11 is formed on the substrate 10. The undercoat layer 11 includes a silicon nitride film (SiN _x ), a silicon oxide film (SiO _y ), a silicon oxynitride film (SiO _y N _x ), and the like. The undercoat layer 11 has a function of preventing impurities such as sodium and phosphorus contained in the substrate 10 from entering the second silicon layer and the first silicon layer 16. The undercoat layer 11 also has a function of reducing the influence of heat on the substrate 10 in a high-temperature heat treatment process such as a laser annealing method. The film thickness of the undercoat layer is preferably set to 300 to 500 nm.

  The gate electrode 12 is patterned in a predetermined shape on the undercoat layer 11. The gate electrode 12 can have a single layer structure or a multilayer structure such as a conductive material and an alloy thereof, for example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti) ), Chromium (Cr), molybdenum tungsten (MoW), or the like. The film thickness of the gate electrode is preferably set to 50 to 300 nm.

  The gate insulating layer 13 is formed so as to cover the gate electrode 12. The gate insulating layer can be composed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, an aluminum oxide film, and a laminated film thereof. The film thickness of the gate insulating layer 13 can be designed according to demands such as the breakdown voltage of the TFT, and is preferably 50 to 500 nm, for example. In the present embodiment, for example, a stacked film of a silicon oxide film and a silicon nitride film is used for the gate insulating layer 13.

  The first silicon layer 16 and the second silicon layer 15 are formed in a region on the gate insulating layer 13 corresponding to the gate electrode 12. The first silicon layer 16 is made of crystalline silicon such as polycrystalline silicon, and the second silicon layer 15 is made of microcrystalline or amorphous silicon. As will be described later, the first silicon layer 16 and the second silicon layer 15 are amorphous silicon layers (not shown in FIG. 1) that are precursors of the first silicon layer 16 and the second silicon layer 15. The amorphous silicon layer is crystallized by irradiating with laser light.

  Although not shown in FIG. 1 because it is not essential for obtaining the effects of the invention, for example, as shown in FIG. 3H, the channel protective layer 17 is positioned above the gate electrode 12 of the second silicon layer 15. It may be formed on the region to be formed and on the first silicon layer 16. When the channel protective layer 17 is provided, the channel protective layer 17 is formed of a silicon film, a silicon nitride film, an organic material, or the like, and the film thickness is desirably 100 to 700 nm.

The pair of contact layers 18 are formed so as to cover the upper surface of the first silicon layer 16 and, when the channel protective layer is present, the side surface of the channel protective layer and the end of the upper surface connected to the side surface. It is not formed above the first silicon layer 16. The contact layer 18 is composed of an amorphous semiconductor film containing impurities at a high concentration. The contact layer 18 can be configured by, for example, an n-type semiconductor film doped with phosphorus (P) as an impurity in amorphous silicon or a p-type semiconductor film doped with boron (B), which is 1 × 10 ¹⁸ to 1 × 10 6. Impurities in the range of ²¹ atm / cm ³ are included. Accordingly, the thin film transistor of the present invention can be applied to either an n-type thin film transistor or a p-type thin film transistor.

  The source and drain electrodes 19 are formed on the contact layer 18. The source electrode and the drain electrode 19 can have a single layer structure or a multilayer structure such as a conductive material and an alloy thereof, for example, aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), It is composed of titanium (Ti), chromium (Cr), or the like. The film thickness of the source / drain electrodes is preferably 50 to 300 nm.

  Next, a method for manufacturing the thin film transistor 100 according to this embodiment will be described with reference to FIGS. 3A to 3H are cross-sectional views for explaining a method of manufacturing the thin film transistor 100 according to the embodiment of the present invention.

  First, as shown to FIG. 3A, the board | substrate 10 comprised with a glass substrate is prepared (1st process).

Next, an undercoat layer 11 composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like is formed on the substrate 10 by plasma CVD (Chemical Vapor Deposition) or the like, and a gate electrode is formed on the undercoat layer 11. 12 is formed (second step). In this second step, for example, after a gate metal film made of molybdenum tungsten (MoW) is formed on the undercoat layer 11 by sputtering, the gate metal film is patterned using a photolithography method and a wet etching method. By doing so, the gate electrode 12 having a predetermined shape can be formed. The wet etching of molybdenum tungsten (MoW) can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed in a predetermined composition.

Thereafter, as shown in FIG. 3B, a gate insulating layer 13 is formed so as to cover the gate electrode 12 and the undercoat layer 11 (third step). In the third step, first, a silicon nitride film made of silicon nitride (SiN _x ) is formed by plasma CVD or the like so as to cover the plurality of gate electrodes 12 and the undercoat layer 11. Thereafter, a silicon oxide film made of silicon oxide (SiO _x ) is formed on the silicon nitride film by plasma CVD or the like. The silicon oxide film can be formed, for example, by introducing silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) at a predetermined concentration ratio.

Note that the extinction coefficient of the gate insulating layer 13 with respect to the wavelength of the laser light is preferably 0.01 or less. Such a gate insulating layer 13 can be regarded as a transparent layer that hardly absorbs laser light. Thereafter, an amorphous silicon layer 14 is formed on the gate insulating layer 13 (fourth step). In the fourth step, an amorphous silicon layer 14 made of amorphous silicon is formed by plasma CVD or the like. The amorphous silicon layer 14 can be formed by introducing, for example, silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) at a predetermined concentration ratio.

  Here, the crystal structure formed when the amorphous silicon layer 14 is melted and recrystallized by laser light irradiation, and the absorption rate of the laser light of the amorphous silicon layer 14 (hereinafter referred to as light absorption). Will be explained.

  The light absorptance of the multilayer thin film constituting the thin film transistor or the like is obtained by calculating the amplitude reflectance and the amplitude transmittance for each thin film. FIG. 4 is a diagram for explaining a calculation method of the amplitude reflectance and the amplitude transmittance, and is a diagram showing a model structure of a multilayer structure in which the structure of the thin film transistor is modeled.

The model structure shown in FIG. 4 is obtained by stacking a fourth layer 404, a third layer 403, a second layer 402, and a first layer 401 in order from the bottom. In this model structure, the first layer 401 has a film thickness d ₁ and a complex refractive index N ₁ , and the second layer 402 has a film thickness d ₂ and a complex refractive index N ₂ , and the third layer 403 has a film thickness of d ₃ and a complex refractive index of N ₃ , and the fourth layer 404 has a film thickness of d ₄ and a complex refractive index of N ₄ . Further, the region where the complex refractive index is N ₀ shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. The region where the complex refractive index is N ₀ is, for example, an air or N ₂ gas atmosphere region.

In FIG. 4, when N _n is a complex refractive index in the n-th layer, the complex refractive index can be expressed by a refractive index n (real part) and an extinction coefficient k (imaginary part). the second layer 402, the complex refractive index of the third layer 403 and fourth layer _{404, n 1 = n 1 -ik 1} , n 2 = n 2 -ik 2, n 3 = n 3 -ik 3, n 4 = N ₄ −ik ₄ . The external complex refractive index can be expressed as N ₀ = n ₀ -ik ₀ .

In FIG. 4, when θ _n is an incident angle in the n-th layer, the incident angle from the outside to the first layer 401, the incident angle from the first layer 401 to the second layer 402, and the second layer 402 to the second layer The incident angle to the third layer 403 and the incident angle from the third layer 403 to the fourth layer 404 can be expressed as θ ₀ , θ ₁ , θ _2, and θ ₃ .

  Here, according to Snell's law, the following (formula 7) is established.

In FIG. 4, when ρ _mn is the amplitude reflection coefficient of light incident on the m-th layer from the m-th layer, the amplitude reflection coefficient ρ ₀₁ for light incident on the first layer 401 from the outside, the first layer 401 Amplitude reflection coefficient ρ ₁₂ for light incident on the second layer 402 from the second layer, amplitude reflection coefficient ρ ₂₃ for light incident on the third layer 403 from the second layer 402, and from the third layer 403 to the fourth layer 404. The amplitude reflection coefficient ρ ₃₄ for incident light can be expressed by the following (Equation 8) to (Equation 10), respectively.

In FIG. 4, when τ _mn is an amplitude transmission coefficient of light incident on the m-th layer from the m-th layer, the amplitude transmission coefficient τ _{01 of} light incident on the first layer 401 from the outside, the first layer 401 The amplitude transmission coefficient τ _{12 of} light incident on the second layer 402 from the second layer 402, the amplitude transmission coefficient τ _{23 of} light incident on the third layer 403 from the second layer 402, and the fourth layer 404 from the third layer 403 The amplitude transmission coefficient τ ₃₄ of the incident light can be expressed by the following (Expression 11) to (Expression 13).

Here, when the two layers of the third layer 403 and the second layer 402 are assumed to be a single layer, the amplitude reflection coefficient and the amplitude transmission coefficient are ρ ₁₂₃ and τ ₁₂₃ , respectively. Assuming that the amplitude reflection coefficient and the amplitude transmission coefficient when the three layers of the layer 402 and the first layer 401 are combined into one layer are ρ ₀₁₂₃ and τ ₀₁₂₃ , respectively, ρ ₁₂₃ , τ ₁₂₃ , ρ ₀₁₂₃ , and τ ₀₁₂₃ is given by the following (formula 14) to (formula 19). Note that λ represents the wavelength of the laser light incident on the first layer 401.

By substituting (Equation 8) to (Equation 13) into (Equation 14) to (Equation 19), the reflectances R ₁ and R ₂ and the transmittances T ₁ and T ₂ are calculated. ) To (Equation 23).

The light absorption rate A of the first layer 401 can be expressed by the following (Equation 24) using R ₁ and T ₁ .

Using the calculation method described above, a laser beam having a wavelength λ with an incident angle θ ₀ perpendicular to the model structure shown in FIG. 4, that is, in a range in which θ ₀ = 0 ° (sin θ ₀ = 0) approximately holds. Is incident, the light absorption rate of the amorphous silicon thin film on the gate electrode can be calculated.

  In this embodiment mode, as a model structure of a thin film semiconductor device, as illustrated in FIG. 5, a gate electrode 411 is formed on a substrate 410 as a structure corresponding to the fourth layer 404, and a third structure is formed on the gate electrode 411. A first gate insulating layer 412a is formed as a structure corresponding to the layer 403, a second gate insulating layer 412b is formed as a structure corresponding to the second layer 402 on the first gate insulating layer 412a, and a second gate insulating layer is formed. Considering a configuration in which an amorphous silicon thin film 413 corresponding to the first layer 401 is formed on 412b, the light absorption rate A of the amorphous silicon thin film 413 corresponding to the first layer 401 is ( It can be calculated by equation 24).

  Subsequently, as shown in FIG. 3C, the amorphous silicon layer 14 is a thick film in the first region located on the central portion in the gate length direction of the gate electrode 12, and the gate electrode 12 In the second region (that is, the region other than the first region) located on both ends in the length direction, a convex structure is processed so as to become a thin film (fifth step).

  The preferred thicknesses of the first and second regions of the amorphous silicon layer 14 and the gate insulating layer 13 are described above from the desirable light absorption rates of the first and second regions of the amorphous silicon layer 14. It is determined by the calculation method.

  As an example, X is a value obtained by dividing the film thickness of the amorphous silicon layer 14 by the wavelength of the laser beam, and the refractive index of the gate insulating layer is set to the film thickness of the gate insulating layer 13 formed in the third step. When the value obtained by dividing the optical film thickness of the gate insulating layer, which is an integrated value, by the wavelength of the laser is Y, the first region is represented by (Expression 3) or (Expression 4), and the second region is represented by (Expression It is desirable that the film thickness satisfy the range defined by 5) or (Formula 6).

0.32 ≦ X ≦ 0.47 and 0.33 ≦ Y ≦ 0.39 (Formula 3)
0.41 ≦ X ≦ 0.59 and 0.51 ≦ Y ≦ 0.69 (Formula 4)
0.20 ≦ X ≦ 0.28 and 0.33 ≦ Y ≦ 0.39 (Formula 5)
0.20 ≦ X ≦ 0.28 and 0.51 ≦ Y ≦ 0.69 (Formula 6)

  FIG. 6 shows the range of XY defined by (Expression 3) to (Expression 6). From FIG. 6, in order to form the first silicon layer 16 and the second silicon layer 15 by the laser annealing method, films suitable for the first region and the second region of the gate insulating layer 13 and the amorphous silicon layer 14, respectively. It can be seen that a range of thickness exists. More specifically, in FIG. 6, a region surrounded by a broken line is a first region, that is, a preferred energy absorption rate range of the convex thick film portion, and a region surrounded by a solid line is a second region, That is, it is a preferable energy absorption rate range of the convex-shaped thin film portion.

  7 shows the values of the X-axis and Y-axis shown in FIG. 6 as the actual film thicknesses of the amorphous silicon layer 14 and the gate insulating layer 13 when the laser beam wavelength is 532 nm. It is. As shown in FIG. 7, in the formation process in the fifth step, the thick film portion, that is, the first region is formed in the range of the broken line region, and the film thickness of the second region is reduced to 29 nm or less, for example, by etching, It shows that a preferable convex shape of the crystalline silicon layer 14 is obtained.

As shown in FIG. 3D, the first silicon layer 16 and the second silicon layer 15 are formed by crystallizing the amorphous silicon layer 14 processed into a convex shape in the fifth step by laser annealing (sixth silicon layer 16). Process). In this sixth step, the amorphous silicon layer 14 formed and processed in the fourth step and the fifth step is subjected to dehydrogenation treatment (for example, at 500 ° C. for 20 minutes) and then laser annealing. Then, the entire region of the amorphous silicon layer 14 is irradiated with laser light from a laser light source (not shown) (as an example, 70 kW, 400 mm ² / sec).

  In this laser annealing method, the laser light focused linearly by moving the laser light source relative to the substrate 10 in a predetermined direction while the position of the stage on which the substrate 10 is mounted is fixed. Is irradiated while scanning the entire area of the amorphous silicon layer 14. Alternatively, the stage on which the substrate 10 is mounted can be configured to move relative to the laser light source in a predetermined direction while the position of the laser light source is fixed. In this embodiment mode, laser light used in the laser annealing method is green laser light having a wavelength of 473 nm to 561 nm.

  Note that the laser light is preferably irradiated in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because the amorphous silicon layer 14 can be held in a molten state by irradiating laser light in a continuous oscillation mode or a pseudo continuous oscillation mode. The laser light source can be constituted by a solid-state laser device or a laser device using a semiconductor laser element.

  In the sixth step, in order to stably crystallize the first silicon layer 16 and the second silicon layer 15, the energy density of the laser light irradiated in the sixth step is a predetermined relational expression (formula 1). (Formula 2) is preferably satisfied.

FIG. 8 is a diagram showing the relationship between the laser beam absorption rate of the amorphous silicon layer 14 and the energy density of the laser beam. In FIG. 8, the horizontal axis (X axis) represents the laser light absorption rate (%) of the amorphous silicon layer 14. The vertical axis (Y-axis) indicates the energy density of the laser beam. When the absorption rate of the laser beam of the amorphous silicon layer 14 is 23.2%, the amorphous silicon layer 14 is crystallized to form the first silicon. The energy value (J / cm ² ) of the laser beam required at least for forming the layer 16 is expressed as a relative value.

  The laser beam absorptance X of the amorphous silicon layer 14 and the energy density Y of the laser beam irradiated in the sixth step are in the preferred range defined by the following (Expression 1) and (Expression 2). , Y is preferably satisfied.

Y ≦ 1.2 (Formula 1)
Y ≧ 42.9X− ^1.19 (Formula 2)

  In FIG. 8, the upper graph represents (Expression 1), and the lower graph represents (Expression 2). By configuring the amorphous silicon layer 14 so that the absorption rate of the laser beam and the energy density of the laser beam satisfy X and Y belonging to a preferable range defined by the following formulas 2 and 13, The first silicon layer 16 can be stably formed from the first region of the porous silicon layer 14. FIG. 9A is a surface SEM image of the first region after the laser irradiation with the conditions in the preferred range. The first region is crystallized to form the first silicon layer 16.

  If the value of Y is smaller than the range defined by (Expression 2), the energy density of the laser light is too low to form the first silicon layer 16. FIG. 9B is a surface SEM image of the first region after the laser is irradiated under conditions where the energy density is too low outside the preferred range. The first region remains amorphous and the first silicon layer 16 is not formed.

  When the value of Y is larger than the range defined by (Equation 1), the energy density of the laser beam is too high, and even the second silicon layer 15 has high crystallinity (for example, polycrystalline silicon). There is a risk that it will be formed.

  Next, as shown in FIG. 3E, the channel protective layer 17 is formed. For example, a film formed by plasma CVD (silicon oxide film or silicon nitride film) or an organic film formed by a coating process is used to form the channel protective layer 17. Thereafter, as shown in FIG. 3F, a process for leaving the channel protective layer 17 on the gate electrode (for example, a process using the gate electrode as a mask) is performed to form the channel protective layer 17.

  Thereafter, as shown in FIG. 3G, a contact layer 18 is formed so as to cover the side surfaces of the first silicon layer 16 and the second silicon layer 15 and the channel protective layer 17. In this step, for example, the contact layer 18 made of amorphous silicon doped with impurities such as phosphorus (P) or boron (B) is formed by plasma CVD (eighth step).

  Thereafter, as shown in FIG. 3F, the source / drain electrodes 19 are formed on the contact layer 18 by patterning (9th step). In the ninth step, first, as shown in FIG. 3G, a source / drain metal film made of the material of the source / drain electrode 19 is formed by sputtering, for example. Thereafter, in order to form a source / drain electrode 19 having a predetermined shape, a resist material is applied onto the source / drain electrode film, and exposure and development are performed to form a resist patterned in a predetermined shape.

  Next, by performing wet etching using this resist as a mask and patterning the source / drain metal film, a source / drain electrode 19 having a predetermined shape is formed as shown in FIG. 3H. The source / drain electrodes are formed on the contact layer via the second silicon layer 15 and are not formed on the contact layer 18 via the first silicon layer 16. At this time, the contact layer 18 functions as an etching stopper layer. Thereafter, the resist on the source / drain electrode 19 is removed.

  Thereafter, as shown in FIG. 3H, by performing dry etching using the source / drain electrode 19 as a mask, the contact layer 18 is patterned, and the source / drain electrode 19 is patterned into an island shape. Thereby, the contact layer 18 and the source / drain electrode 19 can be formed in an island shape. At this time, the channel protective layer 17 functions as an etching stopper layer. Note that a chlorine-based gas can be used as a dry etching condition.

  As described above, the thin film transistor 100 according to the embodiment can be manufactured.

(Second Embodiment)
In the actual manufacturing process, the first silicon layer 16 and the second silicon layer 15 are formed by utilizing the difference in absorption rate of laser light between the first region and the second region of the amorphous silicon layer 14, for example, the difference in film thickness. Various combinations such as a polycrystalline silicon layer and an amorphous silicon layer, a polycrystalline silicon layer and a microcrystalline silicon layer can be used.

  An example is shown in the second embodiment. In the second embodiment, components made of the same or similar materials as the components described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  10A to 10B are cross-sectional views for explaining a manufacturing process of the thin film transistor according to the second embodiment. As shown in FIG. 10A, after the amorphous silicon layer 14 is formed according to the description of the manufacturing steps from FIG. 3A to FIG. 3B, the amorphous silicon layer 14 is then processed into a convex shape. FIG. 11 shows the distribution of the film thickness and laser absorption rate of each of the amorphous silicon layer 14 and the gate insulating layer 13 as in FIG. A value obtained by dividing the optical film thickness of the gate insulating layer 13 by the wavelength of the laser, which is a value obtained by adding the refractive index of the gate insulating layer 13 to the film thickness of the gate insulating layer 13. The XY distribution of the laser light absorptance of the amorphous silicon layer 14 when Y is Y is shown.

  When the conditions shown in FIG. 11 are satisfied, that is, the first region is defined by (Expression 25) or (Expression 26), and the second region is defined by the range of (Expression 27) or (Expression 28), the laser light absorption rate of the second region. Therefore, the second silicon layer 20 made of microcrystalline silicon is formed from the second region of the amorphous silicon layer 14. The broken line portion and the solid line portion in FIG. 11 correspond to the first region and the second region, respectively, and indicate that there is a condition that actually forms the structure shown in FIG. 10B.

0.32 ≦ X ≦ 0.47 and 0.33 ≦ Y ≦ 0.39 (Equation 25)
0.41 ≦ X ≦ 0.59 and 0.51 ≦ Y ≦ 0.69 (Formula 26)
0.28 ≦ X ≦ 0.33 and 0.33 ≦ Y ≦ 0.39 (Expression 27)
0.30 ≦ X ≦ 0.36 and 0.51 ≦ Y ≦ 0.69 (Equation 28)

  In this case, since the channel layer is composed of polycrystalline silicon and microcrystalline silicon, a high on-current can be expected, and the microcrystalline silicon layer as the second silicon layer region plays the role of the charge relaxation layer. By carrying this, there is an effect of reducing off-current.

  The thin film transistor 100 according to the present embodiment can be mounted on a display device 200 as shown in FIG. 15, for example. A display device 200 shown in FIG. 5 includes a display panel 21 including a liquid crystal panel and an organic EL panel. The display panel 21 is driven by the thin film transistor 100.

  Although the embodiment of the present invention has been described above, the configuration shown in the above embodiment is an example, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

  The thin film transistor according to the present invention can be widely used in display devices such as a television set, a personal computer, and a mobile phone, or other various electric devices having a thin film transistor.

DESCRIPTION OF SYMBOLS 10 Substrate 11 Undercoat layer 12 Gate electrode 13 Gate insulating layer 14 Amorphous silicon layer 15 Second silicon layer 16, 20 First silicon layer 17 Channel protective layer 18 Contact layer 19 Source / drain electrode 21 Display panel 100 Thin film transistor 200 Display Device 401 First layer 402 Second layer 403 Third layer 404 Fourth layer 410 Substrate 411 Gate electrode 412a First gate insulating layer 412b Second gate insulating layer 413 Silicon thin film

Claims (16)

A substrate,
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A first silicon layer formed on the gate insulating layer above the central portion in the gate length direction of the gate electrode;
A pair of second silicon layers formed on both sides of the first silicon layer on the gate insulating layer above both ends in the gate length direction of the gate electrode;
A pair of source / drain electrodes formed above each of the second silicon layers along an upper surface of the second silicon layer;
With
The first silicon layer is thicker than each of the second silicon layers,
The first silicon layer is made of crystalline silicon;
Each of the second silicon layers is made of crystalline silicon or amorphous silicon having an average grain size smaller than the average grain size of crystal grains contained in the first silicon layer.
Thin film transistor. And a channel protective layer formed on the first silicon layer and the second silicon layer.
The thin film transistor according to claim 1. The portion of the first silicon layer that is not in contact with the second silicon layer is made of crystalline silicon having an average particle size smaller than the portion that is in contact with the second silicon layer.
The thin film transistor according to claim 1. The first silicon layer includes crystalline silicon having a particle diameter of 50 nm or more.
The thin-film transistor of any one of Claims 1-3. The second silicon layer includes microcrystalline silicon having a particle diameter of 10 nm or less;
The thin-film transistor of any one of Claims 1-3. The second silicon layer includes amorphous silicon;
The thin-film transistor of any one of Claims 1-3. The gate insulating layer is silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride.
The thin film transistor according to any one of claims 1 to 6. A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating layer on the gate electrode;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
The thickness of the first region in which the amorphous silicon layer is located on the central portion in the gate length direction of the gate electrode is located on both end portions in the gate length direction of the gate electrode. A fifth step of processing into a convex shape thicker than the thickness of the second region;
A first silicon layer made of crystalline silicon is formed from the first region of the amorphous silicon layer by irradiating laser light from above the amorphous silicon layer after processing into a convex shape. And a second silicon layer composed of crystalline silicon or amorphous silicon having an average grain size smaller than the average grain size of crystal grains contained in the first silicon layer from the second region of the amorphous silicon layer. A sixth step of forming
A seventh step of forming a channel protective layer formed on the first silicon layer;
An eighth step of forming a contact layer only along the upper surface of the end portion of the channel protective layer, the side surface of the channel protective layer, and the upper surface of the second silicon layer;
A ninth step of forming a source electrode formed above one of the contact layers and a drain electrode formed above the other of the contact layers,
A method for manufacturing a thin film transistor. The method of manufacturing a thin film transistor according to claim 8, wherein the amorphous silicon layer is laser-annealed in the sixth step. 10. The method of manufacturing a thin film transistor according to claim 8, wherein, in the sixth step, the amorphous silicon layer is irradiated with a green laser having a laser wavelength of 473 nm to 561 nm. In the sixth step, the laser light is generated by a laser light source operating in a continuous oscillation mode or a pseudo laser oscillation mode, and the amorphous silicon layer is irradiated.
The manufacturing method of the thin-film transistor of any one of Claims 8-10. The laser light absorption rate (%) of the amorphous silicon layer formed in the fourth step is X, and the laser light absorption rate of the amorphous silicon layer formed in the fourth step is 23. When the relative value Y is 1 when the energy density of the laser beam necessary for crystallizing the amorphous silicon layer is 1 when X is 2%, X and Y are
Y ≦ 1.2 (Formula 1)
Y ≧ 42.9X− ^1.19 (Formula 2)
Is a numerical value that satisfies the range specified in
The manufacturing method of the thin-film transistor of any one of Claims 8-11. A value obtained by dividing the film thickness of the amorphous silicon layer formed in the fifth step by the wavelength of the laser beam is X, and the refractive index of the gate insulating layer is calculated as the film thickness of the gate insulating layer formed in the third step. When the value obtained by dividing the optical film thickness of the gate insulating layer by the laser wavelength is Y, the first region of the amorphous silicon layer is represented by (Equation 3) or (Equation 4). And the second region satisfies (Expression 5) or (Expression 6).
0.32 ≦ X ≦ 0.47 and 0.33 ≦ Y ≦ 0.39 (Formula 3)
0.41 ≦ X ≦ 0.59 and 0.51 ≦ Y ≦ 0.69 (Formula 4)
0.20 ≦ X ≦ 0.28 and 0.33 ≦ Y ≦ 0.39 (Formula 5)
0.20 ≦ X ≦ 0.28 and 0.51 ≦ Y ≦ 0.69 (Formula 6)
The manufacturing method of the thin-film transistor of Claim 8. In the fourth step, the second region of the amorphous silicon layer is formed with a constant thickness regardless of the presence or absence of the gate electrode.
The manufacturing method of the thin-film transistor of Claim 8. In the eighth step, the pair of source / drain electrodes are formed on the second region of the amorphous silicon layer through the channel protective layer formed in the seventh step.
The thin-film transistor manufacturing method of Claim 8.   A display device comprising: a display panel; and the thin film transistor according to claim 1, wherein the thin film transistor drives the display panel.