WO2013061574A1 - Thin film semiconductor device - Google Patents
Thin film semiconductor device Download PDFInfo
- Publication number
- WO2013061574A1 WO2013061574A1 PCT/JP2012/006771 JP2012006771W WO2013061574A1 WO 2013061574 A1 WO2013061574 A1 WO 2013061574A1 JP 2012006771 W JP2012006771 W JP 2012006771W WO 2013061574 A1 WO2013061574 A1 WO 2013061574A1
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- Prior art keywords
- layer
- amorphous semiconductor
- semiconductor layer
- thin film
- gate electrode
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Definitions
- the present invention relates to a thin film semiconductor device, and more particularly to a thin film semiconductor device used in a pixel circuit of a display device.
- Organic EL displays are current-driven display devices, unlike voltage-driven liquid crystal displays. For this reason, development of a thin film transistor (TFT: Thin Film Transistor) having excellent characteristics as a drive circuit for an active matrix display device has been urgently required.
- the thin film transistor is used as a switching element for selecting a pixel, a driving transistor for driving the pixel, or the like.
- a thin film semiconductor device 900 shown in FIG. 7 includes a substrate 910, a gate electrode 920, a gate insulating film 930, a crystalline silicon layer 940, an amorphous silicon layer 950, a channel protective layer 960, and a pair of contact layers 971. 972, a source electrode 981 and a drain electrode 982 are stacked in this order, and are bottom-gate thin film transistors.
- the back channel is a path of a parasitic current flowing from the source electrode 981 toward the drain electrode 982 via the vicinity of the interface with the channel protective layer 960 in the crystalline silicon layer 940.
- an amorphous silicon layer 950 made of an amorphous silicon film is formed between the crystalline silicon layer 940 and the channel protective layer 960.
- the amorphous silicon layer 950 can perform electric field shielding by offsetting the positive fixed charge of the channel protective layer 960 by the charge density of negative carriers. Thereby, the formation of a back channel can be suppressed and the leakage current at the time of OFF can be suppressed, so that the OFF characteristics can be improved.
- the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a thin film semiconductor device in which the off-current is improved by suppressing the leakage current at the off time and the on-resistance is reduced.
- a thin film semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a polycrystal formed on the gate insulating film.
- a channel layer made of a semiconductor, a first amorphous semiconductor layer formed on the channel layer, an organic insulating layer formed on the first amorphous semiconductor layer, and the first amorphous semiconductor layer And a pair of second amorphous semiconductor layers formed on one side surface and the other side surface of the channel layer, and the second non-crystalline semiconductor layer on each of the pair of second amorphous semiconductor layers.
- the gate electrode, the channel layer, the first amorphous semiconductor layer, and the organic insulating layer are stacked so that outlines thereof coincide when viewed from above, and the first amorphous
- the localized state density of the crystalline semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer, and the band gap of the second amorphous semiconductor layer is the same as that of the first amorphous semiconductor layer. It is characterized by being larger than the band gap.
- the present invention it is possible to obtain a thin film semiconductor device in which the off-current is improved by suppressing the leakage current at the off time and the on-resistance is reduced.
- FIG. 1 is a cross-sectional view showing the structure of a thin film semiconductor device according to an embodiment of the present invention.
- FIG. 2A is a diagram illustrating the configuration and operational effects of the thin film semiconductor device of Comparative Example 1.
- FIG. 2B is a diagram showing a configuration and operational effects of the thin film semiconductor device of Comparative Example 2.
- FIG. 2C is a diagram showing a configuration and operational effects of the thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3A is a cross-sectional view schematically showing a substrate preparation step in the method for manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3A is a cross-sectional view schematically showing a substrate preparation step in the method for manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3B is a cross-sectional view schematically showing a gate electrode forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3C is a cross-sectional view schematically showing a gate insulating film forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3D is a cross-sectional view schematically showing a crystalline silicon thin film forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3E is a cross-sectional view schematically showing a first amorphous silicon film forming step in the method for manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3F is a cross-sectional view schematically showing an insulating film forming step in the method for manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3G is a cross-sectional view schematically showing a channel protective layer forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3H is a cross-sectional view schematically showing a channel layer / first amorphous semiconductor layer forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3I is a cross-sectional view schematically showing a second amorphous silicon film forming step in the method for manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3J is a cross-sectional view schematically showing a contact layer thin film forming step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 3K is a cross-sectional view schematically showing a source electrode / drain electrode formation step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- FIG. 4 is a diagram illustrating an example of a stacking relationship between the gate electrode, the channel layer, the first amorphous semiconductor layer, and the channel protective layer.
- FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment of the present invention.
- FIG. 6 is a diagram showing a circuit configuration of a pixel using the thin film semiconductor device according to the embodiment of the present invention.
- FIG. 7 is a cross-sectional view showing a configuration of a conventional thin film semiconductor device.
- the amorphous silicon layer 950 is required to have a high local level density and a high band gap. However, it is extremely difficult to realize such a performance by the amorphous silicon layer 950 made of a single layer.
- the amorphous silicon layer 950 is interposed between the crystalline silicon layer 940 including the channel region and the source electrode 981 and the drain electrode 982. That is, since the high-resistance amorphous silicon layer 950 is included in the current path, the on-resistance is increased.
- An object of the present invention is to provide a thin film semiconductor device in which an off characteristic is improved by suppressing a leakage current at an off time and an on-resistance is reduced.
- a thin film semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and the gate insulation.
- a pair of contact layers formed to contact the side surface of the channel layer through the second amorphous semiconductor layer, and a source electrode formed on one of the pair of contact layers, And other contact layers And the gate electrode, the channel layer, the first amorphous semiconductor layer, and the organic insulating layer are stacked so that outlines thereof coincide when viewed from above.
- the localized level density of the first amorphous semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer, and the band gap of the second amorphous semiconductor layer is It is characterized by being larger than the band gap of one amorphous semiconductor layer.
- the gate electrode, the source electrode, and the drain electrode do not overlap in the left and right regions of the channel protective layer, the parasitic capacitance in this region can be reduced.
- the contact layer is in contact with the side surface of the channel layer through the second amorphous semiconductor layer.
- the first amorphous semiconductor layer having high resistance can be removed from the current path, so that the on-resistance can be reduced.
- the performance of the thin film semiconductor device can be dramatically improved. it can.
- the outline of the lower surface of the organic insulating layer recedes by 0.5 ⁇ m or less inside the outline of the gate electrode when viewed from above. May be.
- the outer contour line on the lower surface of the organic insulating layer is located inside the outer contour line of the gate electrode when viewed from above. It may be set back more than the thickness of the layer.
- the second amorphous semiconductor layer is formed at a position overlapping the gate electrode, the on-resistance can be reduced.
- the pair of second amorphous semiconductor layers, the pair of contact layers, the source electrode, and the drain electrode are part of an upper surface of the organic insulating layer. And may extend on a side surface of the organic insulating layer.
- the film thickness of the first amorphous semiconductor layer may be 50 nm or less.
- the first amorphous semiconductor layer has a high light absorption rate in the exposure process, and if it is too thick, the exposure amount required for the organic insulating layer does not reach and exposure may be insufficient. is there. Alternatively, there is a concern that a long exposure process is required to obtain a necessary exposure amount, and productivity is significantly reduced.
- the thickness of the first amorphous semiconductor layer can be 50 nm or more if the amount of light used in the exposure process is increased.
- the method for manufacturing a thin film semiconductor device includes a first step of preparing a substrate, a second step of forming a gate electrode on the substrate, and forming a gate insulating film on the gate electrode.
- the second amorphous layer is formed on each of the amorphous semiconductor layers.
- the outer contour line on the lower surface of the organic insulating layer is formed so as to recede to the inner side of the outer contour line of the gate electrode when viewed from above.
- the etching is performed using the developed organic insulating layer as a mask, whereby an outer shape of the lower surface of the organic insulating layer is formed.
- the outline may be formed so as to recede by more than the thickness of the second amorphous semiconductor layer inside the outline outline of the gate electrode when viewed from above.
- the localized level density of the first amorphous semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer.
- the band gap of the second amorphous semiconductor layer may be larger than the band gap of the first amorphous semiconductor layer.
- FIG. 1 is a cross-sectional view showing a schematic configuration of a thin film semiconductor device 100 according to the present embodiment.
- the thin film semiconductor device 100 includes a substrate 110, a gate electrode 120, a gate insulating film 130, a channel layer 140, a first amorphous semiconductor layer 150, a channel protective layer 160,
- the bottom-gate thin film transistor includes a pair of second amorphous semiconductor layers 171 and 172, a pair of contact layers 181 and 182, and a source electrode 191 and a drain electrode 192 that are stacked in this order.
- the substrate 110 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass.
- a silicon nitride film (SiN x ), silicon oxide (SiO y ), or silicon acid is formed on the substrate 110.
- An undercoat layer made of a nitride film (SiO y N x ) or the like may be formed.
- the undercoat layer may play a role of mitigating the influence of heat on the substrate 110 in a high-temperature heat treatment process such as laser annealing.
- the film thickness of the undercoat layer can be, for example, about 100 nm to 2000 nm.
- the gate electrode 120 is patterned in a predetermined shape on the substrate 110.
- Examples of the material constituting the gate electrode 120 include molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), chromium (Cr), and molybdenum tungsten (MoW). Can be used.
- the film thickness of the gate electrode 120 can be about 20 to 500 nm, for example.
- the gate insulating film 130 is formed on the entire surface of the substrate 110 so as to cover the gate electrode 120.
- Examples of the material constituting the gate insulating film 130 include silicon oxide (SiO y ), silicon nitride (SiN x ), silicon oxynitride film (SiO y N x ), aluminum oxide (AlO z ), or tantalum oxide (TaO w). )) Or a laminated film thereof.
- the film thickness of the gate insulating film 130 can be set to, for example, 50 nm to 300 nm.
- the channel layer 140 is formed of a crystalline silicon thin film as will be described later, it is preferable to use silicon oxide for the gate insulating film 130. Silicon oxide is suitable for improving the interface state between the channel layer 140 and the gate insulating film 130, thereby improving the threshold voltage characteristics of the thin film semiconductor device 100.
- the channel layer 140 is a semiconductor film patterned at a position overlapping the gate electrode 120 on the gate insulating film 130, and a predetermined channel region that is a region in which carrier movement is controlled by the voltage of the gate electrode 120. Have.
- the gate electrode 120 and the channel layer 140 are stacked so that the outer contour lines match when viewed from above.
- the outer contour lines match means that the gate electrode 120 and the channel layer 140 have the same shape (the same shape and area), and the gate electrode 120 and the channel layer 140 are displaced in the horizontal direction. It means that it is arranged without.
- the channel layer 140 is a crystalline silicon thin film having a crystalline structure, and is made of a microcrystalline silicon thin film or a polycrystalline silicon thin film.
- the channel layer 140 can be formed by crystallizing amorphous amorphous silicon (amorphous silicon), for example.
- the channel layer 140 can be a silicon thin film having a mixed crystal structure of amorphous silicon (non-crystalline silicon) and crystalline silicon. In this case, in order to obtain excellent on characteristics, it is preferable to increase the ratio of crystalline silicon in at least the channel region.
- the film thickness of the channel layer 140 can be about 30 nm to 200 nm, for example.
- the principal plane orientation of the silicon crystal included in the channel layer 140 is preferably [100]. Thereby, the channel layer 140 having excellent crystallinity can be formed.
- the average crystal grain size of crystalline silicon in the channel layer 140 is about 5 nm to 1000 nm.
- the channel layer 140 has a polycrystal having an average crystal grain size of 100 nm or more as described above, or an average crystal grain size. Also included are microcrystals called microcrystals ( ⁇ c) of 10 nm to 100 nm.
- the first amorphous semiconductor layer 150 is patterned on the channel layer 140.
- the gate electrode 120, the channel layer 140, and the first amorphous semiconductor layer 150 are stacked so that their outlines match when viewed from above.
- the first amorphous semiconductor layer 150 is formed of, for example, an amorphous silicon film (intrinsic amorphous silicon) that is not intentionally doped with impurities.
- the first amorphous semiconductor layer 150 is set to have a higher localized level density (trap density) than the channel layer 140. That is, the electric field shielding can be performed by offsetting the positive fixed charges of the channel protective layer 160 by the charge density of the negative carriers of the first amorphous semiconductor layer 150. Thereby, the formation of the back channel can be suppressed and the leakage current at the time of OFF can be suppressed, so that the OFF characteristics of the thin film semiconductor device 100 are improved.
- the channel protective layer 160 is patterned at a position overlapping the channel layer 140 on the first amorphous semiconductor layer 150.
- the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 are stacked so that their outlines match when viewed from above.
- the channel protective layer 160 shown in FIG. 1 has a tapered shape in which a cross-sectional area decreases from the lower surface toward the upper surface, at least the outer contour lines of the lower surface of the channel protective layer 160 are the gate electrode 120 and the channel. It is only necessary to match the outer contour lines of the layer 140 and the first amorphous semiconductor layer 150.
- the channel protective layer 160 functions as a channel etching stopper (CES) layer that protects the channel layer 140 and the first amorphous semiconductor layer 150. That is, the channel protective layer 160 is formed by the channel layer 140 and the first amorphous semiconductor layer 150 during the etching process when forming the pair of second amorphous semiconductor layers 171 and 172 and the pair of contact layers 181 and 182. Has a function of preventing etching.
- CES channel etching stopper
- the channel protective layer 160 for example, an organic material mainly containing an organic material containing silicon, oxygen, and carbon can be used.
- the channel protective layer 160 in this embodiment can be formed by patterning and solidifying a photosensitive coating type organic material.
- the organic material constituting the channel protective layer 160 includes, for example, an organic resin material, a surfactant, a solvent, and a photosensitizer.
- the organic resin material a photosensitive or non-photosensitive organic resin material composed of one or more of polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, and the like can be used.
- the surfactant a surfactant made of a silicon compound such as siloxane can be used.
- an organic solvent such as propylene glycol monomethyl ether acetate or 1,4-dioxane can be used.
- the photosensitizer a positive photosensitizer such as naphthoquinone diazite can be used. Note that the photosensitive agent contains not only carbon but also sulfur.
- the above organic material can be formed using a coating method such as a spin coating method.
- a coating method such as a spin coating method.
- the channel protective layer 160 can be formed not only by a coating method but also by other methods such as a droplet discharge method.
- an organic material having a predetermined shape can be selectively formed by using a printing method that can form a predetermined pattern such as screen printing or offset printing.
- the film thickness of the channel protective layer 160 can be, for example, 300 nm to 1000 nm.
- the lower limit of the thickness of the channel protective layer 160 is determined in consideration of a margin due to etching and suppression of the influence of fixed charges in the channel protective layer 160.
- the upper limit of the thickness of the channel protective layer 160 is that the process reliability decreases with an increase in the steps with the second amorphous semiconductor layers 171 and 172, the contact layers 181 and 182, the source electrode 191, and the drain electrode 192. It is determined in consideration of the suppression.
- the pair of second amorphous semiconductor layers 171 and 172 are patterned so as to cover the channel protective layer 160, the first amorphous semiconductor layer 150, and the channel layer 140.
- the second amorphous semiconductor layer 171 and the second amorphous semiconductor layer 172 are arranged to face each other with a predetermined interval.
- the second amorphous semiconductor layer 171 includes a part of the upper surface of the channel protective layer 160, a side surface on one side (left side in FIG. 1) of the channel protective layer 160, and the first amorphous semiconductor layer 150. 1 is formed so as to straddle the side surface on one side (left side in FIG. 1) and the side surface on one side (left side in FIG. 1) of the channel layer 140.
- the second amorphous semiconductor layer 171 is in contact with the side surface on one side of the channel layer 140.
- the second amorphous semiconductor layer 172 includes a part of the upper surface of the channel protective layer 160, a side surface on the other side of the channel protective layer 160 (right side in FIG. 1), and the other side of the first amorphous semiconductor layer 150 ( It is formed so as to straddle the side surface on the right side in FIG.
- the second amorphous semiconductor layer 172 is in contact with the other side surface of the channel layer 140.
- the second amorphous semiconductor layers 171 and 172 are extended from the upper surface of the channel protective layer 160 to the side surface of the channel layer 140.
- the semiconductor layers 171 and 172 may be provided so as to cover at least the side surface of the channel layer 140. The same applies to the contact layers 181 and 182, the source electrode 191, and the drain electrode 192.
- the second amorphous semiconductor layers 171 and 172 may be made of an amorphous silicon film (intrinsic amorphous silicon) that is not intentionally doped with impurities. If the influence on the on-resistance is too great, a layer doped at a lower concentration of 1-2 digits or less than the contact layers 181 and 182 may be used. Alternatively, even if the doping is not intentionally performed, the layer having the above-described concentration can be formed by forming a film using the memory effect of the residual dopant in the doping chamber.
- the second amorphous semiconductor layers 171 and 172 in the present embodiment are composed of only amorphous amorphous components and are not intentionally crystallized.
- the first amorphous semiconductor layer 150 and the pair of second amorphous semiconductor layers 171 and 172 are formed so that the localized level density (localized level) and the band gap are different from each other.
- the first amorphous semiconductor layer 150 is formed so that the localized level density is higher than the localized level density of the second amorphous semiconductor layers 171 and 172.
- the band gaps of the second amorphous semiconductor layers 171 and 172 are formed to be larger than the band gap of the first amorphous semiconductor layer 150.
- the localized level density is a defect level density (trap density) in the semiconductor film, and represents a density of states of charge (DOS: Density Of State).
- the localized level density of the first amorphous semiconductor layer 150 in this embodiment is [1 ⁇ 10 18 ] cm ⁇ 3
- the localized level density of the second amorphous semiconductor layers 171 and 172 is , [1 ⁇ 10 17 ] cm ⁇ 3
- the band gap of the first amorphous semiconductor layer 150 is [1.3] eV
- the band gap of the intrinsic amorphous silicon film 6 is [1.7] eV.
- the pair of contact layers 181 and 182 are stacked on the pair of second amorphous semiconductor layers 171 and 172, respectively.
- the contact layer 181 and the contact layer 182 are arranged to face each other with a predetermined interval.
- the contact layer 181 is in contact with the side surface on one side (the left side in FIG. 1) of the channel layer 140 through the second amorphous semiconductor layer 171.
- the contact layer 182 is in contact with the other side surface (the right side in FIG. 1) of the channel layer 140 through the second amorphous semiconductor layer 172.
- the contact layers 181 and 182 are amorphous semiconductor films containing impurities at a high concentration, and are n + layers containing impurities at a high concentration of 1 ⁇ 10 19 [atm / cm 3 ] or more. More specifically, the contact layers 181 and 182 can be formed of an n-type semiconductor film obtained by doping amorphous silicon with phosphorus (P) as an impurity.
- the film thickness of the contact layers 181 and 182 can be set to 5 nm to 100 nm, for example.
- the source electrode 191 and the drain electrode 192 are patterned at positions overlapping the channel layer 140 on the contact layers 181 and 182. In other words, the source electrode 191 and the drain electrode 192 are disposed to face each other with a predetermined interval.
- the source electrode 191 and the drain electrode 192 can have a single-layer structure or a multilayer structure such as a conductive material and an alloy thereof.
- it is composed of aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), titanium (Ti), chromium (Cr), or the like.
- the source electrode 191 and the drain electrode 192 have a three-layer structure of MoW / Al / MoW.
- the film thickness of the source electrode 191 and the drain electrode 192 can be, for example, about 100 nm to 500 nm.
- the outer contour lines of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 match. ing. As will be described later, these outlines coincide with each other by self-alignment.
- FIG. 2A is a diagram showing a configuration and operational effects of the thin film semiconductor device 900A of the first comparative example.
- FIG. 2B is a diagram showing a configuration and operational effects of the thin film semiconductor device 900B of Comparative Example 2.
- FIG. 2C is a diagram showing a configuration and operational effects of the thin film semiconductor device 100 according to the present embodiment.
- the gate electrode 920, the crystalline silicon layer 940, the amorphous silicon layer 950, and the channel protective layer 960 are not used.
- the outlines of the gate electrode 920, the crystalline silicon layer 940, and the amorphous silicon layer 950 are longer than the channel protective layer 960. Therefore, in the thin film semiconductor device 900A of Comparative Example 1, current can be injected from a wide contact region.
- the contact region itself located above the amorphous silicon layer 950 above the gate electrode 920 is large (that is, the region to which voltage is applied is large). ), Carrier injection characteristics are relatively good.
- the thin film semiconductor device 900A of Comparative Example 1 although the crystalline silicon layer 940 (polysilicon) and the contact layer 971 are in direct contact with each other at both ends of the crystalline silicon layer 940 without passing through the amorphous silicon layer 950, Since the contact region above the amorphous silicon layer 950 becomes dominant, direct injection of carriers from the contact layer 971 to the crystalline silicon layer 940 does not substantially occur.
- the thin film semiconductor device 900A of Comparative Example 1 has a problem that the parasitic capacitance is large because the gate electrode 920 is long.
- the channel protective layer 960 and the gate electrode 920 are self-aligned, and the crystalline silicon layer 940 and the amorphous silicon layer 950 are not self-aligned. That is, the outer contour lines of the channel protective layer 960 and the gate electrode 920 are identical, but the outer contour lines of the channel protective layer 960 and the gate electrode 920 are identical with the crystalline silicon layer 940 and the amorphous silicon layer 950. However, the lengths of the crystalline silicon layer 940 and the amorphous silicon layer 950 are longer than the lengths of the gate electrode 920 and the channel protective layer 960.
- the contact area between the amorphous silicon layer 950 and the contact layer 971 is large, the contact region is not located above the gate electrode 920, and no voltage is applied to the contact region, so that carrier injection occurs. do not do. For this reason, carriers are injected from a narrow contact region of only a small part where voltage is applied, and the current characteristics become very poor. Also in this case, similarly to Comparative Example 1, carrier injection from the amorphous silicon layer 950 becomes dominant, so that even if the crystalline silicon layer 940 and the contact layer 971 are in direct contact with each other, the contact silicon layer 971 and the crystalline silicon layer Direct injection of carriers into layer 940 does not occur substantially.
- the outline of the gate electrode 120 and the lower surface of the channel protective layer 160 coincide with each other when viewed from above.
- the left and right end portions of the lower surface of the channel protective layer 160 are positioned on the extension lines of the left and right side surfaces of the gate electrode 120.
- the gate electrode 120, the source electrode 191 and the drain electrode 192 do not overlap in the left and right regions of the channel protective layer 160, so that the parasitic capacitance in this region can be reduced.
- the outer contour lines of the gate electrode 120, the channel layer 140 (crystalline silicon), and the first amorphous semiconductor layer (amorphous silicon) are made to coincide.
- the second amorphous semiconductor layers 171 and 172 are brought into direct contact with the side surfaces of the channel layer 140, and the contact layers 181 and 182 are further contacted with the side surfaces of the channel layer 140 via the second amorphous semiconductor layers 171 and 172. Contact. For this reason, carrier injection from the channel layer 140 is not dominant, and current injection can be performed directly from the end face of the channel layer 140.
- the current path when a voltage is applied to the gate electrode 120, the current path includes the source electrode 191, the contact layer 181, the second amorphous semiconductor layer 171, the channel layer 140, the second amorphous semiconductor layer 172, the contact layer 182, And the drain electrode 192.
- the high resistance first amorphous semiconductor layer 150 can be removed from the current path, the on-resistance can be reduced.
- the thin film semiconductor device 100 it is possible to achieve both improvement in carrier injection characteristics and suppression of parasitic capacitance.
- the off characteristics can be improved by increasing the band gap of the second amorphous semiconductor layers 171 and 172.
- the first amorphous semiconductor layer 150 having a high localized state density and the second amorphous semiconductor layers 171 and 172 having a large band gap an amorphous state can be obtained as in the prior art.
- the performance of the thin film semiconductor device 100 is greatly improved. Can be improved.
- FIGS. 3A to 3K are cross-sectional views schematically showing the configuration of each step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
- a substrate 110 is prepared.
- an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the substrate 110 by plasma CVD or the like before forming the gate electrode 120.
- a gate electrode 120 having a predetermined shape is formed on the substrate 110.
- a gate metal film made of MoW is formed on the substrate 110 by sputtering, and the gate metal film is patterned using a photolithography method and a wet etching method, whereby the gate electrode 120 having a predetermined shape can be formed.
- MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water are mixed in a predetermined composition.
- a gate insulating film 130 is formed over the entire upper surface of the substrate 110 so as to cover the gate electrode 120.
- the gate insulating film 130 made of silicon oxide is formed by plasma CVD or the like. Silicon oxide can be formed, for example, by introducing silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) at a predetermined concentration ratio.
- a crystalline silicon thin film 140 ⁇ / b> M that becomes the channel layer 140 is formed over the entire upper surface of the gate insulating film 130.
- the crystalline silicon thin film 140M for example, an amorphous silicon thin film made of amorphous silicon (amorphous silicon) is formed by plasma CVD or the like, and after dehydrogenation annealing treatment, the amorphous silicon thin film is annealed to be crystallized. Can be formed.
- the amorphous silicon thin film can be formed, for example, by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio.
- the amorphous silicon thin film is crystallized by laser annealing using an excimer laser.
- a laser annealing method using a pulse laser having a wavelength of about 370 to 900 nm, a wavelength of A laser annealing method using a continuous wave laser of about 370 to 900 nm or an annealing method by rapid thermal processing (RTP) may be used.
- the crystalline silicon thin film 140M may be formed by a method such as direct growth by CVD.
- a hydrogen plasma process is performed on the crystalline silicon thin film 140M to perform a hydrogenation process on silicon atoms in the crystalline silicon thin film 140M.
- hydrogen plasma is generated by radio frequency (RF) power using a gas containing hydrogen gas such as H 2 or H 2 / argon (Ar) as a raw material, and the crystalline silicon thin film 140M is irradiated with the hydrogen plasma. Is done.
- a first amorphous silicon film 150M which is a precursor film of the first amorphous semiconductor layer 150, is formed over the entire upper surface of the crystalline silicon thin film 140M.
- the first amorphous silicon film 150M can be formed by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio by, for example, CVD.
- the first amorphous silicon film 150M is formed by using a parallel plate RF plasma CVD apparatus, for example, with a predetermined concentration ratio of silane gas (SiH 4 ) and hydrogen gas (H 2 ), and a silane gas flow rate of 5 to 15 sccm. Then, the hydrogen gas is introduced at a flow rate of 40 to 75 sccm, the pressure is set to 1 to 5 Torr, the RF power is set to 0.1 to 0.4 kw / cm ⁇ 2, and the distance between the electrode substrates is set to 200 to 600 mm. be able to.
- a parallel plate RF plasma CVD apparatus for example, with a predetermined concentration ratio of silane gas (SiH 4 ) and hydrogen gas (H 2 ), and a silane gas flow rate of 5 to 15 sccm. Then, the hydrogen gas is introduced at a flow rate of 40 to 75 sccm, the pressure is set to 1 to 5 Torr, the RF power is set to 0.1 to 0.4
- the flow rate of silane gas and the flow rate of hydrogen gas is 1: 7
- the pressure is 5 Torr
- the RF power is 0.2 kW. / Cm ⁇ 2 and the distance between the electrode substrates is 300 mm.
- the first amorphous silicon film 150M has a high absorptance with respect to light in an exposure process described later. Therefore, if the first amorphous silicon film 150M is too thick, the exposure amount necessary for the insulating film 160M does not reach and exposure may be insufficient. Alternatively, there is a concern that a long exposure process is required to obtain a necessary exposure amount, and productivity is significantly reduced. Therefore, the thickness of the first amorphous silicon film 150M is desirably 50 nm or less. However, if the amount of light used in the exposure process is increased, the thickness of the first amorphous silicon film 150M can be 50 nm or more.
- an insulating film 160M to be the channel protective layer 160 is formed over the entire upper surface of the first amorphous silicon film 150M.
- an organic material as a precursor of the channel protective layer 160 is applied on the first amorphous silicon film 150M by a predetermined coating method, and spin coating or slit coating is performed to thereby apply the first amorphous silicon film 150M.
- An insulating film 160M is formed over the entire upper surface.
- the film thickness of the organic material can be controlled by the viscosity of the organic material and the coating conditions (rotation speed, blade speed, etc.). Note that as a material of the insulating film 160M, a photosensitive coating organic material containing silicon, oxygen, and carbon can be used.
- pre-baking is performed on the insulating film 160M at a temperature of about 110 ° C. for about 60 seconds to pre-fire the insulating film 160M.
- the solvent contained in the insulating film 160M is vaporized.
- the gate electrode 120 is used as a mask to irradiate the insulating film 160M with light for exposing the insulating film 160M from the back surface (the surface opposite to the surface on which the gate electrode 120 is formed) of the substrate 110, thereby exposing the insulating film 160M.
- a channel protective layer 160 having a predetermined shape is formed in a region overlapping with the gate electrode 120 as shown in FIG. 3G.
- post-baking is performed on the patterned channel protection layer 160 at a temperature of 280 ° C. to 300 ° C. for about 1 hour, and the channel protection layer 160 is finally baked and solidified. Thereby, a part of the organic component is vaporized and decomposed, and the channel protective layer 160 with improved film quality can be formed.
- the gate electrode 120 formed of a light-shielding conductive material as a mask, the external contour lines of the gate electrode 120 and the lower surface of the channel protective layer 160 are matched so as to match each other. Aligned. Thereby, since the gate electrode 120 does not overlap with the source electrode 191 and the drain electrode 192 in the left and right regions of the channel protective layer 160, the parasitic capacitance generated in this region can be reduced.
- the channel protective layer 160 becomes smaller than the desired size by ⁇ L, as shown in FIG. That is, the outer contour line on the lower surface of the channel protective layer 160 recedes inside the outer contour line on the upper surface of the gate electrode 120. Further, since the channel layer 140 and the first amorphous semiconductor layer 150 are formed using the channel protective layer 160 as a mask as will be described later, like the channel protective layer 160, the inside of the outline of the gate electrode 120. Retreat to.
- the stacking relationship of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 will be described with reference to FIG. In FIG. 4, the illustration of the gate insulating film 130 and the like is omitted.
- ⁇ L 0.5 ⁇ m that occurs during the manufacturing process is included in the range of “the outline contours match”.
- ⁇ L may be set to be equal to or greater than the film thickness of the second amorphous semiconductor layers 171 and 172. Accordingly, the second amorphous semiconductor layer 171 is formed at a position overlapping with the gate electrode 120, so that the on-resistance can be reduced.
- ⁇ L in this embodiment may be 0 (the outer contour lines of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 are completely matched).
- the thickness may be set to be not less than the thickness of the second amorphous semiconductor layers 171 and 172 and not more than 0.5 ⁇ m.
- the channel protective layer 160 By using the channel protective layer 160 as a mask, the outer contour lines of the channel layer 140 and the first amorphous semiconductor layer 150 coincide with the outer contour line of the lower surface of the channel protective layer 160 by self-alignment. As a result, the second amorphous semiconductor layers 171 and 172 formed in the steps described later can be in direct contact with the side surface of the channel layer 140. As a result, the high-resistance first amorphous semiconductor layer 150 is not included in the current path between the source electrode 191 and the drain electrode 192 and the channel layer 140, so that the on-resistance can be reduced.
- an intrinsic second amorphous silicon film 170M to be a pair of second amorphous semiconductor layers 171 and 172 is formed so as to cover the channel protective layer 160 and the gate insulating film 130.
- the intrinsic second amorphous silicon film 170M can be formed by plasma CVD or the like, for example.
- the intrinsic second amorphous silicon film 170M can be formed, for example, by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio.
- the flow rate of silane gas and the flow rate of hydrogen gas is 6: 1, the pressure is 5 Torr, and the RF power is 0.03 kW. / Cm ⁇ 2 and the distance between the electrode substrates is 525 mm.
- the first amorphous semiconductor layer 150 having a relatively high localized level density.
- the second amorphous semiconductor layers 171 and 172 having a relatively large band gap can be obtained.
- a contact layer film 180M to be the contact layers 181 and 182 is formed over the entire upper surface of the intrinsic second amorphous silicon film 170M.
- a contact layer film 180M made of amorphous silicon doped with an impurity of a pentavalent element such as phosphorus is formed by plasma CVD.
- the contact layer film 180M may be composed of two layers, a lower-layer low-concentration electric field relaxation layer and an upper-layer high-concentration contact layer.
- the low-concentration electric field relaxation layer can be formed by doping about 1 ⁇ 10 17 [atm / cm 3 ] phosphorus.
- the two layers can be formed continuously in, for example, a CVC apparatus.
- a source electrode 191 and a drain electrode 192 are patterned on the contact layer film 180M.
- a source / drain metal film made of a material to be the source electrode 191 and the drain electrode 192 is formed by sputtering, for example.
- a resist patterned in a predetermined shape is formed on the source / drain metal film, and wet etching is performed to pattern the source / drain metal film.
- the contact layer film 180M functions as an etching stopper. After that, by removing the resist, the source electrode 191 and the drain electrode 192 having a predetermined shape can be formed.
- the contact layer film 180M and the intrinsic second amorphous silicon film 170M are patterned in an island shape by performing dry etching using the source electrode 191 and the drain electrode 192 as a mask.
- the pair of contact layers 181 and 182 and the pair of second amorphous semiconductor layers 171 and 172 can be formed in a predetermined shape.
- a chlorine-based gas may be used for dry etching.
- a pair of contact layers 181 and 182 and a pair of second amorphous semiconductor layers 171 and 172 are formed under the source electrode 191 and the drain electrode 192.
- the thin film semiconductor device according to the embodiment of the present invention as shown in FIG. 1 can be manufactured.
- FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment of the present invention.
- the thin film semiconductor device 100 described above can be used as a switching transistor or a driving transistor of an active matrix substrate in an organic EL display device.
- the organic EL display device 10 corresponds to an active matrix substrate (TFT array substrate) 11, a plurality of pixels 12 arranged in a matrix on the active matrix substrate 11, and a plurality of pixels 12.
- the organic EL elements 13 formed in this way, the plurality of scanning lines (gate lines) 17 formed along the row direction of the pixels 12, and the plurality of video signal lines (sources) formed along the column direction of the pixels 12. Line) 18 and a power line 19 (not shown) formed in parallel with the video signal line 18.
- the organic EL element 13 includes an anode 14, an organic EL layer 15, and a cathode 16 (transparent electrode) that are sequentially stacked on the active matrix substrate 11. Note that a plurality of anodes 14 are actually formed corresponding to each pixel 12.
- the organic EL layer 15 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.
- FIG. 6 is a diagram showing a circuit configuration of a pixel using the thin film semiconductor device 100 according to the embodiment of the present invention.
- each pixel 12 is partitioned by orthogonal scanning lines 17 and video signal lines 18, and includes a drive transistor 21, a switching transistor 22, a capacitor 23, and an organic EL element 13. .
- the drive transistor 21 is a transistor for driving the organic EL element 13
- the switching transistor 22 is a transistor for selecting the pixel 12.
- One or both of the drive transistor 21 and the switching transistor 22 can be configured by the thin film semiconductor device 100 shown in FIG.
- the gate electrode 21G is connected to the drain electrode 22D of the switching transistor 22, the source electrode 21S is connected to the anode of the organic EL element 13 via a relay electrode (not shown), and the drain electrode 21D is connected to the power supply line 19. Connected to.
- the gate electrode 22G is connected to the scanning line 17
- the source electrode 22S is connected to the video signal line 18
- the drain electrode 22D is connected to the capacitor 23 and the gate electrode 21G of the driving transistor 21.
- the video signal voltage supplied via the video signal line 18 is written to the capacitor 23.
- the video signal voltage written in the capacitor 23 is held as a holding voltage throughout one frame period. Due to this holding voltage, the conductance of the drive transistor 21 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 13. Thereby, the organic EL element 13 emits light and a predetermined image is displayed.
- the present invention can also be applied to other display devices using an active matrix substrate such as a liquid crystal display device.
- the display device configured as described above can be used as a flat panel display and can be applied to an electronic apparatus having any display panel such as a television set, a personal computer, and a mobile phone.
- the silicon thin film is used as the semiconductor film (semiconductor layer).
- a semiconductor film other than the silicon thin film can be used.
- a polycrystalline semiconductor film can be formed by crystallizing a semiconductor film made of germanium (Ge) or SiGe.
- the present invention is useful for thin film semiconductor devices such as thin film transistors, and can be widely used in display devices such as organic EL display devices and liquid crystal display devices.
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Abstract
A thin film semiconductor device (100) is provided with a gate electrode (120), a channel layer (140), a first amorphous semiconductor layer (150), a channel protection layer (160), a pair of second amorphous semiconductor layers (171, 172) formed on both side surfaces of the channel layer (140), and a pair of contact layers (181, 182) that comes into contact with the side surfaces of the channel layer (140) with the second amorphous semiconductor layers (171, 172) therebetween, wherein: the gate electrode (120), the channel layer (140), the fist amorphous semiconductor layer (150), and the channel protection layer (160) are laminated in a manner such that the contours thereof overlap when viewed from above; the local energy level density of the first amorphous semiconductor layer (150) is higher than the local energy level densities of the second amorphous semiconductor layers (171, 172); and the band gaps of the second amorphous semiconductor layers (171, 172) are greater than the band gap of the first amorphous semiconductor layer (150).
Description
本発明は、薄膜半導体装置に関し、特に、表示装置の画素回路に用いられる薄膜半導体装置に関するものである。
The present invention relates to a thin film semiconductor device, and more particularly to a thin film semiconductor device used in a pixel circuit of a display device.
近年、液晶ディスプレイに変わる次世代フラットパネルディスプレイの一つとしての有機材料のＥＬ（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ）を利用した有機ＥＬディスプレイが注目されている。
In recent years, an organic EL display using an organic material EL (Electro Luminescence) as one of the next generation flat panel displays replacing the liquid crystal display has been attracting attention.
有機ＥＬディスプレイは、電圧駆動型の液晶ディスプレイと異なり、電流駆動型のディスプレイデバイスである。このことから、アクティブマトリクス方式の表示装置の駆動回路として優れた特性を有する薄膜トランジスタ（ＴＦＴ：Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ）の開発が急がれている。薄膜トランジスタは、画素を選択するスイッチング素子、或いは画素を駆動する駆動トランジスタ等として用いられる。
Organic EL displays are current-driven display devices, unlike voltage-driven liquid crystal displays. For this reason, development of a thin film transistor (TFT: Thin Film Transistor) having excellent characteristics as a drive circuit for an active matrix display device has been urgently required. The thin film transistor is used as a switching element for selecting a pixel, a driving transistor for driving the pixel, or the like.
図７を参照して、従来の薄膜半導体装置（薄膜トランジスタ）の構成を説明する(例えば、特許文献１、２参照)。図７に示される薄膜半導体装置９００は、基板９１０と、ゲート電極９２０と、ゲート絶縁膜９３０と、結晶シリコン層９４０と、非結晶シリコン層９５０と、チャネル保護層９６０と、一対のコンタクト層９７１、９７２と、ソース電極９８１及びドレイン電極９８２とを、この順に積層して構成されるボトムゲート型の薄膜トランジスタである。
Referring to FIG. 7, the configuration of a conventional thin film semiconductor device (thin film transistor) will be described (see, for example, Patent Documents 1 and 2). A thin film semiconductor device 900 shown in FIG. 7 includes a substrate 910, a gate electrode 920, a gate insulating film 930, a crystalline silicon layer 940, an amorphous silicon layer 950, a channel protective layer 960, and a pair of contact layers 971. 972, a source electrode 981 and a drain electrode 982 are stacked in this order, and are bottom-gate thin film transistors.
上記構成の薄膜半導体装置９００では、チャネル保護層９６０に正の固定電荷が存在する。このため、この固定電荷によってチャネル領域を含む結晶シリコン層９４０にバックチャネルが形成されてリーク電流が発生し、オフ特性が劣化する。ここで、バックチャネルとは、結晶シリコン層９４０内のチャネル保護層９６０との界面付近を経由して、ソース電極９８１からドレイン電極９８２に向かって流れる寄生電流の経路のことである。
In the thin film semiconductor device 900 having the above configuration, positive fixed charges exist in the channel protective layer 960. For this reason, a back channel is formed in the crystalline silicon layer 940 including the channel region by this fixed charge, a leak current is generated, and the off-characteristic is deteriorated. Here, the back channel is a path of a parasitic current flowing from the source electrode 981 toward the drain electrode 982 via the vicinity of the interface with the channel protective layer 960 in the crystalline silicon layer 940.
そこで、結晶シリコン層９４０とチャネル保護層９６０との間に、アモルファスシリコン膜からなる非結晶シリコン層９５０を形成する。この非結晶シリコン層９５０は、負キャリアの電荷密度によってチャネル保護層９６０の正の固定電荷を相殺して電界遮蔽を行うことができる。これにより、バックチャネルの形成を抑制することができ、オフ時のリーク電流を抑制することができるので、オフ特性を向上させることができる。
Therefore, an amorphous silicon layer 950 made of an amorphous silicon film is formed between the crystalline silicon layer 940 and the channel protective layer 960. The amorphous silicon layer 950 can perform electric field shielding by offsetting the positive fixed charge of the channel protective layer 960 by the charge density of negative carriers. Thereby, the formation of a back channel can be suppressed and the leakage current at the time of OFF can be suppressed, so that the OFF characteristics can be improved.
しかしながら、従来の薄膜半導体装置では、オフ時のリーク電流を抑制してオフ特性を向上させると共に、オン抵抗を低減することは難しい。
However, in the conventional thin film semiconductor device, it is difficult to suppress the leakage current at the time of off and improve the off characteristics and reduce the on-resistance.
本発明は、上記の課題に鑑みてなされたものであり、オフ時のリーク電流を抑制してオフ特性を向上させると共に、オン抵抗を低減した薄膜半導体装置を提供することを目的とする。
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a thin film semiconductor device in which the off-current is improved by suppressing the leakage current at the off time and the on-resistance is reduced.
本発明の一形態に係る薄膜半導体装置は、基板と、前記基板上に形成されたゲート電極と、前記ゲート電極上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された多結晶半導体からなるチャネル層と、前記チャネル層上に形成された第１非晶質半導体層と、前記第１非晶質半導体層上に形成された有機絶縁層と、前記第１非晶質半導体層及び前記チャネル層の一方側の側面及び他方側の側面のそれぞれに形成された一対の第２非晶質半導体層と、前記一対の第２非晶質半導体層それぞれの上に、前記第２非晶質半導体層を介して前記チャネル層の側面にコンタクトするように形成された一対のコンタクト層と、前記一対のコンタクト層の一方の上に形成されたソース電極、及び前記コンタクト層の他方の上に形成されたドレイン電極とを備え、前記ゲート電極、前記チャネル層、前記第１非晶質半導体層、及び前記有機絶縁層は、上面視したときに外形輪郭線が一致するように積層され、前記第１非晶質半導体層の局在準位密度は、前記第２非晶質半導体層の局在準位密度より高く、前記第２非晶質半導体層のバンドギャップは、前記第１非晶質半導体層のバンドギャップより大きいことを特徴とする。
A thin film semiconductor device according to one embodiment of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a polycrystal formed on the gate insulating film. A channel layer made of a semiconductor, a first amorphous semiconductor layer formed on the channel layer, an organic insulating layer formed on the first amorphous semiconductor layer, and the first amorphous semiconductor layer And a pair of second amorphous semiconductor layers formed on one side surface and the other side surface of the channel layer, and the second non-crystalline semiconductor layer on each of the pair of second amorphous semiconductor layers. A pair of contact layers formed to contact a side surface of the channel layer through a crystalline semiconductor layer; a source electrode formed on one of the pair of contact layers; and the other of the contact layer Drain formed on The gate electrode, the channel layer, the first amorphous semiconductor layer, and the organic insulating layer are stacked so that outlines thereof coincide when viewed from above, and the first amorphous The localized state density of the crystalline semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer, and the band gap of the second amorphous semiconductor layer is the same as that of the first amorphous semiconductor layer. It is characterized by being larger than the band gap.
本発明によれば、オフ時のリーク電流を抑制してオフ特性を向上させると共に、オン抵抗を低減した薄膜半導体装置を得ることができる。
According to the present invention, it is possible to obtain a thin film semiconductor device in which the off-current is improved by suppressing the leakage current at the off time and the on-resistance is reduced.
（本開示に至った経緯）
図７に示す従来の薄膜半導体装置９００において、チャネル保護層９６０として有機材料を用いる場合、非結晶シリコン層９５０には、高い局在準位密度と高いバンドギャップとが要求される。しかしながら、単一の層からなる非結晶シリコン層９５０によってこのような性能を実現するのは極めて困難である。 (Background to the disclosure)
In the conventional thinfilm semiconductor device 900 shown in FIG. 7, when an organic material is used as the channel protective layer 960, the amorphous silicon layer 950 is required to have a high local level density and a high band gap. However, it is extremely difficult to realize such a performance by the amorphous silicon layer 950 made of a single layer.
図７に示す従来の薄膜半導体装置９００において、チャネル保護層９６０として有機材料を用いる場合、非結晶シリコン層９５０には、高い局在準位密度と高いバンドギャップとが要求される。しかしながら、単一の層からなる非結晶シリコン層９５０によってこのような性能を実現するのは極めて困難である。 (Background to the disclosure)
In the conventional thin
また、上記構成の薄膜半導体装置９００によれば、チャネル領域を含む結晶シリコン層９４０とソース電極９８１及びドレイン電極９８２との間に非結晶シリコン層９５０が介在している。すなわち、高抵抗の非結晶シリコン層９５０が電流パスに含まれるため、オン抵抗が高くなってしまう。
Further, according to the thin film semiconductor device 900 having the above structure, the amorphous silicon layer 950 is interposed between the crystalline silicon layer 940 including the channel region and the source electrode 981 and the drain electrode 982. That is, since the high-resistance amorphous silicon layer 950 is included in the current path, the on-resistance is increased.
本発明は、オフ時のリーク電流を抑制してオフ特性を向上させると共に、オン抵抗を低減した薄膜半導体装置を提供することを目的とする。
An object of the present invention is to provide a thin film semiconductor device in which an off characteristic is improved by suppressing a leakage current at an off time and an on-resistance is reduced.
上記目的を達成するために、本発明の一形態に係る薄膜半導体装置は、基板と、前記基板上に形成されたゲート電極と、前記ゲート電極上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成された多結晶半導体からなるチャネル層と、前記チャネル層上に形成された第１非晶質半導体層と、前記第１非晶質半導体層上に形成された有機絶縁層と、前記第１非晶質半導体層及び前記チャネル層の一方側の側面及び他方側の側面のそれぞれに形成された一対の第２非晶質半導体層と、前記一対の第２非晶質半導体層それぞれの上に、前記第２非晶質半導体層を介して前記チャネル層の側面にコンタクトするように形成された一対のコンタクト層と、前記一対のコンタクト層の一方の上に形成されたソース電極、及び前記コンタクト層の他方の上に形成されたドレイン電極とを備え、前記ゲート電極、前記チャネル層、前記第１非晶質半導体層、及び前記有機絶縁層は、上面視したときに外形輪郭線が一致するように積層され、前記第１非晶質半導体層の局在準位密度は、前記第２非晶質半導体層の局在準位密度より高く、前記第２非晶質半導体層のバンドギャップは、前記第１非晶質半導体層のバンドギャップより大きいことを特徴とする。
In order to achieve the above object, a thin film semiconductor device according to one embodiment of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and the gate insulation. A channel layer made of a polycrystalline semiconductor formed on the film, a first amorphous semiconductor layer formed on the channel layer, an organic insulating layer formed on the first amorphous semiconductor layer, A pair of second amorphous semiconductor layers formed on one side surface and the other side surface of the first amorphous semiconductor layer and the channel layer, respectively, and the pair of second amorphous semiconductor layers, respectively. A pair of contact layers formed to contact the side surface of the channel layer through the second amorphous semiconductor layer, and a source electrode formed on one of the pair of contact layers, And other contact layers And the gate electrode, the channel layer, the first amorphous semiconductor layer, and the organic insulating layer are stacked so that outlines thereof coincide when viewed from above. The localized level density of the first amorphous semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer, and the band gap of the second amorphous semiconductor layer is It is characterized by being larger than the band gap of one amorphous semiconductor layer.
上記構成によれば、チャネル保護層の左右の領域でゲート電極とソース電極及びドレイン電極とが重畳しないので、この領域の寄生容量を削減することができる。また、コンタクト層を第２非晶質半導体層を介してチャネル層の側面とコンタクトさせている。これにより、高抵抗の第１非晶質半導体層を電流パスから外すことができるので、オン抵抗を低減することができる。さらに、局在準位密度を高くした第１非晶質半導体層と、バンドギャップを大きくした第２非晶質半導体層とを設けることにより、薄膜半導体装置の性能を飛躍的に向上させることができる。
According to the above configuration, since the gate electrode, the source electrode, and the drain electrode do not overlap in the left and right regions of the channel protective layer, the parasitic capacitance in this region can be reduced. The contact layer is in contact with the side surface of the channel layer through the second amorphous semiconductor layer. As a result, the first amorphous semiconductor layer having high resistance can be removed from the current path, so that the on-resistance can be reduced. Furthermore, by providing the first amorphous semiconductor layer having a high localized state density and the second amorphous semiconductor layer having a large band gap, the performance of the thin film semiconductor device can be dramatically improved. it can.
さらに、本発明の一形態に係る薄膜半導体装置において、前記有機絶縁層の下面の外形輪郭線は、上面視したときに、前記ゲート電極の外形輪郭線の内側に、０．５μｍ以下後退していてもよい。
Furthermore, in the thin film semiconductor device according to one embodiment of the present invention, the outline of the lower surface of the organic insulating layer recedes by 0.5 μm or less inside the outline of the gate electrode when viewed from above. May be.
なお、本明細書において、製造プロセスによって生じる０．５μｍ程度の誤差は、「外形輪郭線が一致する」の範囲内に含めるものとする。
In this specification, an error of about 0.5 μm caused by the manufacturing process is included in the range of “the outline contours match”.
さらに、本発明の一形態に係る薄膜半導体装置において、前記有機絶縁層の下面の外形輪郭線は、上面視したときに、前記ゲート電極の外形輪郭線の内側に、前記第２非晶質半導体層の膜厚以上後退していてもよい。
Furthermore, in the thin film semiconductor device according to an aspect of the present invention, the outer contour line on the lower surface of the organic insulating layer is located inside the outer contour line of the gate electrode when viewed from above. It may be set back more than the thickness of the layer.
これにより、第２非晶質半導体層がゲート電極に重畳する位置に形成されることになるので、オン抵抗を低減することができる。
Thereby, since the second amorphous semiconductor layer is formed at a position overlapping the gate electrode, the on-resistance can be reduced.
また、本発明の一形態に係る薄膜半導体装置において、前記一対の第２非晶質半導体層、前記一対のコンタクト層、前記ソース電極、及び前記ドレイン電極は、前記有機絶縁層の上面の一部および前記有機絶縁層の側面に延在していてもよい。
In the thin film semiconductor device according to one embodiment of the present invention, the pair of second amorphous semiconductor layers, the pair of contact layers, the source electrode, and the drain electrode are part of an upper surface of the organic insulating layer. And may extend on a side surface of the organic insulating layer.
また、本発明の一形態に係る薄膜半導体装置において、前記第１非晶質半導体層の膜厚は、５０ｎｍ以下であってもよい。
In the thin film semiconductor device according to one embodiment of the present invention, the film thickness of the first amorphous semiconductor layer may be 50 nm or less.
第１非晶質半導体層は、露光工程での光に対しての吸収率が高く、厚くしすぎると、有機絶縁層に必要な露光量が届かず、露光が不十分になってしまう恐れがある。もしくは、必要な露光量を得るために長時間の露光工程が必要になってしまい、生産性を著しく落としてしまう懸念がある。但し、第１非晶質半導体層の厚みは、露光工程で用いる光の光量を強くすれば５０ｎｍ以上とすることもできる。
The first amorphous semiconductor layer has a high light absorption rate in the exposure process, and if it is too thick, the exposure amount required for the organic insulating layer does not reach and exposure may be insufficient. is there. Alternatively, there is a concern that a long exposure process is required to obtain a necessary exposure amount, and productivity is significantly reduced. However, the thickness of the first amorphous semiconductor layer can be 50 nm or more if the amount of light used in the exposure process is increased.
また、本発明の一形態に係る薄膜半導体装置の製造方法は、基板を準備する第１工程と、前記基板上にゲート電極と形成する第２工程と、前記ゲート電極上にゲート絶縁膜を形成する第３工程と、前記ゲート絶縁膜上に結晶半導体層を形成する第４工程と、前記結晶半導体層上に、非晶質半導体層を形成する第５工程と、前記非晶質半導体層上に、有機絶縁層を形成する第６工程と、前記結晶半導体層および前記非晶質半導体層をエッチングして、前記ゲート電極に重畳する位置にチャネル層及び第１非晶質半導体層を形成する第７工程と、前記チャネル層及び前記第１非晶質半導体層の一方側の側面及び他方側の側面のそれぞれに第２非晶質半導体層を形成する第８工程と、前記一対の第２非晶質半導体層それぞれの上に、前記第２非晶質半導体層を介して前記チャネル層の側面にコンタクトするように一対のコンタクト層を形成する第９工程と、前記一対のコンタクト層の一方の上にソース電極を形成し、及び前記一対のコンタクト層の他方の上にドレイン電極を形成する第９工程とを含み、前記第６工程では、前記非晶質半導体層上に有機絶縁層の前駆体の有機材料を塗布し、乾燥させる工程と、前記基板の前記ゲート電極が形成された面と反対側の面から、前記有機材料に対して前記ゲート電極をマスクに用いて前記有機材料を感光させる光で露光する工程と、前記有機材料を現像する工程とにより、前記有機絶縁層の下面の外形輪郭線が、上面視したときに、前記ゲート電極の外形輪郭線の内側に後退するように形成することを特徴とする。
The method for manufacturing a thin film semiconductor device according to an aspect of the present invention includes a first step of preparing a substrate, a second step of forming a gate electrode on the substrate, and forming a gate insulating film on the gate electrode. A third step of forming a crystalline semiconductor layer on the gate insulating film, a fifth step of forming an amorphous semiconductor layer on the crystalline semiconductor layer, and on the amorphous semiconductor layer And a sixth step of forming an organic insulating layer, and etching the crystalline semiconductor layer and the amorphous semiconductor layer to form a channel layer and a first amorphous semiconductor layer at a position overlapping with the gate electrode. A seventh step, an eighth step of forming a second amorphous semiconductor layer on each of the one side surface and the other side surface of the channel layer and the first amorphous semiconductor layer, and the pair of second layers The second amorphous layer is formed on each of the amorphous semiconductor layers. A ninth step of forming a pair of contact layers so as to contact the side surfaces of the channel layer via a semiconductor layer; forming a source electrode on one of the pair of contact layers; and A ninth step of forming a drain electrode on the other, and in the sixth step, a step of applying an organic material as a precursor of an organic insulating layer on the amorphous semiconductor layer and drying, and the substrate A step of exposing the organic material to light from the surface opposite to the surface on which the gate electrode is formed, using the gate electrode as a mask to expose the organic material, and a step of developing the organic material Thus, the outer contour line on the lower surface of the organic insulating layer is formed so as to recede to the inner side of the outer contour line of the gate electrode when viewed from above.
また、本発明の一形態に係る薄膜半導体装置の製造方法において、前記第７工程において、現像された前記有機絶縁層をマスクに用いて前記エッチングを行うことにより、前記有機絶縁層の下面の外形輪郭線が、上面視したときに、前記ゲート電極の外形輪郭線の内側に、前記第２非晶質半導体層の膜厚以上後退するように形成してもよい。
Further, in the method of manufacturing a thin film semiconductor device according to one aspect of the present invention, in the seventh step, the etching is performed using the developed organic insulating layer as a mask, whereby an outer shape of the lower surface of the organic insulating layer is formed. The outline may be formed so as to recede by more than the thickness of the second amorphous semiconductor layer inside the outline outline of the gate electrode when viewed from above.
また、本発明の一形態に係る薄膜半導体装置の製造方法において、前記第１非晶質半導体層の局在準位密度は、前記第２非晶質半導体層の局在準位密度より高くなるように形成され、前記第２非晶質半導体層のバンドギャップは、前記第１非晶質半導体層のバンドギャップより大きくなるように形成されてもよい。
In the method for manufacturing a thin film semiconductor device according to one embodiment of the present invention, the localized level density of the first amorphous semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer. The band gap of the second amorphous semiconductor layer may be larger than the band gap of the first amorphous semiconductor layer.
（実施の形態）
以下、図面を参照して、本発明に係る薄膜半導体装置及びその製造方法を説明する。なお、以下で説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。従って、以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程、工程の順序などは、一例であり、本発明を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、請求項に記載されていない構成要素は、本発明の課題を達成するのに必ずしも必要ではない。また、各図は模式図であり、必ずしも厳密に図示したものではない。なお、各図面において、実質的に同一の構成、動作、及び効果を表す要素については、同一の符号を付す。 (Embodiment)
Hereinafter, a thin film semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. Therefore, numerical values, shapes, materials, components, arrangement positions and connection forms of components, connection steps, steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Therefore, among the constituent elements in the following embodiments, constituent elements not described in the claims are not necessarily required to achieve the object of the present invention. Each figure is a mimetic diagram and is not necessarily illustrated strictly. In addition, in each drawing, the same code | symbol is attached | subjected about the element showing substantially the same structure, operation | movement, and an effect.
以下、図面を参照して、本発明に係る薄膜半導体装置及びその製造方法を説明する。なお、以下で説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。従って、以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程、工程の順序などは、一例であり、本発明を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、請求項に記載されていない構成要素は、本発明の課題を達成するのに必ずしも必要ではない。また、各図は模式図であり、必ずしも厳密に図示したものではない。なお、各図面において、実質的に同一の構成、動作、及び効果を表す要素については、同一の符号を付す。 (Embodiment)
Hereinafter, a thin film semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. Therefore, numerical values, shapes, materials, components, arrangement positions and connection forms of components, connection steps, steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Therefore, among the constituent elements in the following embodiments, constituent elements not described in the claims are not necessarily required to achieve the object of the present invention. Each figure is a mimetic diagram and is not necessarily illustrated strictly. In addition, in each drawing, the same code | symbol is attached | subjected about the element showing substantially the same structure, operation | movement, and an effect.
まず、図１を参照して、本発明の実施の形態に係る薄膜半導体装置１００の構成を説明する。図１は、本実施の形態に係る薄膜半導体装置１００の模式的な構成を示す断面図である。
First, the configuration of a thin film semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a schematic configuration of a thin film semiconductor device 100 according to the present embodiment.
薄膜半導体装置１００は、図１に示されるように、基板１１０と、ゲート電極１２０と、ゲート絶縁膜１３０と、チャネル層１４０と、第１非晶質半導体層１５０と、チャネル保護層１６０と、一対の第２非晶質半導体層１７１、１７２と、一対のコンタクト層１８１、１８２と、ソース電極１９１及びドレイン電極１９２とを、この順に積層して構成されるボトムゲート型の薄膜トランジスタである。
As shown in FIG. 1, the thin film semiconductor device 100 includes a substrate 110, a gate electrode 120, a gate insulating film 130, a channel layer 140, a first amorphous semiconductor layer 150, a channel protective layer 160, The bottom-gate thin film transistor includes a pair of second amorphous semiconductor layers 171 and 172, a pair of contact layers 181 and 182, and a source electrode 191 and a drain electrode 192 that are stacked in this order.
基板１１０は、例えば、石英ガラス、無アルカリガラス、高耐熱性ガラス等のガラス材料からなるガラス基板である。なお、ガラス基板の中に含まれるナトリウムやリン等の不純物がチャネル層１４０に侵入することを防止するために、基板１１０上にシリコン窒化膜（ＳｉＮｘ）、酸化シリコン（ＳｉＯｙ）又はシリコン酸窒化膜（ＳｉＯｙＮｘ）等からなるアンダーコート層を形成してもよい。また、アンダーコート層は、レーザアニールなどの高温熱処理プロセスにおいて、基板１１０への熱の影響を緩和させる役割を担うこともある。アンダーコート層の膜厚は、例えば１００ｎｍ～２０００ｎｍ程度とすることができる。
The substrate 110 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass. In order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the channel layer 140, a silicon nitride film (SiN x ), silicon oxide (SiO y ), or silicon acid is formed on the substrate 110. An undercoat layer made of a nitride film (SiO y N x ) or the like may be formed. In addition, the undercoat layer may play a role of mitigating the influence of heat on the substrate 110 in a high-temperature heat treatment process such as laser annealing. The film thickness of the undercoat layer can be, for example, about 100 nm to 2000 nm.
ゲート電極１２０は、基板１１０上に所定形状でパターン形成される。ゲート電極１２０を構成する材料としては、例えば、モリブデン（Ｍｏ）、アルミニウム（Ａｌ）、銅（Ｃｕ）、タングステン（Ｗ）、チタン（Ｔｉ）、クロム（Ｃｒ）、及びモリブデンタングステン（ＭｏＷ）等を用いることができる。ゲート電極１２０の膜厚は、例えば２０～５００ｎｍ程度とすることができる。
The gate electrode 120 is patterned in a predetermined shape on the substrate 110. Examples of the material constituting the gate electrode 120 include molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), chromium (Cr), and molybdenum tungsten (MoW). Can be used. The film thickness of the gate electrode 120 can be about 20 to 500 nm, for example.
ゲート絶縁膜１３０は、ゲート電極１２０を覆うように、基板１１０上の全面に形成される。ゲート絶縁膜１３０を構成する材料としては、例えば、酸化シリコン（ＳｉＯｙ）、窒化シリコン（ＳｉＮｘ）、シリコン酸窒化膜（ＳｉＯｙＮｘ）、酸化アルミニウム（ＡｌＯｚ）又は酸化タンタル（ＴａＯｗ）の単層膜又はこれらの積層膜によって構成することができる。ゲート絶縁膜１３０の膜厚は、例えば５０ｎｍ～３００ｎｍとすることができる。
The gate insulating film 130 is formed on the entire surface of the substrate 110 so as to cover the gate electrode 120. Examples of the material constituting the gate insulating film 130 include silicon oxide (SiO y ), silicon nitride (SiN x ), silicon oxynitride film (SiO y N x ), aluminum oxide (AlO z ), or tantalum oxide (TaO w). )) Or a laminated film thereof. The film thickness of the gate insulating film 130 can be set to, for example, 50 nm to 300 nm.
なお、本実施の形態では、後述するようにチャネル層１４０を結晶性シリコン薄膜で形成しているので、ゲート絶縁膜１３０に酸化シリコンを用いることが好ましい。酸化シリコンは、チャネル層１４０とゲート絶縁膜１３０との界面状態を良好にするのに適しており、これによって薄膜半導体装置１００の閾値電圧特性が向上する。
In this embodiment, since the channel layer 140 is formed of a crystalline silicon thin film as will be described later, it is preferable to use silicon oxide for the gate insulating film 130. Silicon oxide is suitable for improving the interface state between the channel layer 140 and the gate insulating film 130, thereby improving the threshold voltage characteristics of the thin film semiconductor device 100.
チャネル層１４０は、ゲート絶縁膜１３０上のゲート電極１２０に重畳する位置にパターン形成される半導体膜であって、ゲート電極１２０の電圧によってキャリアの移動が制御される領域である所定のチャネル領域を有する。
The channel layer 140 is a semiconductor film patterned at a position overlapping the gate electrode 120 on the gate insulating film 130, and a predetermined channel region that is a region in which carrier movement is controlled by the voltage of the gate electrode 120. Have.
本実施の形態において、ゲート電極１２０とチャネル層１４０とは、上面視したときに外形輪郭線が一致するように積層される。ここで、「外形輪郭線が一致する」とは、ゲート電極１２０とチャネル層１４０とが同一形状（形及び面積が同一）であって、且つゲート電極１２０とチャネル層１４０とが水平方向にズレることなく配置されていることを指す。
In the present embodiment, the gate electrode 120 and the channel layer 140 are stacked so that the outer contour lines match when viewed from above. Here, “the outer contour lines match” means that the gate electrode 120 and the channel layer 140 have the same shape (the same shape and area), and the gate electrode 120 and the channel layer 140 are displaced in the horizontal direction. It means that it is arranged without.
チャネル層１４０は、結晶性の組織構造を有する結晶性シリコン薄膜であって、微結晶シリコン薄膜又は多結晶シリコン薄膜からなる。チャネル層１４０は、例えば、非結晶性の非晶質シリコン（アモルファスシリコン）を結晶化することによって形成することができる。また、チャネル層１４０は、アモルファスシリコン（非結晶シリコン）と結晶性シリコンとの混晶構造を有するシリコン薄膜とすることができる。この場合、優れたオン特性を得るために、少なくともチャネル領域の結晶性シリコンの割合を多くするのが好ましい。チャネル層１４０の膜厚は、例えば、３０ｎｍ～２００ｎｍ程度とすることができる。なお、チャネル層１４０に含まれるシリコン結晶の主面方位は［１００］であることが好ましい。これにより、結晶性に優れたチャネル層１４０を形成することができる。
The channel layer 140 is a crystalline silicon thin film having a crystalline structure, and is made of a microcrystalline silicon thin film or a polycrystalline silicon thin film. The channel layer 140 can be formed by crystallizing amorphous amorphous silicon (amorphous silicon), for example. The channel layer 140 can be a silicon thin film having a mixed crystal structure of amorphous silicon (non-crystalline silicon) and crystalline silicon. In this case, in order to obtain excellent on characteristics, it is preferable to increase the ratio of crystalline silicon in at least the channel region. The film thickness of the channel layer 140 can be about 30 nm to 200 nm, for example. The principal plane orientation of the silicon crystal included in the channel layer 140 is preferably [100]. Thereby, the channel layer 140 having excellent crystallinity can be formed.
なお、チャネル層１４０における結晶シリコンの平均結晶粒径は、５ｎｍ～１０００ｎｍ程度であり、チャネル層１４０には、上記のような平均結晶粒径が１００ｎｍ以上の多結晶、あるいは、平均結晶粒径が１０ｎｍ～１００ｎｍのマイクロクリスタル（μｃ）と呼ばれる微結晶も含まれる。
Note that the average crystal grain size of crystalline silicon in the channel layer 140 is about 5 nm to 1000 nm. The channel layer 140 has a polycrystal having an average crystal grain size of 100 nm or more as described above, or an average crystal grain size. Also included are microcrystals called microcrystals (μc) of 10 nm to 100 nm.
第１非晶質半導体層１５０は、チャネル層１４０上にパターン形成される。本実施の形態において、ゲート電極１２０とチャネル層１４０と第１非晶質半導体層１５０とは、上面視したときに外形輪郭線が一致するように積層される。
The first amorphous semiconductor layer 150 is patterned on the channel layer 140. In the present embodiment, the gate electrode 120, the channel layer 140, and the first amorphous semiconductor layer 150 are stacked so that their outlines match when viewed from above.
第１非晶質半導体層１５０は、例えば、意図的に不純物のドーピングを行っていないアモルファスシリコン膜（真性アモルファスシリコン）によって形成されている。この第１非晶質半導体層１５０は、局在準位密度（トラップ密度）がチャネル層１４０より高く設定される。すなわち、第１非晶質半導体層１５０の負キャリアの電荷密度によってチャネル保護層１６０の正の固定電荷を相殺して電界遮蔽を行うことができる。これにより、バックチャネルの形成を抑制することができ、オフ時のリーク電流を抑制することができるので、薄膜半導体装置１００のオフ特性が向上する。
The first amorphous semiconductor layer 150 is formed of, for example, an amorphous silicon film (intrinsic amorphous silicon) that is not intentionally doped with impurities. The first amorphous semiconductor layer 150 is set to have a higher localized level density (trap density) than the channel layer 140. That is, the electric field shielding can be performed by offsetting the positive fixed charges of the channel protective layer 160 by the charge density of the negative carriers of the first amorphous semiconductor layer 150. Thereby, the formation of the back channel can be suppressed and the leakage current at the time of OFF can be suppressed, so that the OFF characteristics of the thin film semiconductor device 100 are improved.
チャネル保護層１６０は、第１非晶質半導体層１５０上のチャネル層１４０に重畳する位置にパターン形成される。本実施の形態において、ゲート電極１２０とチャネル層１４０と第１非晶質半導体層１５０とチャネル保護層１６０とは、上面視したときに外形輪郭線が一致するように積層される。
The channel protective layer 160 is patterned at a position overlapping the channel layer 140 on the first amorphous semiconductor layer 150. In this embodiment, the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 are stacked so that their outlines match when viewed from above.
なお、図１に示されるチャネル保護層１６０は、下面から上面に向かって断面積が小さくなるテーパ形状となっているので、少なくともチャネル保護層１６０の下面の外形輪郭線が、ゲート電極１２０、チャネル層１４０、及び第１非晶質半導体層１５０の外形輪郭線に一致すればよい。
Note that since the channel protective layer 160 shown in FIG. 1 has a tapered shape in which a cross-sectional area decreases from the lower surface toward the upper surface, at least the outer contour lines of the lower surface of the channel protective layer 160 are the gate electrode 120 and the channel. It is only necessary to match the outer contour lines of the layer 140 and the first amorphous semiconductor layer 150.
チャネル保護層１６０は、チャネル層１４０及び第１非晶質半導体層１５０を保護するチャネルエッチングストッパ（ＣＥＳ）層として機能する。すなわち、チャネル保護層１６０は、一対の第２非晶質半導体層１７１、１７２及び一対のコンタクト層１８１、１８２を形成するときのエッチング処理時において、チャネル層１４０及び第１非晶質半導体層１５０がエッチングされることを防止する機能を有する。
The channel protective layer 160 functions as a channel etching stopper (CES) layer that protects the channel layer 140 and the first amorphous semiconductor layer 150. That is, the channel protective layer 160 is formed by the channel layer 140 and the first amorphous semiconductor layer 150 during the etching process when forming the pair of second amorphous semiconductor layers 171 and 172 and the pair of contact layers 181 and 182. Has a function of preventing etching.
チャネル保護層１６０を形成する材料には、例えば、シリコン、酸素及びカーボンを含む有機材料を主として含有する有機材料を用いることができる。本実施の形態におけるチャネル保護層１６０は、感光性塗布型の有機材料をパターニング及び固化することによって形成することができる。
As a material for forming the channel protective layer 160, for example, an organic material mainly containing an organic material containing silicon, oxygen, and carbon can be used. The channel protective layer 160 in this embodiment can be formed by patterning and solidifying a photosensitive coating type organic material.
また、チャネル保護層１６０を構成する有機材料には、例えば、有機樹脂材料、界面活性剤、溶媒及び感光剤が含まれる。有機樹脂材料としては、ポリイミド、アクリル、ポリアミド、ポリイミドアミド、レジスト又はベンゾシクロブテン等の中の１種又は複数種からなる感光性又は非感光性の有機樹脂材料を用いることができる。界面活性剤としては、シロキサン等のシリコン化合物からなる界面活性剤を用いることができる。溶媒としては、プロピレングリコールモノメチルエーテルアセテート又は１，４－ジオキサン等の有機溶媒を用いることができる。また、感光剤としては、ナフトキノンジアジト等のポジ型感光剤を用いることができる。なお、感光剤には、炭素だけではなく硫黄も含まれている。
The organic material constituting the channel protective layer 160 includes, for example, an organic resin material, a surfactant, a solvent, and a photosensitizer. As the organic resin material, a photosensitive or non-photosensitive organic resin material composed of one or more of polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, and the like can be used. As the surfactant, a surfactant made of a silicon compound such as siloxane can be used. As the solvent, an organic solvent such as propylene glycol monomethyl ether acetate or 1,4-dioxane can be used. As the photosensitizer, a positive photosensitizer such as naphthoquinone diazite can be used. Note that the photosensitive agent contains not only carbon but also sulfur.
チャネル保護層１６０を形成する場合、上記の有機材料をスピンコート法等の塗布法を用いて形成することができる。なお、チャネル保護層１６０の形成には、塗布法だけではなく、滴吐出法等その他の方法を用いることもできる。例えば、スクリーン印刷やオフセット印刷等の所定のパターンを形成することができる印刷法等を用いることにより、所定形状の有機材料を選択的に形成することもできる。
When the channel protective layer 160 is formed, the above organic material can be formed using a coating method such as a spin coating method. Note that the channel protective layer 160 can be formed not only by a coating method but also by other methods such as a droplet discharge method. For example, an organic material having a predetermined shape can be selectively formed by using a printing method that can form a predetermined pattern such as screen printing or offset printing.
チャネル保護層１６０の膜厚は、例えば、３００ｎｍ～１０００ｎｍとすることができる。チャネル保護層１６０の膜厚の下限は、エッチングによるマージン及びチャネル保護層１６０中の固定電荷の影響を抑制すること等を考慮して決定される。また、チャネル保護層１６０の膜厚の上限は、第２非晶質半導体層１７１、１７２、コンタクト層１８１、１８２、ソース電極１９１、及びドレイン電極１９２との段差の増大に伴うプロセス信頼性の低下を抑制することを考慮して決定される。
The film thickness of the channel protective layer 160 can be, for example, 300 nm to 1000 nm. The lower limit of the thickness of the channel protective layer 160 is determined in consideration of a margin due to etching and suppression of the influence of fixed charges in the channel protective layer 160. In addition, the upper limit of the thickness of the channel protective layer 160 is that the process reliability decreases with an increase in the steps with the second amorphous semiconductor layers 171 and 172, the contact layers 181 and 182, the source electrode 191, and the drain electrode 192. It is determined in consideration of the suppression.
一対の第２非晶質半導体層１７１、１７２は、チャネル保護層１６０、第１非晶質半導体層１５０、及びチャネル層１４０を覆うようにパターン形成される。また、第２非晶質半導体層１７１と第２非晶質半導体層１７２とは、互いに所定の間隔をあけて対向配置される。
The pair of second amorphous semiconductor layers 171 and 172 are patterned so as to cover the channel protective layer 160, the first amorphous semiconductor layer 150, and the channel layer 140. In addition, the second amorphous semiconductor layer 171 and the second amorphous semiconductor layer 172 are arranged to face each other with a predetermined interval.
より具体的には、第２非晶質半導体層１７１は、チャネル保護層１６０の上面の一部、チャネル保護層１６０の一方側（図１の左側）の側面、第１非晶質半導体層１５０の一方側（図１の左側）の側面、及びチャネル層１４０の一方側（図１の左側）の側面に跨るように形成されている。そして、第２非晶質半導体層１７１は、チャネル層１４０の一方側の側面とコンタクトしている。
More specifically, the second amorphous semiconductor layer 171 includes a part of the upper surface of the channel protective layer 160, a side surface on one side (left side in FIG. 1) of the channel protective layer 160, and the first amorphous semiconductor layer 150. 1 is formed so as to straddle the side surface on one side (left side in FIG. 1) and the side surface on one side (left side in FIG. 1) of the channel layer 140. The second amorphous semiconductor layer 171 is in contact with the side surface on one side of the channel layer 140.
また、第２非晶質半導体層１７２は、チャネル保護層１６０の上面の一部、チャネル保護層１６０の他方側（図１の右側）の側面、第１非晶質半導体層１５０の他方側（図１の右側）の側面、及びチャネル層１４０の他方側（図１の右側）の側面に跨るように形成される。そして、第２非晶質半導体層１７２は、チャネル層１４０の他方側の側面とコンタクトしている。
The second amorphous semiconductor layer 172 includes a part of the upper surface of the channel protective layer 160, a side surface on the other side of the channel protective layer 160 (right side in FIG. 1), and the other side of the first amorphous semiconductor layer 150 ( It is formed so as to straddle the side surface on the right side in FIG. The second amorphous semiconductor layer 172 is in contact with the other side surface of the channel layer 140.
なお、本実施の形態では、第２非晶質半導体層１７１、１７２をチャネル保護層１６０の上面からチャネル層１４０の側面にまで延在させたが、これに限ることなく、第２非晶質半導体層１７１、１７２は、少なくともチャネル層１４０の側面を覆うように設けられていればよい。コンタクト層１８１、１８２、ソース電極１９１、及びドレイン電極１９２についても同様である。
In this embodiment, the second amorphous semiconductor layers 171 and 172 are extended from the upper surface of the channel protective layer 160 to the side surface of the channel layer 140. However, the present invention is not limited to this. The semiconductor layers 171 and 172 may be provided so as to cover at least the side surface of the channel layer 140. The same applies to the contact layers 181 and 182, the source electrode 191, and the drain electrode 192.
第２非晶質半導体層１７１、１７２は、意図的に不純物のドーピングを行っていないアモルファスシリコン膜（真性アモルファスシリコン）からなってもよい。オン抵抗に対して影響が大きすぎる場合、コンタクト層１８１、１８２よりも１－２桁以下の低濃度にドーピングされた層を用いても良い。もしくはあえて意図的にドーピングを行わなくても、ドーピングを行うチャンバーの残留ドーパントによるメモリー効果を用いて成膜することでも上記濃度の層を形成することができる。本実施の形態における第２非晶質半導体層１７１、１７２は、非結晶のアモルファス成分のみによって構成されており、意図的な結晶化は行っていない。
The second amorphous semiconductor layers 171 and 172 may be made of an amorphous silicon film (intrinsic amorphous silicon) that is not intentionally doped with impurities. If the influence on the on-resistance is too great, a layer doped at a lower concentration of 1-2 digits or less than the contact layers 181 and 182 may be used. Alternatively, even if the doping is not intentionally performed, the layer having the above-described concentration can be formed by forming a film using the memory effect of the residual dopant in the doping chamber. The second amorphous semiconductor layers 171 and 172 in the present embodiment are composed of only amorphous amorphous components and are not intentionally crystallized.
さらに、第１非晶質半導体層１５０と一対の第２非晶質半導体層１７１、１７２とは、局在準位密度（局在準位）及びバンドギャップが互いに異なるように形成される。具体的には、第１非晶質半導体層１５０の局在準位密度は、第２非晶質半導体層１７１、１７２の局在準位密度よりも高くなるように形成される。一方、第２非晶質半導体層１７１、１７２のバンドギャップは、第１非晶質半導体層１５０のバンドギャップよりも大きくなるように形成されている。ここで、局在準位密度とは、半導体膜における欠陥準位密度（トラップ密度）であって、電荷の状態密度（ＤＯＳ：Ｄｅｎｓｉｔｙ Ｏｆ Ｓｔａｔｅ）を表している。
Further, the first amorphous semiconductor layer 150 and the pair of second amorphous semiconductor layers 171 and 172 are formed so that the localized level density (localized level) and the band gap are different from each other. Specifically, the first amorphous semiconductor layer 150 is formed so that the localized level density is higher than the localized level density of the second amorphous semiconductor layers 171 and 172. On the other hand, the band gaps of the second amorphous semiconductor layers 171 and 172 are formed to be larger than the band gap of the first amorphous semiconductor layer 150. Here, the localized level density is a defect level density (trap density) in the semiconductor film, and represents a density of states of charge (DOS: Density Of State).
本実施の形態における第１非晶質半導体層１５０の局在準位密度は、［１×１０１８］ｃｍ－３であり、第２非晶質半導体層１７１、１７２の局在準位密度は、［１×１０１７］ｃｍ－３である。また、第１非晶質半導体層１５０のバンドギャップは［１．３］ｅＶであり、真性非結晶質シリコン膜６のバンドギャップは、［１．７］ｅＶである。
The localized level density of the first amorphous semiconductor layer 150 in this embodiment is [1 × 10 18 ] cm −3 , and the localized level density of the second amorphous semiconductor layers 171 and 172 is , [1 × 10 17 ] cm −3 . The band gap of the first amorphous semiconductor layer 150 is [1.3] eV, and the band gap of the intrinsic amorphous silicon film 6 is [1.7] eV.
一対のコンタクト層１８１、１８２は、それぞれ一対の第２非晶質半導体層１７１、１７２上に積層されている。コンタクト層１８１とコンタクト層１８２とは、互いに所定の間隔をあけて対向配置されている。そして、コンタクト層１８１は、第２非晶質半導体層１７１を介してチャネル層１４０の一方側（図１の左側）の側面とコンタクトしている。同様に、コンタクト層１８２は、第２非晶質半導体層１７２を介してチャネル層１４０の他方側（図１の右側）の側面とコンタクトしている。
The pair of contact layers 181 and 182 are stacked on the pair of second amorphous semiconductor layers 171 and 172, respectively. The contact layer 181 and the contact layer 182 are arranged to face each other with a predetermined interval. The contact layer 181 is in contact with the side surface on one side (the left side in FIG. 1) of the channel layer 140 through the second amorphous semiconductor layer 171. Similarly, the contact layer 182 is in contact with the other side surface (the right side in FIG. 1) of the channel layer 140 through the second amorphous semiconductor layer 172.
コンタクト層１８１、１８２は、不純物を高濃度に含む非晶質半導体膜であり、１×１０１９［ａｔｍ／ｃｍ３］以上の高濃度の不純物を含むｎ＋層である。より具体的には、コンタクト層１８１、１８２は、アモルファスシリコンに不純物としてリン（Ｐ）をドーピングしたｎ型半導体膜によって構成することができる。また、コンタクト層１８１、１８２の膜厚は、例えば５ｎｍ～１００ｎｍとすることができる。
The contact layers 181 and 182 are amorphous semiconductor films containing impurities at a high concentration, and are n + layers containing impurities at a high concentration of 1 × 10 19 [atm / cm 3 ] or more. More specifically, the contact layers 181 and 182 can be formed of an n-type semiconductor film obtained by doping amorphous silicon with phosphorus (P) as an impurity. The film thickness of the contact layers 181 and 182 can be set to 5 nm to 100 nm, for example.
ソース電極１９１及びドレイン電極１９２は、コンタクト層１８１、１８２上のチャネル層１４０に重畳する位置にパターン形成される。すなわち、ソース電極１９１とドレイン電極１９２とは、互いに所定の間隔をあけて対向配置される。
The source electrode 191 and the drain electrode 192 are patterned at positions overlapping the channel layer 140 on the contact layers 181 and 182. In other words, the source electrode 191 and the drain electrode 192 are disposed to face each other with a predetermined interval.
本実施の形態において、ソース電極１９１及びドレイン電極１９２は、導電性材料及びその合金等の単層構造又は多層構造とすることができる。例えば、アルミニウム（Ａｌ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、銅（Ｃｕ）、チタン（Ｔｉ）及びクロム（Ｃｒ）等によって構成される。本実施の形態では、ソース電極１９１及びドレイン電極１９２は、ＭｏＷ／Ａｌ／ＭｏＷの三層構造によって形成されている。ソース電極１９１及びドレイン電極１９２の膜厚は、例えば、１００ｎｍ～５００ｎｍ程度とすることができる。
In this embodiment mode, the source electrode 191 and the drain electrode 192 can have a single-layer structure or a multilayer structure such as a conductive material and an alloy thereof. For example, it is composed of aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), titanium (Ti), chromium (Cr), or the like. In the present embodiment, the source electrode 191 and the drain electrode 192 have a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 191 and the drain electrode 192 can be, for example, about 100 nm to 500 nm.
このように、本実施の形態における薄膜半導体装置１００では、上面視したときに、ゲート電極１２０、チャネル層１４０、第１非晶質半導体層１５０及びチャネル保護層１６０の各外形輪郭線が一致している。後述するように、これらの外形輪郭線は、セルフアライメントによって一致している。
As described above, in the thin film semiconductor device 100 according to the present embodiment, when viewed from the top, the outer contour lines of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 match. ing. As will be described later, these outlines coincide with each other by self-alignment.
ここで、本実施の形態における薄膜半導体装置１００の作用効果について、図２Ａ、図２Ｂ及び図２Ｃを用いて説明する。図２Ａは、比較例１の薄膜半導体装置９００Ａの構成及び作用効果を示す図である。図２Ｂは、比較例２の薄膜半導体装置９００Ｂの構成及び作用効果を示す図である。図２Ｃは、本実施の形態に係る薄膜半導体装置１００の構成及び作用効果を示す図である。
Here, the operation and effect of the thin film semiconductor device 100 in the present embodiment will be described with reference to FIGS. 2A, 2B, and 2C. FIG. 2A is a diagram showing a configuration and operational effects of the thin film semiconductor device 900A of the first comparative example. FIG. 2B is a diagram showing a configuration and operational effects of the thin film semiconductor device 900B of Comparative Example 2. FIG. 2C is a diagram showing a configuration and operational effects of the thin film semiconductor device 100 according to the present embodiment.
図２Ａに示すように、比較例１の薄膜半導体装置９００Ａでは、本実施の形態のようにセルフアラインされていないので、ゲート電極９２０、結晶シリコン層９４０、非結晶シリコン層９５０及びチャネル保護層９６０の各外形輪郭線が一致しておらず、ゲート電極９２０、結晶シリコン層９４０及び非結晶シリコン層９５０の長さは、チャネル保護層９６０の長さよりも長くなっている。従って、比較例１の薄膜半導体装置９００Ａでは、広いコンタクト領域から電流を注入することができる。このため、非結晶シリコン層９５０（アモルファスシリコン）による抵抗は大きいものの、ゲート電極９２０上方の非結晶シリコン層９５０の上方に位置するコンタクト領域自体が大きいため（すなわち電圧が印加される領域が大きいため）、キャリア注入特性は比較的良好なものとなる。
As shown in FIG. 2A, since the thin film semiconductor device 900A of Comparative Example 1 is not self-aligned as in this embodiment, the gate electrode 920, the crystalline silicon layer 940, the amorphous silicon layer 950, and the channel protective layer 960 are not used. The outlines of the gate electrode 920, the crystalline silicon layer 940, and the amorphous silicon layer 950 are longer than the channel protective layer 960. Therefore, in the thin film semiconductor device 900A of Comparative Example 1, current can be injected from a wide contact region. Therefore, although the resistance due to the amorphous silicon layer 950 (amorphous silicon) is large, the contact region itself located above the amorphous silicon layer 950 above the gate electrode 920 is large (that is, the region to which voltage is applied is large). ), Carrier injection characteristics are relatively good.
一方、比較例１の薄膜半導体装置９００Ａにおいて、結晶シリコン層９４０（ポリシリコン）とコンタクト層９７１とは、結晶シリコン層９４０の両端部において非結晶シリコン層９５０を介さずに直接接しているものの、非結晶シリコン層９５０の上方におけるコンタクト領域が支配的になるため、コンタクト層９７１から結晶シリコン層９４０へのキャリアの直接注入は実質的に起こらない。また、比較例１の薄膜半導体装置９００Ａでは、ゲート電極９２０が長いので、寄生容量が大きいという問題もある。
On the other hand, in the thin film semiconductor device 900A of Comparative Example 1, although the crystalline silicon layer 940 (polysilicon) and the contact layer 971 are in direct contact with each other at both ends of the crystalline silicon layer 940 without passing through the amorphous silicon layer 950, Since the contact region above the amorphous silicon layer 950 becomes dominant, direct injection of carriers from the contact layer 971 to the crystalline silicon layer 940 does not substantially occur. In addition, the thin film semiconductor device 900A of Comparative Example 1 has a problem that the parasitic capacitance is large because the gate electrode 920 is long.
また、図２Ｂに示すように、比較例２の薄膜半導体装置９００Ｂは、チャネル保護層９６０及びゲート電極９２０がセルフアラインされ、結晶シリコン層９４０及び非結晶シリコン層９５０はセルフアラインされていない。つまり、チャネル保護層９６０とゲート電極９２０との外形輪郭線は一致しているが、チャネル保護層９６０及びゲート電極９２０と結晶シリコン層９４０及び非結晶シリコン層９５０とは外形輪郭線が一致していておらず、結晶シリコン層９４０及び非結晶シリコン層９５０の長さは、ゲート電極９２０及びチャネル保護層９６０の長さよりも長くなっている。
2B, in the thin film semiconductor device 900B of Comparative Example 2, the channel protective layer 960 and the gate electrode 920 are self-aligned, and the crystalline silicon layer 940 and the amorphous silicon layer 950 are not self-aligned. That is, the outer contour lines of the channel protective layer 960 and the gate electrode 920 are identical, but the outer contour lines of the channel protective layer 960 and the gate electrode 920 are identical with the crystalline silicon layer 940 and the amorphous silicon layer 950. However, the lengths of the crystalline silicon layer 940 and the amorphous silicon layer 950 are longer than the lengths of the gate electrode 920 and the channel protective layer 960.
この場合、チャネル保護層９６０とゲート電極９２０との外形輪郭線が一致しているので、寄生容量を抑制することができる。
In this case, since the outer contour lines of the channel protective layer 960 and the gate electrode 920 match, parasitic capacitance can be suppressed.
しかし、非結晶シリコン層９５０とコンタクト層９７１との接触面積は大きいものの、その接触領域はゲート電極９２０の上方に位置しておらず、当該接触領域には電圧がかかっていなためキャリア注入が発生しない。そのため、電圧がかかるごく一部の領域のみの狭いコンタクト領域からキャリアが注入されることになり、電流特性は非常に悪くなる。この場合も、比較例１と同様に、非結晶シリコン層９５０からのキャリア注入が支配的になるため、結晶シリコン層９４０とコンタクト層９７１とが直接接しているとしても、コンタクト層９７１から結晶シリコン層９４０へのキャリアの直接注入は実質的に起こらない。
However, although the contact area between the amorphous silicon layer 950 and the contact layer 971 is large, the contact region is not located above the gate electrode 920, and no voltage is applied to the contact region, so that carrier injection occurs. do not do. For this reason, carriers are injected from a narrow contact region of only a small part where voltage is applied, and the current characteristics become very poor. Also in this case, similarly to Comparative Example 1, carrier injection from the amorphous silicon layer 950 becomes dominant, so that even if the crystalline silicon layer 940 and the contact layer 971 are in direct contact with each other, the contact silicon layer 971 and the crystalline silicon layer Direct injection of carriers into layer 940 does not occur substantially.
これに対して、図２Ｃに示すように、本実施の形態における薄膜半導体装置１００によれば、ゲート電極１２０とチャネル保護層１６０の下面とは、上面視したときに外形輪郭線が一致する。これにより、図１に示される断面において、チャネル保護層１６０の下面の左右の端部が、ゲート電極１２０の左右の側面の延長線上に位置することになる。その結果、チャネル保護層１６０の左右の領域でゲート電極１２０とソース電極１９１及びドレイン電極１９２とが重畳しないので、この領域の寄生容量を削減することができる。
On the other hand, as shown in FIG. 2C, according to the thin film semiconductor device 100 in the present embodiment, the outline of the gate electrode 120 and the lower surface of the channel protective layer 160 coincide with each other when viewed from above. Thereby, in the cross section shown in FIG. 1, the left and right end portions of the lower surface of the channel protective layer 160 are positioned on the extension lines of the left and right side surfaces of the gate electrode 120. As a result, the gate electrode 120, the source electrode 191 and the drain electrode 192 do not overlap in the left and right regions of the channel protective layer 160, so that the parasitic capacitance in this region can be reduced.
また、薄膜半導体装置１００によれば、ゲート電極１２０、チャネル層１４０（結晶性シリコン）及び第１非晶質半導体層（アモルファスシリコン）の各外形輪郭線を一致させている。これにより、第２非晶質半導体層１７１、１７２をチャネル層１４０の側面に直接コンタクトさせ、さらに、コンタクト層１８１、１８２を第２非晶質半導体層１７１、１７２を介してチャネル層１４０の側面とコンタクトさせている。このため、チャネル層１４０からのキャリア注入は支配的にならず、チャネル層１４０の端面から直接電流注入が可能になる。従って、ゲート電極１２０に電圧を印加したときの電流パスは、ソース電極１９１、コンタクト層１８１、第２非晶質半導体層１７１、チャネル層１４０、第２非晶質半導体層１７２、コンタクト層１８２、及びドレイン電極１９２となる。すなわち、高抵抗の第１非晶質半導体層１５０を電流パスから外すことができるので、オン抵抗を低減することができる。
Further, according to the thin film semiconductor device 100, the outer contour lines of the gate electrode 120, the channel layer 140 (crystalline silicon), and the first amorphous semiconductor layer (amorphous silicon) are made to coincide. As a result, the second amorphous semiconductor layers 171 and 172 are brought into direct contact with the side surfaces of the channel layer 140, and the contact layers 181 and 182 are further contacted with the side surfaces of the channel layer 140 via the second amorphous semiconductor layers 171 and 172. Contact. For this reason, carrier injection from the channel layer 140 is not dominant, and current injection can be performed directly from the end face of the channel layer 140. Therefore, when a voltage is applied to the gate electrode 120, the current path includes the source electrode 191, the contact layer 181, the second amorphous semiconductor layer 171, the channel layer 140, the second amorphous semiconductor layer 172, the contact layer 182, And the drain electrode 192. In other words, since the high resistance first amorphous semiconductor layer 150 can be removed from the current path, the on-resistance can be reduced.
このように、薄膜半導体装置１００では、キャリア注入特性の向上と寄生容量の抑制とを両立を図ることができる。
Thus, in the thin film semiconductor device 100, it is possible to achieve both improvement in carrier injection characteristics and suppression of parasitic capacitance.
さらに、第１非晶質半導体層１５０の局在準位密度を高くすることにより、チャネル保護層１６０に含まれる固定電荷によるバックチャネル効果を抑制することができる。一方、第２非晶質半導体層１７１、１７２のバンドギャップを大きくすることにより、オフ特性を向上させることができる。このように、局在準位密度を高くした第１非晶質半導体層１５０と、バンドギャップを大きくした第２非晶質半導体層１７１、１７２とを設けることにより、従来のように、非結晶シリコン層９５０（図１の第１非晶質半導体層１５０に相当する）に高い局在準位密度と大きいバンドギャップとを付与しようとする場合と比較して、薄膜半導体装置１００の性能を飛躍的に向上させることができる。
Furthermore, by increasing the local level density of the first amorphous semiconductor layer 150, the back channel effect due to the fixed charges contained in the channel protective layer 160 can be suppressed. On the other hand, the off characteristics can be improved by increasing the band gap of the second amorphous semiconductor layers 171 and 172. In this manner, by providing the first amorphous semiconductor layer 150 having a high localized state density and the second amorphous semiconductor layers 171 and 172 having a large band gap, an amorphous state can be obtained as in the prior art. Compared with the case where a high localized state density and a large band gap are to be imparted to the silicon layer 950 (corresponding to the first amorphous semiconductor layer 150 in FIG. 1), the performance of the thin film semiconductor device 100 is greatly improved. Can be improved.
次に、図３Ａ～図３Ｋを参照して、本発明の実施の形態に係る薄膜半導体装置の製造方法を説明する。図３Ａ～図３Ｋは、本発明の実施の形態に係る薄膜半導体装置の製造方法における各工程の構成を模式的に示した断面図である。
Next, a method for manufacturing a thin film semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3K. 3A to 3K are cross-sectional views schematically showing the configuration of each step in the method of manufacturing a thin film semiconductor device according to the embodiment of the present invention.
まず、図３Ａに示されるように、基板１１０を準備する。なお、ゲート電極１２０を形成する前に、プラズマＣＶＤ等によって基板１１０上にシリコン窒化膜、シリコン酸化膜、及びシリコン酸窒化膜などからなるアンダーコート層を形成してもよい。
First, as shown in FIG. 3A, a substrate 110 is prepared. Note that an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the substrate 110 by plasma CVD or the like before forming the gate electrode 120.
次に、図３Ｂに示されるように、基板１１０上に、所定形状のゲート電極１２０を形成する。例えば、基板１１０上にＭｏＷからなるゲート金属膜をスパッタによって成膜し、フォトリソグラフィ法及びウェットエッチング法を用いてゲート金属膜をパターニングすることにより、所定形状のゲート電極１２０を形成することができる。ＭｏＷのウェットエッチングは、例えば、リン酸（ＨＰＯ４）、硝酸（ＨＮＯ３）、酢酸（ＣＨ３ＣＯＯＨ）及び水を所定の配合で混合した薬液を用いて行うことができる。
Next, as shown in FIG. 3B, a gate electrode 120 having a predetermined shape is formed on the substrate 110. For example, a gate metal film made of MoW is formed on the substrate 110 by sputtering, and the gate metal film is patterned using a photolithography method and a wet etching method, whereby the gate electrode 120 having a predetermined shape can be formed. . MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water are mixed in a predetermined composition.
次に、図３Ｃに示されるように、ゲート電極１２０を覆うように、基板１１０の上面全域にゲート絶縁膜１３０を形成する。例えば、酸化シリコンからなるゲート絶縁膜１３０をプラズマＣＶＤ等によって成膜する。酸化シリコンは、例えば、シランガス（ＳｉＨ４）と亜酸化窒素ガス（Ｎ２Ｏ）とを所定の濃度比で導入することで、成膜することができる。
Next, as illustrated in FIG. 3C, a gate insulating film 130 is formed over the entire upper surface of the substrate 110 so as to cover the gate electrode 120. For example, the gate insulating film 130 made of silicon oxide is formed by plasma CVD or the like. Silicon oxide can be formed, for example, by introducing silane gas (SiH 4 ) and nitrous oxide gas (N 2 O) at a predetermined concentration ratio.
次に、図３Ｄに示されるように、ゲート絶縁膜１３０の上面全域に、チャネル層１４０となる結晶シリコン薄膜１４０Ｍを形成する。結晶シリコン薄膜１４０Ｍは、例えば、アモルファスシリコン（非晶質シリコン）からなる非結晶シリコン薄膜をプラズマＣＶＤ等によって成膜し、脱水素アニール処理を行った後に、非結晶シリコン薄膜をアニールして結晶化させることによって形成することができる。なお、非結晶シリコン薄膜は、例えば、シランガス（ＳｉＨ４）と水素ガス（Ｈ２）とを所定の濃度比で導入することで、成膜することができる。
Next, as illustrated in FIG. 3D, a crystalline silicon thin film 140 </ b> M that becomes the channel layer 140 is formed over the entire upper surface of the gate insulating film 130. As for the crystalline silicon thin film 140M, for example, an amorphous silicon thin film made of amorphous silicon (amorphous silicon) is formed by plasma CVD or the like, and after dehydrogenation annealing treatment, the amorphous silicon thin film is annealed to be crystallized. Can be formed. The amorphous silicon thin film can be formed, for example, by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio.
なお、本実施の形態では、エキシマレーザを用いたレーザアニールによって非結晶シリコン薄膜を結晶化させたが、結晶化の方法としては、波長３７０～９００ｎｍ程度のパルスレーザを用いたレーザアニール法、波長３７０～９００ｎｍ程度の連続発振レーザを用いたレーザアニール法、又は急速熱処理（ＲＴＰ）によるアニール法を用いても構わない。また、非結晶シリコン薄膜を結晶化するのではなく、ＣＶＤによる直接成長などの方法によって結晶シリコン薄膜１４０Ｍを成膜してもよい。
In this embodiment, the amorphous silicon thin film is crystallized by laser annealing using an excimer laser. However, as a crystallization method, a laser annealing method using a pulse laser having a wavelength of about 370 to 900 nm, a wavelength of A laser annealing method using a continuous wave laser of about 370 to 900 nm or an annealing method by rapid thermal processing (RTP) may be used. Further, instead of crystallizing the amorphous silicon thin film, the crystalline silicon thin film 140M may be formed by a method such as direct growth by CVD.
その後、結晶シリコン薄膜１４０Ｍに対して水素プラズマ処理を行うことにより、結晶シリコン薄膜１４０Ｍのシリコン原子に対して水素化処理を行う。水素プラズマ処理は、例えばＨ２、Ｈ２／アルゴン（Ａｒ）等の水素ガスを含むガスを原料として高周波（ＲＦ）電力により水素プラズマを発生させて、当該水素プラズマを結晶シリコン薄膜１４０Ｍに照射することにより行われる。この水素プラズマ処理によって、シリコン原子のダングリングボンド（欠陥）が水素終端され、結晶シリコン薄膜１４０Ｍの結晶欠陥密度が低減して結晶性が向上する。
Thereafter, a hydrogen plasma process is performed on the crystalline silicon thin film 140M to perform a hydrogenation process on silicon atoms in the crystalline silicon thin film 140M. In the hydrogen plasma treatment, for example, hydrogen plasma is generated by radio frequency (RF) power using a gas containing hydrogen gas such as H 2 or H 2 / argon (Ar) as a raw material, and the crystalline silicon thin film 140M is irradiated with the hydrogen plasma. Is done. By this hydrogen plasma treatment, dangling bonds (defects) of silicon atoms are terminated with hydrogen, the crystal defect density of the crystalline silicon thin film 140M is reduced, and crystallinity is improved.
次に、図３Ｅに示すように、結晶シリコン薄膜１４０Ｍの上面全域に、第１非晶質半導体層１５０の前駆体膜である第１アモルファスシリコン膜１５０Ｍを形成する。第１アモルファスシリコン膜１５０Ｍは、例えば、ＣＶＤ法により、シランガス（ＳｉＨ４）と水素ガス（Ｈ２）とを所定の濃度比で導入することで、成膜することができる。
Next, as shown in FIG. 3E, a first amorphous silicon film 150M, which is a precursor film of the first amorphous semiconductor layer 150, is formed over the entire upper surface of the crystalline silicon thin film 140M. The first amorphous silicon film 150M can be formed by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio by, for example, CVD.
第１アモルファスシリコン膜１５０Ｍは、例えば、平行平板型ＲＦプラズマＣＶＤ装置を用いて、シランガス（ＳｉＨ４）と水素ガス（Ｈ２）とを所定の濃度比で、且つシランガスの流量を５～１５ｓｃｃｍで、水素ガスの流量を４０～７５ｓｃｃｍでそれぞれ導入し、圧力を１～５Ｔｏｒｒとし、ＲＦ電力を０．１～０．４ｋｗ／ｃｍ－２とし、電極基板間距離を２００～６００ｍｍとして、成膜することができる。本実施の形態では、例えば、電極の直径が１０インチの平行平板型ＲＦプラズマＣＶＤ装置で、シランガスの流量と水素ガスの流量とを１：７とし、圧力を５Ｔｏｒｒとし、ＲＦ電力を０．２ｋｗ／ｃｍ－２とし、電極基板間距離を３００ｍｍとして成膜する。
The first amorphous silicon film 150M is formed by using a parallel plate RF plasma CVD apparatus, for example, with a predetermined concentration ratio of silane gas (SiH 4 ) and hydrogen gas (H 2 ), and a silane gas flow rate of 5 to 15 sccm. Then, the hydrogen gas is introduced at a flow rate of 40 to 75 sccm, the pressure is set to 1 to 5 Torr, the RF power is set to 0.1 to 0.4 kw / cm −2, and the distance between the electrode substrates is set to 200 to 600 mm. be able to. In the present embodiment, for example, in a parallel plate RF plasma CVD apparatus having an electrode diameter of 10 inches, the flow rate of silane gas and the flow rate of hydrogen gas is 1: 7, the pressure is 5 Torr, and the RF power is 0.2 kW. / Cm −2 and the distance between the electrode substrates is 300 mm.
第１アモルファスシリコン膜１５０Ｍは、後述の露光工程での光に対しての吸収率が高い。そのため、第１アモルファスシリコン膜１５０Ｍを厚くしすぎると、絶縁膜１６０Ｍに必要な露光量が届かず、露光が不十分になってしまう恐れがある。もしくは、必要な露光量を得るために長時間の露光工程が必要になってしまい、生産性を著しく落としてしまう懸念がある。そこで、第１アモルファスシリコン膜１５０Ｍの厚みは望ましくは５０ｎｍ以下である。但し、露光工程で用いる光の光量を強くすれば、第１アモルファスシリコン膜１５０Ｍの厚みは、５０ｎｍ以上とすることもできる。
The first amorphous silicon film 150M has a high absorptance with respect to light in an exposure process described later. Therefore, if the first amorphous silicon film 150M is too thick, the exposure amount necessary for the insulating film 160M does not reach and exposure may be insufficient. Alternatively, there is a concern that a long exposure process is required to obtain a necessary exposure amount, and productivity is significantly reduced. Therefore, the thickness of the first amorphous silicon film 150M is desirably 50 nm or less. However, if the amount of light used in the exposure process is increased, the thickness of the first amorphous silicon film 150M can be 50 nm or more.
次に、図３Ｆに示されるように、第１アモルファスシリコン膜１５０Ｍの上面全域に、チャネル保護層１６０となる絶縁膜１６０Ｍを形成する。具体的には、まず、所定の塗布方式によってチャネル保護層１６０の前駆体としての有機材料を第１アモルファスシリコン膜１５０Ｍ上に塗布し、スピンコートやスリットコートを行うことによって第１アモルファスシリコン膜１５０Ｍの上面全域に絶縁膜１６０Ｍを成膜する。有機材料の膜厚は、有機材料の粘度やコーティング条件（回転数、ブレードの速度など）で制御することができる。なお、絶縁膜１６０Ｍの材料としては、シリコン、酸素及びカーボンを含む感光性塗布型の有機材料を用いることができる。
Next, as shown in FIG. 3F, an insulating film 160M to be the channel protective layer 160 is formed over the entire upper surface of the first amorphous silicon film 150M. Specifically, first, an organic material as a precursor of the channel protective layer 160 is applied on the first amorphous silicon film 150M by a predetermined coating method, and spin coating or slit coating is performed to thereby apply the first amorphous silicon film 150M. An insulating film 160M is formed over the entire upper surface. The film thickness of the organic material can be controlled by the viscosity of the organic material and the coating conditions (rotation speed, blade speed, etc.). Note that as a material of the insulating film 160M, a photosensitive coating organic material containing silicon, oxygen, and carbon can be used.
次に、絶縁膜１６０Ｍに対して約１１０℃の温度で約６０秒間のプリベークを行って、絶縁膜１６０Ｍを仮焼成する。これにより、絶縁膜１６０Ｍに含まれる溶剤が気化する。その後、ゲート電極１２０をマスクとして基板１１０の裏面（ゲート電極１２０が形成されている面の反対側の面）側から絶縁膜１６０Ｍを感光させる光を照射し、絶縁膜１６０Ｍを露光させる。そして、露光された絶縁膜１６０Ｍをパターニングすることによって、図３Ｇに示されるように、ゲート電極１２０に重畳する領域に所定形状のチャネル保護層１６０を形成する。
Next, pre-baking is performed on the insulating film 160M at a temperature of about 110 ° C. for about 60 seconds to pre-fire the insulating film 160M. Thereby, the solvent contained in the insulating film 160M is vaporized. Thereafter, the gate electrode 120 is used as a mask to irradiate the insulating film 160M with light for exposing the insulating film 160M from the back surface (the surface opposite to the surface on which the gate electrode 120 is formed) of the substrate 110, thereby exposing the insulating film 160M. Then, by patterning the exposed insulating film 160M, a channel protective layer 160 having a predetermined shape is formed in a region overlapping with the gate electrode 120 as shown in FIG. 3G.
次に、パターン形成されたチャネル保護層１６０に対して２８０℃～３００℃の温度で約１時間のポストベークを行ってチャネル保護層１６０を本焼成して固化する。これにより、有機成分の一部が気化及び分解して、膜質が改善されたチャネル保護層１６０を形成することができる。
Next, post-baking is performed on the patterned channel protection layer 160 at a temperature of 280 ° C. to 300 ° C. for about 1 hour, and the channel protection layer 160 is finally baked and solidified. Thereby, a part of the organic component is vaporized and decomposed, and the channel protective layer 160 with improved film quality can be formed.
このように、遮光性導電性材料で形成されたゲート電極１２０をマスクとして絶縁膜１６０Ｍを露光することにより、ゲート電極１２０とチャネル保護層１６０の下面との外形輪郭線が一致するように、セルフアライメントされる。これにより、チャネル保護層１６０の左右の領域でゲート電極１２０とソース電極１９１及びドレイン電極１９２とが重畳しないので、この領域に生じる寄生容量を削減することができる。
In this way, by exposing the insulating film 160M using the gate electrode 120 formed of a light-shielding conductive material as a mask, the external contour lines of the gate electrode 120 and the lower surface of the channel protective layer 160 are matched so as to match each other. Aligned. Thereby, since the gate electrode 120 does not overlap with the source electrode 191 and the drain electrode 192 in the left and right regions of the channel protective layer 160, the parasitic capacitance generated in this region can be reduced.
なお、絶縁膜１６０Ｍをパターニングすると、チャネル保護層１６０は、図４に示されるように、所望の大きさよりΔＬだけ小さくなる。すなわち、チャネル保護層１６０の下面の外形輪郭線は、ゲート電極１２０の上面の外形輪郭線の内側に後退している。また、チャネル層１４０及び第１非晶質半導体層１５０は、後述するようにチャネル保護層１６０をマスクとして形成されるので、チャネル保護層１６０と同じように、ゲート電極１２０の外形輪郭線の内側に後退する。
Note that when the insulating film 160M is patterned, the channel protective layer 160 becomes smaller than the desired size by ΔL, as shown in FIG. That is, the outer contour line on the lower surface of the channel protective layer 160 recedes inside the outer contour line on the upper surface of the gate electrode 120. Further, since the channel layer 140 and the first amorphous semiconductor layer 150 are formed using the channel protective layer 160 as a mask as will be described later, like the channel protective layer 160, the inside of the outline of the gate electrode 120. Retreat to.
そこで、図４を参照して、ゲート電極１２０、チャネル層１４０、第１非晶質半導体層１５０、及びチャネル保護層１６０の積層関係を説明する。なお、図４では、ゲート絶縁膜１３０等の図示を省略している。まず、本明細書では、製造プロセス中に生じるΔＬ＝０．５μｍ以内の誤差は、「外形輪郭線が一致する」の範囲内に含めるものとする。また、ΔＬを第２非晶質半導体層１７１、１７２の膜厚以上に設定してもよい。これにより、第２非晶質半導体層１７１がゲート電極１２０に重畳する位置に形成されることになるので、オン抵抗を低減することができる。
Therefore, the stacking relationship of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 will be described with reference to FIG. In FIG. 4, the illustration of the gate insulating film 130 and the like is omitted. First, in this specification, an error within ΔL = 0.5 μm that occurs during the manufacturing process is included in the range of “the outline contours match”. Further, ΔL may be set to be equal to or greater than the film thickness of the second amorphous semiconductor layers 171 and 172. Accordingly, the second amorphous semiconductor layer 171 is formed at a position overlapping with the gate electrode 120, so that the on-resistance can be reduced.
すなわち、本実施の形態におけるΔＬは、０（ゲート電極１２０、チャネル層１４０、第１非晶質半導体層１５０、及びチャネル保護層１６０の外形輪郭線が完全に一致する）であってもよいし、第２非晶質半導体層１７１、１７２の膜厚以上で、且つ０．５μｍ以下の範囲内に設定してもよい。
That is, ΔL in this embodiment may be 0 (the outer contour lines of the gate electrode 120, the channel layer 140, the first amorphous semiconductor layer 150, and the channel protective layer 160 are completely matched). The thickness may be set to be not less than the thickness of the second amorphous semiconductor layers 171 and 172 and not more than 0.5 μm.
次に、チャネル保護層１６０をマスクとして、結晶シリコン薄膜１４０Ｍ及び第１アモルファスシリコン膜１５０Ｍにドライエッチングを施す。これにより、図３Ｈに示されるように、ゲート電極１２０に重畳する位置に、チャネル層１４０及び第１非晶質半導体層１５０を同時に形成する。
Next, dry etching is performed on the crystalline silicon thin film 140M and the first amorphous silicon film 150M using the channel protective layer 160 as a mask. As a result, as shown in FIG. 3H, the channel layer 140 and the first amorphous semiconductor layer 150 are simultaneously formed at a position overlapping the gate electrode 120.
チャネル保護層１６０をマスクとして用いることにより、セルフアライメントによって、チャネル層１４０及び第１非晶質半導体層１５０の外形輪郭線がチャネル保護層１６０の下面の外形輪郭線に一致する。これにより、後述の工程で形成される第２非晶質半導体層１７１、１７２をチャネル層１４０の側面と直接コンタクトさせることができる。その結果、ソース電極１９１及びドレイン電極１９２とチャネル層１４０との間の電流パスに、高抵抗の第１非晶質半導体層１５０が含まれなくなるので、オン抵抗を低減することができる。
By using the channel protective layer 160 as a mask, the outer contour lines of the channel layer 140 and the first amorphous semiconductor layer 150 coincide with the outer contour line of the lower surface of the channel protective layer 160 by self-alignment. As a result, the second amorphous semiconductor layers 171 and 172 formed in the steps described later can be in direct contact with the side surface of the channel layer 140. As a result, the high-resistance first amorphous semiconductor layer 150 is not included in the current path between the source electrode 191 and the drain electrode 192 and the channel layer 140, so that the on-resistance can be reduced.
次に、図３Ｉに示すように、チャネル保護層１６０及びゲート絶縁膜１３０を覆うようにして、一対の第２非晶質半導体層１７１、１７２となる真性の第２アモルファスシリコン膜１７０Ｍを形成する。真性の第２アモルファスシリコン膜１７０Ｍは、例えば、プラズマＣＶＤ等によって成膜することができる。真性の第２アモルファスシリコン膜１７０Ｍは、例えば、シランガス（ＳｉＨ４）と水素ガス（Ｈ２）とを所定の濃度比で導入することで成膜することができる。本実施の形態では、例えば、電極の直径が１０インチの平行平板型ＲＦプラズマＣＶＤ装置で、シランガスの流量と水素ガスの流量とを６：１とし、圧力を５Ｔｏｒｒとし、ＲＦ電力を０．０３ｋｗ／ｃｍ－２とし、電極基板間距離を５２５ｍｍとして成膜する。
Next, as shown in FIG. 3I, an intrinsic second amorphous silicon film 170M to be a pair of second amorphous semiconductor layers 171 and 172 is formed so as to cover the channel protective layer 160 and the gate insulating film 130. . The intrinsic second amorphous silicon film 170M can be formed by plasma CVD or the like, for example. The intrinsic second amorphous silicon film 170M can be formed, for example, by introducing silane gas (SiH 4 ) and hydrogen gas (H 2 ) at a predetermined concentration ratio. In this embodiment, for example, in a parallel plate type RF plasma CVD apparatus having an electrode diameter of 10 inches, the flow rate of silane gas and the flow rate of hydrogen gas is 6: 1, the pressure is 5 Torr, and the RF power is 0.03 kW. / Cm −2 and the distance between the electrode substrates is 525 mm.
第１非晶質半導体層１５０及び第２非晶質半導体層１７１、１７２の形成条件を上記のように異ならせることにより、相対的に局在準位密度の高い第１非晶質半導体層１５０と、相対的にバンドギャップの大きい第２非晶質半導体層１７１、１７２とを得ることができる。
By changing the formation conditions of the first amorphous semiconductor layer 150 and the second amorphous semiconductor layers 171 and 172 as described above, the first amorphous semiconductor layer 150 having a relatively high localized level density. Thus, the second amorphous semiconductor layers 171 and 172 having a relatively large band gap can be obtained.
次に、図３Ｊに示すように、真性の第２アモルファスシリコン膜１７０Ｍの上面全域に、コンタクト層１８１、１８２となるコンタクト層用膜１８０Ｍを形成する。例えば、プラズマＣＶＤによって、リン等の５価元素の不純物をドープしたアモルファスシリコンからなるコンタクト層用膜１８０Ｍを成膜する。
Next, as shown in FIG. 3J, a contact layer film 180M to be the contact layers 181 and 182 is formed over the entire upper surface of the intrinsic second amorphous silicon film 170M. For example, a contact layer film 180M made of amorphous silicon doped with an impurity of a pentavalent element such as phosphorus is formed by plasma CVD.
なお、コンタクト層用膜１８０Ｍは下層の低濃度の電界緩和層と上層の高濃度のコンタクト層との２層から構成されてもよい。低濃度の電界緩和層は１×１０１７［ａｔｍ／ｃｍ３］程度のリンをドーピングすることによって形成することができる。上記２層は、例えばＣＶＣ装置において連続的に形成することが可能である。
The contact layer film 180M may be composed of two layers, a lower-layer low-concentration electric field relaxation layer and an upper-layer high-concentration contact layer. The low-concentration electric field relaxation layer can be formed by doping about 1 × 10 17 [atm / cm 3 ] phosphorus. The two layers can be formed continuously in, for example, a CVC apparatus.
次に、図３Ｋに示すように、コンタクト層用膜１８０Ｍ上に、ソース電極１９１及びドレイン電極１９２をパターン形成する。この場合、まず、ソース電極１９１及びドレイン電極１９２となる材料で構成されたソースドレイン金属膜を、例えばスパッタによって成膜する。その後、ソースドレイン金属膜上に所定形状にパターニングされたレジストを形成し、ウェットエッチングを施すことによってソースドレイン金属膜をパターニングする。このとき、コンタクト層用膜１８０Ｍがエッチングストッパとして機能する。その後、レジストを除去することにより、所定形状のソース電極１９１及びドレイン電極１９２を形成することができる。
Next, as shown in FIG. 3K, a source electrode 191 and a drain electrode 192 are patterned on the contact layer film 180M. In this case, first, a source / drain metal film made of a material to be the source electrode 191 and the drain electrode 192 is formed by sputtering, for example. Thereafter, a resist patterned in a predetermined shape is formed on the source / drain metal film, and wet etching is performed to pattern the source / drain metal film. At this time, the contact layer film 180M functions as an etching stopper. After that, by removing the resist, the source electrode 191 and the drain electrode 192 having a predetermined shape can be formed.
次に、ソース電極１９１及びドレイン電極１９２をマスクとしてドライエッチングを施すことにより、コンタクト層用膜１８０Ｍ及び真性の第２アモルファスシリコン膜１７０Ｍを島状にパターニングする。これにより、一対のコンタクト層１８１、１８２と、一対の第２非晶質半導体層１７１、１７２とを所定形状に形成することができる。なお、ドライエッチングには、塩素系ガスを用いるとよい。
Next, the contact layer film 180M and the intrinsic second amorphous silicon film 170M are patterned in an island shape by performing dry etching using the source electrode 191 and the drain electrode 192 as a mask. Thus, the pair of contact layers 181 and 182 and the pair of second amorphous semiconductor layers 171 and 172 can be formed in a predetermined shape. Note that a chlorine-based gas may be used for dry etching.
この工程で、ソース電極１９１及びドレイン電極１９２の下に一対のコンタクト層１８１、１８２及び一対の第２非晶質半導体層１７１、１７２が形成される。このようにして、図１に示されるような本発明の実施の形態に係る薄膜半導体装置を製造することができる。
In this step, a pair of contact layers 181 and 182 and a pair of second amorphous semiconductor layers 171 and 172 are formed under the source electrode 191 and the drain electrode 192. Thus, the thin film semiconductor device according to the embodiment of the present invention as shown in FIG. 1 can be manufactured.
次に、上記の実施の形態に係る薄膜半導体装置１００を表示装置に適用した例について、図５を用いて説明する。なお、本実施の形態では、有機ＥＬ表示装置への適用例について説明する。
Next, an example in which the thin film semiconductor device 100 according to the above embodiment is applied to a display device will be described with reference to FIG. In this embodiment, an application example to an organic EL display device will be described.
図５は、本発明の実施の形態に係る有機ＥＬ表示装置の一部切り欠き斜視図である。上述の薄膜半導体装置１００は、有機ＥＬ表示装置におけるアクティブマトリクス基板のスイッチングトランジスタ又は駆動トランジスタとして用いることができる。
FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment of the present invention. The thin film semiconductor device 100 described above can be used as a switching transistor or a driving transistor of an active matrix substrate in an organic EL display device.
図５に示すように、有機ＥＬ表示装置１０は、アクティブマトリクス基板（ＴＦＴアレイ基板）１１と、アクティブマトリクス基板１１においてマトリクス状に複数配置された画素１２と、複数の画素１２のそれぞれに対応して形成された有機ＥＬ素子１３と、画素１２の行方向に沿って形成された複数の走査線（ゲート線）１７と、画素１２の列方向に沿って形成された複数の映像信号線（ソース線）１８と、映像信号線１８と並行して形成された電源線１９（不図示）とを備える。有機ＥＬ素子１３は、アクティブマトリクス基板１１上に順次積層された、陽極１４、有機ＥＬ層１５及び陰極１６（透明電極）を有する。なお、陽極１４は、実際には各画素１２に対応して複数形成される。有機ＥＬ層１５は、電子輸送層、発光層、正孔輸送層等の各層が積層されて構成されている。
As shown in FIG. 5, the organic EL display device 10 corresponds to an active matrix substrate (TFT array substrate) 11, a plurality of pixels 12 arranged in a matrix on the active matrix substrate 11, and a plurality of pixels 12. The organic EL elements 13 formed in this way, the plurality of scanning lines (gate lines) 17 formed along the row direction of the pixels 12, and the plurality of video signal lines (sources) formed along the column direction of the pixels 12. Line) 18 and a power line 19 (not shown) formed in parallel with the video signal line 18. The organic EL element 13 includes an anode 14, an organic EL layer 15, and a cathode 16 (transparent electrode) that are sequentially stacked on the active matrix substrate 11. Note that a plurality of anodes 14 are actually formed corresponding to each pixel 12. The organic EL layer 15 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.
次に、上記有機ＥＬ表示装置１０における画素１２の回路構成について、図６を用いて説明する。図６は、本発明の実施の形態に係る薄膜半導体装置１００を用いた画素の回路構成を示す図である。
Next, the circuit configuration of the pixel 12 in the organic EL display device 10 will be described with reference to FIG. FIG. 6 is a diagram showing a circuit configuration of a pixel using the thin film semiconductor device 100 according to the embodiment of the present invention.
図６に示すように、各画素１２は、直交する走査線１７と映像信号線１８とによって区画されており、駆動トランジスタ２１と、スイッチングトランジスタ２２と、コンデンサ２３と、有機ＥＬ素子１３とを備える。駆動トランジスタ２１は、有機ＥＬ素子１３を駆動するためのトランジスタであり、また、スイッチングトランジスタ２２は、画素１２を選択するためのトランジスタである。そして、駆動トランジスタ２１及びスイッチングトランジスタ２２の一方及び両方は、図１に示される薄膜半導体装置１００で構成することができる。
As shown in FIG. 6, each pixel 12 is partitioned by orthogonal scanning lines 17 and video signal lines 18, and includes a drive transistor 21, a switching transistor 22, a capacitor 23, and an organic EL element 13. . The drive transistor 21 is a transistor for driving the organic EL element 13, and the switching transistor 22 is a transistor for selecting the pixel 12. One or both of the drive transistor 21 and the switching transistor 22 can be configured by the thin film semiconductor device 100 shown in FIG.
駆動トランジスタ２１において、ゲート電極２１Ｇがスイッチングトランジスタ２２のドレイン電極２２Ｄに接続され、ソース電極２１Ｓが中継電極（不図示）を介して有機ＥＬ素子１３のアノードに接続され、ドレイン電極２１Ｄが電源線１９に接続される。
In the drive transistor 21, the gate electrode 21G is connected to the drain electrode 22D of the switching transistor 22, the source electrode 21S is connected to the anode of the organic EL element 13 via a relay electrode (not shown), and the drain electrode 21D is connected to the power supply line 19. Connected to.
また、スイッチングトランジスタ２２において、ゲート電極２２Ｇは走査線１７に接続され、ソース電極２２Ｓは映像信号線１８に接続され、ドレイン電極２２Ｄはコンデンサ２３及び駆動トランジスタ２１のゲート電極２１Ｇに接続されている。
In the switching transistor 22, the gate electrode 22G is connected to the scanning line 17, the source electrode 22S is connected to the video signal line 18, and the drain electrode 22D is connected to the capacitor 23 and the gate electrode 21G of the driving transistor 21.
この構成において、走査線１７にゲート信号が入力されて、スイッチングトランジスタ２２がオン状態になると、映像信号線１８を介して供給された映像信号電圧がコンデンサ２３に書き込まれる。そして、コンデンサ２３に書き込まれた映像信号電圧は、保持電圧として１フレーム期間を通じて保持される。この保持電圧により、駆動トランジスタ２１のコンダクタンスがアナログ的に変化し、発光階調に対応した駆動電流が、有機ＥＬ素子１３のアノードからカソードへと流れる。これにより、有機ＥＬ素子１３が発光し、所定の画像が表示される。
In this configuration, when a gate signal is input to the scanning line 17 and the switching transistor 22 is turned on, the video signal voltage supplied via the video signal line 18 is written to the capacitor 23. The video signal voltage written in the capacitor 23 is held as a holding voltage throughout one frame period. Due to this holding voltage, the conductance of the drive transistor 21 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 13. Thereby, the organic EL element 13 emits light and a predetermined image is displayed.
なお、本実施の形態では、有機ＥＬ素子を用いた有機ＥＬ表示装置について説明したが、液晶表示装置等、アクティブマトリクス基板が用いられる他の表示装置にも適用することができる。また、このように構成される表示装置については、フラットパネルディスプレイとして利用することができ、テレビジョンセット、パーソナルコンピュータ、携帯電話などのあらゆる表示パネルを有する電子機器に適用することができる。
Note that although an organic EL display device using an organic EL element has been described in this embodiment mode, the present invention can also be applied to other display devices using an active matrix substrate such as a liquid crystal display device. In addition, the display device configured as described above can be used as a flat panel display and can be applied to an electronic apparatus having any display panel such as a television set, a personal computer, and a mobile phone.
また、上記の実施の形態では、半導体膜（半導体層）としてシリコン薄膜を用いたが、シリコン薄膜以外の半導体膜を用いることもできる。例えば、ゲルマニウム（Ｇｅ）又はＳｉＧｅからなる半導体膜を結晶化させて多結晶半導体膜を形成することもできる。
In the above embodiment, the silicon thin film is used as the semiconductor film (semiconductor layer). However, a semiconductor film other than the silicon thin film can be used. For example, a polycrystalline semiconductor film can be formed by crystallizing a semiconductor film made of germanium (Ge) or SiGe.
以上、図面を参照してこの発明の実施形態を説明したが、この発明は、図示した実施形態のものに限定されない。図示した実施形態に対して、この発明と同一の範囲内において、あるいは均等の範囲内において、種々の修正や変形を加えることが可能である。
As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the thing of embodiment shown in figure. Various modifications and variations can be made to the illustrated embodiment within the same range or equivalent range as the present invention.
本発明は、薄膜トランジスタ等の薄膜半導体装置に有用であり、有機ＥＬ表示装置や液晶表示装置等の表示装置等において広く利用することができる。
The present invention is useful for thin film semiconductor devices such as thin film transistors, and can be widely used in display devices such as organic EL display devices and liquid crystal display devices.
１０ 有機ＥＬ表示装置
１１ アクティブマトリクス基板
１２ 画素
１３ 有機ＥＬ素子
１４ 陽極
１５ 有機ＥＬ層
１６ 陰極
１７ 走査線
１８ 映像信号線
２１ 駆動トランジスタ
２２ スイッチングトランジスタ
２１Ｇ，２２Ｇ，１２０，９２０ ゲート電極
２１Ｓ，２２Ｓ，１９１，９８１ ソース電極
２１Ｄ，２２Ｄ，１９２，９８２ ドレイン電極
２３ コンデンサ
１００，９００，９００Ａ，９００Ｂ 薄膜半導体装置
１１０，９１０ 基板
１３０，９３０ ゲート絶縁膜
１４０ チャネル層
１４０Ｍ 結晶シリコン薄膜
１５０ 第１非晶質半導体層
１５０Ｍ 第１アモルファスシリコン膜
１６０，９６０ チャネル保護層
１６０Ｍ 絶縁膜
１７０Ｍ 第２アモルファスシリコン膜
１７１，１７２ 第２非晶質半導体層
１８０Ｍ コンタクト層用膜
１８１，１８２，９７１，９７２ コンタクト層
９４０ 結晶シリコン層
９５０ 非結晶シリコン層 DESCRIPTION OFSYMBOLS 10 Organic EL display device 11 Active matrix substrate 12 Pixel 13 Organic EL element 14 Anode 15 Organic EL layer 16 Cathode 17 Scan line 18 Video signal line 21 Drive transistor 22 Switching transistor 21G, 22G, 120, 920 Gate electrode 21S, 22S, 191 , 981 Source electrode 21D, 22D, 192, 982 Drain electrode 23 Capacitor 100, 900, 900A, 900B Thin film semiconductor device 110, 910 Substrate 130, 930 Gate insulating film 140 Channel layer 140M Crystal silicon thin film 150 First amorphous semiconductor layer 150M First amorphous silicon film 160,960 Channel protective layer 160M Insulating film 170M Second amorphous silicon film 171,172 Second amorphous semiconductor layer 180M For contact layer 181,182,971,972 contact layer 940 crystalline silicon layer 950 amorphous silicon layer
１１ アクティブマトリクス基板
１２ 画素
１３ 有機ＥＬ素子
１４ 陽極
１５ 有機ＥＬ層
１６ 陰極
１７ 走査線
１８ 映像信号線
２１ 駆動トランジスタ
２２ スイッチングトランジスタ
２１Ｇ，２２Ｇ，１２０，９２０ ゲート電極
２１Ｓ，２２Ｓ，１９１，９８１ ソース電極
２１Ｄ，２２Ｄ，１９２，９８２ ドレイン電極
２３ コンデンサ
１００，９００，９００Ａ，９００Ｂ 薄膜半導体装置
１１０，９１０ 基板
１３０，９３０ ゲート絶縁膜
１４０ チャネル層
１４０Ｍ 結晶シリコン薄膜
１５０ 第１非晶質半導体層
１５０Ｍ 第１アモルファスシリコン膜
１６０，９６０ チャネル保護層
１６０Ｍ 絶縁膜
１７０Ｍ 第２アモルファスシリコン膜
１７１，１７２ 第２非晶質半導体層
１８０Ｍ コンタクト層用膜
１８１，１８２，９７１，９７２ コンタクト層
９４０ 結晶シリコン層
９５０ 非結晶シリコン層 DESCRIPTION OF
Claims (8)
- 基板と、
前記基板上に形成されたゲート電極と、
前記ゲート電極上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成された多結晶半導体からなるチャネル層と、
前記チャネル層上に形成された第１非晶質半導体層と、
前記第１非晶質半導体層上に形成された有機絶縁層と、
前記第１非晶質半導体層及び前記チャネル層の一方側の側面及び他方側の側面のそれぞれに形成された一対の第２非晶質半導体層と、
前記一対の第２非晶質半導体層それぞれの上に、前記第２非晶質半導体層を介して前記チャネル層の側面にコンタクトするように形成された一対のコンタクト層と、
前記一対のコンタクト層の一方の上に形成されたソース電極、及び前記コンタクト層の他方の上に形成されたドレイン電極とを備え、
前記ゲート電極、前記チャネル層、前記第１非晶質半導体層、及び前記有機絶縁層は、上面視したときに外形輪郭線が一致するように積層され、
前記第１非晶質半導体層の局在準位密度は、前記第２非晶質半導体層の局在準位密度より高く、
前記第２非晶質半導体層のバンドギャップは、前記第１非晶質半導体層のバンドギャップより大きい
薄膜半導体装置。 A substrate,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A channel layer made of a polycrystalline semiconductor formed on the gate insulating film;
A first amorphous semiconductor layer formed on the channel layer;
An organic insulating layer formed on the first amorphous semiconductor layer;
A pair of second amorphous semiconductor layers formed respectively on one side surface and the other side surface of the first amorphous semiconductor layer and the channel layer;
A pair of contact layers formed on each of the pair of second amorphous semiconductor layers so as to contact side surfaces of the channel layer via the second amorphous semiconductor layer;
A source electrode formed on one of the pair of contact layers, and a drain electrode formed on the other of the contact layers,
The gate electrode, the channel layer, the first amorphous semiconductor layer, and the organic insulating layer are stacked so that the outline contours match when viewed from above.
The localized level density of the first amorphous semiconductor layer is higher than the localized level density of the second amorphous semiconductor layer,
A thin film semiconductor device in which a band gap of the second amorphous semiconductor layer is larger than a band gap of the first amorphous semiconductor layer. - 前記有機絶縁層の下面の外形輪郭線は、上面視したときに、前記ゲート電極の外形輪郭線の内側に、０．５μｍ以下後退している
請求項１に記載の薄膜半導体装置。 The thin film semiconductor device according to claim 1, wherein an outer contour line on a lower surface of the organic insulating layer recedes by 0.5 μm or less inside an outer contour line of the gate electrode when viewed from above. - 前記有機絶縁層の下面の外形輪郭線は、上面視したときに、前記ゲート電極の外形輪郭線の内側に、前記第２非晶質半導体層の膜厚以上後退している
請求項２に記載の薄膜半導体装置。 3. The outline of the lower surface of the organic insulating layer recedes more than the thickness of the second amorphous semiconductor layer inside the outline of the gate electrode when viewed from above. Thin film semiconductor device. - 前記一対の第２非晶質半導体層、前記一対のコンタクト層、前記ソース電極、及び前記ドレイン電極は、前記有機絶縁層の上面の一部および前記有機絶縁層の側面に延在する
請求項１～３のいずれか１項に記載の薄膜半導体装置。 The pair of second amorphous semiconductor layers, the pair of contact layers, the source electrode, and the drain electrode extend to a part of an upper surface of the organic insulating layer and a side surface of the organic insulating layer. 4. The thin film semiconductor device according to any one of items 1 to 3. - 前記第１非晶質半導体層の膜厚は、５０ｎｍ以下である
請求項１～４のいずれか１項に記載の薄膜半導体装置。 The thin film semiconductor device according to any one of claims 1 to 4, wherein a film thickness of the first amorphous semiconductor layer is 50 nm or less. - 基板を準備する第１工程と、
前記基板上にゲート電極と形成する第２工程と、
前記ゲート電極上にゲート絶縁膜を形成する第３工程と、
前記ゲート絶縁膜上に結晶半導体層を形成する第４工程と、
前記結晶半導体層上に、非晶質半導体層を形成する第５工程と、
前記非晶質半導体層上に、有機絶縁層を形成する第６工程と、
前記結晶半導体層および前記非晶質半導体層をエッチングして、前記ゲート電極に重畳する位置にチャネル層及び第１非晶質半導体層を形成する第７工程と、
前記チャネル層及び前記第１非晶質半導体層の一方側の側面及び他方側の側面のそれぞれに第２非晶質半導体層を形成する第８工程と、
前記一対の第２非晶質半導体層それぞれの上に、前記第２非晶質半導体層を介して前記チャネル層の側面にコンタクトするように一対のコンタクト層を形成する第９工程と、
前記一対のコンタクト層の一方の上にソース電極を形成し、及び前記一対のコンタクト層の他方の上にドレイン電極を形成する第９工程とを含み、
前記第６工程では、前記非晶質半導体層上に有機絶縁層の前駆体の有機材料を塗布し、乾燥させる工程と、前記基板の前記ゲート電極が形成された面と反対側の面から、前記有機材料に対して前記ゲート電極をマスクに用いて前記有機材料を感光させる光で露光する工程と、前記有機材料を現像する工程とにより、前記有機絶縁層の下面の外形輪郭線が、上面視したときに、前記ゲート電極の外形輪郭線の内側に後退するように形成する
薄膜半導体装置の製造方法。 A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating film on the gate electrode;
A fourth step of forming a crystalline semiconductor layer on the gate insulating film;
A fifth step of forming an amorphous semiconductor layer on the crystalline semiconductor layer;
A sixth step of forming an organic insulating layer on the amorphous semiconductor layer;
Etching the crystalline semiconductor layer and the amorphous semiconductor layer to form a channel layer and a first amorphous semiconductor layer at a position overlapping the gate electrode;
An eighth step of forming a second amorphous semiconductor layer on each of one side surface and the other side surface of the channel layer and the first amorphous semiconductor layer;
A ninth step of forming a pair of contact layers on each of the pair of second amorphous semiconductor layers so as to contact the side surfaces of the channel layer via the second amorphous semiconductor layers;
Forming a source electrode on one of the pair of contact layers, and forming a drain electrode on the other of the pair of contact layers,
In the sixth step, a step of applying an organic material as a precursor of an organic insulating layer on the amorphous semiconductor layer and drying, and a surface of the substrate opposite to the surface on which the gate electrode is formed, The organic material is exposed to light using the gate electrode as a mask to expose the organic material, and the organic material is developed. A method of manufacturing a thin film semiconductor device, wherein the thin film semiconductor device is formed so as to recede to the inside of the outline of the gate electrode when viewed. - 前記第７工程において、現像された前記有機絶縁層をマスクに用いて前記エッチングを行うことにより、前記有機絶縁層の下面の外形輪郭線が、上面視したときに、前記ゲート電極の外形輪郭線の内側に、前記第２非晶質半導体層の膜厚以上後退するように形成する
請求項６に記載の薄膜半導体装置の製造方法。 In the seventh step, by performing the etching using the developed organic insulating layer as a mask, the outer contour of the lower surface of the organic insulating layer is the outer contour of the gate electrode when viewed from above. The method for manufacturing a thin film semiconductor device according to claim 6, wherein the thin film semiconductor device is formed so as to recede more than the thickness of the second amorphous semiconductor layer. - 前記第１非晶質半導体層の局在準位密度は、前記第２非晶質半導体層の局在準位密度より高くなるように形成され、
前記第２非晶質半導体層のバンドギャップは、前記第１非晶質半導体層のバンドギャップより大きくなるように形成される
請求項６又は７に記載の薄膜半導体装置の製造方法。 The localized level density of the first amorphous semiconductor layer is formed to be higher than the localized level density of the second amorphous semiconductor layer,
8. The method of manufacturing a thin film semiconductor device according to claim 6, wherein a band gap of the second amorphous semiconductor layer is formed to be larger than a band gap of the first amorphous semiconductor layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425266A (en) * | 2013-08-23 | 2015-03-18 | 业鑫科技顾问股份有限公司 | Thin film transistor and method for manufacturing display array substrate using the thin film transistor |
| CN104425621A (en) * | 2013-08-23 | 2015-03-18 | 业鑫科技顾问股份有限公司 | Thin film transistor and display array substrate using same |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013118233A1 (en) * | 2012-02-06 | 2013-08-15 | パナソニック株式会社 | Thin film semiconductor device manufacturing method and thin film semiconductor device |
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| WO2015001755A1 (en) | 2013-07-05 | 2015-01-08 | パナソニック株式会社 | Thin-film transistor element, method for manufacturing same, and display device |
| JP2017143135A (en) * | 2016-02-09 | 2017-08-17 | 株式会社ジャパンディスプレイ | Thin film transistor |
| CN105845737B (en) * | 2016-05-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and its manufacturing method, array substrate, display device |
| KR20180045964A (en) * | 2016-10-26 | 2018-05-08 | 삼성디스플레이 주식회사 | Display device and manufacturing method thereof |
| CN107221503A (en) * | 2017-06-02 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of preparation method of thin film transistor (TFT), thin film transistor (TFT) and display base plate |
| CN109508135B (en) * | 2017-09-15 | 2022-05-27 | 上海耕岩智能科技有限公司 | Electronic equipment command executing method based on fingerprint identification and electronic equipment |
| CN113314615A (en) * | 2021-06-04 | 2021-08-27 | 华南理工大学 | Thin film transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270701A (en) * | 1997-03-27 | 1998-10-09 | Advanced Display:Kk | Thin film transistor and its production |
| JP2001119029A (en) * | 1999-10-18 | 2001-04-27 | Fujitsu Ltd | Thin-film transistor, manufacturing method therefor, and liquid crystal display provided, with the transistor |
| JP2009076894A (en) * | 2007-08-31 | 2009-04-09 | Semiconductor Energy Lab Co Ltd | Display device and manufacturing method of the same |
| JP2010287634A (en) * | 2009-06-09 | 2010-12-24 | Casio Computer Co Ltd | Transistor substrate having transistor, and method of manufacturing transistor substrate having transistor |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS644071A (en) | 1987-06-26 | 1989-01-09 | Nippon Telegraph & Telephone | Thin film transistor and manufacture thereof |
| JPH098311A (en) | 1995-06-21 | 1997-01-10 | Hitachi Ltd | Fabrication and structure of thin film semiconductor device |
| JP4524298B2 (en) | 2007-06-04 | 2010-08-11 | パナソニック株式会社 | Manufacturing method of semiconductor device |
| JP2009049384A (en) | 2007-07-20 | 2009-03-05 | Semiconductor Energy Lab Co Ltd | Light emitting device |
| JP2010135640A (en) | 2008-12-05 | 2010-06-17 | Panasonic Corp | Field-effect transistor |
| JP5367092B2 (en) | 2010-06-04 | 2013-12-11 | パナソニック株式会社 | Method for manufacturing thin film transistor substrate |
| JP5849215B2 (en) | 2010-06-21 | 2016-01-27 | パナソニックＩｐマネジメント株式会社 | Ultraviolet semiconductor light emitting device |
| CN102959712A (en) | 2011-06-17 | 2013-03-06 | 松下电器产业株式会社 | Thin-film transistor and method of manufacturing thin-film transistor |
-
2012
- 2012-10-23 US US13/997,802 patent/US8796692B2/en active Active
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- 2012-10-23 CN CN201280004416.XA patent/CN103314444B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270701A (en) * | 1997-03-27 | 1998-10-09 | Advanced Display:Kk | Thin film transistor and its production |
| JP2001119029A (en) * | 1999-10-18 | 2001-04-27 | Fujitsu Ltd | Thin-film transistor, manufacturing method therefor, and liquid crystal display provided, with the transistor |
| JP2009076894A (en) * | 2007-08-31 | 2009-04-09 | Semiconductor Energy Lab Co Ltd | Display device and manufacturing method of the same |
| JP2010287634A (en) * | 2009-06-09 | 2010-12-24 | Casio Computer Co Ltd | Transistor substrate having transistor, and method of manufacturing transistor substrate having transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425266A (en) * | 2013-08-23 | 2015-03-18 | 业鑫科技顾问股份有限公司 | Thin film transistor and method for manufacturing display array substrate using the thin film transistor |
| CN104425621A (en) * | 2013-08-23 | 2015-03-18 | 业鑫科技顾问股份有限公司 | Thin film transistor and display array substrate using same |
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