JPWO2013072966A1 - Thin film semiconductor device and manufacturing method thereof - Google Patents

Abstract

The band gap energy of the semiconductor layer (4) formed on the gate insulating film (3) is 1.6 eV or less. The insulating layer (5) formed on the semiconductor layer (4) includes a first insulating layer region (5a) disposed outside the first contact opening (8) and a second contact opening (9). And a second insulating layer region (5b) disposed on the outer side. The first insulating layer region (5a) is disposed above one end portion of the gate electrode (2), and the second insulating layer region (5b) is disposed above the other end portion of the gate electrode (2).

Description

  The present invention relates to a thin film semiconductor device used in a display device such as an organic EL display and a method for manufacturing the same.

  In recent years, organic EL displays using organic EL (Electro Luminescence) have attracted attention as one of the next generation flat panel displays that replace liquid crystal displays. A thin film semiconductor device called a thin film transistor (TFT) is used for an active matrix display device such as an organic EL display.

  As this thin film semiconductor device, a bottom gate type thin film semiconductor device in which a gate electrode is formed on the substrate side with respect to a semiconductor layer is generally used (for example, see Patent Documents 1 to 3). FIG. 13 is a cross-sectional view showing a configuration of a conventional bottom gate type thin film semiconductor device. In the illustrated thin film semiconductor device 500, a gate electrode 52 is formed on a substrate 51, and a gate insulating film 53 is formed on the gate electrode 52 and on the substrate 51 outside the both ends. A semiconductor layer 54 having a channel region is formed on the gate insulating film 53. The semiconductor layer 54 is a polycrystalline silicon thin film formed by crystallizing amorphous silicon (amorphous silicon). A source electrode 57S and a drain electrode 57D are formed on the semiconductor layer 54 with a pair of contact layers 56 interposed therebetween. A channel protective layer 55 that functions as a channel etching stopper layer is formed above the channel region of the semiconductor layer 54.

In the manufacturing process of the thin film semiconductor device 500, when the gate insulating film 53 is formed by plasma CVD (Chemical Vapor Deposition) or the like, due to the film thickness of the gate electrode 52, gate insulation corresponding to both ends of the gate electrode 52 is obtained. A stepped portion 58 is formed at the site of the film 53. FIG. 14 is an electron micrograph showing a cross section of a stepped portion of a gate insulating film in a conventional thin film semiconductor device. As shown in FIG. 14, the film thickness t ₁ of the flat portion 59 of the gate insulating film 53 is about 110 nm, the film thickness t ₂ of the gate electrode 52 is about 50 nm, and the film thickness ratio R is R = t ₁ / t ₂ = 110 nm / 50 nm = 2.2. The film thickness t ₃ in the step portion 58 of the gate insulating film 53 is about 70 nm, which is thinner than the film thickness t ₁ in the flat portion 59 of the gate insulating film 53.

Japanese Patent Laid-Open No. 4-348041 JP-A-4-360575 JP 2011-9719 A

In the structure of the conventional thin film semiconductor device 500 described above, by the film thickness t ₃ at the stepped portion 58 of the gate insulating film 53 becomes thinner, the electric field at the site of the semiconductor layer 54 corresponding to the stepped portion 58 of the gate insulating film 53 concentrate. As a result, when the thin film semiconductor device 500 is turned off, a leak current due to a tunnel current is generated in the portion of the semiconductor layer 54. Therefore, in the conventional thin film semiconductor device 500, it has been a problem to improve the off characteristics by suppressing the leakage current during the off operation.

Generally, in order to lower the wiring resistance of the thin film semiconductor device 500, the thickness t ₂ of the gate electrode 52 is thicker is preferred. Further, in order to increase the ON current of the thin film semiconductor device 500, the thickness t ₁ in the flat portion 59 of the gate insulating film 53 is preferably thin. That is, in order to simultaneously realize a decrease in wiring resistance and an increase in on-current, the film thickness t ₁ in the flat portion 59 of the gate insulating film 53 and the film of the gate electrode 52 are set so that the film thickness ratio R becomes smaller. the thickness t ₂ of the need to set respectively.

However, when the thickness ratio R decreases, it becomes steeper shape of the step portion 58 of the gate insulating film 53, the thickness t ₃ becomes thinner in the step portion 58 of the gate insulating film 53. As a result, the electric field strength at the portion of the semiconductor layer 54 increases during the off operation, and the magnitude of the leak current generated also increases.

  FIG. 15 is a diagram showing a result of simulating a current density distribution during an off operation in a conventional thin film semiconductor device. In this simulation, a thin film semiconductor device 500 having the structure shown in FIG. 13 is used, molybdenum tungsten (MoW) having a thickness of 50 nm as the gate electrode 52, silicon oxide (SiO) having a thickness of 120 nm as the gate insulating film 53, and the semiconductor layer 54. Polycrystalline silicon having a thickness of 50 nm, silicon oxide (SiO) having a thickness of 500 nm as the channel protective layer 55, amorphous silicon having a thickness of 40 nm as the contact layer 56, and aluminum having a thickness of 600 nm as the source electrode 57S and the drain electrode 57D ( Al) was used. Further, −20 V was applied as the gate-source voltage, and 5.1 V was applied as the drain-source voltage. In FIG. 15, the density distribution of the leak current generated during the off operation is represented by contour lines. As shown by the contour lines in FIG. 15, it can be understood that the leakage current flows through the semiconductor layer 54 during the off operation. The leakage current flows in the direction indicated by the arrow in FIG.

FIG. 16 is a diagram showing a simulation result of a band-to-band tunnel rate during an off operation in a conventional thin film semiconductor device. The simulation conditions are substantially the same as the simulation conditions of FIG. In FIG. 16, the distribution of the band-to-band tunnel rate (/ scm ³ ) is represented by contour lines. As can be seen from the contour lines surrounded by the solid line in FIG. 16, it can be understood that a leakage current is generated at the portion of the semiconductor layer 54 corresponding to the step portion of the gate insulating film 53 during the off operation.

  As described above, in the configuration of the conventional thin film semiconductor device, the electric field concentrates at the portion of the semiconductor layer corresponding to the step portion due to the thin film thickness at the step portion of the gate insulating film. Therefore, there is a problem that a leakage current due to a tunnel current is generated during the off operation, and the off characteristics are not good. Further, when the film thickness ratio R is decreased, the film thickness at the stepped portion of the gate insulating film becomes thinner, so that the magnitude of the leak current is further increased. Therefore, the film thickness ratio R cannot be reduced, and there is a problem that it is difficult to simultaneously realize a decrease in wiring resistance and an increase in on-current.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide a thin film semiconductor device capable of suppressing a leakage current during an off operation and a manufacturing method thereof.

  In order to achieve the above object, a thin film semiconductor device according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, the gate electrode, and the substrate outside the both ends thereof. A gate insulating film formed across, a semiconductor layer formed on the gate insulating film and having a channel region, a first contact opening formed on the semiconductor layer, and spaced apart; An insulating layer having a contact opening; a source electrode formed above the insulating layer; and a drain electrode formed above the insulating layer and opposed to the source electrode. The band gap energy of the layer is 1.6 eV or less, and the insulating layer includes a first insulating layer region disposed outside the first contact opening and an outside of the second contact opening. A second insulating layer region disposed on the gate electrode, wherein the first insulating layer region is disposed above one end portion of the gate electrode, and the second insulating layer region is disposed on the other end portion of the gate electrode. The source electrode is electrically connected to the channel region through the first contact opening, and the drain electrode is electrically connected to the channel region through the second contact opening. Yes.

  As described above, in the thin film semiconductor device of the present invention, the first insulating layer region is disposed above one end portion of the gate electrode, and the second insulating layer region is disposed above the other end portion of the gate electrode. ing. Since the path of leakage current can be blocked by the first insulating layer region and the second insulating layer region, the electric field concentration portion of the semiconductor layer, that is, the portion of the semiconductor layer corresponding to both ends of the gate electrode, No longer contributes to Thereby, it can suppress that the generated tunnel current contributes as a leak current, and can improve an OFF characteristic. In addition, by increasing the thickness of the gate electrode and reducing the thickness of the flat portion of the gate insulating film, the thickness of the gate insulating film corresponding to both ends of the gate electrode is further reduced. However, since the leakage current can be suppressed as described above, it is possible to simultaneously realize a decrease in wiring resistance and an increase in on-current.

FIG. 1 is a cross-sectional view showing a configuration of a thin film semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is an enlarged cross-sectional view showing a part of the thin film semiconductor device of FIG. FIG. 3A is a plan view showing the positional relationship between the gate electrode and the insulating layer. FIG. 3B is a plan view showing the positional relationship between the gate electrode, the insulating layer, the source electrode, and the drain electrode. FIG. 4A is a cross-sectional view showing a first step in the method of manufacturing a thin film semiconductor device. FIG. 4B is a cross-sectional view showing a second step in the method of manufacturing a thin film semiconductor device. FIG. 4C is a cross-sectional view showing a third step in the method of manufacturing a thin film semiconductor device. FIG. 4D is a cross-sectional view showing a fourth step in the method of manufacturing a thin film semiconductor device. FIG. 4E is a cross-sectional view showing a fifth step in the method of manufacturing a thin film semiconductor device. FIG. 4F is a cross-sectional view showing a sixth step in the method for manufacturing the thin film semiconductor device. FIG. 4G is a cross-sectional view showing a step of forming a contact layer in the method for manufacturing a thin film semiconductor device. FIG. 4H is a cross-sectional view showing a seventh step in the method for manufacturing the thin film semiconductor device. FIG. 4I is a cross-sectional view showing a seventh step in the method for manufacturing the thin film semiconductor device. FIG. 5A is a diagram showing the results of simulating the electrical characteristics of the thin film semiconductor device of the present invention and the electrical characteristics of a conventional thin film semiconductor device. FIG. 5B is a diagram showing the results of testing the electrical characteristics of the thin film semiconductor device of the present invention and the electrical characteristics of the conventional thin film semiconductor device using actual devices. FIG. 6 is a diagram showing the result of simulating the current density distribution during the off operation in the thin film semiconductor device of the present invention. FIG. 7A is a diagram illustrating a result of simulating a change in drain current with respect to band gap energy of a semiconductor layer. FIG. 7B is a diagram illustrating a result of simulating a change in drain current with respect to a gate-source voltage. FIG. 8A is a plan view for explaining the definition of dimension A, dimension B, and dimension C. FIG. FIG. 8B is a plan view for explaining the definition of the dimension A, the dimension B, and the dimension C. FIG. 9A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension C when the dimension W is 5 μm, the dimension A is 2 μm, and the dimension B is 3 μm. FIG. 9B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension C when the dimension W is 50 μm, the dimension A is 2 μm, and the dimension B is 3 μm. FIG. 9C is a diagram more clearly showing the change in parasitic resistance by reducing the scale of the vertical axis in FIG. 9B. FIG. 10A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension A when the dimension W is 5 μm, the dimension B is 3 μm, and the dimension C is 3 μm. FIG. 10B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension A when the dimension W is 50 μm, the dimension B is 3 μm, and the dimension C is 3 μm. FIG. 11A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension B when the dimension W is 5 μm, the dimension A is 2 μm, and the dimension C is 3 μm. FIG. 11B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension B when the dimension W is 50 μm, the dimension A is 2 μm, and the dimension C is 3 μm. FIG. 11C is a diagram for explaining a model of parasitic resistance. FIG. 12A is a plan view showing the positional relationship between the gate electrode and the insulating layer in the thin film semiconductor device according to Embodiment 2 of the present invention. FIG. 12B is a plan view showing an arrangement relationship of the gate electrode, the insulating layer, the source electrode, and the drain electrode in the thin film semiconductor device according to Embodiment 2 of the present invention. FIG. 13 is a cross-sectional view showing a configuration of a conventional thin film semiconductor device. FIG. 14 is an electron micrograph showing a cross section of a stepped portion of a gate insulating film in a conventional thin film semiconductor device. FIG. 15 is a diagram showing a result of simulating a current density distribution during an off operation in a conventional thin film semiconductor device. FIG. 16 is a diagram showing a result of simulating a band-to-band tunnel rate during an off operation in a conventional thin film semiconductor device.

  One aspect of a thin film semiconductor device according to the present invention includes a substrate, a gate electrode formed on the substrate, and a gate insulating film formed on the gate electrode and on the substrate outside the both end portions. A semiconductor layer formed on the gate insulating film and having a channel region; and an insulating layer formed on the semiconductor layer and having a first contact opening and a second contact opening spaced apart from each other. A source electrode formed above the insulating layer; and a drain electrode formed above the insulating layer and formed to face the source electrode. The band gap energy of the semiconductor layer is 1. 6 eV or less, and the insulating layer includes a first insulating layer region disposed outside the first contact opening and a second insulating layer region disposed outside the second contact opening. The first insulating layer region is disposed above one end portion of the gate electrode, and the second insulating layer region is disposed above the other end portion of the gate electrode, and the source electrode Is electrically connected to the channel region through the first contact opening, and the drain electrode is electrically connected to the channel region through the second contact opening.

  According to this aspect, the first insulating layer region is disposed above one end portion of the gate electrode, and the second insulating layer region is disposed above the other end portion of the gate electrode. Since the path of leakage current can be blocked by the first insulating layer region and the second insulating layer region, the electric field concentration portion of the semiconductor layer, that is, the portion of the semiconductor layer corresponding to both ends of the gate electrode, No longer contributes to Thereby, it can suppress that the generated tunnel current contributes as a leak current, and can improve an OFF characteristic. In addition, by increasing the thickness of the gate electrode and reducing the thickness of the flat portion of the gate insulating film, the thickness of the gate insulating film corresponding to both ends of the gate electrode is further reduced. However, since the leakage current can be suppressed as described above, it is possible to simultaneously realize a decrease in wiring resistance and an increase in on-current.

  In one aspect of the thin film semiconductor device according to the present invention, the insulating layer further includes a third insulating layer region disposed between the first contact opening and the second contact opening, The third insulating layer region is preferably disposed above the central portion of the gate electrode and functions as a channel etching stopper layer that covers the channel region.

  According to this aspect, by functioning the third insulating layer region as a channel etching stopper layer, the channel region of the semiconductor layer can be prevented from being etched in the etching process in the manufacturing process of the thin film semiconductor device.

  In the aspect of the thin film semiconductor device according to the present invention, it is preferable that the source electrode and the drain electrode have a size in the channel width direction larger than the size of the third insulating layer region in the channel width direction.

  According to this aspect, the parasitic resistance between the channel region of the semiconductor layer and the source electrode and the drain electrode can be reduced.

  In the aspect of the thin film semiconductor device according to the present invention, it is preferable that the source electrode and the drain electrode protrude 2 μm or more from both ends in the channel width direction of the third insulating layer region.

  According to this aspect, it is possible to effectively reduce the parasitic resistance between the channel region of the semiconductor layer and the source electrode and the drain electrode.

  In the aspect of the thin film semiconductor device according to the present invention, it is preferable that the source electrode and the drain electrode protrude 4 μm or more from both ends in the channel width direction of the third insulating layer region.

  According to this aspect, the parasitic resistance between the channel region of the semiconductor layer and the source electrode and the drain electrode can be more effectively reduced.

  In addition, according to one aspect of the method for manufacturing a thin film semiconductor device according to the present invention, a first step of preparing a substrate, a second step of forming a gate electrode on the substrate, and on the gate electrode and on both ends thereof A third step of forming a gate insulating film over the outer substrate, a fourth step of forming a semiconductor layer having a channel region on the gate insulating film, and a second step of forming an insulating layer on the semiconductor layer. 5 steps, a 6th step of forming a first contact opening and a second contact opening spaced apart in the insulating layer, and a source electrode and the source electrode above the insulating layer And forming a drain electrode. In the fourth step, the semiconductor layer having a band gap energy of 1.6 eV or less is formed. In the sixth step, the first contact is formed on the insulating layer. By forming the opening and the second contact opening, a first insulating layer region disposed above one end of the gate electrode is formed outside the first contact opening, and the first contact opening is formed. A second insulating layer region disposed above the other end of the gate electrode is formed outside the two contact opening, and in the seventh step, the source electrode is passed through the first contact opening. The drain region is electrically connected to the channel region, and the drain electrode is electrically connected to the channel region through the second contact opening.

  According to this aspect, in the sixth step, the first insulating layer region disposed above the one end portion of the gate electrode is formed, and the second insulating layer region disposed above the other end portion of the gate electrode. Is formed. Since the path of leakage current can be blocked by the first insulating layer region and the second insulating layer region, the electric field concentration portion of the semiconductor layer, that is, the portion of the semiconductor layer corresponding to both ends of the gate electrode, No longer contributes to Thereby, it can suppress that the generated tunnel current contributes as a leak current, and can improve an OFF characteristic. Further, in the second step, the gate electrode film is formed thick, and in the third step, the gate insulating film corresponding to both ends of the gate electrode is formed by reducing the film thickness in the flat part of the gate insulating film. Even when the thickness is reduced, the leakage current can be suppressed as described above, so that a reduction in wiring resistance and an increase in on-current can be realized at the same time.

(Embodiment)
Hereinafter, a thin film semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. The present invention is specified based on the description of the scope of claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the claims are not necessarily required to achieve the object of the present invention, but are described as constituting more preferable embodiments. . Each figure is a schematic diagram and is not necessarily shown strictly.

(Embodiment 1)
First, the configuration of the thin film semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a configuration of a thin film semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is an enlarged cross-sectional view showing a part of the thin film semiconductor device of FIG.

  As shown in FIG. 1, a thin film semiconductor device 100 according to the present embodiment is a bottom gate type thin film transistor device. The thin film semiconductor device 100 includes a substrate 1, a gate electrode 2, a gate insulating film 3, a semiconductor layer 4, an insulating layer 5, a pair of contact layers 6, a source electrode 7S, and a drain electrode 7D. Hereinafter, each component of the thin film semiconductor device 100 according to the present embodiment will be described in detail.

The substrate 1 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass. In order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the semiconductor layer 4, a silicon nitride film (SiN _x ), silicon oxide (SiO _y ), or silicon oxynitride is formed on the substrate 1. An undercoat layer composed of a film (SiO _y N _x ) or the like may be formed. This undercoat layer may play a role of mitigating the influence of heat on the substrate 1 in a high-temperature heat treatment process such as laser annealing.

The gate electrode 2 is patterned in a predetermined shape on the substrate 1. The gate electrode 2 can have a single layer structure or a multilayer structure such as a conductive material and an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti) ), Chromium (Cr), molybdenum tungsten (MoW), or the like. The film thickness t ₂ (see FIG. 2) of the gate electrode 2 is about 50 nm, for example.

The gate insulating film 3 is formed over the gate electrode 2 and the substrate 1 outside the both ends in the channel length direction (left-right direction in FIG. 1). That is, the gate insulating film 3 is formed on the entire surface of the substrate 1 so as to cover the gate electrode 2. The gate insulating film 3 is, for example, a single layer film of silicon oxide (SiO _y ), silicon nitride (SiN _x ), silicon oxynitride film (SiO _y N _x ), aluminum oxide (AlO _z ), and tantalum oxide (TaO _w ). Or it can comprise by these laminated films. The film thickness t ₁ (see FIG. 2) in the flat portion 11 of the gate insulating film 3 is, for example, about 110 nm. Further, as shown in FIG. 2, a stepped portion 10 is formed in the portion of the gate insulating film 3 corresponding to both end portions of the gate electrode 2. The film thickness t ₃ in the step portion 10 of the gate insulating film 3 is thinner than the film thickness t ₁ and is, for example, about 70 nm.

  The semiconductor layer 4 is formed on the gate insulating film 3 and has a channel region. This channel region is a region where the movement of carriers is controlled by the voltage of the gate electrode 2. The semiconductor layer 4 is composed of a polycrystalline silicon thin film having a crystalline structure. The polycrystalline silicon thin film is formed by crystallizing amorphous amorphous silicon (amorphous silicon), for example. The film thickness of the semiconductor layer 4 can be, for example, about 20 nm to 100 nm. As will be described later, the band gap energy of the semiconductor layer 4 is configured to be 1.6 eV or less. When the semiconductor layer 4 is composed of a polycrystalline silicon thin film as in the present embodiment, the band gap energy of the semiconductor layer 4 is about 1.1 eV.

  The insulating layer 5 is configured as an organic material layer mainly containing an organic material containing silicon, oxygen, and carbon. In the present embodiment, the insulating layer 5 can be formed by patterning and solidifying a photosensitive coating type organic material.

  The organic material constituting the insulating layer 5 includes, for example, an organic resin material, a surfactant, a solvent, and a photosensitive agent. The organic resin material that is the main component of the insulating layer 5 is a photosensitive or non-photosensitive organic resin composed of one or more of polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, and the like. Materials can be used. As the surfactant, a surfactant composed of a silicon compound such as siloxane can be used. As the solvent, an organic solvent such as propylene glycol monomethyl ether acetate or 1,4-dioxane can be used. As the photosensitizer, a positive photosensitizer such as naphthoquinone diazite can be used. Note that the photosensitive agent contains not only carbon but also sulfur.

  The insulating layer 5 can be formed by a coating method such as a spin coating method using the organic material. The insulating layer 5 can be formed not only by a coating method but also by various methods such as a droplet discharge method. For example, an organic material having a predetermined shape can be selectively formed by using a printing method that can form a predetermined pattern such as screen printing or offset printing. The film thickness of the insulating layer 5 can be, for example, 300 nm to 1000 nm. In the present embodiment, the insulating layer 5 is made of an organic material. However, instead of this structure, the insulating layer 5 can be made of an inorganic material.

  The insulating layer 5 is formed with a first contact opening 8 and a second contact opening 9 that are spaced apart from each other. By forming the first contact opening 8 and the second contact opening 9, the insulating layer 5 is divided into a first insulating layer region 5a, a second insulating layer region 5b, and a third insulating layer region 5c. . FIG. 3A is a plan view showing the positional relationship between the gate electrode and the insulating layer. As shown in FIG. 3A, the first insulating layer region 5a covers the part of the semiconductor layer 4 above one end of the gate electrode 2, that is, the semiconductor layer 4 corresponding to one stepped part 10 of the gate insulating film 3 from above. In addition, it is disposed outside the first contact opening 8 in the channel length direction. The second insulating layer region 5b covers the portion of the semiconductor layer 4 corresponding to the other stepped portion 10 of the gate insulating film 3 from above the other end portion of the gate electrode 2, and the second insulating layer region 5b. The two contact openings 9 are disposed outside the channel length direction. The third insulating layer region 5c is provided above the central portion of the gate electrode 2, that is, so as to cover the portion of the semiconductor layer 4 corresponding to the flat portion 11 of the gate insulating film from above, and the first contact opening portion. 8 and the second contact opening 9.

  The third insulating layer region 5 c functions as a channel etching stopper (CES) layer that protects the channel region of the semiconductor layer 4. Thereby, the third insulating layer region 5 c prevents the channel region of the semiconductor layer 4 from being etched in the etching process when forming the pair of contact layers 6. That is, in the etching process when forming the pair of contact layers 6, the upper surface of the third insulating layer region 5c that functions as a channel etching stopper layer is etched.

The pair of contact layers 6 are formed above the channel region of the semiconductor layer 4 via the insulating layer 5. In addition, the pair of contact layers 6 are disposed to face each other with a gap therebetween. The contact layer 6 is composed of an amorphous semiconductor film containing impurities at a high concentration. The contact layer 6 can be formed of, for example, an n-type semiconductor film obtained by doping amorphous silicon with phosphorus (P) as an impurity. The contact layer 6 is an n ⁺ layer containing a high-concentration impurity of 1 × 10 ¹⁹ atm / cm ³ or more. is there. The film thickness of the contact layer 6 can be set to 5 nm to 100 nm, for example.

Note that the contact layer 6 may be composed of two layers, a low-concentration electric field relaxation layer (n ⁻ layer) as a lower layer and a high-concentration contact layer (n ⁺ layer) as an upper layer. The low concentration electric field relaxation layer is doped with phosphorus (P) of about 1 × 10 ¹⁷ atm / cm ³ . The two layers can be formed continuously in a CVD apparatus. Alternatively, the contact layer 6 includes three layers of a low-concentration electric field relaxation layer (n ⁻ layer), a high-concentration contact layer (n ⁺ layer), and an i-layer that is an amorphous silicon layer that is not doped with impurities. Can also be configured.

  The source electrode 7S is formed above the first insulating layer region 5a and the third insulating layer region 5c with one contact layer 6 interposed therebetween. The drain electrode 7D is formed above the second insulating layer region 5b and the third insulating layer region 5c with the other contact layer 6 interposed therebetween. The source electrode 7S and the drain electrode 7D are arranged to face each other with a space therebetween.

  The source electrode 7S and the drain electrode 7D can have a single layer structure or a multilayer structure such as a conductive material and an alloy thereof, for example, aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu). , Titanium (Ti) and chromium (Cr). The film thickness of the source electrode 7S and the drain electrode 7D can be, for example, about 100 nm to 500 nm.

  FIG. 3B is a plan view showing a positional relationship among the gate electrode 2, the insulating layer 5, the source electrode 7S, and the drain electrode 7D. As shown in FIG. 3B, the size of the source electrode 7S in the channel width direction (the direction perpendicular to the channel length direction and the vertical direction in FIG. 3B) and the size of the drain electrode 7D in the channel width direction are respectively The third insulating layer region 5c is configured to be larger than the size in the channel width direction. That is, the source electrode 7S and the drain electrode 7D each protrude 4 μm or more from both ends in the channel width direction of the third insulating layer region 5c. As will be described later, the length C (hereinafter referred to as “dimension C”) from which the source electrode 7S and the drain electrode 7D protrude from both end portions in the channel width direction of the third insulating layer region 5c is 2 μm or more. Preferably, it is 4 μm or more. In FIG. 3B, the entire region of the semiconductor layer 4 is completely covered by the third insulating layer region 5c, the source electrode 7S, and the drain electrode 7D.

  Next, a method for manufacturing the thin film semiconductor device 100 according to the present embodiment will be described with reference to FIGS. 4A to 4I. 4A to 4I are cross-sectional views showing each step in the method of manufacturing the thin film semiconductor device according to Embodiment 1 of the present invention.

  First, as shown to FIG. 4A, a glass substrate is prepared as the board | substrate 1 (1st process). In addition, before forming the gate electrode 2 in the second step to be described later, an undercoat layer composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the substrate 1 by plasma CVD or the like. Good.

Thereafter, as shown in FIG. 4B, a gate electrode 2 is formed on the substrate 1 (second step). In this second step, for example, after a gate metal film made of molybdenum tungsten (MoW) is formed on the substrate 1 by sputtering, the gate metal film is patterned using a photolithography method and a wet etching method. Thus, the gate electrode 2 having a predetermined shape can be formed. The wet etching of molybdenum tungsten (MoW) can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed in a predetermined composition.

Thereafter, as shown in FIG. 4C, a gate insulating film 3 is formed so as to cover the gate electrode 2 and the substrate 1 (third step). In the third step, for example, the gate insulating film 3 made of silicon oxide (SiO) is formed by plasma CVD or the like. For example, silicon oxide can be formed by introducing silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) at a predetermined concentration ratio. When the gate insulating film 3 is formed in the third step, due to the film thickness of the gate electrode 2, the stepped portion 10 is formed in the portion of the gate insulating film 3 corresponding to both ends of the gate electrode 2. .

  Thereafter, as shown in FIG. 4D, a semiconductor layer 4 having a channel region is formed on the gate insulating film 3 (fourth step). In this fourth step, for example, an amorphous silicon thin film made of amorphous silicon (amorphous silicon) is formed by plasma CVD or the like, and then a dehydrogenation annealing process is performed. By annealing and crystallizing, the semiconductor layer 4 composed of a polycrystalline silicon thin film can be formed. In the present embodiment, in the fourth step, the band gap is adjusted by polycrystallizing the amorphous silicon thin film, and the band gap energy Eg of the semiconductor layer 4 is adjusted to 1.6 eV or less (eg, 1.1 eV). To do.

  Note that although the amorphous silicon thin film is crystallized by laser annealing using an excimer laser in this embodiment mode, the present invention is not limited to this. For example, as a crystallization method, a laser annealing method using a pulse laser with a wavelength of about 370 nm to 900 nm, a laser annealing method using a continuous wave laser with a wavelength of about 370 nm to 900 nm, or an annealing method by rapid thermal processing (RTP) is used. You can also. In addition, the semiconductor layer 4 composed of a polycrystalline silicon thin film can be formed by using a method such as direct growth by CVD instead of crystallizing the amorphous silicon thin film.

Thereafter, a hydrogen plasma process is performed on the semiconductor layer 4 to perform a hydrogenation process on silicon atoms contained in the semiconductor layer 4. In the hydrogen plasma treatment, for example, hydrogen plasma is generated by radio frequency (RF) power using a gas containing hydrogen gas such as H ₂ , H ₂ / argon (Ar) as a raw material, and the semiconductor layer 4 is irradiated with the hydrogen plasma. Is done. By this hydrogen plasma treatment, dangling bonds (defects) of silicon atoms are terminated with hydrogen, the crystal defect density of the semiconductor layer 4 is reduced, and crystallinity is improved.

  Thereafter, as shown in FIG. 4E, an insulating layer 5 is formed on the semiconductor layer 4 (fifth step). Next, as shown in FIG. 4F, a first contact opening 8 and a second contact opening 9 are formed in a predetermined portion of the insulating layer 5 (sixth step). In the fifth and sixth steps, first, a predetermined organic material for forming the insulating layer 5 is applied on the semiconductor layer 4 by a predetermined coating method, and then spin coating or slit coating is performed. An insulating film forming film is formed on the entire surface of the semiconductor layer 4. The film thickness of the organic material can be controlled by the viscosity of the organic material and the coating conditions (for example, the rotation speed and the blade speed). Note that as a material for the insulating film formation film, a photosensitive coating type organic material containing silicon, oxygen, and carbon can be used. Thereafter, the insulating film forming film is pre-baked at a temperature of about 110 ° C. for about 60 seconds to pre-fire the insulating film forming film. As a result, the solvent contained in the insulating film forming film is vaporized. Thereafter, the insulating film forming film is patterned by performing exposure and development using a photomask, and the insulating layer 5 having a predetermined shape (that is, the first insulating layer region 5a, the second insulating layer region 5b, and the third insulating layer). Layer region 5c) is formed. Thereafter, post-baking is performed on the patterned insulating layer 5 at a temperature of 280 ° C. to 300 ° C. for about 1 hour, so that the insulating layer 5 is finally baked and solidified. Thereby, a part of the organic component in the insulating layer 5 is vaporized and decomposed, and the insulating layer 5 with improved film quality can be formed.

  Thereafter, as shown in FIG. 4G, a contact layer 6 is formed on the semiconductor layer 4 so as to cover the insulating layer 5. In this step, the contact layer 6 made of amorphous silicon doped with an impurity of a pentavalent element such as phosphorus (P) is formed by plasma CVD, for example.

  Thereafter, as shown in FIG. 4H and FIG. 4I, the source electrode 7S and the drain electrode 7D are patterned on the contact layer 6 (seventh step). In the seventh step, first, as shown in FIG. 4H, the source / drain metal film 7 made of the material of the source electrode 7S and the drain electrode 7D is formed by sputtering, for example. Thereafter, in order to form the source electrode 7S and the drain electrode 7D having a predetermined shape, a resist material is applied on the source / drain metal film 7, and exposure and development are performed to form a resist patterned in a predetermined shape. Next, by performing wet etching using this resist as a mask and patterning the source / drain metal film 7, a source electrode 7S and a drain electrode 7D having a predetermined shape are formed as shown in FIG. 4I. At this time, the contact layer 6 functions as an etching stopper layer. Thereafter, the resist on the source electrode 7S and the drain electrode 7D is removed. In this seventh step, the source electrode 7S is electrically connected to the channel region of the semiconductor layer 4 through the first contact opening 8 and the one contact layer 6, and the drain electrode 7D is connected to the second contact opening. It is electrically connected to the channel region of the semiconductor layer 4 through the part 9 and the other contact layer 6.

  Thereafter, dry etching is performed using the source electrode 7S and the drain electrode 7D as a mask, thereby patterning the contact layer 6 and patterning the semiconductor layer 4 in an island shape. Thereby, a pair of contact layers 6 and island-shaped semiconductor layers 4 having a predetermined shape can be formed. As dry etching conditions, a chlorine-based gas can be used. The contact layer 6 and the semiconductor layer 4 can also be patterned by dry etching using a resist mask after the source electrode 7S and the drain electrode 7D are wet-etched.

  As described above, the thin film semiconductor device 100 according to the first embodiment of the present invention can be manufactured.

  Next, functions and effects of the thin film semiconductor device 100 according to the present embodiment will be described. As described above, the first insulating layer region 5 a corresponds to one end portion of the gate electrode 2, that is, covers the portion of the semiconductor layer 4 corresponding to one stepped portion 10 of the gate insulating film 3 from above. Are arranged. The second insulating layer region 5b is disposed so as to correspond to the other end portion of the gate electrode 2, that is, to cover the portion of the semiconductor layer 4 corresponding to the other stepped portion 10 of the gate insulating film 3 from above. Has been. With this configuration, the leakage current path due to the tunnel current is blocked by the first insulating layer region 5a and the second insulating layer region 5b, so that the electric field concentration portion of the semiconductor layer 4, that is, the step portion of the gate insulating film 3 The portion of the semiconductor layer 4 corresponding to 10 does not contribute to leakage current conduction. Thereby, it can suppress that the generated tunnel current contributes as a leak current. Similarly, the heat generation current can be suppressed from contributing as a leak current.

  FIG. 5A is a diagram showing the results of simulating the electrical characteristics of the thin film semiconductor device of the present invention and the conventional thin film semiconductor device. FIG. 5B is a diagram showing the results of testing the electrical characteristics of the thin film semiconductor device of the present invention and the conventional thin film semiconductor device using actual devices, respectively. 5A and 5B, the horizontal axis represents the magnitude of the voltage between the gate and the source, and the vertical axis represents the magnitude of the drain current. 5A and 5B, the solid line graph shows the result of simulation or test using the configuration of the thin film semiconductor device 100 of the present embodiment, and the alternate long and short dash line graph shows the conventional thin film semiconductor shown in FIG. A simulation or test result using the configuration of the apparatus 500 is shown.

  As is apparent from the results shown in FIGS. 5A and 5B, in the thin film semiconductor device 100 of the present embodiment, the current value during the off operation (that is, the gate-source voltage is negative) is the same as that of the conventional thin film. Compared to semiconductor devices. From this, it can be said that the thin film semiconductor device 100 of the present embodiment has an effect of suppressing the generated tunnel current from contributing as a leakage current during the off operation.

  FIG. 6 is a diagram showing a result of simulating the current density distribution during the off operation in the thin film semiconductor device 100 according to the present embodiment. In this simulation, the thin film semiconductor device 100 having the structure shown in FIG. 1 is used, molybdenum tungsten (MoW) having a thickness of 50 nm as the gate electrode 2, silicon oxide (SiO) having a thickness of 120 nm as the gate insulating film 3, and a semiconductor layer. 4 is polycrystalline silicon with a film thickness of 50 nm, silicon oxide (SiO) with a film thickness of 500 nm as the insulating layer 5, amorphous silicon with a film thickness of 40 nm as the contact layer 6, and aluminum with a film thickness of 600 nm as the source electrode 7S and the drain electrode 7D. (Al) was used. Further, −20 V was applied as the gate-source voltage, and 5.1 V was applied as the drain-source voltage. In FIG. 6, the density distribution of the leak current generated during the off operation is represented by contour lines.

  As shown by the contour lines in FIG. 6, the distribution of leakage current flowing through the semiconductor layer 4 is significantly reduced as compared with the simulation result shown in FIG. Therefore, in the thin film semiconductor device 100 of the present embodiment, there is an effect that the leakage current path indicated by the broken arrow in FIG. 6 is blocked by the first insulating layer region 5a and the second insulating layer region 5b. It can be said.

  In the present embodiment, the band gap energy of the semiconductor layer 4 is configured to be 1.6 eV or less. FIG. 7A is a diagram illustrating a result of simulating a change in drain current with respect to band gap energy of a semiconductor layer. In FIG. 7A, square plots show simulation results using the thin film semiconductor device 100 of the present embodiment, and diamond plots show simulation results using the conventional thin film semiconductor device 500 shown in FIG. . In this simulation, when the band gap energy of the semiconductor layers 4 and 54 is changed from 1.0 eV to 1.7 eV with -10 V applied as the gate-source voltage and 5.1 V applied as the drain-source voltage. The magnitude of the drain current was obtained. As is apparent from the results shown in FIG. 7A, in the region where the band gap energy is 1.6 eV or less, the drain current during the off operation in the thin film semiconductor device 100 of the present embodiment is the off current in the conventional thin film semiconductor device 500. It becomes smaller than the drain current during operation. Therefore, in this embodiment, the off characteristics can be effectively improved by setting the band gap energy of the semiconductor layer 4 to 1.6 eV or less.

  FIG. 7B is a diagram showing the result of simulating the change of the drain current with respect to the gate-source voltage. In FIG. 7B, the solid line graph shows the simulation result using the thin film semiconductor device 100 of the present embodiment, and the alternate long and short dash line graph shows the simulation result using the conventional thin film semiconductor device 500 shown in FIG. Yes. In this simulation, the electric power when the band gap energy (Eg) of the semiconductor layers 4 and 54 is changed to 1.0 eV, 1.4 eV, and 1.7 eV with 5.1 V applied as the drain-source voltage. Characteristics (ie, change in drain current with respect to gate-source voltage) were obtained. As is apparent from the results shown in FIG. 7B, when the band gap energy is 1.4 eV and 1.6 eV, the drain current during the off operation in the thin film semiconductor device 100 of the present embodiment is the conventional thin film semiconductor device. This is much smaller than the drain current during the off operation at 500. Therefore, in this embodiment, the off characteristics can be effectively improved by setting the band gap energy of the semiconductor layer 4 to 1.6 eV or less.

  Next, the relationship between the above-described dimension C and parasitic resistance will be described. Here, the parasitic resistance means a resistance between the channel region of the semiconductor layer 4 and the source electrode 7S and the drain electrode 7D. 8A and 8B are plan views for explaining the definition of the dimension A, the dimension B, and the dimension C. FIG. The dimensions A and B will be described later. As shown in FIG. 8B, the sign of the dimension C in a state where the source electrode 7S and the drain electrode 7D protrude from the third insulating layer region 5c in the channel width direction is defined as positive, and as shown in FIG. The sign of the dimension C in a state where the drain electrode 7D bites into the third insulating layer region 5c in the channel width direction is defined as negative. Further, a width that becomes a bottleneck of the width of the current path is defined as a dimension W corresponding to the channel width. That is, as shown in FIG. 8B, when the sign of the dimension C is positive, the size of the third insulating layer region 5c in the channel width direction is defined as the dimension W, and as shown in FIG. 8A, the dimension C Is negative, the size of the source electrode 7S and the drain electrode 7D in the channel width direction is defined as a dimension W.

  FIG. 9A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension C when the dimension W is 5 μm, the dimension A is 2 μm, and the dimension B is 3 μm. FIG. 9B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension C when the dimension W is 50 μm, the dimension A is 2 μm, and the dimension B is 3 μm. FIG. 9C is a diagram more clearly showing the change in parasitic resistance by reducing the scale of the vertical axis in FIG. 9B. 9A, 9B, and 9C, the horizontal axis represents the size C, and the vertical axis represents the parasitic resistance (Rsd). As is clear from the results shown in FIGS. 9A, 9B, and 9C, when the sign of the dimension C is negative, the parasitic resistance is larger in the planar structure having the dimension W of 50 μm than in the planar structure having the dimension W of 5 μm. The size of is getting smaller. That is, it can be seen that there is a parasitic resistance inversely proportional to the contact area S (approximately proportional to the dimension W) where the source electrode 7S and drain electrode 7D are in contact with the semiconductor layer 4. On the other hand, when the sign of the dimension C is positive, the magnitude of the parasitic resistance converges to approximately the same value when the dimension W is 5 μm and when the dimension W is 50 μm. That is, in this case, it can be seen that there is a constant parasitic resistance that does not depend on the size of the contact area S. In addition, the parasitic resistance can be kept low in the region where the dimension C is 2 μm or more regardless of the size W, and the parasitic resistance can be more effectively suppressed in the region where the dimension C is 4 μm or more. You can see that

  Next, the relationship between the dimension A and the parasitic resistance will be described. As shown in FIGS. 8A and 8B, the dimension A means the overlapping width in the channel length direction (left and right direction in FIGS. 8A and 8B) between the third insulating layer region 5c, the source electrode 7S, and the drain electrode 7D. . FIG. 10A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension A when the dimension W is 5 μm, the dimension B is 3 μm, and the dimension C is 3 μm. FIG. 10B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension A when the dimension W is 50 μm, the dimension B is 3 μm, and the dimension C is 3 μm. 10A and 10B, the horizontal axis represents the size of the dimension A, and the vertical axis represents the size of the parasitic resistance (Rsd). As is clear from the results shown in FIGS. 10A and 10B, the magnitude of the parasitic resistance hardly changes even when the dimension A is increased. Therefore, it can be said that the size of the dimension A hardly affects the change of the parasitic resistance. Regardless of the size of the dimension A, the parasitic resistance converges to substantially the same value when the dimension W is 5 μm and when the dimension W is 50 μm. From this, it can be seen that the size of the dimension W hardly affects the change of the parasitic resistance.

  Next, the relationship between the dimension B and the parasitic resistance will be described. As shown in FIGS. 8A and 8B, the dimension B is a gate in an outer portion than the third insulating layer region 5c and in an inner portion than the first insulating layer region 5a and the second insulating layer region 5b. It means the overlapping width in the channel length direction between the electrode 2 and the source electrode 7S and drain electrode 7D. FIG. 11A is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension B when the dimension W is 5 μm, the dimension A is 2 μm, and the dimension C is 3 μm. FIG. 11B is a diagram illustrating an experimental result of evaluating a change in parasitic resistance with respect to the dimension B when the dimension W is 50 μm, the dimension A is 2 μm, and the dimension C is 3 μm. 11A and 11B, the horizontal axis represents the size of dimension B, and the vertical axis represents the size of parasitic resistance (Rsd). As is apparent from the results shown in FIGS. 11A and 11B, when the dimension B is increased, the contact area S increases at the same time, and thus the parasitic resistance tends to decrease. Will only decline slightly. Therefore, in this case, it can be said that the size of the dimension B hardly affects the change of the parasitic resistance. Regardless of the size of the dimension B, the parasitic resistance converges to almost the same value when the dimension W is 5 μm and when the dimension W is 50 μm. From this, it can be said that the size of the dimension W hardly affects the change of the parasitic resistance.

  The summary of the above experimental results is as follows. The parasitic resistance has a clear dependency on the dimension C that changes the magnitude relationship in the channel width direction between the source electrode 7S and drain electrode 7D and the third insulating layer region 5c. In addition, it means that the planar structure changes from the structure shown in FIG. 8A to the structure shown in FIG. 8B as the sign of the dimension C changes from negative to positive. When the sign of the dimension C is positive, the change in the parasitic resistance with respect to the dimension W, the dimension A, and the dimension B that change the contact area S is small. On the other hand, when the sign of the dimension C is negative, the parasitic resistance has a dependence inversely proportional to the contact area S (approximately proportional to the dimension W). Regarding the dependency of the parasitic resistance on the dimension W, the dimension A, the dimension B, and the dimension C, not only the magnitude of the parasitic resistance changes depending on the size of the contact area S, but also the source as shown in FIGS. 8A and 8B. The magnitude of the parasitic resistance varies depending on whether or not the electrode 7S and the drain electrode 7D cover the four corners of the third insulating layer region 5c having a quadrangular planar structure.

  From the above consideration, a model of the parasitic resistance Rsd shown in FIG. 11C is derived. That is, the parasitic resistance component R1 that is inversely proportional to the contact area S (approximately proportional to W) and the parasitic resistance component R2 having a constant value caused by the corner of the third insulating layer region 5c exist in parallel. A resistor Rsd is configured. As shown in FIG. 8A, in the planar structure in which the sign of the dimension C is negative, the source electrode 7S and the drain electrode 7D do not cover the four corners of the third insulating layer region 5c configured by a rectangular planar structure. Therefore, the parasitic resistance Rsd is composed of only the parasitic resistance component R1 that is inversely proportional to the contact area S (approximately proportional to W). On the other hand, in the planar structure in which the sign of the dimension C is positive as shown in FIG. 8B, the corner portion of the third insulating layer region 5c is covered with the source electrode 7S and the drain electrode 7D, so that the parasitic resistance Rsd is It consists of a parasitic resistance component R1 and a parasitic resistance component R2. Here, since the parasitic resistance component R2 is smaller than the parasitic resistance component R1, the parasitic resistance Rsd is controlled by the parasitic resistance component R2 caused by the corner of the third insulating layer region 5c. For this reason, even if the dimension W, the dimension A, the dimension B, and the dimension C change, the parasitic resistance Rsd hardly changes.

  From the above, it can be seen that in order to reduce the parasitic resistance Rsd, a planar structure in which the sign of the dimension C is positive and the parasitic resistance Rsd can be controlled by the parasitic resistance component R2 is desirable. For this reason, in the region where the dimension C is 2 μm or more, the parasitic resistance can be suppressed low, and in the region where the dimension C is 4 μm or more, the parasitic resistance can be suppressed more effectively.

(Embodiment 2)
FIG. 12A is a plan view showing the positional relationship between the gate electrode and the insulating layer in the thin film semiconductor device according to Embodiment 2 of the present invention. FIG. 12B is a plan view showing an arrangement relationship of the gate electrode, the insulating layer, the source electrode, and the drain electrode in the thin film semiconductor device according to Embodiment 2 of the present invention.

  As shown in FIGS. 12A and 12B, in the thin film semiconductor device 200 of the present embodiment, the insulating layer 5 'is integrally formed. That is, the first insulating layer region 5a ', the second insulating layer region 5b', and the third insulating layer region 5c 'are connected to each other at both ends in the channel width direction. The first insulating layer region 5a 'is disposed above one end portion of the gate electrode 2 and outside the first contact opening 8' in the channel length direction. The second insulating layer region 5b 'is disposed above the other end of the gate electrode 2 and outside the second contact opening 9' in the channel length direction. The third insulating layer region 5c 'is disposed above the central portion of the gate electrode 2 and between the first contact opening 8' and the second contact opening 9 '.

  Even if it is the structure like this Embodiment, the effect similar to Embodiment 1 can be acquired.

  As mentioned above, although Embodiment 1 and 2 of this invention were demonstrated, the structure shown in the said Embodiment 1 and 2 is an example, Comprising: Various deformation | transformation can be added in the range which does not deviate from the meaning of invention. Needless to say.

  The thin film semiconductor device according to the present invention can be widely used in various electric apparatuses having a display device such as a television set, a personal computer, a mobile phone, or other thin film semiconductor devices.

1, 51 Substrate 2, 52 Gate electrode 3, 53 Gate insulating film 4, 54 Semiconductor layer 5, 5 'Insulating layer 5a, 5a' First insulating layer region 5b, 5b 'Second insulating layer region 5c, 5c' Third Insulating layer region 6, 56 Contact layer 7S, 57S Source electrode 7D, 57D Drain electrode 8, 8 'First contact opening 9, 9' Second contact opening 10, 58 Step part 11, 59 Flat part 55 Channel protective layer 100, 200, 500 Thin film semiconductor device

Claims (6)

A substrate,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode and on the substrate outside both ends thereof;
A semiconductor layer formed on the gate insulating film and having a channel region;
An insulating layer formed on the semiconductor layer and having a first contact opening and a second contact opening spaced apart from each other;
A source electrode formed above the insulating layer;
A drain electrode formed above the insulating layer and formed to face the source electrode,
The band gap energy of the semiconductor layer is 1.6 eV or less,
The insulating layer has a first insulating layer region disposed outside the first contact opening, and a second insulating layer region disposed outside the second contact opening,
The first insulating layer region is disposed above one end portion of the gate electrode, and the second insulating layer region is disposed above the other end portion of the gate electrode.
The thin film semiconductor device, wherein the source electrode is electrically connected to the channel region through the first contact opening, and the drain electrode is electrically connected to the channel region through the second contact opening. The insulating layer further includes a third insulating layer region disposed between the first contact opening and the second contact opening,
The thin film semiconductor device according to claim 1, wherein the third insulating layer region is disposed above a central portion of the gate electrode and functions as a channel etching stopper layer that covers the channel region. 3. The thin film semiconductor device according to claim 1, wherein sizes of the source electrode and the drain electrode in a channel width direction are larger than sizes of the third insulating layer region in a channel width direction. 4. The thin film semiconductor device according to claim 3, wherein the source electrode and the drain electrode protrude 2 μm or more from both ends of the third insulating layer region in the channel width direction. 5. The thin film semiconductor device according to claim 4, wherein the source electrode and the drain electrode each protrude 4 μm or more from both ends in the channel width direction of the third insulating layer region. A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating film over the gate electrode and the substrate outside both ends thereof;
A fourth step of forming a semiconductor layer having a channel region on the gate insulating film;
A fifth step of forming an insulating layer on the semiconductor layer;
A sixth step of forming a first contact opening and a second contact opening spaced from each other in the insulating layer;
A seventh step of forming a source electrode and a drain electrode facing the source electrode above the insulating layer,
In the fourth step, the semiconductor layer having a band gap energy of 1.6 eV or less is formed,
In the sixth step, by forming the first contact opening and the second contact opening in the insulating layer, the outer side of the first contact opening is above one end of the gate electrode. Forming a first insulating layer region to be disposed, and forming a second insulating layer region disposed above the other end of the gate electrode outside the second contact opening;
In the seventh step, the source electrode is electrically connected to the channel region through the first contact opening, and the drain electrode is electrically connected to the channel region through the second contact opening. A method for manufacturing a semiconductor device.

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