JPWO2012172617A1 - THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR - Google Patents

Abstract

A thin film transistor (10) according to the present invention is formed on a substrate (1), a gate electrode (2) formed on the substrate, a gate insulating film (3) formed on the gate electrode, and the gate insulating film. An organic protection made of an organic material formed on the amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer (5) formed on the crystalline silicon semiconductor layer, an amorphous silicon semiconductor layer (5) formed on the crystalline silicon semiconductor layer A film (6), and a source electrode (8S) and a drain electrode (8D) formed by sandwiching an organic protective film on the amorphous silicon semiconductor layer, and the amorphous silicon semiconductor layer (5) The charge density of the negative carriers contained is 3-1011 cm-2 or more.

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor, and more particularly to a channel protective thin film transistor and a method for manufacturing the same.

  In recent years, an organic EL display using an organic material EL (Electro Luminescence) as one of the next generation flat panel displays replacing a liquid crystal display has attracted attention. In an active matrix display device such as an organic EL display, a thin film semiconductor device called a thin film transistor (TFT) is used.

  In particular, an organic EL display is a current-driven display device unlike a voltage-driven liquid crystal display, and development of a thin film transistor having excellent on / off characteristics as a drive circuit of an active matrix display device has been urgently developed. A thin film transistor has a structure in which a gate electrode, a semiconductor layer (channel layer), a source electrode, and a drain electrode are formed on a substrate, and a silicon thin film is generally used for the channel layer.

  In addition, display devices are required to have a large screen and a low cost, and as a thin film transistor that can be easily reduced in cost, generally a bottom gate type in which a gate electrode is formed on the substrate side from a channel layer. The thin film transistor is used.

  Bottom-gate thin film transistors are roughly classified into two types: a channel etching type thin film transistor in which a channel layer is etched, and a channel protection type (etching stopper type) thin film transistor that protects the channel layer from an etching process.

  A channel etching type thin film transistor has an advantage that the number of photolithography steps can be reduced and a manufacturing cost can be reduced as compared with a channel protection type thin film transistor.

  On the other hand, the channel protective thin film transistor can prevent damage to the channel layer due to etching treatment, and can suppress increase in variation in characteristics in the substrate plane. In addition, a channel protection type thin film transistor is advantageous for high definition because a channel layer can be thinned and a parasitic resistance component can be reduced to improve on-state characteristics.

  Therefore, the channel protection type thin film transistor is suitable for a driving transistor in a current driving type organic EL display device using an organic EL element, for example. Even if the manufacturing cost is increased as compared with the channel etching type thin film transistor, Attempts have been made to employ it in pixel circuits of EL display devices.

  For example, Patent Document 1 discloses a channel protection type TFT using a microcrystalline semiconductor film as a channel layer, and describes forming a channel protection layer on the channel layer through a buffer layer.

JP 2009-76894 A

  However, it has been found that in a channel protection type thin film transistor, when a channel protection layer is formed by applying an organic material, an S value (subthreshold swing value) indicating characteristics of the thin film transistor is deteriorated.

  In particular, it was found that the fluctuation of the rising region of the S value was large. The rising region of the S value corresponds to a low gradation region in the display device, that is, a region that emits black light, and the characteristic of the region that emits black light is important in an organic EL display unlike a liquid crystal display.

  Thus, a thin film transistor having a channel protective layer formed by applying an organic material has a problem that the S value is bad.

  The present invention has been made to solve the above problems, and provides a thin film transistor having an excellent S value and a method for manufacturing the thin film transistor in a channel protective thin film transistor using an organic protective film as a channel protective layer. Objective.

In order to achieve the above object, one embodiment of a thin film transistor according to the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and the gate insulating film. A crystalline silicon semiconductor layer formed on the amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer formed on the crystalline silicon semiconductor layer, and an organic protective film made of an organic material formed on the amorphous silicon semiconductor layer. A source electrode and a drain electrode formed on the amorphous silicon semiconductor layer with the organic protective film interposed therebetween, and a charge density of negative carriers contained in the amorphous silicon semiconductor layer is 3 × 10 ¹¹ cm ⁻² or more.

  According to the present invention, it is possible to realize a thin film transistor having excellent transistor characteristics, particularly an excellent S value.

FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the relationship between the interface electric field between the amorphous silicon semiconductor layer and the crystalline silicon semiconductor layer, and the film thickness and density of states in the amorphous silicon semiconductor layer in the thin film transistor according to this embodiment. . FIG. 3A is a cross-sectional view illustrating the configuration and operation of a thin film transistor according to a comparative example. FIG. 3B is a diagram illustrating current-voltage characteristics of a thin film transistor according to a comparative example. FIG. 4A is a cross-sectional view showing the configuration and operation of the thin film transistor according to the embodiment of the present invention. FIG. 4B is a diagram showing current-voltage characteristics of the thin film transistor according to the embodiment of the present invention. FIG. 5A is a diagram showing current-voltage characteristics of the thin film transistor according to the comparative example shown in FIG. 3A. FIG. 5B is a diagram showing current-voltage characteristics of the thin film transistor (film thickness of the amorphous silicon semiconductor layer = 10 nm) according to the present invention shown in FIG. FIG. 5C is a diagram showing current-voltage characteristics of the thin film transistor (film thickness of the amorphous silicon semiconductor layer = 20 nm) according to the present invention shown in FIG. FIG. 6 is a diagram showing the relationship between the amorphous silicon semiconductor layer 5 and the S value in the thin film transistor according to the embodiment of the present invention. FIG. 7 is a diagram showing the relationship between the film thickness of the organic protective film and the minimum off-leakage current in the thin film transistor according to this embodiment. FIG. 8A is a cross-sectional view schematically showing a substrate preparation step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8B is a cross-sectional view schematically showing a gate electrode forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8C is a cross-sectional view schematically showing a gate insulating film forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8D is a cross-sectional view schematically showing a crystalline silicon semiconductor layer forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8E is a cross-sectional view schematically showing an amorphous silicon semiconductor layer forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8F is a cross-sectional view schematically showing an organic protective film forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 8G is a cross-sectional view schematically showing a contact layer forming step and a source / drain electrode forming step in the method of manufacturing a thin film transistor according to the embodiment of the present invention. FIG. 9 is a diagram showing the relationship between the growth temperature and the spin density when forming the amorphous silicon semiconductor layer 5 in the method of manufacturing a thin film transistor in the embodiment of the present invention.

One embodiment of a thin film transistor according to the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, and a crystalline silicon semiconductor formed on the gate insulating film A layer, an amorphous silicon semiconductor layer formed on the crystalline silicon semiconductor layer, an organic protective film made of an organic material formed on the amorphous silicon semiconductor layer, and the amorphous silicon semiconductor layer A source electrode and a drain electrode formed on both sides of the organic protective film, and the charge density of negative carriers contained in the amorphous silicon semiconductor layer is 3 × 10 ¹¹ cm ⁻² or more. .

  As a result, the positive fixed charge of the organic protective film is offset by the fixed charge of the negative carrier trapped in the trap level (such as a trap due to crystal defects or a structural trap) of the amorphous silicon semiconductor layer, thereby shielding the electric field. It is possible to suppress the formation of the back channel at the time of ON, and the S value can be improved.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, it is preferable that a thickness of the organic protective film in a region overlapping with the source electrode or the drain electrode is 300 nm or more and 1 μm or less. In one embodiment of the thin film transistor according to the present invention, it is preferable that a thickness of the organic protective film in a region overlapping with the source electrode or the drain electrode is 500 nm or more and 1 μm or less.

Accordingly, positive fixed charges generated in the organic protective film can be offset by the amorphous silicon semiconductor layer in which the charge density of the negative carriers is 3 × 10 ¹¹ cm ⁻² or more.

  Furthermore, in one embodiment of the thin film transistor according to the present invention, the polarity of the fixed charge contained in the organic protective film and the total charge of the charge at the interface between the organic protective film and the amorphous silicon semiconductor layer is positive. Also good.

Furthermore, in one embodiment of the thin film transistor according to the present invention, the thickness of the amorphous silicon semiconductor layer is 10 nm to 60 nm, and the charge density of the amorphous silicon semiconductor layer is measured by a TVS measurement method It is preferable that it is 1 × 10 ¹⁷ cm ⁻³ or more and 7 × 10 ¹⁷ cm ⁻³ or less. Further, in one embodiment of the thin film transistor according to the present invention, the amorphous silicon semiconductor layer has a thickness of 20 nm to 40 nm, and the amorphous silicon semiconductor layer has a charge density of 1 × 10 ¹⁷ cm ^−3. It is preferable that it is 5 * 10 < ¹⁷ > cm < ^-3 > or less.

Thereby, an amorphous silicon semiconductor layer in which the charge density of negative carriers is 3 × 10 ¹¹ cm ⁻² or more can be formed.

According to another aspect of the method for manufacturing a thin film transistor according to the present invention, a first step of preparing a substrate, a second step of forming a gate electrode on the substrate, and a gate insulating film on the gate electrode are formed. 3 steps, a fourth step of forming a crystalline silicon semiconductor layer on the gate insulating film, a fifth step of forming an amorphous silicon semiconductor layer on the crystalline silicon semiconductor layer, and the amorphous silicon A sixth step of forming an organic protective film by applying an organic material on the semiconductor layer; a seventh step of forming a source electrode and a drain electrode with the organic protective film sandwiched on the amorphous silicon semiconductor layer; The charge density of the negative carriers contained in the amorphous silicon semiconductor layer is 3 × 10 ¹¹ cm ⁻² or more.

  Thus, a thin film transistor capable of improving the S value by offsetting the positive fixed charge of the organic protective film by the negative carriers of the amorphous silicon semiconductor layer can be manufactured.

Furthermore, in one aspect of the method for manufacturing a thin film transistor according to the present invention, in the fifth step, the amorphous silicon semiconductor layer is subjected to a film formation condition in which a plasma density is 0.1 W / cm ² to 1 W / cm ^2. In addition, it is preferable to form a source gas containing any one of silane gas, disilane gas and trisilane gas and an inert gas containing any of argon, hydrogen and helium. Furthermore, in one mode of the method for manufacturing a thin film transistor according to the present invention, in the fifth step, the amorphous silicon semiconductor layer may be formed under a film forming condition in which a growth temperature is 300 ° C. to 400 ° C. preferable.

Accordingly, an amorphous silicon semiconductor layer having a desired trap density can be formed, and an amorphous silicon semiconductor layer having a negative carrier charge density of 3 × 10 ¹¹ cm ⁻² or more can be formed.

(Embodiment)
Hereinafter, a thin film transistor and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  First, the structure of the thin film transistor 10 according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to an embodiment of the present invention.

  As shown in FIG. 1, a thin film transistor 10 according to an embodiment of the present invention is a channel protection type bottom gate type thin film transistor, and includes a substrate 1, a gate electrode 2 formed on the substrate 1, and a gate electrode. 2, a gate insulating film 3 formed on the gate insulating film 3, a crystalline silicon semiconductor layer 4 formed on the gate insulating film 3, an amorphous silicon semiconductor layer 5 formed on the crystalline silicon semiconductor layer 4, and a non- An organic protective film 6 made of an organic material formed on the crystalline silicon semiconductor layer 5 and a source electrode 8S and a drain electrode 8D formed on the amorphous silicon semiconductor layer 5 with the organic protective film 6 interposed therebetween. To do. Furthermore, the thin film transistor 10 in this embodiment includes a pair of contact layers 7 formed between the amorphous silicon semiconductor layer 5 and the source electrode 8S or the drain electrode 8D above the crystalline silicon semiconductor layer 4. .

  Hereinafter, each component of the thin film transistor 10 according to the present embodiment will be described in detail.

  The substrate 1 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass. In order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the crystalline silicon semiconductor layer 4, a silicon nitride film (SiNx), silicon oxide (SiOy) or silicon is formed on the substrate 1. An undercoat layer made of an oxynitride film (SiOyNx) or the like may be formed. In addition, the undercoat layer may play a role of mitigating the influence of heat on the substrate 1 in a high-temperature heat treatment process such as laser annealing. The film thickness of the undercoat layer is, for example, about 100 nm to 2000 nm.

  The gate electrode 2 is made of a single layer structure or a multilayer structure such as a conductive material or an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), A pattern is formed in a predetermined shape on the substrate 1 using chromium (Cr), molybdenum tungsten (MoW), or the like. The film thickness of the gate electrode 2 is, for example, about 20 to 500 nm.

  The gate insulating film 3 is made of, for example, silicon oxide (SiOy), silicon nitride (SiNx), silicon oxynitride film (SiOyNx), aluminum oxide (AlOz), tantalum oxide (TaOw), or a laminated film thereof. Is formed on the substrate 1 and the gate electrode 2 so as to cover the substrate 1 on which is formed.

  In this embodiment, since the crystalline silicon semiconductor layer 4 is used as the channel layer, it is preferable to use silicon oxide as the gate insulating film 3. In order to maintain a good threshold voltage characteristic in the TFT, it is preferable to make the interface state between the crystalline silicon semiconductor layer 4 and the gate insulating film 3 good, and silicon oxide is suitable for this. Because. The film thickness of the gate insulating film 3 is, for example, 50 nm to 300 nm.

  The crystalline silicon semiconductor layer 4 is a channel layer having a channel region in which carrier movement is controlled by the voltage of the gate electrode 2. In the present embodiment, the crystalline silicon semiconductor layer 4 can be formed by crystallizing amorphous silicon (amorphous silicon).

  The crystalline silicon semiconductor layer 4 can be composed of crystalline silicon made of microcrystalline silicon or polycrystalline silicon, or a mixed crystal structure of amorphous silicon and crystalline silicon. In this case, in order to obtain excellent on-characteristics, at least the channel region of the crystalline silicon semiconductor layer 4 is preferably composed of a film having a high proportion of crystalline silicon. The crystal grain size of crystalline silicon in the crystalline silicon semiconductor layer 4 is, for example, about 5 nm to 1000 nm. The film thickness of the crystalline silicon semiconductor layer 4 is, for example, about 10 nm to 90 nm.

The amorphous silicon semiconductor layer 5 is a charge suppression layer that suppresses positive fixed charges contained in the organic protective film 6. The amorphous silicon semiconductor layer 5 in the present embodiment is composed of an amorphous silicon film, and includes negative carriers having a charge density of 3 × 10 ¹¹ cm ⁻² or more. The film thickness of the amorphous silicon semiconductor layer 5 can be 10 nm to 60 nm.

The organic protective film 6 is a channel protective film that protects the channel layer, and is formed on the amorphous silicon semiconductor layer 5. In the present embodiment, the organic protective film 6 functions as a channel etching stopper (CES) layer for preventing the channel layer from being etched during the etching process when forming the pair of contact layers 7. . That is, the upper portion of the organic protective film 6 is etched by etching when the contact layer 7 is patterned (not shown). Here, the film thickness of the organic protective film 6 in the region overlapping with the source electrode 8S or the drain electrode 8D (portion not etched by channel etching) is, for example, 300 nm to 1 μm. Furthermore, this film thickness is preferably 500 nm or more and 1 μm or less. In the case of the organic protective film 6 having a film thickness in this range, positive fixed charges generated in the organic protective film 6 by the amorphous silicon semiconductor layer 5 in which the charge density of negative carriers is 3 × 10 ¹¹ cm ⁻² or more. Can be offset.

  The organic protective film 6 is made of an organic material, and is formed by applying polysiloxane in the present embodiment. Polysiloxane has a silica bond as a main chain, and is bonded with an organic component having carbon such as a methyl group. The organic protective film 6 can be formed by applying an organic material by spin coating or the like. In addition to a coating method such as a spin coating method, it can also be formed by a droplet discharge method or a printing method that can form a predetermined pattern such as screen printing or offset printing.

The pair of contact layers 7 are made of an amorphous semiconductor layer containing impurities at a high concentration or a polycrystalline semiconductor layer containing impurities at a high concentration, and are formed on the amorphous silicon semiconductor layer 5. The pair of contact layers 7 are disposed on the organic protective film 6 so as to face each other at a predetermined interval. In the present embodiment, the pair of contact layers 7 are, for example, n-type semiconductor layers in which amorphous silicon is doped with phosphorus (P) as an impurity, and a high-concentration impurity of 1 × 10 ¹⁹ [atm / cm ³ ] or more is used. The n ⁺ layer can be included. The thickness of each contact layer 7 can be set to, for example, 5 nm to 100 nm.

  The pair of source electrode 8S and drain electrode 8D are formed on the pair of contact layers 7 so as to be flush with the pair of contact layers 7 and are arranged to face each other with a predetermined interval. In this embodiment, the source electrode 8S and the drain electrode 8D can each have a single-layer structure or a multilayer structure made of a conductive material, an alloy, or the like. For example, aluminum (Al), molybdenum (Mo), tungsten ( W), copper (Cu), titanium (Ti), or chromium (Cr). The source electrode 8S and the drain electrode 8D can have, for example, a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 8S and the drain electrode 8D is, for example, about 100 nm to 500 nm. it can.

In the thin film transistor 10 according to the present embodiment configured as described above, as described above, the amorphous silicon semiconductor layer 5 is configured to include negative carriers having a charge density of 3 × 10 ¹¹ cm ⁻² or more. Has been. The charge density of negative carriers in the amorphous silicon semiconductor layer 5 will be described with reference to FIG. FIG. 2 shows an interface electric field between an amorphous silicon semiconductor layer and a crystalline silicon semiconductor layer, a film thickness and a state density (DOS: Density Of State) in the amorphous silicon semiconductor layer in the thin film transistor according to this embodiment. It is a figure which shows the relationship.

  The defect level density (trap density) on the vertical axis in FIG. 2 represents the density of states (DOS), and changes as the film quality of the amorphous silicon semiconductor layer 5 changes. The density of states (DOS) can be calculated by a defect level measurement method called a TVS (Transient Voltage Spectroscopy) method disclosed in Japanese Patent Application Laid-Open No. 8-247799. The TVS method is a measurement method that detects a temporal change in the holding ratio of a voltage between terminals of a capacitor element including a laminate of a metal, an insulating film, and a semiconductor, and calculates a state density in a forbidden band of the semiconductor from the detection signal. . By using this TVS method, the carriers trapped in the trap level existing in the forbidden band of the semiconductor can be obtained as a fixed charge density.

In the thin film transistor 10 according to the present embodiment, the density of states of the amorphous silicon semiconductor layer 5 is measured using the TVS method. Specifically, a predetermined voltage is applied to the gate electrode 2 and the source electrode 8S at different times to obtain a temporal change in the voltage between the gate electrode 2 and the source electrode 8S, and the state density is determined based on the temporal change. Can be calculated. Actually, the state density (DOS) of the 20-nm amorphous silicon semiconductor layer 5 formed in this embodiment is 4.68 × 10 ¹⁷ cm ⁻³ when measured using the TVS method. The amorphous silicon semiconductor layer 5 at this time uses SiH ₄ and H ₂ as source gases, a growth temperature of 320 ° C., a pressure of 2 Torr, a plasma density of 0.137 W / cm ² , SiH ₄ and H _The film was formed with a gas flow rate of ₂ at 10 sccm and 60 sccm, respectively.

Here, when the positive fixed charge density included in the organic protective film 6 is 5 × 10 ¹¹ cm ⁻² or more, a parasitic current due to the back channel is generated, and as shown by the broken line in FIG. By setting the charge density of the negative carriers contained in the amorphous silicon semiconductor layer 5 to 3 × 10 ¹¹ cm ⁻² or more, the positive charges can be canceled out.

That is, by forming the amorphous silicon semiconductor layer 5 having negative carriers having a charge density of 3 × 10 ¹¹ cm ⁻² or more with respect to positive fixed charges existing in the organic protective film 6, the amorphous The silicon semiconductor layer 5 can act as a charge suppression layer, and the formation of a back channel can be suppressed. Thereby, the S value which is one of the characteristics of the thin film transistor can be improved.

As shown in FIG. 2, the charge density of the amorphous silicon semiconductor layer 5 is determined by the product of the film thickness of the amorphous silicon semiconductor layer 5 and the density of states of charge (DOS). For example, in the case of the amorphous silicon semiconductor layer 5 having a film thickness of 20 nm and a state density of 2.00 × 10 ¹⁷ cm ⁻³ , the charge density of negative carriers in the amorphous silicon semiconductor layer 5 is (20 nm) × (2.00 × 10 ¹⁷ cm ⁻³ ) = 4.0 × 10 ¹¹ cm ⁻² .

  As described above, the charge density of the amorphous silicon semiconductor layer is determined by the product of the film thickness and the state density of charge, but if the film thickness of the amorphous silicon semiconductor layer is too thick, the on-characteristics deteriorate. If the density of states is too large, leakage current will be caused. Therefore, it is preferable to set the film thickness and the state density of the amorphous silicon semiconductor layer in a desired range as shown in FIG.

For example, when the film thickness of the amorphous silicon semiconductor layer 5 is 10 nm or more and 60 nm or less, the state density (DOS) of the amorphous silicon semiconductor layer 5 when measured by the TVS measurement method is 1 × 10 ¹⁷ cm ^−. It is preferable that it is ³ or more and 7 * 10 < ¹⁷ > cm < ^-3 > or less. Thereby, the charge density of the negative carriers contained in the amorphous silicon semiconductor layer 5 can be 3 × 10 ¹¹ cm ⁻² or more, and the positive fixed contained in the organic protective film 6 having a film thickness of 300 nm to 1 μm. The charge can be canceled out.

Further, in the case where the film thickness of the amorphous silicon semiconductor layer 5 is 20 nm or more and 40 nm or less, the state density (DOS) of the amorphous silicon semiconductor layer 5 when measured by the TVS measurement method is 1 × 10 ¹⁷ cm. ^-3 or more and 5 × 10 ¹⁷ cm ⁻³ or less is preferable.

  Next, the operation of the thin film transistor according to this embodiment will be described in more detail with reference to FIGS. 3A, 3B, 4A, and 4B. FIG. 3A is a cross-sectional view illustrating the configuration and operation of a thin film transistor according to a comparative example. FIG. 3B is a diagram illustrating current-voltage characteristics of the thin film transistor according to the comparative example. FIG. 4A is a cross-sectional view showing the configuration and operation of the thin film transistor according to the embodiment of the present invention. FIG. 4B is a diagram showing current-voltage characteristics of the thin film transistor according to the embodiment of the present invention. In FIG. 3A, the same components as those shown in FIG.

  As shown in FIG. 3A, the thin film transistor 10A according to the comparative example is different from the thin film transistor 10 according to the present embodiment in that the amorphous silicon semiconductor layer 5 is not formed. When the current-voltage characteristics of the thin film transistor 10A according to the comparative example were measured, it was found that the S value deteriorated as described above, and in particular, the rising region of the S value was blurred.

  As a result of intensive analysis and examination of the cause of the deterioration of the S value, the inventor of the present application has found that when an organic material is used as the channel protective layer, the channel protective layer contains a lot of positive fixed charges. It was found that a back channel was formed in the channel layer when a current was passed, and this was the cause of the deterioration of the S value.

  The front channel is a path of on-current (drain current) passing from the source electrode toward the drain electrode through the vicinity of the interface with the gate electrode in the channel layer. On the other hand, the back channel is a path of parasitic current passing through the vicinity of the interface with the channel protective layer in the channel layer from the source electrode to the drain electrode.

  The thin film transistor 10A according to the comparative example includes a positive fixed charge in the organic protective film 6 (or the interface between the organic protective film 6 and the crystalline silicon semiconductor layer 4). A back channel is formed in the vicinity of the interface on the organic protective film 6 side in the porous silicon semiconductor layer 4.

  Therefore, at the time of turning on, although the front channel formed in the vicinity of the interface on the gate electrode 2 side in the crystalline silicon semiconductor layer 4 is originally a necessary path, the back channel is formed due to the formation of the back channel. As shown in FIG. 3B, the current-voltage characteristics of the thin film transistor 10A are the characteristics in which the characteristics due to the front channel (curve shown as drain current in FIG. 3B) and the characteristics due to the back channel (curve shown as parasitic current in FIG. 3B) are superimposed. Become.

  In the rise from off to on, once it rises, it converges to the same characteristic even if the characteristic due to the back channel is superimposed on the characteristic due to the front channel. It will appear superimposed in an inconsistent form. This is considered to cause blurring in the rising region of the S value.

  The inventors of the present application further examined the fixed charge in the organic protective film 6 and obtained the following knowledge.

  Although a positive charge is accumulated at the interface of the organic protective film 6, it is considered that a negative fixed charge is charged in the bulk portion of the organic protective film 6. Therefore, if the film thickness of the organic protective film 6 increases, negative fixed charges increase, and it is considered that there is an action of suppressing positive charges existing at the interface of the organic protective film 6.

  However, it has been found that when the thickness of the organic protective film 6 is set to a certain thickness or more, the effect of suppressing positive charges at the interface of the organic protective film 6 does not increase further. This is because when the negative fixed charge in the bulk portion of the organic protective film 6 is present in a region close to the interface of the organic protective film 6, the effect on the interface is large and an action of suppressing positive charges can be expected. If the thickness of the protective film 6 increases and the negative fixed charge in the bulk portion of the organic protective film 6 moves away from the interface, it is considered that the action of suppressing the positive charge is inversely proportional to the square of the distance. It is.

  Therefore, even if the thickness of the organic protective film 6 is increased, if the film thickness exceeds a certain value, the effect of suppressing positive charges at the interface of the organic protective film 6 is lost. This fixed charge remains as positive. Thus, the polarities of the fixed charges contained in the organic protective film 6 and the total charges at the interface between the organic protective film 6 and the amorphous silicon semiconductor layer 5 are positive.

  Here, when comparing a thin film transistor using an inorganic protective film made of an inorganic material as a channel protective film and a thin film transistor using an organic protective film made of an organic material as a channel protective film, the case where an organic protective film is used is better. The threshold voltage was found to shift to the negative side. From this, it can be seen that the positive charge is higher when the organic protective film is used than when the inorganic protective film is used.

  Therefore, even if there is a thin film transistor having a structure in which an intrinsic amorphous silicon semiconductor layer is formed between the channel protective film of the inorganic protective film and the crystalline silicon semiconductor layer, an intrinsic amorphous film In the quality silicon semiconductor layer, the influence of the positive charge that increases due to the use of the organic protective film cannot be suppressed. Also, even if it is not an intrinsic amorphous silicon semiconductor layer, the normal amorphous silicon semiconductor layer often does not stick to the film quality, and in this case also, the influence of the positive charge that increases due to the use of the organic protective film is suppressed. Can not do it. This is because an amorphous silicon semiconductor layer is generally introduced for the purpose of suppressing off-current, so that an intrinsic amorphous silicon semiconductor layer can sufficiently suppress off-current. Because it can.

  Thus, the intrinsic amorphous silicon semiconductor layer cannot function as a charge suppression layer. Accordingly, the formation of the back channel due to the organic protective film cannot be suppressed by simply applying the amorphous silicon semiconductor layer to the thin film transistor having the organic protective film as the channel layer.

  Therefore, the present invention is based on the above findings, as shown in FIG. 4A, as a charge suppression layer between the organic protective film 6 and the crystalline silicon semiconductor layer 4 as in the thin film transistor 10 according to the present embodiment. The idea of introducing an amorphous silicon semiconductor layer 5 containing negative carriers of a predetermined charge amount was obtained. In other words, in the present invention, an amorphous silicon semiconductor layer having a density of states containing negative carriers, that is, an amorphous silicon semiconductor layer having a high defect density with a large number of traps, is used in the organic protective film 6. We decided to mitigate the effects of positive charges.

In this embodiment, the amorphous silicon semiconductor layer 5 is configured so as to include negative carriers having a charge density of 3 × 10 ¹¹ cm ⁻² or more, so that the amorphous silicon semiconductor layer 5 is negatively charged. It has been found that electric field shielding can be performed by offsetting the positive charge of the organic protective film 6 by carriers. With such a configuration, as shown in FIG. 4A, the formation of a back channel at the time of ON can be suppressed, and the parasitic current due to the back channel can be suppressed as shown in FIG. 4B. As a result, the current-voltage characteristic of the thin film transistor 10 is realized by the characteristic of the front channel (curve shown as the drain current in FIG. 4B), and the blurring that occurs in the rising region of the S value can be suppressed and the S value can be improved. Can do.

  Further, in the thin film transistor 10 according to this embodiment, since the formation of a back channel can be suppressed, a shift in threshold voltage can also be suppressed.

  As described above, since the thin film transistor 10 according to the present embodiment can improve the S value and suppress the shift of the threshold voltage, the thin film transistor 10 according to the present embodiment is driven by an organic EL display. When used as a transistor, the accuracy of the black emission region can be improved.

  Here, since the thin film transistor was actually manufactured and the current-voltage characteristic was measured, the measurement result is demonstrated using FIG. 5A, FIG. 5B, and FIG. 5C. FIG. 5A is a diagram showing current-voltage characteristics of the thin film transistor according to the comparative example shown in FIG. 3A. 5B and 5C are diagrams showing current-voltage characteristics of the thin film transistor according to the present invention shown in FIG. 5B shows a case where the amorphous silicon semiconductor layer 5 has a thickness of 10 nm, and FIG. 5C shows a case where the amorphous silicon semiconductor layer 5 has a thickness of 20 nm.

Note that, as described above, the amorphous silicon semiconductor layer is not formed in the thin film transistor according to the comparative example showing the characteristics of FIG. 5A. 5B and 5C, the thin film transistor according to the present invention has the amorphous silicon semiconductor layer 5 in which the film quality is fixed and the film thickness is changed, and the DOS of the amorphous silicon semiconductor layer 5 is All are 4.0 × 10 ¹¹ cm ⁻² , and the film thickness of the organic protective film 6 is 500 nm.

  As shown in FIGS. 5A to 5C, it can be seen that the thin film transistor 10 according to the present invention suppresses fluctuations in the rising region of the S value and improves the S value compared to the thin film transistor 10A according to the comparative example. Further, as shown in FIGS. 5B and 5C, it can be seen that the S value is further improved by increasing the film thickness of the amorphous silicon semiconductor layer 5.

  Next, the relationship between the film thickness of the amorphous silicon semiconductor layer 5 and the S value will be described with reference to FIG. FIG. 6 is a diagram showing the relationship between the amorphous silicon semiconductor layer 5 and the S value in the thin film transistor according to the embodiment of the present invention. In FIG. 6, the amorphous silicon semiconductor layer 5 has the same film quality (constant density of state) and is measured by changing only the film thickness.

  As shown in FIG. 6, it can be seen that increasing the film thickness of the amorphous silicon semiconductor layer 5 improves the S value and improves the electric field shielding effect. Further, as shown in FIG. 6, it can be seen that the S value becomes constant when the film thickness of the amorphous silicon semiconductor layer 5 is 20 nm or more, and the electric field shielding effect is saturated. If the film thickness of the amorphous silicon semiconductor layer 5 is larger than 40 nm, the film thickness becomes too thick and the on-characteristics deteriorate. Therefore, the film thickness of the amorphous silicon semiconductor layer 5 is preferably 20 nm to 40 nm.

Next, in the thin film transistor according to the present embodiment, a change in the minimum off-leakage current with respect to a change in the thickness of the organic protective film 6 will be described with reference to FIG. FIG. 7 is a diagram showing the relationship between the film thickness of the organic protective film and the minimum off-leakage current in the thin film transistor according to this embodiment. In FIG. 7, the DOS of the amorphous silicon semiconductor layer 5 is 4.0 × 10 ¹¹ cm ⁻² and the film thickness is 20 nm.

Since the minimum off-leakage current needs to be 0.1 nA (1.0 × 10 ⁻¹¹ A) for device reliability of the thin film transistor, the thickness of the organic protective film 6 is 500 nm or more as shown in FIG. It is preferable to do. When the thickness of the organic protective film 6 is less than 500 nm, the leakage current at the OFF time increases due to damage to the channel layer by the etching process. Therefore, by setting the film thickness of the organic protective film 6 to 500 nm or more, it is possible to suppress the generation of leakage current at the time of OFF, and to realize a highly reliable thin film transistor.

(Thin Film Transistor Manufacturing Method)
Hereinafter, a method of manufacturing the thin film transistor 10 according to the embodiment of the present invention will be described with reference to FIGS. 8A to 8G. 8A to 8G are cross-sectional views schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the embodiment of the present invention.

  First, as shown in FIG. 8A, a substrate 1 is prepared. As the substrate 1, for example, a glass substrate can be used. After that, before forming the gate electrode 2, an undercoat layer made of an insulating film such as a silicon oxide film or a silicon nitride film may be formed on the substrate 1 by plasma CVD or the like.

  Next, as shown in FIG. 8B, a gate electrode 2 having a predetermined shape is formed on the substrate 1 in a pattern. For example, a gate metal film made of molybdenum tungsten (MoW) or the like is formed on the entire upper surface of the substrate 1 by sputtering, and the gate metal film is patterned by performing photolithography and wet etching to form a gate electrode 2 having a predetermined shape. Form.

  Next, as shown in FIG. 8C, a gate insulating film 3 is formed above the substrate 1. For example, a gate insulating film 3 made of an insulating film such as silicon oxide is formed on the entire upper surface of the substrate 1 so as to cover the gate electrode 2 by plasma CVD or the like.

Next, as shown in FIG. 8D, a crystalline silicon semiconductor layer 4 is formed on the gate insulating film 3. In this case, first, an amorphous silicon thin film made of, for example, an amorphous silicon film (a-Si) is formed on the gate insulating film 3 by plasma CVD or the like. The amorphous silicon film can be formed under a predetermined film forming condition by introducing, for example, silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) at a predetermined concentration ratio. Thereafter, after performing a dehydrogenation annealing process, the amorphous silicon thin film is crystallized by annealing the amorphous silicon thin film at a predetermined temperature. Thereby, the crystalline silicon semiconductor layer 4 can be formed on the gate insulating film 3.

  Note that in this embodiment mode, crystallization of the amorphous silicon thin film is performed by laser annealing by irradiation with laser light. For the laser annealing, laser annealing (ELA) using an excimer laser, laser annealing using a pulse laser, or laser annealing using a continuous wave laser (CW laser) can be used. In addition to laser annealing, crystallization may be performed by rapid thermal annealing (RTA), or the crystalline silicon semiconductor layer 4 may be formed by direct growth by CVD.

  Next, as shown in FIG. 8E, an amorphous silicon semiconductor layer 5 is formed on the crystalline silicon semiconductor layer 4. For example, an amorphous silicon film can be formed as the amorphous silicon semiconductor layer 5. The amorphous silicon film can be formed under a predetermined film formation condition by plasma CVD or the like using a predetermined source gas. For example, a film can be formed by introducing silane gas and hydrogen gas at a predetermined concentration ratio.

In the present embodiment, the amorphous silicon semiconductor layer 5 is formed under film forming conditions in which the plasma density is 0.1 to 1.0 [W / cm ² ] and the growth temperature is 300 to 400 ° C. It is preferable. As the source gas for the amorphous silicon semiconductor layer 5, a gas containing any one of silane gas (SiH ₄ ), disilane gas (Si ₂ H ₆ ), and trisilane gas (Si ₃ H ₈ ) can be used. In addition to hydrogen gas (H ₂ ), argon gas (Ar) or helium gas (He) can be used as the inert gas introduced together with the source gas.

  Next, as shown in FIG. 8F, an organic protective film 6 is formed on the amorphous silicon semiconductor layer 5. For example, the organic protective film 6 can be formed by applying and baking a predetermined organic material on the amorphous silicon semiconductor layer 5 by a predetermined coating method.

  In the present embodiment, first, polysiloxane is applied onto the amorphous silicon semiconductor layer 5 and spin-coated to form the organic protective film 6 on the entire surface of the amorphous silicon semiconductor layer 5. Then, after prebaking and pre-baking the organic protective film 6, it exposes and develops using a photomask and forms the organic protective film 6 of a predetermined shape. Thereafter, post-baking is performed and the organic protective film 6 is baked. Thereby, the organic protective film 6 which becomes a channel protective layer can be formed.

  Next, as shown in FIG. 8G, a pair of contact layers 7, a source electrode 8S, and a drain electrode 8D are formed on the amorphous silicon semiconductor layer 5 with the organic protective film 6 interposed therebetween.

  In this case, first, amorphous silicon doped with an impurity of a pentavalent element such as phosphorus is used as a contact layer film for forming the contact layer 7 on the amorphous silicon semiconductor layer 5 so as to cover the organic protective film 6. A film is formed by plasma CVD. Thereafter, a source / drain metal film to be the source electrode 8S and the drain electrode 8D is formed on the contact layer film by sputtering. Then, a resist having a predetermined shape is formed on the source / drain metal film in order to form the source electrode 8S and the drain electrode 8D having a predetermined shape, and the source / drain metal film is patterned by performing wet etching using the resist as a mask. . Thereby, as shown in FIG. 8G, a source electrode 8S and a drain electrode 8D having a predetermined shape are formed. At this time, the contact layer film functions as an etching stopper.

  Thereafter, the resist on the source electrode 8S and the drain electrode 8D is removed, and etching such as dry etching is performed using the source electrode 8S and the drain electrode 8D as a mask to pattern the contact layer film. The crystalline silicon semiconductor layer 5 and the crystalline silicon semiconductor layer 4 are patterned into island shapes. As a result, as shown in FIG. 8G, a pair of contact layers 7 having a predetermined shape can be formed, and the amorphous silicon semiconductor layer 5 and the crystalline silicon semiconductor layer 4 patterned into island shapes can be formed.

In this manner, the thin film transistor 10 according to the embodiment of the present invention can be manufactured. In this embodiment, the growth temperature is 320 ° C., the pressure is 2 Torr, the RF power is 50 W (power density is 0.137 W / cm ² ), and the gas flow rates of silane and hydrogen are 10 sccm and 50 sccm, respectively. The amorphous silicon semiconductor layer 5 having a film thickness of 20 nm and a DOS of 4.0 × 10 ¹¹ cm ⁻² was formed according to the film formation conditions.

In the present embodiment, the growth temperature when forming the amorphous silicon semiconductor layer 5 is preferably 300 to 400 ° C. This point will be described with reference to FIG. FIG. 9 is a diagram showing the relationship between the growth temperature and the spin density when forming the amorphous silicon semiconductor layer 5 in the method of manufacturing a thin film transistor in the embodiment of the present invention. In FIG. 9, the vertical axis represents the spin density obtained by an electron spin resonance (ESR) method. The spin density has a correlation with a defect density (dangling bond), that is, a density of states. Further, FIG. 9 shows a case where a film is formed using SiH ₄ and H ₂ , a case where a film is formed using SiH ₄ , and a case where a film is formed using SiH ₄ and Ar.

From FIG. 9, it can be seen that the amorphous silicon semiconductor layer 5 having a film quality with a spin density of 1.0 × 10 ¹⁷ cm ⁻³ to 4 × 10 ¹⁷ cm ⁻³ can be formed. Further, FIG. 9 shows that the growth temperature when forming the amorphous silicon semiconductor layer 5 is preferably about 300 ° C. to 400 ° C.

Note that when an amorphous silicon film is formed under the film formation conditions where the growth temperature is 350 ° C. and the plasma density is 0.01 to 0.06 [W / cm ² ] (no dehydrogenation), the spin density is 4 ×. It was about 10 ^{16 to} 6 × 10 ¹⁶ cm ⁻³ . Moreover, when the film was similarly formed by performing dehydrogenation at 500 ° C. for 20 minutes, the spin density was 3 × 10 ^{18 to} 5 × 10 ¹⁸ cm ⁻³ . In other words, in the present embodiment, the amorphous silicon semiconductor layer 5 having a film quality with a spin density of 1.0 × 10 ¹⁷ to 4 × 10 ¹⁷ cm ⁻³ is formed as described above. An amorphous silicon semiconductor layer 5 having a level different from the film quality (state density) is used.

  As described above, the thin film transistor and the method for manufacturing the thin film transistor according to the present invention have been described based on the embodiment, but the present invention is not limited to the above embodiment.

  For example, the thin film transistor according to this embodiment can be used for a display device such as an organic EL display device or a liquid crystal display device. In addition, the display device can be used as a flat panel display and can be applied to electronic devices such as a television set, a personal computer, and a mobile phone.

  In addition, it is realized by arbitrarily combining the components and functions in each embodiment without departing from the scope of the present invention, or the form obtained by making various modifications conceived by those skilled in the art to each embodiment. Forms to be made are also included in the present invention.

  The thin film transistor according to the present invention can be widely used in a display device such as a television set, a personal computer, a mobile phone, or other various electric devices having a thin film transistor.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Gate insulating film 4 Crystalline silicon semiconductor layer 5 Amorphous silicon semiconductor layer 6 Organic protective film 7 Contact layer 8S Source electrode 8D Drain electrode 10, 10A Thin film transistor

Claims (9)

A substrate,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
A crystalline silicon semiconductor layer formed on the gate insulating film;
An amorphous silicon semiconductor layer formed on the crystalline silicon semiconductor layer;
An organic protective film made of an organic material formed on the amorphous silicon semiconductor layer;
A source electrode and a drain electrode formed on the amorphous silicon semiconductor layer with the organic protective film interposed therebetween,
The charge density of negative carriers contained in the amorphous silicon semiconductor layer is 3 × 10 ¹¹ cm ⁻² or more.
Thin film transistor. The thickness of the organic protective film in a region overlapping with the source electrode or the drain electrode is 300 nm or more and 1 μm or less.
The thin film transistor according to claim 1. The thickness of the organic protective film in a region overlapping with the source electrode or the drain electrode is 500 nm or more and 1 μm or less.
The thin film transistor according to claim 1. The polarity of the fixed charge contained in the organic protective film and the total charge of the charge at the interface between the organic protective film and the amorphous silicon semiconductor layer is positive.
The thin film transistor according to any one of claims 1 to 3. The film thickness of the amorphous silicon semiconductor layer is 10 nm or more and 60 nm or less,
The charge density of the amorphous silicon semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or more and 7 × 10 ¹⁷ cm ⁻³ or less when measured by a TVS measurement method.
The thin film transistor according to any one of claims 1 to 4. The amorphous silicon semiconductor layer has a thickness of 20 nm to 40 nm,
The charge density of the amorphous silicon semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less.
The thin film transistor according to claim 5. A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating film on the gate electrode;
A fourth step of forming a crystalline silicon semiconductor layer on the gate insulating film;
A fifth step of forming an amorphous silicon semiconductor layer on the crystalline silicon semiconductor layer;
A sixth step of forming an organic protective film by applying an organic material on the amorphous silicon semiconductor layer;
Forming a source electrode and a drain electrode across the organic protective film on the amorphous silicon semiconductor layer, and
The charge density of negative carriers contained in the amorphous silicon semiconductor layer is 3 × 10 ¹¹ cm ⁻² or more.
A method for manufacturing a thin film transistor. In the fifth step,
The amorphous silicon semiconductor layer includes a source gas containing any one of silane gas, disilane gas, and trisilane gas, argon, hydrogen, and a film having a plasma density of 0.1 W / cm ² to 1 W / cm ^2. Formed with an inert gas containing any of helium,
A method for manufacturing the thin film transistor according to claim 7. In the fifth step,
The amorphous silicon semiconductor layer is formed under a film forming condition in which a growth temperature is set to 300 ° C. to 400 ° C.
A method for manufacturing the thin film transistor according to claim 7 or 8.

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