JP2003173970A - Semiconductor film, semiconductor device and method for manufacturing them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for reducing the unevenness of elements by effectively removing the metal element for encouraging the crystallization of a semiconductor film and retained in the semiconductor film, after the semiconductor film having a crystal structure is obtained by using the metal element. <P>SOLUTION: In the step of forming a gettering site, a plasma CVD method is used, and as material gases, a monosilane gas, a rare gas element and a hydrogen are used for forming the film. The rare gas element is included in a high concentration such as, for example, 1×10<SP>20</SP>/cm<SP>3</SP>to 1×10<SP>21</SP>/cm<SP>3</SP>. The semiconductor film 16 having an amorphous structure or a noncrystalline silicon film as a representative is provided. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor film having an amorphous structure by a plasma CVD method, and
A thin film transistor using this semiconductor film (hereinafter referred to as TFT
The present invention relates to a semiconductor device having a circuit configured by (1) and a manufacturing method thereof. For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and an electronic device in which such an electro-optical device is mounted as a component.

[0002] In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices.

[0003]

2. Description of the Related Art A thin film transistor (hereinafter referred to as a TFT) is used as a typical semiconductor device using a semiconductor film having a crystal structure.
Is known). The TFT is drawing attention as a technique for forming an integrated circuit on an insulating substrate such as glass, and a drive circuit integrated liquid crystal display device and the like are being put to practical use. In the conventional technique, a semiconductor film having a crystalline structure is obtained by subjecting an amorphous semiconductor film deposited by a plasma CVD method or a low pressure CVD method to a heat treatment or a laser annealing method (a technique of crystallizing a semiconductor film by laser light irradiation). It is made by.

The semiconductor film having a crystal structure produced in this manner is an aggregate of a large number of crystal grains, and its crystal orientation is oriented in an arbitrary direction and cannot be controlled, which is a factor limiting the characteristics of the TFT. ing. In order to solve such a problem, the technique disclosed in JP-A-7-183540 is to add a metal element such as nickel that promotes crystallization of a semiconductor film to produce a semiconductor film having a crystal structure. In addition to the effect of lowering the heating temperature required for crystallization, it is possible to enhance the orientation of crystal orientation in a single direction. When a TFT is formed of a semiconductor film having such a crystal structure, not only the field effect mobility is improved, but also the subthreshold coefficient (S value) is reduced, and the electrical characteristics can be dramatically improved. ing.

The use of a metal element that promotes crystallization makes it possible to control the nucleation during crystallization.
The film quality obtained is uniform compared to other crystallization methods in which nucleation is random, and ideally, it is desirable to completely remove the metal element or reduce it to an allowable range. However, since the metal element that promotes crystallization is added, there is a problem that the metal element remains in the film or the film surface of the semiconductor film having a crystal structure, and the characteristics of the obtained device are varied. . One example thereof is a problem that the off-current increases in the TFT and the TFTs vary among the individual elements. That is, the metal element that promotes crystallization becomes an unnecessary existence once the semiconductor film having the crystal structure is formed.

Gettering using phosphorus is effectively used as a method for removing a metal element that promotes crystallization from a specific region of a semiconductor film having a crystal structure. For example, by adding phosphorus to the source / drain region of the TFT and performing heat treatment at 450 to 700 ° C., the metal element can be easily removed from the channel formation region.

[0007]

Phosphorus is an ion doping method (a method of dissociating PH ₃ or the like with plasma and accelerating the ions with an electric field to implant them into a semiconductor. Basically, mass separation of ions is performed. However, the phosphorus concentration required for gettering is 1 × 10 ²⁰ / cm ³ or more. The addition of phosphorus by the ion doping method brings about amorphization of the semiconductor film having a crystal structure, but an increase in the phosphorus concentration is a problem because it hinders recrystallization by subsequent annealing. Further, the addition of a high concentration of phosphorus causes an increase in the processing time required for doping, which lowers the throughput in the doping process, which is a problem.

Further, the concentration of boron required to invert the conductivity type is 1.5 to 3 times that of phosphorus added to the source / drain regions of the p-channel TFT, which causes recrystallization. Along with the difficulty, the resistance of the source / drain region is increased, which is a problem.

Further, if the gettering is not sufficient in the substrate and the gettering varies, each TFT is
There was a slight difference in characteristics, that is, variation. In the case of a transmissive liquid crystal display device, if the TFTs arranged in the pixel portion have variations in electrical characteristics, variations in the voltage applied to each pixel electrode occur, which causes variations in the amount of transmitted light.
This causes display unevenness and appears in the eyes of the observer.

Further, in the light emitting device using the OLED, the TFT is an essential element for realizing the active matrix driving system. Therefore, in a light emitting device using an OLED, at least a TFT that functions as a switching element and a TFT that supplies a current to the OLED are provided in each pixel. Pixel circuit configuration,
And electrically connected to the OLED regardless of the driving method,
In addition, the on-current (I
_Since the brightness of the pixel is determined by ( _on ), there is a problem that, for example, when the white display is performed on the entire surface, the brightness varies unless the on-current is constant.

The present invention is a means for solving such a problem, which is obtained by obtaining a semiconductor film having a crystal structure using a metal element that promotes crystallization of the semiconductor film, and then remaining in the film. It is an object of the present invention to provide a technique for effectively removing a metal element.

[0012]

The gettering technique is positioned as a main technique in the technique of manufacturing an integrated circuit using a single crystal silicon wafer. Gettering is known as a technique in which metal impurities taken into a semiconductor are segregated at gettering sites by some energy to reduce the impurity concentration in the active region of the device.
It is the extrinsic gettering (Extrinsic G
ettering and Intrinsic gettering
There are two main categories: Gettering). The extrinsic gettering is one in which a gettering effect is brought about by externally applying a strain field or a chemical action. This is the gettering for diffusing high-concentration phosphorus from the back surface of the single crystal silicon wafer, and the above-mentioned gettering using phosphorus can be regarded as a kind of extrinsic gettering.

On the other hand, intrinsic gettering is known to utilize the strain field of lattice defects involving oxygen generated inside a single crystal silicon wafer.
The present invention focuses on intrinsic gettering utilizing such lattice defects or lattice distortion, and adopts the following means for applying to a semiconductor film having a crystal structure with a thickness of about 10 to 100 nm. To do.

The present invention provides a step of forming a first semiconductor film having a crystalline structure on an insulating surface by using a metal element that promotes crystallization of a semiconductor, and an etching stopper on the first semiconductor film. A step of forming a film (barrier layer),
Forming a second semiconductor film (gettering site) containing a rare gas element and nitrogen on the barrier layer; forming a gettering site with a metal element; and removing the second semiconductor film. And the process.

In the present invention, as the step of forming the gettering site, a plasma CVD method is used to form a film by using monosilane, a rare gas element and nitrogen as a raw material gas, and the amorphous gas containing a high concentration of the rare gas element. A semiconductor film having a quality structure,
Typically, an amorphous silicon film is used.
Further, disilane or trisilane may be used instead of monosilane. Since the plasma CVD method can clean the inside of the film forming chamber (also called a chamber) with a gas, it requires less maintenance than the sputtering method.
This film formation method is suitable for mass production.

In the structure of the invention relating to the method for manufacturing a semiconductor film disclosed in this specification, monosilane, a rare gas, and nitrogen are introduced as source gases into a film formation chamber to generate plasma,
A method for manufacturing a semiconductor film having an amorphous structure, which comprises forming a semiconductor film containing a rare gas element and nitrogen and having an amorphous structure on a surface to be coated.

Further, in the above structure, when the plasma is generated, the pressure in the film forming chamber is 2.666P.
It is characterized in that it is a to 133.3 Pa.

Further, in the above structure, the flow rate ratio of nitrogen to the rare gas (N ₂ / rare gas) is controlled to 0.2 to 5.

In the above structure, the RF power density for generating the plasma is 0.0017 W / cm ^2.
It is characterized in that it is ˜1 W / cm ² . 1
When the RF power is higher than W / cm ² , a film is not formed into a powder, but a film-forming defect such as a hemispherical floating on the film is likely to occur.

In the above structure, monosilane, a rare gas element, and nitrogen are used as the source gas, and the ratio (monosilane: rare gas) is 0.1: 99.9 to 1: 9, preferably 1:99 to 5. It is characterized in that a semiconductor film having a high concentration of a rare gas element and having an amorphous structure, typically, an amorphous silicon film is formed. Further, disilane or trisilane may be used instead of monosilane. The film forming temperature is 300 ° C to 500 ° C.
C is preferred.

Monosilane (flow rate 2 sccm) as raw material gas
And argon (flow rate 198sccm) and nitrogen (10sccm)
By controlling the ratio (monosilane: rare gas) to 1:99, the film forming temperature is 350 ° C., and the film forming pressure is 6.665 Pa.
FIG. 19 shows the experimental result obtained by calculating the argon concentration by measuring the argon / silicon intensity ratio near the surface of the amorphous silicon film formed under the film forming conditions of (0.05 Torr) and RF power of 50 W by TXRF. . The highest argon concentration is about 1.7 × 10 ¹⁴ atoms / cm ² ,
It can be said that the amorphous silicon film has a sufficient argon concentration as a gettering site.

In the above structure, the semiconductor film having the amorphous structure has a film thickness of 1 × 10 ¹⁸ / cm ³ to 1 ×.
It is characterized in that it contains nitrogen at a concentration of 10 ²² / cm ³ .

Further, in the above structure, the semiconductor film having the amorphous structure is 1 × 10 ¹⁸ / cm ³ to 1 × in the film.
10 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 1
It is characterized in that it contains a rare gas element at a concentration of 0 ²¹ / cm ³ .

Semiconductor film obtained by the above manufacturing method
Is 1 × 10 in the film¹⁸/ Cm³~ 1 x 10²⁰/ Cm³Nono
Contains rare gas element at a temperature of 1 × 10²⁰/ Cm³~ 1
× 10 ^{twenty one}/ Cm³Characterized by containing nitrogen at a concentration of
A semiconductor film having an amorphous structure.

In addition, the structure of the invention relating to the method for manufacturing a semiconductor device disclosed in this specification includes a first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and the amorphous structure. A second step of adding a metal element to the first semiconductor film having: and a third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure; A fourth step of forming a barrier layer on the surface of the first semiconductor film, a fifth step of forming a second semiconductor film containing a rare gas element and nitrogen on the barrier layer, and the second semiconductor A sixth step of removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element into the film, and a seventh step of removing the second semiconductor film A method for manufacturing a semiconductor device, comprising:

In the above structure, the second semiconductor film is formed by a plasma CVD method in which monosilane, a rare gas, and nitrogen are introduced as source gases into the film forming chamber and plasma is generated.

In the above structure, the metal element is a metal element that promotes crystallization of silicon, and Fe,
Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, C
It is one or more selected from u and Au.

In each of the above structures, the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.

(Experiment 1) Here, an argon concentration and a nitrogen concentration in a film of an amorphous silicon film formed on a semiconductor substrate (silicon substrate) by using a plasma CVD method and using monosilane, an argon element and nitrogen as a source gas. It was decided to check the concentration.

First, the semiconductor substrate is transferred into the chamber, heated and maintained at 300 ° C., and the pressure in the chamber is adjusted to 66.65 Pa (0.5 Torr) by the exhaust system. Next, Si is introduced into the chamber from the gas introduction system.
Introduce H ₄ gas at a flow rate of 100 sccm, discharge frequency 27.12 MHz from high frequency power supply, and input RF power 2
The first amorphous silicon film was formed by plasma CVD while discharging 0 W (RF power density 0.033 W / cm ² (electrode area 600 cm ² )). The first amorphous silicon film is a reference.

Then, a second amorphous silicon film having a film thickness of 200 nm was laminated on the first amorphous silicon film. After the second amorphous silicon film was maintained at 300 ° C., the pressure inside the chamber was 5.332 Pa (0.
04 Torr), and adjust the exhaust system to supply SiH ₄ gas from the gas introduction system into the chamber at a flow rate of 100 sccc.
m, argon gas flow rate 100 sccm, nitrogen gas 8
It is introduced at 0 sccm, and the discharge frequency is 27.12 MHz from the high frequency power source and the input RF power is 20 W (R
It was formed by a plasma CVD method while discharging with an F power density of 0.033 W / cm ² .

Then, a third amorphous silicon film having a film thickness of 200 nm was laminated on the second amorphous silicon film. After the third amorphous silicon film was maintained at 300 ° C., the pressure inside the chamber was 4 Pa (0.03 Tor).
r) is adjusted by an exhaust system so that SiH ₄ gas is introduced into the chamber from the gas introduction system at a flow rate of 100 sccm, argon gas is introduced at a flow rate of 50 sccm, and nitrogen gas is introduced at 40 sccm.
Plasma C while discharging at 7.12 MHz and input RF power of 20 W (RF power density 0.033 W / cm ² ).
It was formed by the VD method.

Then, a fourth amorphous silicon film having a film thickness of 200 nm was laminated on the third amorphous silicon film. After the fourth amorphous silicon film was maintained at 300 ° C., the pressure in the chamber was 2.666 Pa (0.
02 Torr) so that the flow rate of SiH ₄ gas from the gas introduction system into the chamber is 50 sccm,
Argon gas flow rate 25sccm, nitrogen gas 20sc
cm 2 and a discharge frequency of 27.12 MHz from a high-frequency power source, and a discharge RF power of 20 W (RF power density 0.033 W / cm ² ) while performing discharge by plasma CVD method.
An amorphous silicon film was formed.

Then, a fifth amorphous silicon film having a film thickness of 200 nm was laminated on the third amorphous silicon film. The fifth amorphous silicon film was formed under the same conditions as the first amorphous silicon film.

SIMS analysis is performed on the laminated film thus obtained on the semiconductor substrate, and the result of measuring the argon concentration in the film is shown in FIG. 2 (A), and the result of measuring the fluorine concentration is shown in FIG. 2 (B). The results of measuring the nitrogen concentration are shown in Fig. 3 (A).
3B shows the results of measuring the oxygen concentration. From FIG. 2 (B), the fluorine concentration in the film is 8 × 10 ¹⁷ /
It can be read as about cm ^{3 to} 2 × 10 ¹⁸ / cm ³ . Further, from FIG. 3B, the oxygen concentration in the film is 4 × 10 ¹⁷ / cm ³ to
It can be read as about 3 × 10 ¹⁸ / cm ³ . Although not shown, the carbon concentration in the film is 1 × 10 ¹⁶ / cm ^{3 to} 5 × 1.
It was 0 ¹⁷ / cm ³ .

As is apparent from FIGS. 2 and 3, by using nitrogen, argon and monosilane gas as the source gas, the argon concentration in the amorphous silicon film is 1 × 10 ²⁰ / c.
It increased to m ³ -1 × 10 ²¹ / cm ³ . Therefore, plasma C using nitrogen, argon and monosilane gas as source gases
High concentration by VD method, specifically 1 × 10 ²⁰ / cm
^An amorphous silicon film containing argon can be formed at a concentration of ³ to 1 × 10 ²¹ / cm ³ . On the other hand, when only monosilane and argon gas are used as the source gas, the argon concentration in the film is around 1 × 10 ¹⁸ / cm ³ , that is, 5 × 1.
Only about 0 ¹⁷ / cm ^{3 to} 2 × 10 ¹⁸ / cm ³ could be contained.

By using nitrogen, argon and monosilane gas as the source gas, the nitrogen concentration in the amorphous silicon film was increased to 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ . Nitrogen and argon are relatively inert gases and inexpensive gases, so they are industrially easy to use.

(Experiment 2) Next, by using the plasma CVD method and changing the RF power density condition, the dependence of the RF power density on the argon concentration and the nitrogen concentration in the amorphous silicon film was investigated.

First, plasma CVD was performed under the same conditions as in Experiment 1.
A first amorphous silicon film serving as a reference was formed on the semiconductor substrate by the method.

Then, a second amorphous silicon film having a film thickness of 200 nm was laminated on the first amorphous silicon film. After the second amorphous silicon film was maintained at 300 ° C., the pressure in the chamber was 26.66 Pa (0.
The exhaust system is adjusted to 2 Torr), and the SiH ₄ gas is introduced into the chamber from the gas introduction system at a flow rate of 100 sccm,
Argon gas flow rate 500sccm, nitrogen gas 200
Introduced in sccm, discharge frequency 27.12MHz from high frequency power source, input RF power 20W (RF
It was formed by a plasma CVD method while discharging with a power density of 0.033 W / cm ² .

Next, the condition of only the input RF power is changed,
A third amorphous silicon film (RF power density 0.166 W / cm ² ) on the second amorphous silicon film, a fourth
Amorphous silicon film (RF power density 0.333W
/ Cm ² ), and a fifth amorphous silicon film (RF power density 0.5 W / cm ² ) were sequentially laminated.

SIMS analysis is performed on the laminated film thus obtained on the semiconductor substrate, the result of measuring the argon concentration in the film is shown in FIG. 4A, and the result of measuring the fluorine concentration is shown in FIG. 4B. Fig. 5 (A) shows the result of measuring the nitrogen concentration.
5B shows the results of measuring the oxygen concentration. The carbon concentration is 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ^1.
It was ⁷ / cm ³ .

As is clear from FIGS. 4 and 5, the argon concentration in the amorphous silicon film increased as the RF power density was increased. Even if the RF power density was increased, the fluorine concentration, the nitrogen concentration, the oxygen concentration, and the carbon concentration in the film hardly changed.

(Experiment 3) Next, using the plasma CVD method, the conditions of the pressure in the chamber were changed, and the dependence of the pressure in the chamber on the argon concentration and the nitrogen concentration in the amorphous silicon film was investigated.

First, plasma CVD was performed under the same conditions as in Experiment 1.
A first amorphous silicon film serving as a reference was formed on the semiconductor substrate by the method.

Then, a second amorphous silicon film having a film thickness of 200 nm was laminated on the first amorphous silicon film. After the second amorphous silicon film was maintained at 300 ° C., the pressure in the chamber was set to 6.666 Pa (0.
The gas flow rate of SiH ₄ gas from the gas introduction system to the chamber is 50 sccm,
Argon gas flow rate 25sccm, nitrogen gas 20sc
cm, and a discharge frequency of 27.12 MHz from a high frequency power source, and a discharge RF power of 300 W (RF power density 0.5 W / cm ² ) were discharged to form a plasma CVD method.

Then, only the pressure inside the chamber is changed, and the third amorphous silicon film (pressure 5.332 Pa (0.04 Tor) is formed on the second amorphous silicon film.
r)), the fourth amorphous silicon film (4 Pa (0.0
3 Torr)), a fifth amorphous silicon film (pressure 2.
666 Pa (0.02 Torr)) was sequentially laminated.

SIMS analysis is performed on the laminated film thus obtained on the semiconductor substrate, and the result of measuring the argon concentration in the film is shown in FIG. 6A, and the result of measuring the fluorine concentration is shown in FIG. 6B. Fig. 7 (A) shows the results of measuring the nitrogen concentration.
7B shows the results of measuring the oxygen concentration, respectively. The carbon concentration is 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ^1.
It was ⁷ / cm ³ .

As is clear from FIGS. 6 and 7, the pressure is reduced,
That is, the argon concentration in the amorphous silicon film increased as the vacuum was increased. Even when the pressure was reduced, the fluorine concentration, the nitrogen concentration, the oxygen concentration, and the carbon concentration in the film showed almost no change.

(Experiment 4) Here, the film quality of the amorphous silicon film formed by using the plasma CVD method and using monosilane, argon element and nitrogen as source gases will be described below.

FIG. 18 shows spectroscopic spectrum data obtained by Fourier transform infrared spectroscopy (FT-IR method) of an amorphous silicon film formed by using monosilane, argon element and nitrogen as source gas. In FIG. 18, 656
Peak of Si-Si bond at 85 cm / cm
There is a peak of Si-N bond at the position of ## EQU1 ## and a peak of 2030 / cm. The wave number of 2000 / cm is the peak of Si—H bond, and the wave number of 2100 / cm is the peak of Si—H ₂ bond. The peak of wave number 2030 / cm in FIG. 18 is mainly Si—H bond and slightly Si. It can be said that this is a peak that appears because it has a —H ₂ bond. Further, this film is also characterized in that the peak of N—H bond is not seen and that the refractive index is 3.0 to 4.0.

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

(Embodiment Mode 1) A typical procedure for manufacturing a TFT using the present invention will be briefly described below with reference to FIG. Here, an example is shown in which a semiconductor film containing the rare gas element and nitrogen of the present invention as a gettering site and having an amorphous structure is used.

In FIG. 1A, 10 is a substrate having an insulating surface, 11 is an insulating film serving as a blocking layer, and 12 is a semiconductor film having an amorphous structure.

In FIG. 1A, the substrate 10 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this step may be used.

First, as shown in FIG. 1A, a base insulating film 1 made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film (SiO _x N _y ) is formed on a substrate 10.
1 is formed. A typical example is 2 as the base insulating film 11.
The first silicon oxynitride film, which has a layered structure and is formed by using SiH ₄ , NH ₃ , and N ₂ O as reaction gases, has a thickness of 50 to 1
A structure is employed in which a second silicon oxynitride film formed by using 00 nm, SiH ₄ , and N ₂ O as reaction gases is laminated to a thickness of 100 to 150 nm. Further, as one layer of the base insulating film 11, a silicon nitride film (SiN film) having a film thickness of 10 nm or less, or a second silicon oxynitride film (SiN film).
It is preferable to use _x O _y film (X»Y)). At the time of gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, it is extremely effective to use a silicon nitride film as a base insulating film which is in contact with the semiconductor film. Also, the first
A three-layer structure in which a silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

Next, the first semiconductor film 12 having an amorphous structure is formed on the base insulating film. First semiconductor film 12
Uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and a plasma CVD method or a low pressure CVD method is used.
Method or sputtering method to a thickness of 10 to 100 nm. In order to obtain a semiconductor film having a good crystal structure by the subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor film 12 having an amorphous structure should be 5 × 10 5.
^{It is} preferable to reduce it to ¹⁸ / cm ³ (atomic concentration measured by secondary ion mass spectrometry (SIMS)) or less. These impurities become a factor that hinders later crystallization, and also becomes a factor that increases the density of trap centers and recombination centers even after crystallization. Therefore, not only high-purity material gas is used, but also ultra-high vacuum-compatible CV equipped with a mirror surface treatment (electrolytic polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.
It is desirable to use the D device.

Next, as a technique for crystallizing the first semiconductor film 12 having an amorphous structure, here, Japanese Unexamined Patent Publication No. 8-7832 is used.
Crystallization is performed using the technique described in Japanese Patent No. The technique described in the publication is a crystal structure that expands from an added region as a starting point by selectively adding a metal element that promotes crystallization to an amorphous silicon film (also called an amorphous silicon film) and performing heat treatment. To form a semiconductor film having First, a nickel acetate salt solution containing 1 to 100 ppm by weight of a metal element (nickel in this case) having a catalytic action for promoting crystallization on the surface of the first semiconductor film 12 having an amorphous structure is spinnered. The nickel-containing layer 13 is formed by coating. (FIG. 1B) As a means other than the method of forming the nickel-containing layer 13 by coating, a method of forming an extremely thin film by a sputtering method, a vapor deposition method, or a plasma treatment may be used. In addition, although the example of coating the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Then, heat treatment is performed to perform crystallization.
In this case, in crystallization, silicide is formed in a portion of the semiconductor film which is in contact with a metal element that promotes crystallization of a semiconductor, and crystallization proceeds with the silicide as a nucleus. Thus, the first semiconductor film 14 having the crystal structure shown in FIG. 1C is formed. Note that the oxygen concentration contained in the first semiconductor film 14 after crystallization is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, heat treatment for dehydrogenation (450 ° C.,
After 1 hour, heat treatment for crystallization (550 ° C. to 65 ° C.)
For 4 to 24 hours at 0 ° C. Further, when crystallization is performed by irradiation with intense light, any one of infrared light, visible light, or ultraviolet light or a combination thereof can be used, but typically, a halogen lamp, a metal halide, or the like. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is 1 to 60 seconds,
It is preferable to turn on the light for 30 to 60 seconds, repeat the operation 1 to 10 times, and instantaneously heat the semiconductor film to about 600 to 1000 ° C. Note that, if necessary, heat treatment for releasing hydrogen contained in the first semiconductor film 14 having an amorphous structure may be performed before irradiation with strong light. Also,
Crystallization may be performed by simultaneously performing heat treatment and intense light irradiation. Considering the productivity, it is desirable to perform crystallization by irradiating strong light.

The first semiconductor film 1 thus obtained
In 4, the metal element (here, nickel) remains. It is not evenly distributed in the membrane,
If the average concentration is exceeded, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ . Of course, even in such a state, it is possible to form various semiconductor elements including the TFT, but the element is removed by the method described below.

Then, in order to increase the crystallization rate (ratio of crystal components in the total volume of the film) and repair defects left in the crystal grains, laser light is applied to the first semiconductor film 14 having a crystal structure. Is preferably irradiated. When irradiated with laser light, a thin oxide film (not shown) is formed on the surface. This laser light includes an excimer laser light having a wavelength of 400 nm or less, a second harmonic of a YAG laser, and a third harmonic.
Use harmonics. Further, continuous wave lasers (YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser,
A glass laser, a ruby laser, an alexandrite laser, or a Ti: sapphire laser) may be used to apply the second to fourth harmonics of the fundamental wave. Typically N
The second harmonic (532 nm) or the third harmonic (355 nm) of the d: YVO ₄ laser (fundamental wave 1064 nm) may be applied. When using a continuous wave laser, output 10
Laser light emitted from a Y continuous wave WVO ₄ laser is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a higher harmonic wave. Then, preferably, a rectangular or elliptical laser beam is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. Note that the shape of the laser beam (laser spot) on the irradiation surface is an elliptical shape having a minor axis length of 3 to 100 μm and a major axis length of 100 μm or more by a beam forming means including an optical system. Instead of the elliptical shape, a rectangular shape having a short side length of 3 to 100 μm and a long side length of 100 μm or more may be used. The shape is rectangular or elliptical in order to efficiently perform laser annealing on the entire surface of the substrate. Here, the length of the long diameter (or the long side) is set to 100 μm or more because the practitioner appropriately determines the length of the long diameter (or the long side) as long as the laser light has an energy density suitable for laser annealing. Because you can do it. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. And
The semiconductor film may be moved and irradiated relative to the laser light at a speed of about 10 to 2000 cm / s.

Since the oxide film formed by the irradiation of the laser beam after the crystallization is not sufficient, an oxide film (called chemical oxide) is further formed with an ozone-containing aqueous solution (typically ozone water). And total 1-10 nm
The barrier layer 15 made of the oxide film is formed, and the second semiconductor film 16 containing a rare gas element is formed on the barrier layer 15. (FIG. 1D) Here, the oxide film formed when the first semiconductor film 14 having a crystal structure is irradiated with laser light is also regarded as part of the barrier layer.
The barrier layer 15 functions as an etching stopper when only the second semiconductor film 16 is selectively removed in a later step. Further, instead of the ozone-containing aqueous solution, the chemical oxide can be similarly formed by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid and the like are mixed with hydrogen peroxide solution. As another method of forming the barrier layer 15, ozone may be generated by irradiation of ultraviolet rays in an oxygen atmosphere to oxidize the surface of the semiconductor film having the crystal structure. As another method for forming the barrier layer 15, a plasma CVD method, a sputtering method, a vapor deposition method, or the like is used to form 1 to 10 nm.
A barrier layer may be formed by depositing an oxide film of a certain degree. When a plasma CVD method, a sputtering method, a vapor deposition method, or the like is used for forming the barrier layer, the surface of the semiconductor film having the above-described crystal structure is washed to remove a natural oxide film or an oxide film formed by laser light irradiation. It is desirable to form after removing.

When the plasma CVD method is used to form the barrier layer, silane-based gas (monosilane, disilane, trisilane, etc.) and nitrogen oxide-based gas (N
A gas represented by Ox) is used for pulse oscillation to form a film. For example, as a source gas, monosilane (SiH ₄ )
And nitrous oxide (N ₂ O), or TEOS gas and N
₂ O or TEOS gas and N ₂ O and O ₂ are used, and 10n
A silicon oxynitride film having a thickness of m or less, preferably 5 nm or less is formed. This silicon oxynitride film is an oxide film (called chemical oxide) obtained from an ozone-containing aqueous solution (typically, ozone water) or a semiconductor film having a crystalline structure by generating ozone by irradiation of ultraviolet rays in an oxygen atmosphere. The adhesiveness to the first semiconductor film having a crystalline structure is higher than that of the oxide film obtained by oxidizing the surface of
Peeling does not occur during the formation of the semiconductor film. Argon plasma treatment may be performed before forming the barrier layer in order to further improve the adhesion. Also in the gettering step, if the silicon oxynitride film is in the above film thickness range, the metal element can pass through the barrier layer and be moved to the gettering site.

When the plasma CVD method is used for forming the barrier layer, it is possible to form the second semiconductor film containing a rare gas element and the barrier layer without exposing the barrier layer to the atmosphere. Since it is possible to continuously form a film in the chamber, the throughput is excellent.

As another method for forming the barrier layer 15, a clean oven may be used and heated to about 200 to 350 ° C. to form a thin oxide film. It should be noted that the barrier layer 15 formed by any one of the above methods or a combination of those methods can be formed by the first gettering in the first step.
It is necessary that the film quality or film thickness of nickel in the semiconductor film is such that the nickel can move to the second semiconductor film. In this specification,
The barrier layer refers to a layer that has a film quality or a film thickness that allows a metal element to pass therethrough in the gettering step and that serves as an etching stopper in the step of removing the layer that serves as a gettering site.

Here, the second gas containing a rare gas element and nitrogen is used.
The semiconductor film 16 is formed by a plasma CVD method to form gettering sites. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Of these, argon (Ar), which is an inexpensive gas, is preferable. Here, by using monosilane, argon, or nitrogen as the source gas, argon is 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / A second semiconductor film containing a concentration of cm ³ and having a gettering effect is formed by plasma C
The film can be formed by the VD method. Note that the second semiconductor film contains nitrogen in addition to argon at 1 × 10 ²⁰ / cm ³ to 1 × 10 ^21.
Included at a concentration of / cm ³ .

There are two meanings of containing the rare gas element ion, which is an inert gas, in the film. One is to form dangling bonds to give strain to the semiconductor film, and the other is to give strain to the lattice of the semiconductor film. In order to give strain to the lattice of the semiconductor film, it is remarkably obtained when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), and xenon (Xe) is used. Further, by containing a rare gas element in the film, not only lattice strain but also dangling bonds are formed, which contributes to the gettering action.

Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor film. As the heat treatment for performing gettering, treatment for irradiating strong light or heat treatment may be performed (FIG. 1E). By this gettering, the metal element moves in a direction of an arrow in FIG. 1E (that is, a direction from the substrate side to the surface of the second semiconductor film), and the first semiconductor film covered with the barrier layer 15 is formed. The metal element contained in 16 is removed or the concentration of the metal element is reduced. The distance that the metal element moves during gettering may be at least the thickness of the first semiconductor film, and gettering can be completed in a relatively short time. Here, all the nickel is moved to the second semiconductor film 19 so as not to segregate in the first semiconductor film 16,
Almost no nickel is contained, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1
Sufficient gettering is performed so that the density is not more than × 10 ¹⁷ / cm ³ .

The second semiconductor film may be partially crystallized depending on the condition of the gettering heat treatment or the thickness of the second semiconductor film. When the second semiconductor film is crystallized, dangling bonds, lattice distortion, and dangling bonds are reduced, which leads to a reduction in gettering effect. Therefore, heat treatment in which the second semiconductor film is not crystallized is preferable. Or the thickness of the second semiconductor film. In any case, the second semiconductor film, that is, the amorphous silicon film containing a rare gas element is less likely to be crystallized than the amorphous silicon film containing no rare gas element, and thus is optimal as a gettering site. Is. Nitrogen is also 1 × 10 ²⁰ / c
Since it is contained at a concentration of m ³ to 1 × 10 ²¹ / cm ³ , it is more difficult to crystallize, which is preferable as a gettering site.

Depending on the condition of the heat treatment for gettering, the crystallinity of the first semiconductor film is increased at the same time as gettering, and defects left in the crystal grains are repaired, that is, crystallinity is improved. be able to.

In this specification, gettering means that the metal element in the gettered region (here, the first semiconductor film) is released by thermal energy and moves to the gettering site by diffusion. . Therefore,
Gettering depends on the processing temperature, and the higher the temperature, the shorter the gettering.

When the treatment of irradiating strong light is used, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but it is instantaneously 600 to 1000 ° C., preferably 700 to 75 ° C.
The semiconductor film is heated to about 0 ° C.

When heat treatment is performed, heat treatment may be performed at 450 to 800 ° C. for 1 to 24 hours, for example, 550 ° C. for 14 hours in a nitrogen atmosphere. In addition to the heat treatment, strong light may be irradiated.

Next, the barrier layer 15 is etched by an etching stopper.
Select only the second semiconductor film indicated by 16 as a par
And then removing the barrier layer 15 to remove the first semiconductor film.
16 using a known patterning technique.
The conductor layer 17 is formed. (FIG. 1F) Second semiconductor film
As a method of selectively etching only ClF, ClF ₃
Dry etching without plasma or
Drazine and tetraethylammonium hydroxide
Id (chemical formula (CH₃)_FourAqueous solution containing (NOH)
Can be performed by wet etching with Lucari solution
It In addition, after removing the second semiconductor film, the surface of the barrier layer is removed.
Nickel concentration on the surface was measured by TXRF.
The barrier layer should be removed because the
Should be removed with an etchant containing hydrofluoric acid.
Good. Also, after removing the barrier layer, remove the resist
A thin oxide film on the surface with ozone water before forming the mask.
Is preferably formed.

Then, after cleaning the surface of the semiconductor layer with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component to form the gate insulating film 18 is formed. It is desirable that the surface cleaning and the formation of the gate insulating film be continuously performed without exposing to the atmosphere.

Next, after cleaning the surface of the gate insulating film 18, the gate electrode 19 is formed. Then, in the semiconductor
A source region 20 and a drain region 21 are added by appropriately adding an impurity element imparting a type (P, As, etc.), here phosphorus.
To form. After the addition, heat treatment, strong light irradiation, or laser light irradiation is performed to activate the impurity element. At the same time as activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. Especially room temperature to 300
It is very effective to activate the impurity element by irradiating the second harmonic wave of the YAG laser from the front surface or the back surface in the atmosphere of ° C. The YAG laser is a preferable activation means because it requires less maintenance.

In the subsequent steps, the interlayer insulating film 23 is formed,
Hydrogenation is performed to form a contact hole reaching the source region and the drain region, and a source electrode 24 and a drain electrode 25 are formed to complete a TFT (n-channel TFT). (Fig. 1 (G))

The concentration of the metal element contained in the channel formation region 22 of the TFT thus obtained is 1 × 10 ¹⁷ / cm ^3.
It can be less than.

The present invention is not limited to the TFT structure of FIG. 1G, and if necessary, a low concentration drain (LDD: LDD: LDD region) between the channel forming region and the drain region (or source region). Lightly Doped Drain) structure. In this structure, a region where an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region which is formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Furthermore, a so-called GOLD (Gate-drain) is formed in which the LDD region is arranged so as to overlap the gate electrode via a gate insulating film.
Overlapped LDD) structure.

Although an n-channel TFT is used here, it is needless to say that a p-channel TFT can be formed by using a p-type impurity element instead of the n-type impurity element.

Although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure, for example, a bottom gate type (inverse stagger type) TFT or a forward stagger type TFT. It is possible to apply.

Embodiment Mode 2 Here, an example is shown in which a semiconductor film containing the rare gas element and nitrogen of the present invention and having an amorphous structure is used as an active layer of a TFT.

First, a gate electrode is formed on a substrate having an insulating surface, a gate insulating film is formed to cover the gate electrode, and the rare gas element and nitrogen of the present invention are contained on the gate insulating film. A first semiconductor film having a crystalline structure is formed. Here, by using monosilane, argon, and nitrogen as raw material gases, argon is 1 × 10 ¹⁸
/ Cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰
The first semiconductor film which has a concentration of / cm ³ to 1 × 10 ²¹ / cm ³ and has an amorphous structure can be formed by a plasma CVD method. Next, a second semiconductor film containing an impurity element of one conductivity type (n type or p type) is stacked. Then, unnecessary portions of the first semiconductor film having an amorphous structure other than the portion to be the active layer are removed by etching. Then, after forming a conductive film of a conductive material over the entire surface, a part of the conductive film and the second semiconductor film containing an impurity element of one conductivity type (n-type or p-type) are removed to obtain a semiconductor. A source region and a drain region made of a film are formed, and at the same time, a drain wiring and a source wiring made of a conductive film are also formed. Further, a part of the first semiconductor film is removed to manufacture a channel-etch type bottom gate structure TFT. This TFT
If a pixel electrode is provided in the pixel, it can be used as a TFT in a pixel portion in a liquid crystal display device.

The present invention also relates to amorphous silicon T
The invention is not limited to the above TFT called FT, but can be applied to the active layer of a TFT called polysilicon TFT.

In that case, the first semiconductor film 12 having an amorphous structure provided over the base insulating film described in Embodiment 1 contains the rare gas element and nitrogen of the present invention and has an amorphous structure. The first semiconductor film which is included is used. Then, crystallization is performed by a crystallization technique (a solid phase growth method, a laser crystallization method, a solid phase growth method by a heat treatment using a metal element as a catalyst, etc.) to form a semiconductor having a crystalline structure, and the TFT is patterned. Of the active layer. Here, by using monosilane, argon, and nitrogen as raw material gases, argon is added at 1 × 10 ¹⁸ / cm ³ to 1 × 10 ^22.
/ Cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm
^A first semiconductor film which has a concentration of ³ and has an amorphous structure can be formed by a plasma CVD method.

For example, when performing laser crystallization, after the first semiconductor film containing the rare gas element and nitrogen of the present invention and having an amorphous structure is formed on a substrate having an insulating surface, the laser is used. Crystallize.

The laser light used is a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, etc. Can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when the pulse oscillation type excimer laser is used, the pulse oscillation frequency is 30
Hz and the laser energy density is 100 to 400 mJ
/ cm ² (typically 200 to 300 mJ / cm ² ). Also,
When using a pulse oscillation type YAG laser or YVO ₄ laser, the pulse oscillation frequency is set to 1 to 10 kHz by using the second harmonic or the third harmonic, and the laser energy density is 300 to 600 mJ / cm ² (typically 350-5
00mJ / cm ² ) is recommended. And width 100-1000
Laser light focused in a linear shape with a thickness of, for example, 400 μm may be irradiated over the entire surface of the substrate, and the overlapping ratio of the linear laser light at this time may be set to 80 to 98%.

In addition, YVO_FourContinuous generation represented by laser
When using a vibration type laser, continuous oscillation with an output of 10 W
YVO_FourA laser beam emitted from a laser is used as a nonlinear optical element.
Converts to higher harmonics (2nd to 4th harmonics)
It In the resonator, YVO _FourCrystals and nonlinear optical elements
There is also a method of putting in and emitting a higher harmonic wave. And preferred
Or, if the irradiation surface is rectangular or elliptical,
It is shaped into a laser beam and irradiated onto the object to be processed. At this time
Energy density is 0.01-100 MW / cm²degree
(Preferably 0.1-10 MW / cm²) Is required
It Then, it is recorded at a speed of about 0.5 to 2000 cm / s.
The semiconductor film relative to the laser light
Good.

(Embodiment 3) Further, the semiconductor film of the present invention containing a rare gas element and nitrogen and having an amorphous structure is formed into a substrate and an element such as a TFT after forming each element on the substrate. When separated, it can also be used as a layer (peeling layer) in which a peeling phenomenon occurs in the layer or at the interface due to etching treatment or laser irradiation. The peeling layer is provided in contact with the substrate, and the insulating film and the TF are provided on the peeling layer.
Form T.

Further, since the semiconductor film containing the rare gas element and nitrogen of the present invention and having an amorphous structure has a different etching rate as compared with the conventional semiconductor film having an amorphous structure, various etchings are performed. It can be used as an etching stopper in the process.

Further, the semiconductor film containing a rare gas element of the present invention and having an amorphous structure is a semiconductor film crystallized by a method different from the method described in the first embodiment, and other general films. It can also be used as a gettering site for a typical semiconductor film and a gettering site for a semiconductor substrate.

The present invention having the above structure will be described in more detail with reference to the following examples.

(Example) [Example 1] An example of the present invention will be described with reference to Figs. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail.

First, the base insulating film 101 is formed on the substrate 100 to obtain a first semiconductor film having a crystal structure, and then the semiconductor layers 102 to 106 separated into islands by etching into a desired shape. To form.

As the substrate 100, a glass substrate (# 17
37) and plasma C is used as the base insulating film 101.
By the VD method, the film formation temperature is 400 ° C., the source gases SiH ₄ , NH ₃ ,
Silicon oxynitride film 101a made of N ₂ O (composition ratio Si = 32%, O = 27%, N = 24%, H = 17
%) Is formed to 50 nm (preferably 10 to 200 nm).
Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (diluted by 1/100). Then, the film formation temperature is 400 ° C. by the plasma CVD method, and the source gas is SiH ₄ , N ₂
A silicon oxynitride film 101b made of O (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) was used as 1
A semiconductor film having an amorphous structure (here, amorphous) is formed by laminating a film having a thickness of 00 nm (preferably 50 to 200 nm) and forming the film by a plasma CVD method at a film forming temperature of 300 ° C. and a film forming gas SiH ₄ without exposing to the atmosphere. Silicon film) 54 nm
Is formed (preferably 25 to 80 nm).

Although the base film 101 has a two-layer structure in this embodiment, it may have a single-layer structure of the insulating film or a structure in which two or more layers are laminated. The material of the semiconductor film is not limited, but preferably silicon or silicon germanium (Si _1-x Ge _x (X = 0.0001 to 0.0
2)) Using alloys or the like, known means (sputtering method, LP
It may be formed by a CVD method, a plasma CVD method, or the like. Further, the plasma CVD apparatus may be a single wafer type apparatus or a batch type apparatus. Alternatively, the base insulating film and the semiconductor film may be successively formed in the same film formation chamber without exposure to the air.

After cleaning the surface of the semiconductor film having an amorphous structure, an extremely thin oxide film of about 2 nm is formed on the surface with ozone water. Next, a slight amount of impurity element (boron or phosphorus) is doped to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used, the doping condition is an acceleration voltage of 15 kV, and diborane is hydrogen at 1%.
Flow rate of diluted gas to 30 sccm, dose amount 2 × 10 ¹²
Boron was added to the amorphous silicon film at a rate of / cm ² .

Then, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Instead of coating, a method of spattering nickel element over the entire surface by a sputtering method may be used.

Next, heat treatment is performed to crystallize the semiconductor film having a crystal structure. For this heat treatment, heat treatment of an electric furnace or irradiation of strong light may be used. When it is performed by heat treatment in an electric furnace, it is 4 to 24 at 500 to 650 ° C
You can do it in time. Here, after the heat treatment for dehydrogenation (500 ° C., 1 hour), the heat treatment for crystallization (5
50 ° C., 4 hours) to obtain a silicon film having a crystal structure. Note that here, although crystallization is performed by heat treatment using a furnace, crystallization may be performed by a lamp annealing apparatus. Although a crystallization technique using nickel as a metal element that promotes crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, the crystallization rate is increased,
Irradiation with the first laser light (XeCl: wavelength 308 nm) for repairing defects left in crystal grains is performed in the air or an oxygen atmosphere. Laser light has a wavelength of 400 nm
The following excimer laser light and the second and third harmonics of a YAG laser are used. In any case, using pulsed laser light with a repetition frequency of about 10 to 1000 Hz,
The laser light may be focused at 100 to 500 mJ / cm ² by an optical system and irradiated with an overlap rate of 90 to 95% to scan the surface of the silicon film. Here, irradiation with the first laser light is performed in the atmosphere with a repetition frequency of 30 Hz and an energy density of 393 mJ / cm ² . Since it is performed in the air or an oxygen atmosphere, an oxide film is formed on the surface by irradiation with the first laser light.

Next, after removing the oxide film formed by the irradiation of the first laser light with dilute hydrofluoric acid, the irradiation of the second laser light is performed in a nitrogen atmosphere or in a vacuum to flatten the surface of the semiconductor film. To do. This laser light (second laser light) is an excimer laser light with a wavelength of 400 nm or less, or Y
The second and third harmonics of the AG laser are used. Second
The energy density of the laser light is larger than that of the first laser light, and preferably 30 to 60 m.
Increase J / cm ² . Here, the repetition frequency 30
Irradiation with the second laser beam was performed at a frequency of Hz and an energy density of 453 mJ / cm ² , and the PV value (Peak to Valley, the difference between the maximum height and the minimum height) of the unevenness on the semiconductor film surface was 5
It becomes 0 nm or less. This PV value is obtained by AFM (atomic force microscope).

Although the second laser beam is applied to the entire surface in this embodiment, the OFF current can be reduced by changing the TF of the pixel portion.
Since T is particularly effective, at least the pixel portion may be selectively irradiated.

In this embodiment, the example of irradiating the second laser beam to flatten the surface is shown, but it is not necessary to perform the planarization.

Then, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm.

Next, an amorphous silicon film containing an argon element, which becomes a gettering site, is formed on the barrier layer by the plasma CVD method shown in the first embodiment to a thickness of 150 nm.
To form. The film formation conditions by the plasma CVD method of the present embodiment are as follows: substrate temperature is 300 ° C., pressure in the chamber is 26.66 Pa (0.2 Torr), SiH ₄ gas is introduced into the chamber from a gas introduction system at a flow rate of 100 sccm and argon. Gas flow rate 500sccm, nitrogen gas 200sc
Introduced in cm, and discharged from a high frequency power source at a discharge frequency of 27.12 MHz and an input RF power of 300 W (RF power density 0.5 W / cm ² ). The atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ , and the atomic concentration of nitrogen is 1 × 10 ²⁰ / cm ³ to 1 x 10 ²¹ / cm ³
Is. Then, using a lamp annealing device, 650
Gettering is performed by heat treatment at 3 ° C. for 3 minutes.

Then, the barrier layer is used as an etching stopper to selectively remove the amorphous silicon film containing the argon element which is the gettering site, and then the barrier layer is selectively removed with dilute hydrofluoric acid. In addition, at the time of gettering,
Since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also referred to as a polysilicon film), a mask made of a resist is formed, and an etching treatment is performed into a desired shape. The semiconductor layers 102 to 106 separated into islands are formed. After forming the semiconductor layer, the resist mask is removed.

Then, after removing the oxide film with an etchant containing hydrofluoric acid, the surface of the silicon film is washed at the same time.
An insulating film containing silicon as its main component is formed to be the gate insulating film 107. In this embodiment, 11 is formed by the plasma CVD method.
A silicon oxynitride film with a thickness of 5 nm (composition ratio Si = 32
%, O = 59%, N = 7%, H = 2%).

Next, as shown in FIG. 8A, a first conductive film 108a having a film thickness of 20 to 100 nm and a second conductive film 1 having a film thickness of 100 to 400 nm are formed on the gate insulating film 107.
08b is formed by stacking. In this embodiment, a tantalum nitride film having a thickness of 50 nm and a thickness of 370 are formed on the gate insulating film 107.
nm tungsten films are sequentially stacked.

As the conductive material for forming the first conductive film and the second conductive film, Ta, W, Ti, Mo, Al, Cu
It is formed of an element selected from the above or an alloy material or a compound material containing the above element as a main component. A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus as the first conductive film and the second conductive film,
You may use AgPdCu alloy. Further, the structure is not limited to the two-layer structure.
A three-layer structure in which a Si) film and a titanium nitride film having a film thickness of 30 nm are sequentially laminated may be used. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum may be used instead of the aluminum-silicon alloy (Al-Si) film of the second conductive film. An alloy film of titanium (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.
Further, it may have a single layer structure.

Next, as shown in FIG. 8B, masks 110 to 115 made of resist are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. ICP (In
It is advisable to use an inductively coupled plasma etching method. Using ICP etching method,
Etching conditions (electric power applied to the coil type electrode,
By appropriately adjusting the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc., the film can be etched into a desired tapered shape. As the etching gas, chlorine-based gas represented by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like or CF ₄ , SF ₆ , NF _{3 is used.}
A fluorine-based gas typified by, for example, or O ₂ can be appropriately used.

In this embodiment, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching condition so that the end portion of the first conductive layer is tapered. The etching rate for W under the first etching condition is 200.39 nm / m
Etching rate for in and TaN is 80.32 nm
/ Min, and the selection ratio of W to TaN is about 2.5.
Is. In addition, depending on the first etching condition, W
The taper angle of is about 26 °. Thereafter, the masks 110 to 115 made of resist are not removed, and the second etching condition is changed to CF ₄ and Cl _{2 as} etching gas, and the gas flow rate ratio of each is 30/30 (sccm).
With a pressure of 1 Pa, RF (1 W
(3.56 MHz) Power was applied to generate plasma and etching was performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, Ta
The etching rate for N is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made suitable,
The edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 °.

Thus, the first shape conductive layers 117 to 122 (first conductive layers 117a to 122a and second conductive layer 117b) formed of the first conductive layer and the second conductive layer are formed by the first etching process. ~ 122b) are formed. The insulating film 107 serving as a gate insulating film is etched by about 10 to 20 nm, and becomes a gate insulating film 116 in which a region which is not covered with the first shape conductive layers 117 to 122 is thinned.

Next, a second etching process is performed without removing the resist mask. (FIG. 8 (C)) Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the gas flow rate ratio of each gas is 24/12/24 (scc).
m) and 700 W on the coil type electrode at a pressure of 1.3 Pa
RF (13.56 MHz) power was applied to generate plasma, and etching was performed for 25 seconds. RF (13.56 MHz) power of 10 W is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 227.3 nm / mi.
Etching rate for n and TaN is 32.1 nm / m
in, the selection ratio of W to TaN is 7.1, the etching rate of SiON that is the insulating film 116 is 33.7 nm / min, and W to SiON is W.
The selection ratio is 6.83. As described above, when SF ₆ is used as the etching gas, the selection ratio with the insulating film 116 is high, so that film loss can be suppressed. In this embodiment, the insulating film 116 is reduced in thickness by about 8 nm.

The taper angle of W became 70 ° by this second etching treatment. By this second etching process, second conductive layers 124b to 129b are formed. On the other hand, the first conductive layer is hardly etched,
Of the conductive layers 124a to 129a. Note that the first conductive layers 124a to 129a are the first conductive layers 117a to 12a.
It is almost the same size as 2a. Actually, the width of the first conductive layer is about 0.3 μm as compared with that before the second etching process.
In some cases, the line width may recede by about 0.6 μm, but there is almost no change in size. Further, in FIGS. 8B and 8C, the lengths of the tapered portions of the first conductive layer are illustrated as being the same, but in reality, there is a dependence on the wiring width. The length of the tapered portion of the first conductive layer changes.

Further, instead of the two-layer structure, a three-layer structure in which a tungsten film with a film thickness of 50 nm, an alloy of aluminum and silicon (Al-Si) film with a film thickness of 500 nm, and a titanium nitride film with a film thickness of 30 nm are sequentially laminated is provided. In this case, as the first etching condition of the first etching process, BCl ₃ , Cl ₂ and O ₂ are used as source gases, and the gas flow rate ratio of each is set to 65/10/5 (sccm). The RF power (13.56 MHz) of 300 W is applied to the (sample stage), and the RF power (13.56 MHz) of 450 W is applied to the coil-shaped electrode at a pressure of 1.2 Pa to generate plasma for 117 seconds. Etching may be performed. As the second etching condition of the first etching process, CF ₄ , Cl _2, and O ₂ are used, and the gas flow rate ratio of each is 25/2.
5/10 (sccm), 20W of RF (13.56MHz) power was also applied to the substrate side (sample stage),
RF of 500 W (13.
56MHz) Power is generated and plasma is generated for about 30
It suffices to perform the etching for about a second. BCl ₃ and Cl ₂ are used for the second etching treatment, and the gas flow rate ratio of each is set to 20/60 (sccm) and the substrate side (sample stage)
RF (13.56 MHz) power of 100 W is applied to the coil, and a pressure of 1.2 Pa is applied to the coil-shaped electrode to generate R of 600 W.
It suffices to apply F (13.56 MHz) power to generate plasma and perform etching.

Next, after removing the resist mask, the first doping process is performed to obtain the state of FIG. The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60.
~ 100 keV. Phosphorus (P) or arsenic (As) is typically used as the impurity element imparting n-type. In this case, the first conductive layer and the second conductive layer 124
~ 128 serves as a mask for the impurity element imparting n-type, and the first impurity regions 130 to 134 are formed in a self-aligned manner. 1 × in the first impurity regions 130 to 134
An impurity element imparting n-type is added within a concentration range of 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the first impurity region is also called an n ⁻ region.

Although the first doping process is performed after removing the resist mask in this embodiment, the first doping process may be performed without removing the resist mask. Further, in FIG. 8D, for convenience, the length of the tapered portion of the first conductive layer is illustrated as being the same, but in reality, the length of the tapered portion of the first conductive layer changes depending on the wiring width. ing. Therefore, when a plurality of wirings having different wiring widths are provided on the same substrate, the widths of the doped regions also differ.

Next, as shown in FIG. 9A, masks 135 to 137 made of resist are formed and a second doping process is performed. A mask 135 is a mask that protects a channel formation region of a semiconductor layer forming a p-channel TFT of a drive circuit and a peripheral region thereof, and a mask 136 is a semiconductor layer forming one of n-channel TFTs of the drive circuit. The mask is a mask that protects the channel formation region and its peripheral region, and the mask 137 is a mask that protects the channel formation region of the semiconductor layer forming the TFT of the pixel portion, the peripheral region thereof, and the region serving as the storage capacitor.

The condition of the ion doping method in the second doping process is that the dose amount is 1.5 × 10 ¹⁵ atoms / cm ² and the accelerating voltage is 60 to 100 keV, and phosphorus (P) is doped. Here, the second conductive layers 124 b to 1
Impurity regions are formed in each semiconductor layer in a self-aligned manner using 26b as a mask. Of course, it is not added to the region covered with the masks 135 to 137. Thus, the second impurity regions 138 to 140, 169 and the third impurity region 142.
Is formed. Second impurity regions 138-140, 16
9 is doped with an impurity element imparting n-type in the concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, the second
The region having the same concentration range as the impurity region of is also called an n ⁺ region.

Further, the third impurity region is formed at a lower concentration than the second impurity region by the first conductive layer, and has a concentration of 1 × 1.
An impurity element imparting n-type is added in the concentration range of 0 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end portion of the tapered portion because doping is performed by passing through the portion of the first conductive layer having a tapered shape. . Here, a region having the same concentration range as the third impurity region is also called an n ⁻ region. Further, in the region covered with the masks 136 and 137, the impurity element is not added in the second doping treatment,
The first impurity regions 144 and 145 are formed.

Next, the masks 135 made of resist are formed.
After removing 137, a mask 1 newly made of resist
46 to 148 are formed and a third doping process is performed as shown in FIG.

In the drive circuit, by the third doping process, a fourth impurity element imparting p-type conductivity is added to the semiconductor layer forming the p-channel TFT and the semiconductor layer forming the storage capacitor. Impurity region 149,
150 and fifth impurity regions 151 and 152 are formed.

Further, in the fourth impurity regions 149 and 150,
Is 1 × 10²⁰~ 1 x 10^{twenty one}/cm³P-type in the concentration range of
The impurity element to be added is added. In addition, the fourth failure
Phosphorus (P) was added to the pure regions 149 and 150 in the previous step.
Added region (n^-Region), but the
Conductive because the concentration of pure element is 1.5 to 3 times that of pure element
The mold is p-type. Here, the fourth impurity region and
P in the same concentration range ⁺Also called a region.

The fifth impurity regions 151 and 152 are formed in a region overlapping the tapered portion of the second conductive layer 125a, and have a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. An impurity element imparting p-type is added. Here, a region having the same concentration range as the fifth impurity region is also called ap ⁻ region.

By the steps up to this point, each semiconductor layer is n-doped.
An impurity region having a conductivity type of p-type or p-type is formed. The conductive layers 124 to 127 become gate electrodes of the TFT. In addition, the conductive layer 128 serves as one electrode which forms a storage capacitor in the pixel portion. Further, the conductive layer 129 forms a source wiring in the pixel portion.

Further, as long as the conductive layers 124 to 127 and the impurity regions (first impurity region to fifth impurity region) can be formed, the above process order is not particularly limited, and each etching order and each doping order are appropriately set. You may change it.

Next, an insulating film (not shown) is formed to cover almost the entire surface. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed by the plasma CVD method. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating the back surface with a YAG laser or an excimer laser, a heat treatment using a furnace, or a combination of these methods. By the method.

In this embodiment, an example in which the insulating film is formed before the activation is shown, but after the activation is performed,
It may be a step of forming an insulating film.

Then, a first interlayer insulating film 153 made of a silicon nitride film is formed and heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed to hydrogenate the semiconductor layer. (FIG. 9C) This step is a step of terminating the dangling bond of the semiconductor layer by hydrogen contained in the first interlayer insulating film 153. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as the main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation.

Next, a second interlayer insulating film 154 made of an organic insulating material is formed on the first interlayer insulating film 153. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 129, a contact hole reaching the conductive layers 127 and 128, and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed.
In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using an insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).

After that, wirings and pixel electrodes are formed using Al, Ti, Mo, W or the like. As a material of these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component, or a laminated film thereof. Thus, the source or drain electrodes 155 to 160, the gate wiring 162, the connection wiring 161,
The pixel electrode 163 is formed.

As described above, the n-channel TFT 20
1, p-channel TFT 202, n-channel TFT 2
The pixel portion 207 including the driver circuit 206 including the pixel 03, the pixel TFT 204 including the n-channel TFT, and the storage capacitor 205 can be formed over the same substrate. (FIG. 10) In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the pixel portion 207, the pixel TFT 204
The (n-channel TFT) has a channel forming region 167,
A first impurity region (n ⁻ region) 145 formed outside the conductive layer 127 forming the gate electrode and a second impurity region (n ⁻ ) functioning as a source region or a drain region.
⁺ Area) 140, 169. Further, a fourth impurity region 150 and a fifth impurity region 152 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 205. The storage capacitor 205 is formed of the second electrode 128 and the semiconductor layers 150, 152, 168 using the insulating film (the same film as the gate insulating film) 116 as a dielectric.

In the drive circuit 206, the n-channel TFT 201 (first n-channel TFT) is the channel formation region 164 and the conductive layer 12 forming the gate electrode.
4 and a third impurity region (n
^- has a second impurity region (n ⁺ region) 138 functioning as a region) 142 and a source region or a drain region.

In the drive circuit 206, the p-channel TFT 202 has a channel formation region 165 and a fifth impurity region (p ⁻ region) 151 overlapping a part of the conductive layer 125 forming the gate electrode with an insulating film interposed therebetween. A fourth impurity region (p
⁺ Area) 149.

In the drive circuit 206, the n-channel TFT 203 (second n-channel TFT) has the channel forming region 166 and the conductive layer 1 forming the gate electrode.
A first impurity region (n ⁻ region) 144 and a second impurity region (n ⁺ region) 139 functioning as a source region or a drain region are provided outside 26.

A drive register 206 may be formed by appropriately combining these TFTs 201 to 203 to form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit and the like. For example, when forming a CMOS circuit, an n-channel TFT 201 and a p-channel TFT
It may be formed by connecting 202 complementarily.

In particular, for a buffer circuit having a high driving voltage,
The structure of the n-channel TFT 203 is suitable for the purpose of preventing deterioration due to the hot carrier effect.

Further, for a circuit in which reliability is given the highest priority,
The structure of the n-channel TFT 201 having the GOLD structure is suitable.

Since the reliability can be improved by improving the flatness of the surface of the semiconductor film, G
In the TFT having the OLD structure, sufficient reliability can be obtained even if the area of the impurity region overlapping the gate electrode and the gate insulating film is reduced. Specifically, in the GOLD structure TFT, sufficient reliability can be obtained even if the size of the gate electrode tapered portion is reduced.

Further, in the GOLD structure TFT, the parasitic capacitance increases as the gate insulating film becomes thinner. However, if the size of the tapered portion of the gate electrode (first conductive layer) is reduced to reduce the parasitic capacitance, The f-characteristics are also improved, the higher speed operation is possible, and the TFT has sufficient reliability.

Also in the pixel TFT of the pixel portion 207, the reduction of the off current and the variation can be realized by the irradiation of the second laser light.

In this embodiment, an example of manufacturing an active matrix substrate for forming a reflection type display device is shown. However, when the pixel electrode is formed of a transparent conductive film, the number of photomasks is increased by one, but the transmission is increased. Mold display device can be formed.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 11 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 10, an alignment film is formed on the active matrix substrate of FIG. 10 and rubbing treatment is performed. In this embodiment, before forming the alignment film, the organic resin film such as the acrylic resin film was patterned to form the columnar spacers for holding the substrate distance at desired positions. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light-shielding layer was also provided in the drive circuit portion. A flattening film was provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film was formed on the flattening film in the pixel portion, an alignment film was formed on the entire surface of the counter substrate, and a rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. After that, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate and the like are appropriately provided by using a known technique. Then, the FPC was attached using a known technique.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

A pixel portion 304 is arranged in the center of the active matrix substrate 301. A source signal line driver circuit 302 for driving a source signal line is arranged above the pixel portion 304. A gate signal line driver circuit 303 for driving a gate signal line is arranged on the left and right of the pixel portion 304. In the example shown in this embodiment,
Although the gate signal line driving circuit 303 is arranged symmetrically with respect to the pixel portion, it may be arranged on only one side and may be appropriately selected by the designer in consideration of the substrate size of the liquid crystal module and the like. However, considering the operational reliability of the circuit, the driving efficiency, etc., the symmetrical arrangement shown in FIG. 11 is desirable.

Input of a signal to each drive circuit is performed by a flexible printed circuit (FPC) 3
It starts from 05. The FPC 305 opens contact holes in the interlayer insulating film and the resin film so as to reach the wirings arranged up to a predetermined position on the substrate 301, forms connection electrodes, and then is pressure-bonded through an anisotropic conductive film or the like. It In this embodiment, the connection electrode is made of ITO.

A sealant 307 is applied to the periphery of the driving circuit and the pixel portion along the outer periphery of the substrate, and a constant gap is formed by a spacer previously formed on the active matrix substrate (a gap between the substrate 301 and the counter substrate 306). The counter substrate 306 is attached while maintaining After that, a liquid crystal element is injected from a portion where the sealant 307 is not applied and is sealed with a sealant 308. The liquid crystal module is completed through the above steps.

Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuits.

Further, this embodiment can be freely combined with the first embodiment.

[Embodiment 3] In the embodiment 1, the example of the reflection type display device in which the pixel electrode is formed of the metal material having the reflectivity is shown, but in the present embodiment, the pixel electrode is made of the conductive material having the light transmitting property. An example of a transmissive display device formed of a film is shown.

Example 1 is performed up to the step of forming the interlayer insulating film.
Since it is the same as, it is omitted here. After the interlayer insulating film is formed according to Example 1, the pixel electrode 601 made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium oxide-tin oxide alloy), indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

After that, a contact hole is formed in the interlayer insulating film 600. Next, the connection electrode 6 overlapping the pixel electrode
02 is formed. The connection electrode 602 is connected to the drain region through a contact hole. At the same time as the connection electrode, the source electrode or drain electrode of another TFT is also formed.

Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuits.

The active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module was manufactured according to Example 2, provided with a backlight 604 and a light guide plate 605, and covered with a cover 606, an active matrix type as shown in a part of its sectional view in FIG. The liquid crystal display device is completed. The cover and the liquid crystal module are attached to each other with an adhesive or an organic resin. When the substrate and the counter substrate are attached to each other, they may be surrounded by a frame and filled with an organic resin between the frame and the substrate for adhesion. Since it is a transmissive type, the polarizing plate 603 is attached to both the active matrix substrate and the counter substrate.

Further, this embodiment can be freely combined with the first embodiment or the second embodiment.

[Embodiment 4] In this embodiment, EL (Electr
FIG. 13 shows an example of manufacturing a light emitting display device including an o Luminescence) element.

FIG. 13A is a top view showing the EL module, and FIG. 13B is a sectional view taken along the line AA ′ in FIG. 13A. A substrate 900 having an insulating surface (eg, a glass substrate, a crystallized glass substrate, a plastic substrate, or the like) is provided with a pixel portion 902 and a source side driver circuit 90.
1 and the gate side driving circuit 903 are formed. These pixel portion and drive circuit can be obtained according to the above-described embodiment. Further, reference numeral 918 denotes a seal material, and 919 denotes a DLC film. The pixel portion and the driving circuit portion are covered with the seal material 918, and the seal material is covered with the protective film 919. Further, it is sealed with a cover material 920 using an adhesive material.
The cover material 920 is preferably made of the same material as the substrate 900, for example, a glass substrate in order to withstand deformation due to heat or external force.
Processed into the concave shape (depth 3 to 10 μm) shown in FIG. Recesses that can be further processed to set the desiccant 921 (depth of 50-
200 μm) is desirable. Further, in the case of manufacturing an EL module by multi-chambering, the substrate and the cover material may be bonded together and then cut using a CO ₂ laser or the like so that the end faces are aligned.

Reference numeral 908 denotes a wiring for transmitting a signal input to the source side driving circuit 901 and the gate side driving circuit 903, and a video signal or a clock signal from an FPC (flexible printed circuit) 909 which is an external input terminal. To receive. Although only the FPC is shown here, a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device main body but also the FPC.
Alternatively, the state in which the PWB is attached is also included.

Next, the sectional structure will be described with reference to FIG. An insulating film 910 is provided over a substrate 900, a pixel portion 902 and a gate side driver circuit 903 are formed above the insulating film 910, and the pixel portion 902 is electrically connected to a current control TFT 911 and its drain. And a plurality of pixels including the pixel electrode 912. The gate side drive circuit 903 is an n-channel TFT 91.
CMO combining 3 and p-channel TFT 714
It is formed using an S circuit.

These TFTs (911, 913, 914)
Is included in the n-channel TFT 20 of the first embodiment.
1. It may be manufactured according to the p-channel TFT 202 of the first embodiment.

The insulating film provided between the TFT and the EL element not only blocks diffusion of impurity ions such as alkali metal ions and alkaline earth metal ions, but also
A material that positively adsorbs impurity ions such as alkali metal ions and alkaline earth metal ions is preferable, and a material that can withstand the subsequent process temperature is suitable. As an example of a material satisfying these conditions, a silicon nitride film containing a large amount of fluorine can be given. The concentration of fluorine contained in the silicon nitride film is 1 × 10 ¹⁹ / cm ³ or more, and preferably the composition ratio of fluorine in the silicon nitride film is 1 to 5%. Fluorine in the silicon nitride film is combined with alkali metal ions, alkaline earth metal ions, etc. and adsorbed in the film. As another example, an antimony (Sb) compound that adsorbs an alkali metal ion, an alkaline earth metal ion, or the like,
An organic resin film containing fine particles of a tin (Sn) compound or an indium (In) compound, for example, an organic resin film containing fine particles of antimony pentoxide (Sb ₂ O ₅ .nH ₂ O) can also be mentioned. The organic resin film has an average particle size of 10
It contains fine particles of ˜20 nm and has a very high light transmittance. The antimony compound represented by the antimony pentoxide fine particles easily adsorbs impurity ions such as alkali metal ions and alkaline earth metal ions.

The pixel electrode 912 functions as an anode of a light emitting element (EL element). Further, banks 915 are formed on both ends of the pixel electrode 912, and an EL layer 916 and a cathode 917 of the light emitting element are formed on the pixel electrode 912.

As the EL layer 916, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer or a charge injection layer. For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used. Further, as the EL layer, a thin film formed of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film formed of a light emitting material (triplet compound) that emits light (phosphorescence) by triplet excitation can be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

The cathode 917 also functions as a wiring common to all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. Further, all elements included in the pixel portion 902 and the gate side driver circuit 903 are covered with the cathode 917, the sealant 918, and the protective film 919.

As the sealing material 918, it is preferable to use a material that is as transparent or semitransparent to visible light as possible. Further, it is desirable that the sealing material 918 be a material that does not allow moisture and oxygen to pass therethrough as much as possible.

After the light emitting element is completely covered with the sealing material 918, at least DL as shown in FIG.
A protective film 919 made of a C film or the like is preferably provided on the surface (exposed surface) of the sealing material 918. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to take care so that the protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may not be formed using a mask, or the external input terminal portion may be covered with a tape such as a masking tape used in a CVD apparatus so that the protective film is not formed.

The light emitting element having the above structure is used as the sealing material 9
By enclosing the light emitting element with the protective film 18 and the protective film, the light emitting element can be completely shielded from the outside, and a substance such as moisture or oxygen that promotes deterioration due to oxidation of the EL layer can be prevented from entering from the outside. Therefore, a highly reliable light emitting device can be obtained.

Further, the pixel electrode may be used as an anode, the EL layer and the transparent or semitransparent cathode may be laminated, and light may be emitted in the direction opposite to that shown in FIG. Alternatively, the pixel electrode may serve as a cathode and the EL layer and the anode may be stacked to emit light in a direction opposite to that in FIG. FIG. 14 shows an example thereof. In addition,
Since the top view is the same, it is omitted.

The sectional structure shown in FIG. 14 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used as well as a glass substrate or a quartz substrate. An insulating film 1010 is provided on the substrate 1000,
A pixel portion 1002 and a gate side driver circuit 1003 are formed above the insulating film 1010. The pixel portion 1002 is formed by a plurality of pixels including a current control TFT 1011 and a pixel electrode 1012 electrically connected to its drain. To be done. The gate side driver circuit 1003 is formed using a CMOS circuit in which an n-channel TFT 1013 and a p-channel TFT 1014 are combined. The current control TFT 1011 is preferably an n-channel TFT.

The pixel electrode 1012 functions as the cathode of the light emitting element. In addition, the bank 1 is provided at both ends of the pixel electrode 1012.
015 is formed, and the EL layer 10 is formed on the pixel electrode 1012.
16 and the anode 1017 of the light emitting element are formed.

The anode 1017 also functions as a wiring common to all pixels, and the FPC 1009 is connected via the connection wiring 1008.
Electrically connected to. Further, all elements included in the pixel portion 1002 and the gate side driver circuit 1003 are covered with an anode 1017, a sealant 1018, and a protective film 1019 made of DLC or the like. In addition, the cover material 1020
And the substrate 1000 were bonded together with an adhesive. In addition, a recess is provided in the cover material and a desiccant 1021 is placed therein.

As the sealant 1018, it is preferable to use a material that is as transparent or semitransparent to visible light as possible. Further, it is desirable that the sealing material 1018 be a material that does not allow moisture and oxygen to permeate as much as possible.

Further, in FIG. 14, the pixel electrode is used as a cathode,
Since the EL layer and the anode are laminated, the light emitting direction is the direction of the arrow shown in FIG.

In this example, since the TFT having high electric characteristics and high reliability obtained in Example 1 is used, it is possible to form a light emitting element having higher reliability than the conventional element. In addition, a high-performance electric appliance can be obtained by using a light-emitting device having such a light-emitting element as a display portion.

The present embodiment can be freely combined with the first embodiment.

[Embodiment 5] Various modules (active matrix type liquid crystal module, active matrix type EL) are formed in the driving circuit and the pixel portion formed by implementing the present invention.
Module, active matrix type EC module)
Can be used for. That is, by implementing the present invention, all electronic devices incorporating them are completed.

Examples of such electronic equipment include video cameras, digital cameras, head mounted displays (goggles type displays), car navigations, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.). ) And the like. Examples of these are shown in FIGS.

FIG. 15A shows a personal computer, which has a main body 2001, an image input section 2002, and a display section 20.
03, keyboard 2004 and the like.

FIG. 15B shows a video camera, which includes a main body 2101, a display portion 2102, a voice input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
Including 6 etc.

FIG. 15C shows a mobile computer (mobile computer), which includes a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, a display portion 2205, and the like.

FIG. 15D shows a goggle type display, which includes a main body 2301, a display portion 2302 and an arm portion 230.
Including 3 etc.

FIG. 15E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded, and has a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, operation switches 2405 and the like. This player uses a DVD (D
optical Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet.

FIG. 15F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown) and the like.

FIG. 16A shows a front type projector including a projection device 2601, a screen 2602 and the like. The third embodiment can be applied to the liquid crystal module 2808 forming a part of the projection device 2601 to complete the entire device.

FIG. 16B shows a rear type projector, which includes a main body 2701, a projection device 2702 and a mirror 270.
3, screen 2704 and the like. The third embodiment can be applied to the liquid crystal module 2808 forming a part of the projection device 2702 to complete the entire device.

Note that FIG. 16C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 16A and 16B. Projection device 2601, 27
02 is a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal module 2808, retardation plate 280.
9, a projection optical system 2810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, and an IR film in the optical path indicated by the arrow in FIG. 16C. Good.

FIG. 16D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 16C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813, and a lens array 2813.
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 16D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 16 shows a case where a transmissive electro-optical device is used, and an application example of a reflective electro-optical device and an EL module is not shown.

FIG. 17A shows a mobile phone, which has a main body 29.
01, voice output unit 2902, voice input unit 2903, display unit 2904, operation switch 2905, antenna 290
6. Image input unit (CCD, image sensor, etc.) 2907
Including etc.

FIG. 17B shows a portable book (electronic book) including a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006.
Including etc.

FIG. 17C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103 and the like.

By the way, the display shown in FIG. 17C is a medium-sized or large-sized display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate whose one side is 1 m and perform multi-chambering for mass production.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to the manufacturing methods of electronic devices in all fields. In addition, the electronic device of the present embodiment is
It can be realized by using any combination of four.

[0201]

According to the present invention, the film contains argon at a high concentration, specifically 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ , and the nitrogen concentration in the film is 1 x 10 ²⁰ / c
An amorphous silicon film having a m ³ to 1 × 10 ²¹ / cm ³ can be formed by a plasma CVD method.

Further, according to the present invention, it is possible to obtain a semiconductor film having a crystal structure in which a metal element which sufficiently promotes crystallization is reduced or removed, and the semiconductor film is used as an active layer.
In the FT, it is possible to improve electrical characteristics and reduce variations among individual elements. In particular, in a liquid crystal display device, display unevenness due to variations in TFT characteristics can be reduced.

In addition, in the semiconductor device having the OLED, the on-current (I) of the TFT (TFT that supplies current to the OLED arranged in the driving circuit or the pixel) arranged so that a constant current flows through the pixel electrode. It is possible to reduce the variation of ( _on ) and the variation of the luminance.

Further, according to the present invention, not only the metal element which promotes crystallization but also other metal elements (Fe, C
u) can also be removed or reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a TFT.

FIG. 2A is SIMS data showing an argon concentration, and FIG. 2B is SIMS data showing a fluorine concentration. (Experiment 1)

FIG. 3 (A) is SIMS data showing nitrogen concentration,
(B) SIMS data showing oxygen concentration. (Experiment 1)

FIG. 4A is SIMS data showing argon concentration, and FIG. 4B is SIMS data showing fluorine concentration (RF power dependence). (Experiment 2)

FIG. 5A is SIMS data showing nitrogen concentration,
(B) SIMS data showing oxygen concentration. (Experiment 2)

FIG. 6 SIMS data showing argon concentration (pressure dependence). (Experiment 3)

FIG. 7 (A) is SIMS data showing nitrogen concentration,
(B) SIMS data showing oxygen concentration. (Experiment 3)

FIG. 8 is a diagram showing a manufacturing process of an AM-LCD.

9A to 9C are diagrams illustrating a manufacturing process of an AM-LCD.

FIG. 10 is a sectional structural view of an active matrix substrate.

FIG. 11 is a diagram showing an external view of an AM-LCD.

FIG. 12 is a diagram showing a cross section of a transmissive LCD.

FIG. 13 illustrates a structure of an active matrix EL display device.

FIG. 14 illustrates a structure of an active matrix EL display device.

FIG. 15 illustrates examples of electronic devices.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates an example of an electronic device.

FIG. 18 is a diagram showing spectroscopic spectrum data by an FT-IR method.

FIG. 19 is a graph showing the argon concentration on the surface of the amorphous silicon film of the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 H01L 29/78 627Z (72) Inventor Hideto Onuma 398 Hase, Atsugi, Kanagawa Co., Ltd. Conductor Energy Laboratory (72) Inventor Masato Yonezawa 398 Hase, Atsugi City, Kanagawa Semi-conductor Energy Laboratory F Term (Reference) 2H092 JA24 JA28 KA04 KA05 MA28 NA24 5F045 AA08 AB04 AC00 AC01 AC16 AC17 AD07 AE19 BB14 CA15 5F052 AA02 AA11 AA17 AA24 BB02 BB03 BB04 BB05 BB07 CA02 DA02 DA03 DB02 DB03 DB07 EA16 FA06 FA19 JA01 5F110 AA01 AA06 AA16 AA30 BB02 BB04 CC02 CC05 CC07 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE15 EE23 EE28 FF04 FF12 FF30 FF35 GG01 GG02 GG13 GG25 GG32 GG33 GG34 GG43 GG45 GG47 GG51 GG58 HJ01 HJ04 HJ12 HJ13 HJ23 HL 03 HL04 HL06 HM13 HM15 NN03 NN04 NN23 NN24 NN27 NN35 NN72 NN73 NN78 PP01 PP02 PP03 PP04 PP05 PP06 PP10 PP13 PP29 PP34 PP35 PP38 QQ04 QQ09 QQ11 QQ19 QQ23 QQ25 QQ28

Claims (13)

[Claims] 1. A semiconductor film containing a rare gas element and nitrogen and having an amorphous structure is introduced onto a surface of a surface by introducing monosilane, a rare gas, and nitrogen as source gases into a film formation chamber to generate plasma. A method for manufacturing a semiconductor film having an amorphous structure, characterized in that the film is formed on. 2. The pressure in the film forming chamber at the time of generating the plasma according to claim 1, 2.666 Pa to 1
A method for manufacturing a semiconductor film having an amorphous structure, which has a pressure of 33.3 Pa. 3. The flow rate ratio of nitrogen to the rare gas (N ₂ / rare gas) according to claim 1 or 2, wherein
5. A method for manufacturing a semiconductor film having an amorphous structure, which is characterized by controlling to 5. 4. The RF power density for generating the plasma according to claim 1, wherein the RF power density is 0.001.
The method for manufacturing a semiconductor film having an amorphous structure, which is a ^{7W / cm 2 ~1W / cm 2} . 5. The semiconductor film according to claim 1, wherein the semiconductor film having an amorphous structure has 1 × 10 ¹⁸ / min in the film.
A method for manufacturing a semiconductor film having an amorphous structure, characterized in that nitrogen is contained at a concentration of cm ³ to 1 × 10 ²² / cm ³ . 6. The semiconductor film according to any one of claims 1 to 5, wherein the semiconductor film having an amorphous structure is 1 × 10 ¹⁸ / min.
A method for manufacturing a semiconductor film having an amorphous structure, characterized in that a rare gas element is contained at a concentration of cm ³ to 1 × 10 ²² / cm ³ . 7. The amorphous structure according to claim 1, wherein the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe. A method for manufacturing a semiconductor film having: 8. The flow rate ratio (SiH ₄ : rare gas) of the rare gas and the monosilane introduced into the film forming chamber is set to 0.1: 99.9 to 1: 9 according to any one of claims 1 to 7. A method for manufacturing a semiconductor film, characterized in that 9. The flow rate ratio (SiH ₄ : rare gas) of the rare gas and the monosilane introduced into the film forming chamber is controlled to be 1:99 to 5:95 according to any one of claims 1 to 7. A method for manufacturing a semiconductor film, comprising: 10. A film containing 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²⁰
1 × 10 ²⁰ containing a rare gas element at a concentration of / cm ³
/ Cm ³ to 1 × 10 ²¹ / cm ³ A semiconductor film having an amorphous structure, which contains nitrogen at a concentration of 1. 11. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystalline structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having a crystalline structure. A fifth step of forming a second semiconductor film containing a rare gas element and nitrogen on the barrier layer, and a first step having a crystal structure by gettering the metal element to the second semiconductor film. A method for manufacturing a semiconductor device, comprising: a sixth step of removing or reducing the metal element in the semiconductor film; and a seventh step of removing the second semiconductor film. 12. The method according to claim 11, wherein the second semiconductor film is formed by a plasma CVD method in which monosilane, a rare gas, and nitrogen are introduced as source gases into a film forming chamber and plasma is generated. Method for manufacturing a semiconductor device. 13. The method according to claim 11 or 12,
The metal elements are Fe, Ni, Co, Ru, Rh, Pd,
A method of manufacturing a semiconductor device, which is one or more selected from Os, Ir, Pt, Cu, and Au.