JP4176366B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
The material of the crystalline semiconductor film suitably used for the TFT is silicon. A silicon film having a crystalline structure (hereinafter referred to as a crystalline silicon film) is obtained by subjecting an amorphous silicon film deposited on a substrate such as glass or quartz to a heat treatment or a laser beam by a plasma CVD method or a low pressure CVD method. Those crystallized by irradiation (hereinafter referred to as laser treatment in the present specification) have been applied.
[0005]
[Problems to be solved by the invention]
However, the crystalline silicon film produced by the above-described conventional method has crystal orientation planes at random, and the orientation rate with respect to a specific crystal orientation is low. When the orientation rate is low, it is almost impossible to maintain the continuity of the lattice at the grain boundary where crystals of different orientations collide, and it can be estimated that many dangling bonds are formed. The unpaired bond that can be formed at the grain boundary becomes a trapping center for carriers (electrons and holes), which deteriorates the transport properties. That is, since carriers are scattered or trapped, a TFT having a high field effect mobility cannot be expected even if a TFT is manufactured using such a crystalline semiconductor film.
[0006]
Further, a silicon film having a crystal structure, that is, a polysilicon film, has many strains and defects. These act as carrier traps and deteriorate electrical characteristics. Therefore, even in the TFT channel formation region, the existence form of strain, the volume of lattice defects, and the like are one of the major causes of characteristic fluctuations.
[0007]
An object of the present invention is to provide a means for solving such problems, and to increase the orientation rate of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film and to reduce strain. An object of the present invention is to provide a TFT using a crystalline semiconductor film.
[0008]
[Means for Solving the Problems]
The present invention can increase the orientation rate of the film by crystallizing a rare gas, typically argon, in the semiconductor film during or after the formation of the amorphous semiconductor film, and Compared with before crystallization, strain present in the semiconductor film after crystallization is relieved.
[0009]
In the crystallization according to the present invention, a metal element that promotes crystallization of silicon is introduced, and a crystalline silicon film is formed by a heat treatment at a temperature lower than that in the past. Then, the rare gas in the film is removed or reduced by laser light irradiation performed later.
[0010]
The distribution of crystal orientation may be obtained by a backscattered electron diffraction pattern (EBSP). EBSP is a technique in which a scanning electron microscope (SEM: Scanning Electron Microscopy) is provided with a dedicated detector, and crystal orientation is analyzed from backscattering of primary electrons. When an electron beam is incident on a sample with a crystal structure, inelastic scattering occurs also in the back, including the linear pattern (generally called Kikuchi image) that is unique to the crystal orientation in the sample due to Bragg diffraction. Observed. The EBSP obtains the crystal orientation of the sample by analyzing the Kikuchi image reflected on the detector screen. By repeating the orientation analysis (mapping measurement) while moving the position where the electron beam hits the sample, information on the crystal orientation or orientation can be obtained for the planar sample. When all the crystal orientations of each crystal grain are obtained by mapping measurement, the crystal orientation state with respect to the film can be statistically displayed.
[0011]
The inventors conducted the following experiment.
[0012]
(Experiment)
First, a sample was prepared in which a base insulating film (a silicon oxynitride film, a film thickness of 150 nm) was formed over a glass substrate, and an amorphous silicon film with a film thickness of 54 nm was formed thereon by a plasma CVD method. Next, argon was added to the amorphous silicon film by ion doping. The ion doping conditions at this time are as follows: acceleration voltage is 30 kV, and dose is 2 × 10. ¹⁵ / Cm ² And the concentration of argon contained in the film is about 3 × 10 ²⁰ / Cm ^Three Was set to be. Next, after applying a solution containing 100 ppm of nickel in terms of weight, a heat treatment is performed at 500 ° C. for 1 hour, followed by further heat treatment at 600 ° C. for 8 hours to form a silicon film having a crystal structure. did. The distribution of crystal orientation in the silicon film having the crystal structure thus obtained was examined by EBSP.
[0013]
FIG. 14 shows a diagram of reverse poles obtained from EBSP. The reverse pole figure is often used to display the preferred orientation of a polycrystal, and it is a collective indication of which lattice plane a specific surface of the sample (here, the film surface) matches. It is. Note that the fan-shaped frame in FIG. 14 is generally called a standard triangle, and includes all indexes in the cubic system. In addition, the length in this figure corresponds to the angle in the crystal orientation. For example, 45 degrees between {001} and {101}, 35.26 degrees between {101} and {111}, and 54.74 degrees between {111} and {001}.
[0014]
FIG. 14 is a plot of all the measurement points in the mapping within a standard triangle. Since the density of points is high near {101} and {111}, a specific index (here, It can be seen that the preferential orientation is {101} and {111}).
[0015]
In this way, when it is found that a specific index is preferentially oriented, it is easier to imagine the degree of preferential orientation by quantifying the ratio of how many grains are gathered near that index. Become. In the inverse pole figure shown in FIG. 14, the ratio of the number of points existing in the range of the deviation angle of 10 degrees from {101} can be shown as the orientation rate.
[0016]
The orientation ratio obtained in this way is such that the ratio of the angle formed with the surface of the silicon film of the {101} plane detected by the backscattered electron diffraction pattern method is within 10 degrees is 16%, and the {111} plane The ratio of the angle formed with the surface of the semiconductor film within 10 degrees was 14%, and the ratio formed with the angle of the {001} plane with the surface of the semiconductor film within 10 degrees was 1%. That is, as compared with the {001} plane, the orientation ratio of the crystal is more strongly oriented in the {101} plane and the {111} plane.
[0017]
Information about distortion may be obtained by an X-ray diffraction method. In the X-ray diffraction method, the diffraction intensity is measured while scanning the diffraction angle 2θ. At this time, Bragg's equation (2d sin θ = λ, λ is the wavelength of X-rays) and the lattice plane distance d can be obtained from the measurement of 2θ at which the intensity reaches a peak. Here, if the 2θ scan is delayed and the peak position is accurately obtained, information on the distortion applied to the grating can also be obtained.
[0018]
The configuration of the invention disclosed in this specification is as follows.
A first step of forming a first semiconductor film having an amorphous structure on an insulating surface;
A second step of adding a rare gas element to the first semiconductor film having the amorphous structure;
A third step of adding a metal element to the first semiconductor film having the amorphous structure;
A fourth step of forming a first semiconductor film having a crystal structure by performing crystallization by irradiating a laser beam after heat-treating the first semiconductor film;
A fifth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure;
A sixth step of forming a second semiconductor film containing a rare gas element on the barrier layer;
A seventh step of removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element to the second semiconductor film;
And an eighth step of removing the second semiconductor film.
[0019]
In the above structure, the step of forming the barrier layer oxidizes the surface of the semiconductor film having the crystal structure by laser light irradiation, and then oxidizes the surface of the semiconductor film having the crystal structure with a solution containing ozone. It is a process.
[0020]
In the above structure, in the second step, a rare gas element is added in the film of the first semiconductor film having the amorphous structure to 1 × 10 10. ¹⁷ / Cm ^Three Or more, preferably 1 × 10 ²⁰ / Cm ^Three ~ 3x10 ²⁰ / Cm ^Three It is characterized by adding in the concentration range of.
[0021]
In the above structure, the rare gas element contained in the first semiconductor film is removed or reduced by laser light irradiation in the fourth step.
[0022]
In each of the above configurations, the laser is a continuous wave or pulsed solid laser. Typically, the laser is a continuous wave or pulsed YAG laser, YVO, _Four Laser, YLF laser, YAlO _Three One or more types selected from lasers, glass lasers, ruby lasers, alexandride lasers, and Ti: sapphire lasers. Alternatively, in each of the above-described configurations, the laser is one or more selected from a continuous wave or pulsed excimer laser, an Ar laser, and a Kr laser.
[0023]
An experiment was conducted to confirm that the rare gas element contained in the first semiconductor film is removed or reduced by the laser light. FIG. 15 shows the Ar / Si concentration ratio by TXRF. In the experiment, 580 ° C. was prepared by preparing a sample obtained by applying an amorphous silicon film containing Ar at the time of film formation immediately after film formation and a sample obtained by applying a nickel acetate salt solution containing 10 ppm of Ni in terms of weight with a spinner. The results measured after 6 hours of heat treatment (SPC) and the results measured after irradiation (LC) with excimer laser light are indicated by ◯ marks in FIG. In addition, each sample prepared by applying a nickel acetate solution containing Ni at 100 ppm by weight with a spinner was prepared and measured after heat treatment (SPC) at 550 ° C. for 8 hours, and then irradiated with excimer laser light (LC) The result of measurement after the measurement is indicated by Δ in FIG. It can be seen from FIG. 15 that the rare gas element contained in the semiconductor film is significantly removed or reduced by laser light irradiation.
[0024]
In addition, the configuration of other inventions is as follows:
A first step of forming a first semiconductor film having an amorphous structure on an insulating surface;
A second step of adding a rare gas element to the first semiconductor film having the amorphous structure;
A third step of adding a metal element to the first semiconductor film having the amorphous structure;
A fourth step of forming a first semiconductor film having a crystal structure by performing crystallization by irradiating a laser beam after heat-treating the first semiconductor film;
A fifth step of selectively adding a rare gas element to the first semiconductor film having the crystal structure to form a region containing the rare gas element;
A sixth step of selectively removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element in a region containing the rare gas element;
And a seventh step of removing the region containing the rare gas element.
[0025]
In the above structure, in the second step, a rare gas element is added in the film of the first semiconductor film having the amorphous structure to 1 × 10 10. ¹⁷ / Cm ^Three Or more, preferably 1 × 10 ²⁰ / Cm ^Three ~ 3x10 ²⁰ / Cm ^Three It is characterized by adding in the concentration range of.
[0026]
In the above structure, the rare gas element contained in the first semiconductor film is removed or reduced by laser light irradiation in the fourth step.
[0027]
In each of the above structures, the second semiconductor film is formed by sputtering using a semiconductor as a target in an atmosphere containing a rare gas element. Alternatively, a sputtering method using a semiconductor containing phosphorus or boron as a target may be formed in an atmosphere containing a rare gas element. In each of the above structures, the second semiconductor film may be formed by a PCVD method in which film formation is performed in an atmosphere containing a rare gas element.
[0028]
In each of the above structures, the sixth step is a heat treatment or a treatment of irradiating the semiconductor film with intense light. In addition, the sixth step may be a process of performing a heat treatment and irradiating the semiconductor film with intense light.
[0029]
In each of the above structures, the intense light is light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
[0030]
In each of the above structures, when the sixth step is performed, the concentration of the rare gas element contained in the second semiconductor film is higher than the concentration of the rare gas element contained in the first semiconductor film having a crystal structure. It is preferable to set a high value.
[0031]
Further, after forming a semiconductor film having an amorphous structure by including a rare gas element at the time of film formation, crystallization may be performed using a metal element that promotes crystallization.
A first step of forming a semiconductor film containing a rare gas element on the insulating surface and having an amorphous structure;
A second step of adding a metal element to the semiconductor film having an amorphous structure;
A method for manufacturing a semiconductor device, comprising: a third step of forming a semiconductor film having a crystal structure by crystallization by irradiating a laser beam after heat treatment of the first semiconductor film.
[0032]
In addition, after forming a semiconductor film having an amorphous structure by including a rare gas element during film formation, crystallization may be performed using a metal element that promotes crystallization, and further gettering may be performed. Other configurations are
A first step of forming a first semiconductor film containing a rare gas element on the insulating surface and having an amorphous structure;
A second step of adding a metal element to the first semiconductor film having the amorphous structure;
A third step of forming a first semiconductor film having a crystal structure by performing crystallization by irradiating a laser beam after heat-treating the first semiconductor film;
A fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure;
A fifth step of forming a second semiconductor film containing a rare gas element on the barrier layer;
A sixth step of removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element to the second semiconductor film;
And a seventh step of removing the second semiconductor film.
[0033]
In the above structure, the second semiconductor film may be formed by a sputtering method using a semiconductor as a target in an atmosphere containing a rare gas element, or may be formed in an atmosphere containing a rare gas element. You may form by PCVD method. Alternatively, a sputtering method using a semiconductor containing phosphorus or boron as a target may be formed in an atmosphere containing a rare gas element.
[0034]
In the above structure, when the second semiconductor film formation step is performed, the concentration of the rare gas element contained in the second semiconductor film is set to be that of the rare gas element contained in the first semiconductor film having a crystal structure. It is preferable to set it higher than the concentration.
[0035]
In each of the above structures, the metal element is one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.
[0036]
In each of the above structures, the rare gas element is one or a plurality selected from He, Ne, Ar, Kr, and Xe.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0038]
The present invention includes a process for forming an amorphous semiconductor film over an insulating surface, a process for adding a rare gas element to the amorphous semiconductor film, a process for adding a metal element that promotes crystallization, and heat treatment The first crystallization process and the second crystallization process by laser light irradiation.
[0039]
Note that the heat treatment may be a heat treatment using a furnace, a treatment of irradiating strong light from a lamp light source, or irradiating strong light simultaneously with the heat treatment.
[0040]
Further, it is desirable to remove or reduce the metal element from the semiconductor film having a crystal structure obtained by the above process. The semiconductor film having the crystal structure thus obtained is patterned into a desired shape and used for the active layer of the TFT.
[0041]
Hereinafter, a typical TFT manufacturing procedure using the present invention will be briefly described with reference to FIGS.
[0042]
(Embodiment 1)
In FIG. 1A, 100 is a substrate having an insulating surface, 101 is an insulating film serving as a blocking layer, and 102 is a semiconductor film having an amorphous structure.
[0043]
In FIG. 1A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 100. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this step may be used.
[0044]
First, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y A base insulating film 101 made of an insulating film is formed. A typical example has a two-layer structure as the base insulating film 101, and SiH _Four , NH _Three And N ₂ A first silicon oxynitride film formed using O as a reaction gas is formed in a thickness of 50 to 100 nm, SiH. _Four And N ₂ A structure in which a second silicon oxynitride film formed using O as a reaction gas is formed to a thickness of 100 to 150 nm is employed. Further, as a layer of the base insulating film 101, a silicon nitride film (SiN film) having a thickness of 10 nm or less, or a second silicon oxynitride film (SiN) _x O _y It is preferable to use a film (X >> Y). Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the base insulating film in contact with the semiconductor film. Alternatively, a three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.
[0045]
Next, a first semiconductor film having an amorphous structure is formed over the base insulating film 101. A semiconductor material containing silicon as a main component is used for the first semiconductor film. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and the film is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor film having a good crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the first semiconductor film having an amorphous structure is set to 5 × 10 5. ¹⁸ /cm ^Three It may be reduced to (atomic concentration measured by secondary ion mass spectrometry (SIMS)) or less. These impurities interfere with subsequent crystallization, and also increase the density of capture centers and recombination centers even after crystallization. Therefore, it is desirable not only to use a high-purity material gas but also to use an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electropolishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.
[0046]
Next, a rare gas element is added to the first semiconductor film 102 by an ion doping method or an ion implantation method. (FIG. 1A) As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Here, an example in which these inert gases are used as an ion source and implanted into a semiconductor film by an ion doping method or an ion implantation method is shown. Here, the concentration of the rare gas element is set to 1 × 10. ¹⁷ /cm ^Three Or more, preferably 1 × 10 ²⁰ /cm ^Three ~ 3x10 ²⁰ /cm ^Three Is added to the first semiconductor film. The meaning of implanting these inert gas ions is to alleviate strain by implanting the ions between the lattices of the first semiconductor film. In particular, it is remarkably obtained when an element having a larger atomic radius than silicon, such as argon (Ar), krypton (Kr), xenon (Xe), or the like is used.
[0047]
Although an example in which a rare gas is added after the first semiconductor film is formed is shown here, the first semiconductor film may be formed so that a rare gas element is included in the film formation. For example, argon gas may be mixed with a reaction gas containing silane and the first semiconductor film may be formed by a PCVD method. Alternatively, the first semiconductor film containing the rare gas element in the film and having an amorphous structure may be formed by forming the film by sputtering in an atmosphere containing the rare gas element.
[0048]
Next, the first semiconductor film having an amorphous structure is crystallized. However, since the rare gas element is included in the film, crystallization becomes difficult. Therefore, in the present invention, a metal element that promotes crystallization is selectively added, and heat treatment is performed to form a semiconductor film having a crystal structure that spreads from the added region. First, the surface of the first semiconductor film 102 containing a rare gas element and having an amorphous structure contains 1 to 100 ppm in terms of weight of a metal element (here, nickel) having a catalytic action for promoting crystallization. The nickel-containing layer 103 is formed by applying a nickel acetate salt solution with a spinner. (FIG. 1B) As a means other than the method for forming the nickel-containing layer 103 by coating, a means for forming an extremely thin film by sputtering, vapor deposition, or plasma treatment may be used. Although an example in which the coating is performed on the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.
[0049]
Next, heat treatment is performed for crystallization. Here, after heat treatment for dehydrogenation (450 ° C. to 500 ° C., 1 hour), heat treatment for crystallization (550 ° C. to 650 ° C. for 4 to 24 hours) is performed. . When crystallization is performed by irradiation with strong light, any one of infrared light, visible light, ultraviolet light, or a combination thereof can be used. Typically, a halogen lamp, a metal halide, or the like is used. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, and the semiconductor film may be heated to 600 to 1000 ° C. instantaneously. Note that if necessary, heat treatment for releasing hydrogen contained in the first semiconductor film 102 having an amorphous structure may be performed before irradiation with strong light. In addition, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. In consideration of productivity, it is desirable to perform crystallization by irradiation with strong light. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.
[0050]
Next, the first semiconductor film 104 having a crystal structure is irradiated with laser light in order to increase the crystallization rate (the ratio of the crystal component in the entire volume of the film) and repair defects remaining in the crystal grains. . When laser light is irradiated, a thin oxide film (not shown) is formed on the surface. Further, when the laser beam is irradiated, the rare gas element in the first semiconductor film is removed or reduced. As this laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of YAG laser are used.
[0051]
The first semiconductor film 104 obtained in this way has a high orientation rate and relaxed strain.
[0052]
Although an example using a pulse laser is shown here, a continuous wave laser may be used, and in order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous wave is possible. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, Nd: YVO _Four A second harmonic (532 nm) or a third harmonic (355 nm) of a laser (fundamental wave 1064 nm) may be applied. When a continuous wave laser is used, a continuous wave YVO with an output of 10 W _Four Laser light emitted from the laser is converted into a harmonic by a non-linear optical element. Also, YVO in the resonator _Four There is also a method of emitting harmonics by inserting a crystal and a nonlinear optical element. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. The energy density at this time is 0.01 to 100 MW / cm. ² Degree (preferably 0.1-10 MW / cm ² )is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.
[0053]
Here, a technique of irradiating laser light after performing thermal crystallization using nickel as a metal element for promoting crystallization of silicon is used. However, a continuous wave laser (YVO) is used without adding nickel. _Four The amorphous silicon film may be crystallized by the second harmonic of the laser.
[0054]
In addition, the metal element (in this case, nickel) remains in the first semiconductor film 104 obtained by performing heat treatment after adding the metal element. Although it is not uniformly distributed in the film, if it is an average concentration, it is 1 × 10 ¹⁹ /cm ^Three Remaining at a concentration exceeding Of course, various semiconductor elements including TFT can be formed even in such a state, but the element is removed by the method described below.
[0055]
Since the oxide film formed by the laser light irradiation after crystallization is insufficient, an oxide film (called chemical oxide) is further formed with an aqueous solution containing ozone (typically ozone water). A barrier layer 105 made of an oxide film with a thickness of 1 to 10 nm is formed, and a second semiconductor film 106 containing a rare gas element is formed on the barrier layer 105. Note that here, an oxide film formed when the first semiconductor film 104 having a crystal structure is irradiated with laser light is also regarded as a part of the barrier layer 105. The barrier layer 105 functions as an etching stopper when only the second semiconductor film 106 is selectively removed in a later step. Also, chemical oxide can be formed in the same manner by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid or the like and hydrogen peroxide are mixed instead of the ozone-containing aqueous solution. As another method for forming the barrier layer 105, ozone may be generated by ultraviolet irradiation in an oxygen atmosphere to oxidize the surface of the semiconductor film having the crystal structure. As another method for forming the barrier layer 105, an oxide film of about 1 to 10 nm may be deposited by a plasma CVD method, a sputtering method, an evaporation method, or the like to form a barrier layer. As another method for forming the barrier layer 105, a thin oxide film may be formed by heating to about 200 to 350 ° C. using a clean oven. Note that the barrier layer 105 formed by any one of the above methods or a combination of these methods has a film quality that allows nickel in the first semiconductor film to move to the second semiconductor film by subsequent gettering. Or it is necessary to set it as a film thickness.
[0056]
Here, the second semiconductor film 106 containing a rare gas element is formed by a sputtering method, a plasma CVD method, or the like to form a gettering site. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Among them, argon (Ar) which is an inexpensive gas is preferable. Here, a second semiconductor film is formed using a target made of silicon in an atmosphere containing a rare gas element. There are two meanings of including a rare gas element ion which is an inert gas in the film. One is to form a dangling bond to give distortion to the semiconductor film, and the other is to give distortion to the lattice of the semiconductor film. Distortion between the lattices of the semiconductor film can be obtained remarkably when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), or xenon (Xe) is used. Further, by containing a rare gas element in the film, not only lattice distortion but also dangling bonds are formed, contributing to the gettering action. The rare gas element is 1 × 10 ¹⁹ /cm ^Three ~ 1x10 ^{twenty two} /cm ^Three , Preferably 1 × 10 ²⁰ /cm ^Three ~ 1x10 ^{twenty one} /cm ^Three , More preferably 5 × 10 ²⁰ /cm ^Three A semiconductor film that has a high concentration and can obtain a gettering effect may be formed.
[0057]
In addition, in the case where the second semiconductor film is formed using a target including phosphorus which is an impurity element of one conductivity type, gettering may be performed using the Coulomb force of phosphorus in addition to gettering using a rare gas element. it can.
[0058]
In addition, since nickel tends to move to a region having a high oxygen concentration during gettering, the oxygen concentration contained in the second semiconductor film 106 is higher than the oxygen concentration contained in the first semiconductor film, For example 5 × 10 ¹⁸ / Cm ^Three It is desirable to set it above.
[0059]
Next, heat treatment is performed, and gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor film is performed. (FIG. 2B) As the heat treatment for performing gettering, a treatment for irradiating strong light or heat treatment may be performed. By this gettering, the metal element moves in the direction of the arrow in FIG. 2B (that is, the direction from the substrate side to the surface of the second semiconductor film), and the first semiconductor film covered with the barrier layer 105 The metal element contained in 104 is removed or the concentration of the metal element is reduced. The distance that the metal element travels during gettering may be at least as long as the thickness of the first semiconductor film, and the gettering can be completed in a relatively short time. Here, all the nickel is moved to the second semiconductor film 106 so as not to be segregated in the first semiconductor film 104, and the nickel contained in the first semiconductor film 104 is hardly present, that is, the nickel concentration in the film is 1 ×. 10 ¹⁸ / Cm ^Three Below, desirably 1 × 10 ¹⁷ / Cm ^Three Getter enough to get:
[0060]
Depending on the conditions of the heat treatment for the gettering, the crystallization rate of the first semiconductor film can be increased at the same time as the gettering, and defects remaining in the crystal grains can be repaired, that is, the crystallinity can be improved. .
[0061]
In this specification, gettering means that a metal element in a gettering region (here, the first semiconductor film) is released by thermal energy and moves to a gettering site by diffusion. Accordingly, the gettering depends on the processing temperature, and the gettering proceeds in a shorter time as the temperature is higher.
[0062]
When using the process of irradiating strong light, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 700 to 750 ° C.
[0063]
In the case where the heat treatment is performed, the heat treatment may be performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example, at 550 ° C. for 14 hours. Moreover, you may irradiate strong light in addition to heat processing.
[0064]
Next, using the barrier layer 105 as an etching stopper, only the second semiconductor film indicated by 106 is selectively removed, and then the barrier layer 105 is removed and the first semiconductor film 104 is formed using a known patterning technique. The semiconductor layer 107 having the shape is formed. (FIG. 2C) As a method of selectively etching only the second semiconductor film 106, ClF _Three Dry etching without plasma by hydrazine, tetraethylammonium hydroxide (chemical formula (CH _Three ) _Four NOH) can be performed by wet etching with an alkaline solution such as an aqueous solution containing NOH). Further, after removing the second semiconductor film 106, when the nickel concentration was measured on the surface of the barrier layer by TXRF, since nickel was detected at a high concentration, the barrier layer 105 is desirably removed, and hydrofluoric acid is removed. What is necessary is just to remove with the etchant containing. Further, it is desirable to form a thin oxide film on the surface with ozone water after removing the barrier layer and before forming a resist mask.
[0065]
Next, after cleaning the surface of the semiconductor layer 107 with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component and serving as the gate insulating film 108 is formed. The surface cleaning and the formation of the gate insulating film are desirably performed continuously without exposure to the atmosphere.
[0066]
Next, after cleaning the surface of the gate insulating film 108, a gate electrode 109 is formed. Next, an impurity element imparting n-type conductivity (P, As, or the like), here phosphorus, is added as appropriate to the semiconductor, so that the source region 110 and the drain region 111 are formed. After the addition, heat treatment, intense light irradiation, or laser light irradiation is performed to activate the impurity element. Simultaneously with activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. In particular, in an atmosphere of room temperature to 300 ° C., it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface. A YAG laser is a preferred activation means because it requires less maintenance.
[0067]
In the subsequent steps, an interlayer insulating film 113 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, a source electrode 114 and a drain electrode 115 are formed, and a TFT (n-channel TFT) is formed. To complete. (Fig. 2 (D))
[0068]
The concentration of the metal element contained in the channel formation region 112 of the TFT thus obtained is 1 × 10 ¹⁷ / Cm ^Three Less than.
[0069]
Further, the present invention is not limited to the TFT structure of FIG. 2D, and if necessary, a lightly doped drain (LDD) having an LDD region between a channel formation region and a drain region (or source region). ) Structure may be used. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Further, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed.
[0070]
Although an n-channel TFT has been described here, it goes without saying that a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element.
[0071]
Although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure. For example, it can be applied to a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT. Is possible.
[0072]
Moreover, the process order shown here is only an example and is not particularly limited. For example, here, an example in which a rare gas element is added to the first semiconductor film and then a metal element is added is shown; however, a metal element is added to the first semiconductor film and then a rare gas element is added. Good.
[0073]
(Embodiment 2)
Here, an example using a gettering method different from that in the first embodiment will be described. Note that this embodiment is the same as the first embodiment, and the detailed description thereof will be omitted.
[0074]
First, the state shown in FIG. 1C is obtained in the same manner as in the first embodiment.
[0075]
Next, a mask is formed and a rare gas element is selectively added. Here, a silicon oxide film having a thickness of 100 to 200 nm is formed over the crystalline semiconductor film. A method for forming the silicon oxide film is not limited. For example, tetraethyl orthosilicate (TEOS) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² To discharge and form.
[0076]
Next, a resist mask 207 is formed on the silicon oxide film. After patterning with this mask and forming an insulating layer 206 made of silicon oxide covering a portion to be a semiconductor layer of the TFT, a rare gas element is added to the semiconductor film to form a gettering site 208. Here, an ion doping method or an ion implantation method is used, and the concentration of a rare gas element added to the semiconductor film is set to 1 × 10. ²⁰ ~ 5x10 ^{twenty one} / Cm ^Three Is desirable. At this time, the rare gas element may be doped while the resist mask is left as it is, or the rare gas element may be doped after the resist mask 207 is removed. After doping with the rare gas element, the resist mask is removed. Further, in addition to a rare gas element, a periodic table group 15 element or a periodic table group 13 element may be added.
[0077]
Next, gettering is performed. (FIG. 3B) When gettering is performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example, 550 ° C. for 14 hours, metal elements can be segregated at the gettering site 208. . By this gettering, the metal element contained in the semiconductor film covered with the insulating layer 206 is removed or the concentration of the metal element is reduced. Moreover, you may irradiate strong light instead of heat processing. Moreover, you may irradiate strong light in addition to heat processing. However, when the RTA method using light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp is used as the heating means for gettering, the heating temperature of the semiconductor film is It is desirable to irradiate strong light so that it may become 400 to 550 degreeC.
[0078]
After the gettering is completed, the gettering site is removed using the mask as it is to form a semiconductor layer 209 having a desired shape including a region where the metal element is reduced, and finally an insulating layer made of silicon oxide is formed. Remove. (FIG. 3C) When the insulating layer 206 is removed, the surface of the semiconductor layer 209 is desirably slightly etched.
[0079]
Alternatively, the gettering site may be formed by doping a rare gas element through a silicon oxide film when a resist mask is formed. In this case, after doping, the mask is removed and gettering is performed, and then the silicon oxide film is removed. Thereafter, only the region (gettering site) to which the rare gas element is added is selectively removed from the semiconductor film. Thus, a semiconductor layer is formed. If a dash liquid, a saturated liquid, a Seco liquid, or the like is used as an etchant, the region to which the rare gas element is added is amorphized, so that the region is a crystalline semiconductor film (no rare gas is added). It can be selectively etched.
[0080]
Subsequent steps complete the TFT by the same steps as those in the first embodiment. (Fig. 3 (D))
[0081]
Further, this embodiment mode can be combined with Embodiment Mode 1. It can also be combined with other known gettering techniques.
[0082]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0083]
(Example)
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail.
[0084]
First, the base insulating film 1101 is formed over the glass substrate 1100 by the method described in the above embodiment to obtain a first semiconductor film having a crystal structure, and then etched into a desired shape to be separated into islands. The formed semiconductor layers 1102 to 1106 are formed.
[0085]
Note that the detailed description up to the formation of the semiconductor layers 1102 to 1106 is described in Embodiment Mode 1 and will be briefly described below.
[0086]
In this embodiment, a two-layer structure is used as the base insulating film 1101 provided over the glass substrate. However, a single layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base insulating film 1101, a plasma CVD method is used, and SiH _Four , NH _Three And N ₂ A first silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) formed with O as a reaction gas is formed with a film thickness of 50 nm. Next, as the second layer of the base insulating film 1101, a plasma CVD method is used, and SiH _Four And N ₂ A second silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) formed with O as a reaction gas is formed with a film thickness of 100 nm.
[0087]
Next, an amorphous silicon film using a plasma CVD method is formed with a thickness of 50 nm over the base insulating film 1101. Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used.
[0088]
Next, a rare gas element (here, argon) is added to the amorphous silicon film by an ion doping method. 1 × 10 of rare gas element in the amorphous silicon film ¹⁷ / Cm ^Three Or more, preferably 1 × 10 ²⁰ / Cm ^Three ~ 3x10 ²⁰ / Cm ^Three Add in the concentration range of. Argon is included in the film before crystallization to increase the orientation ratio of the film, and after crystallization, the strain existing in the film is reduced.
[0089]
Next, irradiation with intense light at 700 ° C. for 110 seconds was performed with a multi-task type lamp annealing apparatus using a total of 21 tungsten halogen lamps to obtain a silicon film having a crystal structure. Note that if the temperature is 700 ° C. or less with a lamp annealing apparatus, the semiconductor film is only heated instantaneously and there is almost no change in the shape of the substrate 1100. Although crystallization is performed using a lamp annealing apparatus here, crystallization may be performed by heat treatment using a furnace.
[0090]
Next, irradiation with laser light (XeCl: wavelength 308 nm) is performed to increase the crystallization rate and repair defects remaining in the crystal grains. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of a YAG laser are used. In any case, pulse laser light having a repetition frequency of about 10 to 1000 Hz is used, and the laser light is 100 to 400 mJ / cm in the optical system. ² And the surface of the silicon film may be scanned by irradiating with an overlap rate of 90 to 95%. Note that the laser irradiation here is very important in removing or reducing a rare gas element (in this case, argon) in the film. Next, in addition to the oxide film formed by laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm.
[0091]
Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 150 nm on the barrier layer by a sputtering method. The film formation conditions by the sputtering method of this embodiment are as follows: the film formation pressure is 0.3 Pa, the gas (Ar) flow rate is 50 (sccm), the film formation power is 3 kW, and the substrate temperature is 150 ° C. Note that the atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 3 × 10 ²⁰ / Cm ^Three ~ 6 × 10 ²⁰ / Cm ^Three The atomic concentration of oxygen is 1 × 10 ¹⁹ / Cm ^Three ~ 3x10 ¹⁹ / Cm ^Three It is. Thereafter, heat treatment is performed at 650 ° C. for 3 minutes using a lamp annealing apparatus to perform gettering.
[0092]
Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.
[0093]
Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed and etched into a desired shape to form islands. A separated semiconductor layer is formed. After the semiconductor layer is formed, the resist mask is removed.
[0094]
Further, after forming the semiconductor layer, an impurity element imparting p-type or n-type conductivity may be added in order to control the threshold value (Vth) of the TFT. As impurity elements imparting p-type to a semiconductor, periodic group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) are known. Note that as an impurity element imparting n-type conductivity to a semiconductor, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is known.
[0095]
Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component to be the gate insulating film 1107 is formed. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed to a thickness of 115 nm by plasma CVD.
[0096]
Next, as illustrated in FIG. 4A, a first conductive film 1108a with a thickness of 20 to 100 nm, a second conductive film 1108b with a thickness of 100 to 400 nm, and a thickness of 20 to 20 are formed over the gate insulating film 1107. A third conductive film 1108c having a thickness of 100 nm is stacked. In this embodiment, a 50-nm-thick tungsten film, a 500-nm-thick aluminum and titanium alloy (Al—Ti) film, and a 30-nm-thick titanium film are sequentially stacked over the gate insulating film 1107.
[0097]
As the conductive material for forming the first to third conductive films, an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component is formed. A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used as the first to third conductive films. For example, tungsten nitride may be used instead of tungsten of the first conductive film, or an alloy of aluminum and silicon (Al—Si) instead of the aluminum and titanium alloy (Al—Ti) film of the second conductive film. ) Film may be used, or a titanium nitride film may be used instead of the titanium film of the third conductive film. Moreover, it is not limited to a three-layer structure, For example, the two-layer structure of a tantalum nitride film and a tungsten film may be sufficient.
[0098]
Next, as shown in FIG. 4B, resists 1110 to 1115 are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching gas, Cl ₂ , BCl _Three , SiCl _Four , CCl _Four Chlorine gas or CF represented by _Four , SF ₆ , NF _Three Fluorine gas such as O ₂ Can be used as appropriate.
[0099]
The etching gas used is not limited, but here BCl _Three And Cl ₂ And O ₂ It is suitable to use. Each gas flow rate ratio is 65/10/5 (sccm), 450 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed for 117 seconds. Do. 300 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The Al film and the Ti film are etched under the first etching condition, and the end portion of the first conductive layer is tapered.
[0100]
After that, the second etching condition is changed and the etching gas is changed to CF. _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil electrode at a pressure of 1 Pa to generate plasma for about 30 seconds. Etch to a certain degree. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching conditions in which the Al is mixed, the Al film, Ti film, and W film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0101]
In the first etching process, the first conductive layer, the second conductive layer, and the third conductive layer are formed by the effect of the bias voltage applied to the substrate side by making the shape of the resist mask suitable. The end of the layer is tapered. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 1117 to 1122 (the first conductive layers 1117a to 1122a and the second conductive layers) including the first conductive layer, the second conductive layer, and the third conductive layer are formed by the first etching process. Conductive layers 1117b to 1122b and third conductive layers 1117c to 1122c) are formed. Reference numeral 1116 denotes a gate insulating film. A region which is not covered with the first shape conductive layers 1117 to 1122 is etched and thinned by about 20 to 50 nm.
[0102]
Next, a second etching process is performed as shown in FIG. 4C without removing the resist masks 1110 to 1115. BCl as etching gas _Three And Cl ₂ Each gas flow rate ratio is 20/60 (sccm), 600 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, and plasma is generated to perform etching. 100 W of RF (13.56 MHz) power is applied to the substrate side (sample stage). The second conductive layer and the third conductive layer are etched under the third etching condition. In this manner, the aluminum film and the titanium film containing a small amount of titanium under the third etching condition are anisotropically etched to form the second shape conductive layers 1124 to 1129 (the first conductive layers 1124a to 1129a and the second conductive layer). Layers 1124b to 1129b and third conductive layers 1124c to 1129c) are formed. Reference numeral 1123 denotes a gate insulating film. A region not covered with the second shape conductive layers 1124 to 1129 is slightly etched to form a thinned region.
[0103]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. The doping process may be performed by ion doping or ion implantation. The condition of the ion doping method is that the dose is 1.5 × 10 ¹⁴ atoms / cm ² The acceleration voltage is set to 60 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. In this case, the second shape conductive layers 1124 to 1128 serve as a mask for the impurity element imparting n-type, and the first impurity regions 1130 to 1134 are formed in a self-aligning manner. The first impurity regions 1130 to 1134 have 1 × 10 ¹⁶ ~ 1x10 ¹⁷ /cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0104]
In this embodiment, the first doping process is performed without removing the resist mask, but the first doping process may be performed after the resist mask is removed.
[0105]
Next, after removing the resist mask, resist masks 1135 and 1136 are formed as shown in FIG. 5A, and a second doping process is performed. A mask 1135 is a mask for protecting a channel formation region of a semiconductor layer that forms one of n-channel TFTs of a driver circuit and a peripheral region thereof, and a mask 1136 is a channel formation region of a semiconductor layer that forms a TFT of a pixel portion. And a mask for protecting the surrounding area.
[0106]
The condition of the ion doping method in the second doping process is that the dose is 1.5 × 10 5. ¹⁵ atoms / cm ² Then, phosphorus (P) is doped with an acceleration voltage of 60 to 100 keV. Here, an impurity region is formed in each semiconductor layer by using a difference in film thickness between the second shape conductive layers 1124 to 1128 and the gate insulating film 1123. Of course, phosphorus (P) is not added to the regions covered with the masks 1135 and 1136. Thus, second impurity regions 1180 to 1182 and third impurity regions 1137 to 1141 are formed. The third impurity regions 1137 to 1141 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting n-type is added in a concentration range of. The second impurity region is formed at a lower concentration than the third impurity region due to a difference in film thickness of the gate insulating film, and is 1 × 10 6. ¹⁸ ~ 1x10 ¹⁹ /cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0107]
Next, after removing the resist masks 1135 and 1136, new resist masks 1142 to 1144 are formed, and a third doping process is performed as shown in FIG. 5B. By the third doping treatment, the fourth impurity region 1147 and the fifth impurity regions 1145 and 1146 to which an impurity element imparting p-type conductivity is added are formed in the semiconductor layer forming the p-channel TFT. . The fourth impurity region is formed in a region overlapping with the second shape conductive layer, and is 1 × 10 6. ¹⁸ ~ 1x10 ²⁰ /cm ^Three An impurity element imparting p-type is added in a concentration range of. The fifth impurity regions 1145 and 1146 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting p-type is added in a concentration range of. Note that the fifth impurity region 1146 is a region to which phosphorus (P) is added in the previous step, but the concentration of the impurity element imparting p-type is added 1.5 to 3 times its conductivity type. Is p-type.
[0108]
Note that the fifth impurity regions 1148 and 1149 and the fourth impurity region 1150 are formed in a semiconductor layer which forms a storage capacitor in the pixel portion.
[0109]
Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer. The second shape conductive layers 1124 to 1127 serve as gate electrodes. In addition, the second shape conductive layer 1128 serves as one electrode forming a storage capacitor in the pixel portion. Further, the second shape conductive layer 1129 forms a source wiring in the pixel portion.
[0110]
Next, an insulating film (not shown) that covers substantially the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.
[0111]
Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step may be a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods. However, in this embodiment, since the material mainly composed of aluminum is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the activation process.
[0112]
Simultaneously with the activation treatment, nickel used as a catalyst during crystallization is gettered to the third impurity regions 1137, 1139, and 1140 and the fifth impurity regions 1146 and 1149 containing high-concentration phosphorus. In addition, the nickel concentration in the semiconductor layer that becomes the channel formation region is reduced. As a result, a TFT having a channel formation region has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved. Note that in this example, the first gettering is performed by the method described in Embodiment Mode 1 at the stage of forming the semiconductor layer, so that the gettering by phosphorus here is the second gettering. . In addition, when the gettering is sufficiently performed by the first gettering, it is not particularly necessary to perform the second gettering.
[0113]
Further, in this embodiment, an example in which an insulating film is formed before the activation is shown, but an insulating film may be formed after the activation.
[0114]
Next, a first interlayer insulating film 1151 made of a silicon nitride film is formed and subjected to a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer. (FIG. 5C) This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 1151. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as a main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0115]
Next, a second interlayer insulating film 1152 made of an organic insulating material is formed over the first interlayer insulating film 1151. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 1127 and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using the insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).
[0116]
Thereafter, wirings and pixel electrodes are formed using Al, Ti, Mo, W, or the like. As materials for these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film mainly composed of Al or Ag, or a laminated film thereof. Thus, source or drain wirings 1153 to 1158, a gate wiring 1160, a connection wiring 1159, and a pixel electrode 1161 are formed.
[0117]
As described above, the driver circuit 406 including the n-channel TFT 401, the p-channel TFT 402, and the n-channel TFT 403, and the pixel portion 407 including the n-channel TFT 404 and the storage capacitor 405 can be formed over the same substrate. it can. (FIG. 6) In this specification, such a substrate is referred to as an active matrix substrate for convenience. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0118]
An n-channel TFT 401 (second n-channel TFT) of the driver circuit 406 includes a channel formation region 1162, a second impurity region 1163 partially overlapping with a second shape conductive layer 1124 forming a gate electrode, and a source region. Alternatively, the third impurity region 1164 functioning as a drain region is provided. The p-channel TFT 402 includes a channel formation region 1165, a fourth impurity region 1166 that partially overlaps with the second shape conductive layer 1125 that forms the gate electrode, and a fourth impurity region 1167 that functions as a source region or a drain region. Have. The n-channel TFT 403 (second n-channel TFT) includes a channel formation region 1168, a second impurity region 1169 that partially overlaps with the second shape conductive layer 1126 that forms the gate electrode, and a source or drain region. The third impurity region 1170 functioning as A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, or the like can be formed using such an n-channel TFT and a p-channel TFT. In particular, the structure of the n-channel TFT 401 or 403 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.
[0119]
A pixel TFT 404 (first n-channel TFT) in the pixel portion 407 includes a channel formation region 1171, a first impurity region 1172 formed outside a second shape conductive layer 1128 that forms a gate electrode, and a source region. Alternatively, the third impurity region 1173 functioning as a drain region is provided. A fourth impurity region 1176 and a fifth impurity region 1177 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 405. The storage capacitor 405 is formed of a second shape electrode 1129 and a semiconductor layer 1106 using an insulating film (the same film as the gate insulating film) as a dielectric.
[0120]
In addition, when the pixel electrode is formed using a transparent conductive film, a transmissive display device can be formed although the number of photomasks is increased by one.
[0121]
[Example 2]
In Example 1, an example in which the gate electrode structure has a three-layer structure is shown, but an example in which the gate electrode structure has a two-layer structure is shown. Since this embodiment is the same as the first embodiment except for the gate electrode, only differences will be described.
[0122]
In this embodiment, in this embodiment, a first conductive film made of a TaN film with a thickness of 30 nm and a second conductive film made of a W film with a thickness of 370 nm are stacked. The TaN film is formed by sputtering, and is sputtered in a nitrogen-containing atmosphere using a Ta target. The W film is formed by sputtering using a W target. In place of the W film, an alloy film made of W and Mo may be used.
[0123]
In this example, as in Example 1, the ICP etching method was used, and the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) The film can be etched into a desired taper shape by appropriately adjusting. As an etching gas, Cl ₂ , BCl _Three , SiCl _Four , CCl _Four Chlorine gas or CF represented by _Four , SF ₆ , NF _Three Fluorine gas such as O ₂ Can be used as appropriate.
[0124]
Similar to the first embodiment, the first etching process is performed under the first and second etching conditions. As the first etching condition, CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio is 25/25/10 (sccm) and 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition.
[0125]
Then, the resist mask is not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30/30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and etching for about 30 seconds. I do. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min.
[0126]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.
[0127]
The second etching process is performed in the same manner as in the first embodiment. Here, SF is used as the etching gas. ₆ And Cl ₂ And O ₂ The gas flow ratio is 24/12/24 (sccm), and 700 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.3 Pa to generate plasma and perform etching. 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the oxide that is the gate insulating film The etching rate for the silicon nitride film (SiON) is 33.7 nm / min. By this second etching process, the taper angle of W became 70 °.
[0128]
Compared to Example 1, the gate electrode formed in this example is formed by stacking a W film and a TaN film, and thus has a high electrical resistance value, but has high heat resistance. This has the advantage that it is not affected by the processing conditions.
[0129]
[Example 3]
In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 7 is used for the description.
[0130]
First, after obtaining the active matrix substrate in the state of FIG. 6 according to Example 1, an alignment film is formed on the active matrix substrate of FIG. 6 and a rubbing process is performed. In this embodiment, before the alignment film is formed, columnar spacers for maintaining the distance between the substrates are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0131]
Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light shielding layer was also provided in the drive circuit portion. A flattening film covering the color filter and the light shielding layer was provided. Next, a counter electrode made of a transparent conductive film was formed on the planarizing film in the pixel portion, an alignment film was formed on the entire surface of the counter substrate, and a rubbing process was performed.
[0132]
Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, an active matrix liquid crystal display device is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed using the well-known technique.
[0133]
The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.
[0134]
A pixel portion 804 is disposed at the center of the active matrix substrate 801. A source signal line driver circuit 802 for driving the source signal line is disposed above the pixel portion 804. On the left and right sides of the pixel portion 804, gate signal line driving circuits 803 for driving the gate signal lines are arranged. In the example shown in this embodiment, the gate signal line driver circuit 803 is symmetrically arranged with respect to the pixel portion, but this may be arranged only on one side, and the designer may consider the substrate size of the liquid crystal module and the like. May be appropriately selected. However, considering the operation reliability and driving efficiency of the circuit, the symmetrical arrangement shown in FIG. 7 is desirable.
[0135]
Input of signals to each drive circuit is performed from a flexible printed circuit (FPC) 805. The FPC 805 opens contact holes in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined place on the substrate 801, forms a connection electrode 809, and then performs pressure bonding via an anisotropic conductive film or the like. Is done. In this example, the connection electrode was formed using ITO.
[0136]
A sealant 807 is applied around the periphery of the driving circuit and the pixel portion along the outer periphery of the substrate, and a predetermined gap (a distance between the substrate 801 and the counter substrate 806) is maintained by a spacer 810 formed in advance on the active matrix substrate. In this state, the counter substrate 806 is attached. Thereafter, a liquid crystal element is injected from a portion where the sealant 807 is not applied and sealed with the sealant 808. The liquid crystal module is completed through the above steps.
[0137]
Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.
[0138]
[Example 4]
In Example 1, an example of a reflective display device in which a pixel electrode is formed of a reflective metal material is shown. However, in this embodiment, a transmissive display in which a pixel electrode is formed of a light-transmitting conductive film. An example of an apparatus is shown.
[0139]
The steps up to the step of forming the interlayer insulating film are the same as those in the first embodiment, and are omitted here. After an interlayer insulating film is formed according to Embodiment 1, a pixel electrode 601 made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium oxide zinc oxide alloy (In ₂ O _Three —ZnO), zinc oxide (ZnO), or the like may be used.
[0140]
Thereafter, contact holes are formed in the interlayer insulating film 600. Next, a connection electrode 602 which overlaps with the pixel electrode is formed. The connection electrode 602 is connected to the drain region through a contact hole. In addition, the source electrode or drain electrode of another TFT is formed simultaneously with this connection electrode.
[0141]
Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.
[0142]
An active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module is manufactured in accordance with Embodiment 3, provided with a backlight 604 and a light guide plate 605, and covered with a cover 606, an active matrix type as shown in FIG. A liquid crystal display device is completed. Note that the cover and the liquid crystal module are bonded together using an adhesive or an organic resin. In addition, when the substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded. Further, since it is a transmissive type, the polarizing plate 603 is attached to both the active matrix substrate and the counter substrate.
[0143]
[Example 5]
In this embodiment, an example of manufacturing a light-emitting display device including an EL (Electro Luminescence) element is shown in FIG.
[0144]
9A is a top view showing the EL module, and FIG. 9B is a cross-sectional view taken along line AA ′ of FIG. 9A. A pixel portion 902, a source side driver circuit 901, and a gate side driver circuit 903 are formed over a substrate 900 (eg, a glass substrate, a crystallized glass substrate, or a plastic substrate) having an insulating surface. These pixel portions and driving circuits can be obtained according to the above embodiment. Reference numeral 918 denotes a sealing material, and 919 denotes a DLC film. The pixel portion and the drive circuit portion are covered with a sealing material 918, and the sealing material is covered with a protective film 919. Further, it is sealed with a cover material 920 using an adhesive. In order to withstand deformation due to heat or external force, the cover material 920 is preferably made of the same material as that of the substrate 900, for example, a glass substrate. To process. Further, it is desirable to form a recess (depth 50 to 200 μm) where the desiccant 921 can be installed by processing. In addition, when manufacturing an EL module by multi-chamfering, after bonding the substrate and the cover material, the CO ₂ You may cut | disconnect so that an end surface may correspond using a laser etc.
[0145]
Reference numeral 908 denotes wiring for transmitting signals input to the source side driver circuit 901 and the gate side driver circuit 903, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 909 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.
[0146]
Next, a cross-sectional structure is described with reference to FIG. An insulating film 910 is provided over the substrate 900, and a pixel portion 902 and a gate side driver circuit 903 are formed above the insulating film 910. The pixel portion 902 is electrically connected to the current control TFT 711 and its drain. The pixel electrode 912 is formed by a plurality of pixels. The gate side driver circuit 903 is formed using a CMOS circuit in which an n-channel TFT 913 and a p-channel TFT 714 are combined.
[0147]
These TFTs (including 911, 913, and 914) may be manufactured according to the above embodiment.
[0148]
The pixel electrode 912 functions as an anode of the light emitting element (EL element). A bank 915 is formed on both ends of the pixel electrode 912, and an EL layer 916 and a cathode 917 of a light emitting element are formed on the pixel electrode 912.
[0149]
As the EL layer 916, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular organic EL material or a high molecular organic EL material may be used. In addition, a thin film made of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light emitting material (phosphorescence) that emits light (phosphorescence) by triplet excitation can be used as the EL layer. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0150]
The cathode 917 also functions as a wiring common to all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. Further, all elements included in the pixel portion 902 and the gate side driver circuit 903 are covered with a cathode 917, a sealant 918, and a protective film 919.
[0151]
Note that as the sealant 918, a material that is as transparent or translucent as possible to visible light is preferably used. Further, the sealant 918 is desirably a material that does not transmit moisture and oxygen as much as possible.
[0152]
In addition, after completely covering the light emitting element with the sealant 918, it is preferable to provide a protective film 919 made of a DLC film or the like on the surface (exposed surface) of the sealant 918 at least as shown in FIG. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to pay attention so that a protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may be prevented from being formed using a mask, or the protective film may not be formed by covering the external input terminal portion with a tape such as Teflon (registered trademark) used as a masking tape in a CVD apparatus. Also good.
[0153]
By encapsulating the light-emitting element with the sealing material 918 and the protective film with the above structure, the light-emitting element can be completely shut off from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture or oxygen from the outside. Can be prevented from entering. Therefore, a highly reliable light-emitting device can be obtained.
[0154]
Further, the pixel electrode is an anode (Pt, Cr, W, Ni, etc.), and an EL layer and a light-transmitting cathode (a thin metal layer (AgMg or AlLi) and a transparent conductive film (ITO or ZnO)) 9 may be configured to emit light in a direction opposite to that in FIG 9. In addition, the pixel electrode may be used as a cathode, and an EL layer and an anode may be stacked to emit light in the direction opposite to that in FIG. An example of this is shown here, and the top view is the same and is omitted.
[0155]
The cross-sectional structure shown in FIG. 10 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used in addition to a glass substrate or a quartz substrate. An insulating film 1010 is provided over the substrate 1000, and a pixel portion 1002 and a gate side driver circuit 1003 are formed above the insulating film 1010. The pixel portion 1002 is electrically connected to the current control TFT 1011 and its drain. The pixel electrode 1012 is formed by a plurality of pixels. The gate side driver circuit 1003 is formed using a CMOS circuit in which an n-channel TFT 1013 and a p-channel TFT 1014 are combined.
[0156]
The pixel electrode 1012 functions as a cathode of the light emitting element. A bank 1015 is formed at both ends of the pixel electrode 1012, and an EL layer 1016 and an anode 1017 of a light emitting element are formed on the pixel electrode 1012.
[0157]
The anode 1017 also functions as a wiring common to all pixels, and is electrically connected to the FPC 1009 through the connection wiring 1008. Further, all elements included in the pixel portion 1002 and the gate side driver circuit 1003 are covered with an anode 1017, a sealant 1018, and a protective film 1019 made of DLC or the like. Further, the cover material 1021 and the substrate 1000 were bonded together with an adhesive. Further, the cover material is provided with a recess, and a desiccant 1021 is provided.
[0158]
Note that as the sealant 1018, it is preferable to use a material that is as transparent or translucent as possible to visible light. The sealing material 1018 is desirably a material that does not transmit moisture and oxygen as much as possible.
[0159]
In FIG. 10, since the pixel electrode is a cathode and the EL layer and the anode are stacked, the light emission direction is the direction of the arrow shown in FIG.
[0160]
Note that this embodiment can be combined with the first embodiment, the first embodiment, or the second embodiment.
[0161]
[Example 6]
The driver circuit and the pixel portion formed by implementing the present invention can be used for various modules (active matrix liquid crystal module, active matrix EL module, active matrix EC module). That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.
[0162]
Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.
[0163]
FIG. 11A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0164]
FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102.
[0165]
FIG. 11C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.
[0166]
FIG. 11D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302.
[0167]
FIG. 11E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0168]
FIG. 11F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502.
[0169]
FIG. 12A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to a liquid crystal module 2808 that constitutes a part of the projection device 2601.
[0170]
FIG. 12B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal module 2808 that constitutes a part of the projection device 2702.
[0171]
FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal module 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0172]
FIG. 12D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 12D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0173]
However, the projector shown in FIG. 12 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and an EL module is not shown.
[0174]
FIG. 13A shows a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, an image input portion (CCD, image sensor, etc.) 2907, and the like. The present invention can be applied to the display portion 2904.
[0175]
FIG. 13B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.
[0176]
FIG. 13C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103.
[0177]
Incidentally, the display shown in FIG. 13C is a medium or small size display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate having a side of 1 m and perform mass production by performing multiple chamfering.
[0178]
As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-5.
[0179]
【The invention's effect】
According to the present invention, the orientation ratio of the film can be increased, and distortion existing in the film after crystallization can be reduced as compared with that before crystallization.
[Brief description of the drawings]
FIG. 1 is a process diagram showing a first embodiment.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of a TFT. FIGS. (Embodiment 1)
FIG. 3 is a view showing a manufacturing process of a TFT. (Embodiment 2)
4A and 4B are diagrams illustrating a manufacturing process of an AM-LCD.
FIGS. 5A and 5B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
6A and 6B are diagrams illustrating a manufacturing process of an AM-LCD.
FIG. 7 is a top view showing an external appearance of a liquid crystal module.
FIG. 8 illustrates an example of a cross-sectional view of a liquid crystal display device.
FIG. 9 is a view showing a top surface and a cross section of an EL module.
FIG. 10 is a view showing a cross section of an EL module.
FIG. 11 illustrates an example of an electronic device.
FIG. 12 illustrates an example of an electronic device.
FIG. 13 illustrates an example of an electronic device.
FIG. 14 is a reverse pole figure of a silicon film (including argon) having a crystal structure of the present invention obtained by the EBSP method.
FIG. 15 is a diagram showing an Ar / Si concentration ratio by TXRF.

Claims (16)

Forming a first silicon film having an amorphous structure containing a rare gas element of He, Ne, Ar, Kr, or Xe at a concentration of 1 × 10 ¹⁷ / cm ³ or more on an insulating surface;
After applying a nickel acetate salt solution containing 1 to 100 ppm of Ni to the first silicon film having the amorphous structure,
The first silicon film is crystallized by heat treatment at 550 ° C. to 650 ° C. for 4 hours to 24 hours to form a second silicon film having a crystal structure,
Irradiating the second silicon film having the crystal structure with laser light,
Forming a barrier layer on the surface of the second silicon film having the crystal structure;
Forming a third silicon film containing a rare gas element of He, Ne, Ar, Kr, or Xe at a concentration higher than the concentration of the rare gas element contained in the first silicon film on the barrier layer;
By performing heat treatment at 450 ° C. to 800 ° C. for 1 hour to 24 hours in a nitrogen atmosphere, the third silicon film is gettered with Ni,
A method for manufacturing a semiconductor device, wherein the third silicon film is removed. Forming a first silicon film having an amorphous structure on an insulating surface;
A rare gas element of He, Ne, Ar, Kr, or Xe is added to the first silicon film having an amorphous structure at a concentration of 1 × 10 ¹⁷ / cm ³ or more;
After applying a nickel acetate salt solution containing 1 to 100 ppm of Ni to the first silicon film having the amorphous structure,
The first silicon film is crystallized by heat treatment at 550 ° C. to 650 ° C. for 4 hours to 24 hours to form a second silicon film having a crystal structure,
Irradiating the second silicon film having the crystal structure with laser light,
Forming a barrier layer on the surface of the second silicon film having the crystal structure;
Forming a third silicon film containing a rare gas element of He, Ne, Ar, Kr, or Xe at a concentration higher than the concentration of the rare gas element contained in the first silicon film on the barrier layer;
By performing heat treatment at 450 ° C. to 800 ° C. for 1 hour to 24 hours in a nitrogen atmosphere, the third silicon film is gettered with Ni,
A method for manufacturing a semiconductor device, wherein the third silicon film is removed. In claim 1 or claim 2,
The method of manufacturing a semiconductor device, wherein the laser light is a continuous wave or pulsed solid laser. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the laser light is excimer laser light having a wavelength of 400 nm or less. In claim 1 or claim 2,
The method of manufacturing a semiconductor device, wherein the laser beam is a second harmonic or a third harmonic of a YAG laser. In any one of Claims 1 thru | or 5,
Before the gettering, the second silicon film having the crystal structure contains the Ni at a concentration higher than 1 × 10 ¹⁹ / cm ^3. . In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, wherein an oxygen concentration of the third silicon film is higher than an oxygen concentration of the first silicon film. In claim 7,
The method for manufacturing a semiconductor device, wherein the third silicon film has an oxygen concentration of 1 × 10 ¹⁸ / cm ³ or more. In any one of Claims 1 thru | or 8,
A method for manufacturing a semiconductor device, wherein the concentration of a rare gas element contained in the third silicon film is in a concentration range of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²² / cm ³ . In any one of Claims 1 thru | or 9,
The method for manufacturing a semiconductor device, wherein the barrier layer is formed by oxidizing a surface of the second silicon film having the crystal structure with a solution containing ozone. In any one of Claims 1 thru | or 9,
The method for manufacturing a semiconductor device is characterized in that the barrier layer is formed by generating ozone by irradiation with ultraviolet rays in an oxygen atmosphere to oxidize the surface of the second silicon film having the crystal structure. In any one of Claims 1 thru | or 9,
The barrier layer oxidizes the surface of the second silicon film having the crystal structure by irradiation with the laser beam, and then oxidizes the surface of the second silicon film having the crystal structure with a solution containing ozone. A method for manufacturing a semiconductor device, which is characterized by being formed. In any one of Claims 1 to 12,
The method for manufacturing a semiconductor device, wherein the third silicon film is formed by a sputtering method using silicon as a target in an atmosphere containing a rare gas element. A silicon film having an amorphous structure containing a rare gas element of He, Ne, Ar, Kr, or Xe at a concentration of 1 × 10 ¹⁷ / cm ³ or more is formed on the insulating surface;
After applying a nickel acetate salt solution containing 1 to 100 ppm of Ni to the silicon film having an amorphous structure,
The silicon film is crystallized by heat treatment at 550 ° C. to 650 ° C. for 4 hours to 24 hours to form a silicon film having a crystal structure,
Irradiating a laser beam to the silicon film having the crystal structure,
A rare gas element of He, Ne, Ar, Kr, or Xe is selectively added to the silicon film having the crystal structure in a concentration range of 1 × 10 ²⁰ / cm ^{3 to} 5 × 10 ²¹ / cm ³ , Forming a region containing gas elements,
After gettering the Ni into the region containing the rare gas element by heat treatment at 450 ° C. to 800 ° C. for 1 hour to 24 hours in a nitrogen atmosphere,
A method for manufacturing a semiconductor device, comprising removing a region containing the rare gas element. Forming a silicon film having an amorphous structure on the insulating surface;
Was added the He silicon film having an amorphous structure, Ne, Ar, Kr, or a rare gas element Xe at 1 × ¹⁰ 17 / cm ³ or more concentrations,
After applying a nickel acetate salt solution containing 1 to 100 ppm of Ni to the silicon film having an amorphous structure,
The silicon film is crystallized by heat treatment at 550 ° C. to 650 ° C. for 4 hours to 24 hours to form a silicon film having a crystal structure,
Irradiating a laser beam to the silicon film having the crystal structure,
A rare gas element of He, Ne, Ar, Kr, or Xe is selectively added to the silicon film having the crystal structure in a concentration range of 1 × 10 ²⁰ / cm ^{3 to} 5 × 10 ²¹ / cm ³ , Forming a region containing gas elements,
After gettering the Ni into the region containing the rare gas element by heat treatment at 450 ° C. to 800 ° C. for 1 hour to 24 hours in a nitrogen atmosphere,
A method for manufacturing a semiconductor device, comprising removing a region containing the rare gas element. In claim 14 or claim 15,
After removal of the region including the rare gas element, a method for manufacturing a semiconductor device characterized by also etching the surface of the silicon film having a crystalline structure.

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