JP2002324808A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device whose manufacturing process is simple even when optimizing an FET structure to meet requirements for a pixel portion and a driving circuit, and to solve the problem of sudden off- current increase when forming the FET without sufficiently reducing a concentration of a catalyst chemical element in forming a crystalline semiconductor film by adding the catalyst chemical. SOLUTION: The semiconductor device comprises a first n-channel TFT semiconductor layer including a first impurity region and a second impurity region formed outside a gate electrode, a second n-channel TFT semiconductor layer being arranged so that a part of it overlaps the gate electrode and including a third impurity region arranged outside the gate electrode, and a p-channel TFT semiconductor region including a fourth impurity region arranged so that a part of it overlaps the gate electrode and a fifth impurity region arranged outside of the gate electrode. The catalyst chemical element is moved from the crystalline semiconductor film formed by the catalyst chemical element to the semiconductor film including an inert gas chemical element via a barrier layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor using a semiconductor film having a crystal structure formed on a substrate (hereinafter referred to as a crystalline semiconductor film).
or a TFT hereinafter) and a method for manufacturing the same. In this specification, a semiconductor device generally refers to a device that functions using semiconductor characteristics, and a semiconductor device manufactured according to the present invention is a semiconductor integrated circuit (microprocessor, signal processing circuit, Or a high-frequency circuit or the like) in its category.

[0002]

2. Description of the Related Art A liquid crystal display device having a driving circuit and a pixel portion formed using TFTs on the same substrate has been increasingly formed. A semiconductor film is used as an active layer of a TFT, and among them, a high field-effect mobility has been realized by using a crystalline silicon film as the active layer. The technology is based on a pixel TFT that forms a pixel portion on a single glass substrate,
A monolithic liquid crystal display device in which a TFT of a driving circuit provided around a pixel portion is formed is made possible.

A factor that determines the electrical characteristics of a TFT depends on the quality of a semiconductor film, particularly the field-effect mobility, on the crystallinity. Directly related to the display capability of the liquid crystal display device.

Therefore, methods for forming a high-quality crystalline semiconductor film have been actively studied. For example, a method of once forming an amorphous semiconductor film and then crystallization by irradiating a laser beam, or a method of performing crystallization by performing a heat treatment using an electric furnace is used. However, a semiconductor film manufactured by such a method is composed of a large number of crystal grains, and the crystal orientation cannot be controlled by being oriented in an arbitrary direction. For this reason, carriers do not move smoothly as compared with a single crystal semiconductor, which is a factor that restricts the electrical characteristics of the TFT.

On the other hand, the technology disclosed in Japanese Patent Application Laid-Open No. Hei 7-183540 is a technology for crystallizing a silicon semiconductor film by adding a metal element such as nickel. It is known that it has the effect of promoting heat and lowering the required temperature. In addition, it is possible to enhance the orientation of the crystal orientation. Fe, Ni, Co, Ru, Rh, Pd, Os, I
It is known to be one or more selected from r, Pt, Cu, and Au.

However, since a metal element having a catalytic action (herein, a catalytic element is included in all cases) is added, the metal element remains in the semiconductor film or on the film surface,
There is a problem that the electrical characteristics of the TFT vary.
For example, there is a problem in that the off-state current of the TFT increases, and there is variation among individual elements. In other words, the metal element having a catalytic action on crystallization is unnecessary once the crystalline semiconductor film is formed.

Accordingly, the present applicant applies a gettering technique using phosphorus to remove a metal element added for crystallization from a specific region of a semiconductor film even at a heating temperature of about 500 ° C. A method has been disclosed. For example, phosphorous is added to the source / drain region of the TFT to 450 to 700 ° C.
By performing the heat treatment described above, the metal element added for crystallization can be easily removed from the element formation region.
One example of such a technique is disclosed in Japanese Patent No. 3032801.

Also, by using a high-quality semiconductor film having a high crystal orientation as described above, an active matrix type liquid crystal display device in which a driving circuit and a pixel portion are integrally formed on the same substrate has been developed. became.

A drive circuit of an active matrix type liquid crystal display device is required to have high driving capability (on-current, Ion) and to improve reliability by preventing deterioration due to a hot carrier effect, while a pixel portion has a low off-current ( Ioff)
Is required.

As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, an LDD region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. Among structures that are effective in preventing the deterioration of the on-current value due to hot carriers, an LDD structure in which a part of an LDD region overlaps with a gate electrode (hereinafter, referred to as GOLD with Gate-drain Overlapped LDD omitted) is included. Are known.

[0011]

The present applicant discloses a method of gettering a catalytic element from a semiconductor film after using a low-temperature crystallization process using a catalytic element as described above. For example, a gettering site doped with an element belonging to Group 15 of the periodic table (typically, phosphorus) having a gettering action at a high concentration is formed, and a heat treatment is performed to move the catalytic element to the gettering region. A method for removing gettering sites after this heat treatment step,
A method in which the catalyst element in the semiconductor layer is gettered (moved) to the source region or the drain region in the same heat treatment step as the activation of phosphorus added to the region to be the source region or the drain region later is considered. ing. These gettering enables a metal element introduced into a semiconductor film for crystallization to be removed by performing a heat treatment at 550 ° C. for about 4 hours.

However, the concentration of phosphorus added to the semiconductor film to obtain the gettering action is 1 × 10 ²⁰ / cm ³ or more, preferably 1 × 10 ²¹ / cm ³ , and the semiconductor film is doped with phosphorus. The processing time required for this was a problem. Further, addition of a high concentration of phosphorus by an ion implantation method or an ion doping method (referred to as a method that does not perform mass separation of implanted ions in this specification)
The first is that the subsequent recrystallization of the semiconductor film becomes difficult.
Had the problem of.

Also, in an active matrix type liquid crystal display device integrally formed with a drive circuit, the performance required for the drive circuit and the pixel portion are different. Therefore, when trying to optimize the structure of the TFT according to each requirement. For example, in a method of forming a region including an impurity element such as an LDD region in a self-aligned manner using a gate electrode, the processing accuracy is inevitably deteriorated with an increase in the size of a substrate. In this case, there is a second problem that the manufacturing process is complicated and the number of necessary photomasks is inevitably increased.

As described above, the present invention relates to a technique for solving the first problem relating to a method for removing a catalytic element (metal element) from a crystalline semiconductor film obtained using a catalytic element, It is an object of the present invention to provide a technique for solving the second problem that the manufacturing process becomes complicated when trying to make a TFT structure that meets conditions, and a technique for simultaneously solving the first and second problems. .

[0015]

The present invention is a semiconductor device comprising a first n-channel TFT, a second n-channel TFT, and a p-channel TFT on the same substrate,
The first impurity region and the second impurity region formed in the semiconductor layer of the first n-channel TFT are provided outside the gate electrode, and are formed in the semiconductor layer of the second n-channel TFT. The third impurity region is provided so as to partially overlap the gate electrode, and the third impurity region is provided outside the gate electrode, and the fourth impurity region is formed in the semiconductor layer of the p-channel TFT. The semiconductor device is characterized in that the impurity region is provided so as to partially overlap with the gate electrode, and the fifth impurity region is provided outside the gate electrode.

The present invention also provides a first n-channel type TF
A semiconductor device comprising a T, a second n-channel TFT, and a p-channel TFT on the same substrate, the first being formed in a semiconductor layer of the first n-channel TFT and serving as an LDD region. The impurity region and the second impurity region serving as the source or drain region are provided outside the gate electrode, and are formed in the semiconductor layer of the second n-channel TFT, and the third impurity region serving as the LDD region is A third impurity region provided so as to partially overlap with the gate electrode and serving as a source or drain region is provided outside the gate electrode and is formed in the semiconductor layer of the p-channel TFT to serve as an LDD region. The fourth impurity region is provided so as to partially overlap with the gate electrode, and the fifth impurity region serving as a source or drain region is provided outside the gate electrode. It is characterized in.

According to the present invention, there is provided a liquid crystal display device comprising:
A n-channel TFT and a second n-channel TFT and a p-channel TFT provided in a driver circuit on the same substrate, wherein the semiconductor layer of the first n-channel TFT is The first impurity region and the second impurity region to be formed are provided outside the gate electrode, and the third impurity region is formed in the semiconductor layer of the second n-channel TFT.
Is provided so as to partially overlap the gate electrode, the third impurity region is provided outside the gate electrode, and the fourth impurity region formed in the semiconductor layer of the p-channel TFT is The gate electrode is provided so as to partially overlap with the gate electrode, and the fifth impurity region is provided outside the gate electrode.

Further, according to the present invention, the first
A n-channel TFT and a second n-channel TFT and a p-channel TFT provided in a driver circuit on the same substrate, wherein the semiconductor layer of the first n-channel TFT is First formed to be LDD region
Impurity region and a second region serving as a source or drain region.
The impurity region is provided outside the gate electrode, is formed in the semiconductor layer of the second n-channel TFT, and has an LDD
A third impurity region serving as a region is provided so as to partially overlap with the gate electrode, and a third impurity region serving as a source or drain region is provided outside the gate electrode;
LDD formed in the semiconductor layer of the p-channel TFT
The fourth impurity region serving as a region is provided so as to partially overlap with the gate electrode, and the fifth impurity region serving as a source or drain region is provided outside the gate electrode.

Further, the above invention is characterized in that the second n-channel type TFT is provided in a buffer circuit.

Further, the present invention provides a process for forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalyst element for promoting crystallization to the amorphous semiconductor film to form a first semiconductor film. Forming a crystalline semiconductor film by a heat treatment of
Forming a barrier layer on the crystalline semiconductor film; and forming a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 ×.
Forming a semiconductor film containing a concentration of 10 ²² / cm ³ , transferring the catalytic element to the semiconductor film by a second heat treatment, and removing the semiconductor film;
It is characterized by having.

Further, according to the present invention, a step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalytic element for promoting crystallization to the amorphous semiconductor film, the first Forming a crystalline semiconductor film by a heat treatment of
Irradiating the crystalline semiconductor film with a laser beam; forming a barrier layer on the crystalline semiconductor film; and depositing a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 1
A step of forming a semiconductor film containing a concentration of 0 ²² / cm ³ , a step of transferring the catalytic element to the semiconductor film by a second heat treatment, and a step of removing the semiconductor film.
It is characterized by having.

Further, the present invention provides a step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalyst element for promoting crystallization to the amorphous semiconductor film to form the first semiconductor film. Forming a crystalline semiconductor film by a heat treatment of
Forming a barrier layer on the crystalline semiconductor film; and forming a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 ×.
Forming a semiconductor film containing a concentration of 10 ²² / cm ³ , transferring the catalytic element to the semiconductor film by a second heat treatment, and removing the semiconductor film;
Irradiating the crystalline semiconductor film with laser light.

The present invention also provides a step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, a step of adding a catalytic element for promoting crystallization to the amorphous semiconductor film, Forming a barrier layer on the amorphous semiconductor film; and forming a rare gas element on the barrier layer at 1 × 10 ¹⁹ / cm ^3.
A step of forming a semiconductor film containing a concentration of about 1 × 10 ²² / cm ³ and a heat treatment to crystallize the amorphous semiconductor film to form a crystalline semiconductor film and to form the semiconductor film with the catalytic element. , A step of removing the semiconductor film, and a step of irradiating the crystalline semiconductor film with laser light.

The present invention also provides a step of adding a catalytic element for promoting crystallization to an insulating surface, a step of forming an amorphous semiconductor film containing silicon as a main component on the insulating surface,
Forming a barrier layer on the amorphous semiconductor film; and forming a rare gas element on the amorphous semiconductor film at 1 × 10 ¹⁹ / cm ^3.
A step of forming a semiconductor film containing a concentration of about 1 × 10 ²² / cm ³ and a heat treatment to crystallize the amorphous semiconductor film to form a crystalline semiconductor film and to form the semiconductor film with the catalytic element. , A step of removing the semiconductor film, and a step of irradiating the crystalline semiconductor film with laser light.

The present invention also includes a step of adding a catalytic element for promoting crystallization to an insulating surface, a step of forming an amorphous semiconductor film containing silicon as a main component on the insulating surface,
Forming a barrier layer on the amorphous semiconductor film; and forming a rare gas element on the amorphous semiconductor film at 1 × 10 ¹⁹ / cm ^3.
A step of forming a semiconductor film containing a concentration of about 1 × 10 ²² / cm ³ , a step of adding a rare gas element to the semiconductor film, and a heat treatment to crystallize the amorphous semiconductor film and Forming a semiconductor film and moving the catalytic element to the semiconductor film; removing the semiconductor film; and irradiating the crystalline semiconductor film with laser light.

Further, in the above invention, the barrier layer is a chemical oxide film formed of ozone water.

Further, in the above invention, the barrier layer is formed by oxidizing the surface of the amorphous semiconductor film by plasma treatment.

Further, in the above invention, the barrier layer is formed by irradiating ultraviolet rays in an atmosphere containing oxygen to generate ozone and oxidize the surface of the amorphous semiconductor film.

Further, in the above invention, the barrier layer is formed with a film pressure of 1 to 10 nm and is a porous film.

Further, in the above invention, the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.

[0031] In the above invention, the first heat treatment and the second heat treatment may be one of a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. Alternatively, it is characterized in that it is performed by radiation from a plurality of types.

In the above invention, the first heat treatment is performed using an electric furnace.

Further, in the above invention, the second heat treatment is performed using an electric furnace.

Further, in the above invention, the catalyst element is Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, P
It is characterized by being one or more selected from t, Cu, and Au.

Further, the present invention provides a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first shape conductive layer on the insulating film. A third step of forming a layer, and forming a second layer from the conductive layer having the first shape.
A fourth step of forming a conductive layer having a shape, and a fifth step of forming a first impurity region by adding an impurity element of one conductivity type to the semiconductor layer using the conductive layer having the second shape as a mask. A sixth step of adding one conductivity type impurity element to a selected region of the semiconductor layer using the second shape conductive layer as a mask to form second and third impurity regions; A fifth step of forming fourth and fifth impurity regions by adding an impurity element opposite to one conductivity type to a selected region of the semiconductor layer using the conductive layer having a shape as a mask. And

Also, the present invention provides a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first shape conductive layer on the insulating film. A third step of forming a layer, and forming a second layer from the conductive layer having the first shape.
A fourth step of forming a conductive layer having a shape, and forming a first impurity region by adding an impurity element of one conductivity type to the semiconductor layer at a first dose using the conductive layer having the second shape as a mask. A fifth step of adding a second conductivity type impurity element at a second dose to a selected region of the semiconductor layer using the second shape conductive layer as a mask; Forming a fourth and fifth impurity regions by adding an impurity element opposite to one conductivity type to a selected region of the semiconductor layer using the conductive layer of the second shape as a mask; And a fifth step of forming.

In the above invention, the one conductivity type impurity is an impurity imparting n-type.

In the above invention, the semiconductor layer comprises a crystalline semiconductor film formed by performing a first heat treatment by adding a catalytic element to an amorphous semiconductor film. Forming a semiconductor layer containing a rare gas element at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ on the barrier layer; and performing a second heat treatment on the catalyst layer. Transferring the element to the semiconductor film.

Further, in the above invention, the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.

[0040]

(Embodiment 1) Referring to FIG. 1, after a metal element having a catalytic action is added to the entire surface of an amorphous semiconductor film and crystallized, a rare gas element (this embodiment) is used. A method of forming a semiconductor film containing Ar) and performing gettering using this film as a gettering site will be described.

In FIG. 1A, the material of the substrate 100 is not particularly limited, but barium borosilicate glass, aluminoborosilicate glass, quartz, or the like can be preferably used. On the surface of the substrate 100, an inorganic insulating film with a thickness of 10 to 200 nm is formed as the base insulating film 101. One example of a suitable base insulating film is plasma CV
A silicon oxynitride film formed by a method D
A first silicon oxynitride film made of H ₄ , NH ₃ , and N ₂ O is formed to a thickness of 50 nm, and a _second silicon oxynitride film made of SiH ₄ and N ₂ O is formed to a thickness of 100 nm. Apply the formed one. The base insulating film 101 is provided so that alkali metal contained in the glass substrate does not diffuse into a semiconductor film formed thereover, and can be omitted when quartz is used as the substrate.

The amorphous semiconductor film 102 formed on the base insulating film 101 uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and a plasma CVD method, a low-pressure CVD method, or a
Formed to a thickness of In order to obtain high-quality crystals, the concentration of impurities such as oxygen and nitrogen contained in the amorphous semiconductor film 102 is preferably reduced to 5 × 10 ¹⁸ / cm ³ or less. These impurities are factors that hinder the crystallization of the amorphous semiconductor and increase the density of trapping centers and recombination centers even after crystallization. For this purpose, it is desirable to use not only a high-purity material gas but also an ultra-high vacuum-compatible CVD apparatus provided with a mirror surface treatment (electric polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.

Then, on the surface of the amorphous semiconductor film 102,
A metal element having a catalytic action to promote crystallization is added (FIG. 1B). Examples of metal elements having a catalytic action for promoting crystallization of a semiconductor film include iron (Fe) and nickel (N
i), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (O
s), iridium (Ir), platinum (Pt), copper (C
u), gold (Au), or the like, and one or more selected from them can be used. Typically, nickel is used, and a nickel acetate salt solution containing 1 to 100 ppm by weight of nickel is applied by a spinner to form the catalyst-containing layer 103. In this case, in order to improve the familiarity of the solution, as a surface treatment of the amorphous semiconductor film 102,
An ultra-thin oxide film is formed with an ozone-containing aqueous solution, and the oxide film is etched with a mixture of hydrofluoric acid and hydrogen peroxide to form a clean surface. Is formed. Since the surface of a semiconductor film such as silicon is hydrophobic in nature, a nickel acetate solution can be uniformly applied by forming an oxide film in this manner.

Of course, the catalyst containing layer 103 is not limited to such a method, and may be formed by a sputtering method, a vapor deposition method, a plasma treatment, or the like. The catalyst element-containing layer 103 is formed before the formation of the amorphous semiconductor film 102, that is, the base insulating film 1.
01 may be formed.

Amorphous semiconductor film 102 and catalytic element-containing layer 1
A heat treatment for crystallization is performed while maintaining the state of contact with No. 03. Examples of the heat treatment method include a furnace annealing method using an electric heating furnace and a rapid thermal annealing method using a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, a high-pressure mercury lamp, and the like. (Hereinafter, referred to as RTA method). Considering productivity, it is considered preferable to employ the RTA method.

When the RTA method is used, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds.
It is repeated 1 to 10 times, preferably 2 to 6 times. Although the light emission intensity of the lamp light source is arbitrary, the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably 650 to 75 ° C.
Heat to about 0 ° C. Even at such a high temperature, the semiconductor film is only heated instantaneously, and the substrate 100 itself is not distorted and deformed. Thus, the amorphous semiconductor film is crystallized, and FIG.
Although the crystalline semiconductor film 104 shown in (c) can be obtained, crystallization by such a process can be achieved only by providing a catalyst element-containing layer.

When the furnace annealing method is used as another method, prior to the heat treatment, one hour at 500 ° C.
Heat treatment for about an hour is performed to release hydrogen contained in the amorphous semiconductor film 102. Then, using an electric furnace in a nitrogen atmosphere at 550 to 600 ° C., preferably 580 ° C.
The amorphous semiconductor film 102 is crystallized by performing heat treatment at 4 ° C. for 4 hours. Thus, the crystalline semiconductor film 104 shown in FIG. 1C is formed.

In order to further increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, as shown in FIG.
It is also effective to irradiate 04 with laser light. For the laser light irradiation treatment, a pulse oscillation type or continuous oscillation type gas laser or solid laser may be used. Examples of the gas laser include an excimer laser, an Ar laser, and a Kr laser, and examples of the solid laser include a YAG laser and a YVO ₄ laser.
Laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti:
Sapphire laser and the like can be mentioned. In the case of using these lasers, a laser beam emitted from a laser oscillator may be condensed into a linear, rectangular, or elliptical shape by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 800 mJ / cm ² (typically, 200 to 7 mJ / cm ² ).
00 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and pulse oscillation frequencies 1 to 3 are used.
00 Hz, and a laser energy density of 300 to 10
00 mJ / cm ² (typically 350 to 800 mJ / cm
² ) Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm may be irradiated over the entire surface of the substrate. In the case of using a YVO ₄ laser, a laser beam emitted from a continuous wave YVO ₄ laser of 10W output is converted into a harmonic by a nonlinear optical element, a YVO ₄ crystal and a non-linear optical element in a resonator And may emit harmonics. At this time it may be irradiated with the rectangular shape or an elliptical shape by an optical system, energy density, 0.01 to 100 MW / cm ² about (preferably, 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relatively to the laser light at a speed of about 0.5 to 2000 cm / s.
In any case, using the laser as described above, the laser light is condensed to 100 to 400 mJ / cm ² by an optical system, and the laser processing is performed on the crystalline semiconductor film 104 with an overlap ratio of 90 to 95%. You may go.

The thus obtained crystalline semiconductor film 1
In 05, a catalytic element (here, nickel) remains. It is not evenly distributed in the membrane,
As an average concentration, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ . Of course, even in such a state, it is possible to form various semiconductor elements including the TFT,
The element is removed by gettering by the method described below.

First, a thin layer 106 is formed on the surface of the crystalline semiconductor film 105 as shown in FIG. In this specification, the thin layer 10 provided on the crystalline semiconductor film 105
Reference numeral 6 denotes a layer provided so that the first semiconductor film 105 is not etched when the gettering site is removed later, and is referred to as a barrier layer 106.

The thickness of the barrier layer 106 is about 1 to 10 nm, and a chemical oxide formed by simply treating with ozone water may be used as the barrier layer. Also,
Chemical oxide can be similarly formed by treating with an aqueous solution in which a hydrogen peroxide solution is mixed with sulfuric acid, hydrochloric acid, nitric acid or the like. As another method, the plasma treatment in an oxidizing atmosphere or the oxidation treatment by generating ozone by ultraviolet irradiation in an oxygen-containing atmosphere may be performed. Further, a barrier layer may be formed by heating to about 200 to 350 ° C. using a clean oven to form a thin oxide film. Alternatively, 1 to 5 nm by a plasma CVD method, a sputtering method, an evaporation method, or the like.
An oxide film of a degree may be deposited to form a barrier layer. In any case, in the gettering step, the catalyst element can move to the gettering site side, and in the gettering site removing step, the etchant does not soak (protects the crystalline semiconductor film 105 from the etchant). For example,
A chemical oxide film, a silicon oxide film (SiOx), or a porous film formed by treatment with ozone water may be used.

Next, as a gettering site 107 on the barrier layer 106 by a sputtering method, a second semiconductor film containing a rare gas element at a concentration of 1 × 10 ²⁰ / cm ³ or more (typically, a non- Crystalline silicon film) 25-250 nm
Formed with a thickness of In order to increase the selectivity between the gettering site 107 and the crystalline semiconductor film 105 to be etched later, it is preferable to form a film having a low density.

In this embodiment, the film formation pressure is set to 0.2 to
FIG. 9 shows the result of measuring the concentration of Ar in the formed film by sequentially shaping the film at intervals of 0.2 Pa up to 1.2 Pa. The film forming conditions other than the pressure are as follows:
ccm, the film formation power was 3 kW, and the substrate temperature was 150 ° C.

FIG. 9 shows that the lower the film formation pressure is,
It can be seen that the Ar concentration in the film increases and a film suitable as a gettering site can be formed. The reason is that the lower the deposition pressure of the sputtering, the smaller the probability of collision between the Ar gas in the reaction chamber and the recoil atoms (Ar atoms reflected on the target surface), so that the recoil atoms are likely to be incident on the substrate. It can be raised. Therefore, based on the above experimental results, when the apparatus of the present embodiment is used, the film forming pressure is set to 0.2 to
If the pressure is set to 1.0 Pa and the other conditions shown in Table 1 are adopted, the rare gas element is added in an amount of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²² / c.
m ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / c
m ³ , more preferably at a concentration of 5 × 10 ²⁰ / cm ³ ,
A semiconductor film having a gettering effect can be formed by a sputtering method.

It should be noted that the rare gas element itself is inactive in the semiconductor film, and therefore does not adversely affect the crystalline semiconductor film 105. As the rare gas element, one or a plurality of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. The present invention uses these rare gas elements as an ion source to form a gettering site, and also forms a semiconductor film containing these elements,
The feature is that this film is used as a gettering site.

In order to achieve the gettering reliably, it is necessary to perform a heat treatment thereafter. The heat treatment is performed by a furnace annealing method or an RTA method. When the furnace annealing method is used, 450 to 600 ° C. in a nitrogen atmosphere
For 0.5 to 12 hours. When the RTA method is used, a heating lamp light source is used for 1 to 60 seconds.
It is preferably turned on for 30 to 60 seconds, and it is turned on 1 to 10 times,
Preferably, it is repeated 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is
The temperature is set to about 000 ° C, preferably about 700 to 750 ° C.

In gettering, the catalytic element in the region to be gettered (capture site) is released by thermal energy and moves to the gettering site by diffusion. Therefore, gettering depends on the processing temperature, and the higher the temperature, the faster the gettering proceeds. In the present invention, as shown by an arrow in FIG. 2C, the distance that the catalyst element moves during gettering is about the thickness of the semiconductor film, and the gettering must be completed in a relatively short time. Can be.

Note that 1 × 10 ¹⁹
/ Cm ³ -1 × 10 ²¹ / cm ³ , preferably 1 × 10 ²⁰ / cm ³
cm ³ -1 × 10 ²¹ / cm ³ , more preferably 5 × 10 ²⁰
The semiconductor film 107 containing a rare gas element at a concentration of / cm ³ does not crystallize. This is considered to be because the rare gas element is not re-emitted even in the above-mentioned processing temperature range and remains in the film to inhibit crystallization of the semiconductor film.

As shown in FIG. 14, three patterns of the rare gas containing region 109 can be considered for the semiconductor film (gettering site) 107 containing a rare gas. FIG. 14 (a)
Indicates that the rare gas element is present halfway in the film pressure of the gettering site 107. In this case, the gettered catalyst element can be moved to the rare gas existence region 109 distant from the crystalline semiconductor film 105.
FIG. 14B shows a state in which a rare gas element exists in the entire gettering site 107 film. In this case, since the movement distance of the catalyst element is short, gettering can be performed in a short time. FIG. 14C shows a state in which a rare gas is present from the gettering site 107, passes through the barrier layer 106, and reaches the crystalline semiconductor film 105. It is considered that the barrier layer 106 becomes porous under the influence of a rare gas element having a different atomic size. For this reason, it is considered that the catalyst element easily moves to the gettering site. Note that the rare gas element itself is inactive in the semiconductor film, and thus does not adversely affect the crystalline semiconductor film 105. Sputtering method or plasma CV
Regardless of which of the methods D is used, if the power of film formation is changed, the rare gas existence region shown in FIGS. 14A to 14C can be obtained.

After completion of the gettering step, the amorphous semiconductor 1
07 is selectively etched away. As an etching method, dry etching without plasma using ClF ₃ , hydrazine, tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NO
It can be performed by wet etching using an alkaline solution such as an aqueous solution containing H). At this time, the barrier layer 106 functions as an etching stopper. Also, barrier layer 1
06 may then be removed with hydrofluoric acid.

In this way, as shown in FIG. 2C, a crystalline semiconductor film 108 in which the concentration of the catalytic element is reduced to 1 × 10 ¹⁷ / cm ³ or less can be obtained. The crystalline semiconductor film 108 thus formed is formed as a thin rod-shaped crystal or a thin flat rod-shaped crystal by the action of a catalyst element, and each crystal grows in a specific direction when viewed macroscopically. Such a crystalline semiconductor film 108 can be applied not only to an active layer of a TFT but also to a photoelectric conversion layer of a photosensor or a solar cell.

(Embodiment 2) As a method of forming a semiconductor film containing a rare gas element as a gettering site,
A plasma CVD method can also be used.

After forming the barrier layer 106 according to the first embodiment, a semiconductor film 107 containing a rare gas element is formed on the barrier layer 106 by a plasma CVD method to a thickness of 25 to 250 nm.

The material gas is Ar: SiH ₄ = 500: 10
0 sccm, film formation pressure of 33.3 Pa, power of 35
W, the substrate temperature is set to 300 ° C., and after forming the semiconductor film 107 containing a rare gas element, heat treatment is performed to convert the catalyst element in the crystalline semiconductor film 105 to a gettering site (semiconductor film containing a rare gas) 107. Can be moved. Thus, even if the gettering site is formed by the plasma CVD method, the concentration of the catalyst element is 1 × 10 ¹⁷ /
The crystalline semiconductor film 108 reduced to cm ³ or less can be obtained.

As shown in FIG. 17C, after forming the semiconductor film 107 containing a rare gas, the semiconductor film 107 containing a rare gas is further doped with a rare gas element (helium (He) by an ion doping method. , Neon (Ne), argon (A
r), krypton (Kr) and xenon (Xe)). As described above, after the semiconductor film 107 containing a rare gas is formed, the barrier layer 106 can be made porous by performing a step of adding a rare gas having a different atomic size. Further, a large strain is generated in the semiconductor film 107, and the etching selectivity with the crystalline semiconductor film 105 can be increased.

(Embodiment 3) FIG. 7 is a view for explaining an embodiment of the present invention. After a semiconductor film having a crystal structure is formed by heat treatment, gettering is performed, and furthermore, strong light such as laser light is irradiated. A method for improving crystallinity by irradiation will be described. In FIG. 7, the description will be made using the same reference numerals as those in FIGS.

FIGS. 7A and 7B show the first embodiment.
This is a process similar to that described above.
1. After forming the amorphous semiconductor film 102 and the catalyst element-containing layer 103, a crystalline semiconductor film 104 is formed by heat treatment.

Thereafter, as shown in FIG. 7C, a barrier layer 106 is formed on the surface of the crystalline semiconductor film 104, and a semiconductor film 107 containing a rare gas element is formed. The semiconductor film 107 contains a rare gas element at 1 × 10 ^{20 to} 2.5
The film is formed by a sputtering method or a plasma CVD method so as to be contained at a concentration of × 10 ²² / cm ³ .

Then, as shown in FIG. 7D, a heat treatment is performed by a furnace annealing method or an RTA method. In the case of performing the furnace annealing method, 450-
A heat treatment is performed at 600 ° C. for 0.5 to 12 hours. Also,
When using the RTA method, the lamp light source for heating is 1 to
Light for 60 seconds, preferably 30-60 seconds,
Repeat 10 times, preferably 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but the semiconductor film is
The temperature is set to be about 100 to 1000 ° C., preferably about 700 to 750 ° C. In addition, YAG laser, YL
Second harmonic (wavelength 532n) of F laser and YVO ₄ laser
m) can also perform gettering. In gettering, the catalytic element at the capture site is released by thermal energy and moves to the gettering site by diffusion. Therefore, gettering depends on the processing temperature, and the higher the temperature, the faster the gettering proceeds. As shown by the arrow in FIG. 7D, the direction in which the catalytic element moves is a distance about the thickness of the semiconductor film, and the gettering is completed in a relatively short time.

It should be noted that even with this heat treatment, 1 × 10
¹⁹ / cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰
/ Cm ³ to 1 × 10 ²¹ / cm ³ , more preferably 5 × 10
^The semiconductor film 107 containing a rare gas element at a concentration of ²⁰ / cm ³ does not crystallize. This is considered to be because the rare gas element is not re-emitted even in the above-mentioned processing temperature range and remains in the film to inhibit crystallization of the semiconductor film.

Thereafter, the semiconductor film 107 is selectively etched and removed. As an etching method, ClF
_{3 can be performed} by dry etching without using plasma, or wet etching with an alkali solution such as an aqueous solution containing hydrazine or tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH). At this time, the barrier layer 106 functions as an etching stopper. After that, the barrier layer 106 may be removed with hydrofluoric acid.

In order to further increase the crystallization ratio (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, a semiconductor film having a crystal structure as shown in FIG. It is also effective to irradiate 104 with laser light. As the laser, excimer laser light having a wavelength of 400 nm or less, or the second or third harmonic of a YAG laser is used. In any case, repetition frequency 10 to 1000H
Using a pulse laser beam of about z, the laser beam is focused to 100 to 400 mJ / cm ² by an optical system, and 90 to 95 mJ / cm ^2.
The crystalline semiconductor film 108 is formed by irradiation with a% overlap rate.

(Embodiment 4) FIG. 8 is a view for explaining an embodiment of the present invention, in which a metal element having a catalytic action is added to the entire surface of an amorphous semiconductor film to crystallize and gettering. It is a method that is performed simultaneously.

First, as shown in FIG. 8A, a catalytic element containing layer 302 is formed on a base insulating film 301. This may be formed by applying an aqueous solution or an alcohol solution containing a catalyst element by a spinner, or may be formed by a sputtering method, an evaporation method, a plasma treatment, or the like.

Thereafter, as shown in FIG. 8B, an amorphous semiconductor film 303 is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method.
Further, a barrier layer 304 is formed. These forming methods are the same as in the first embodiment.

As shown in FIG. 8 (C), the embodiment
The sputtering method described in Embodiment 1 and the plasma described in Embodiment 2.
1 × 10 rare gas elements by CVD¹⁹/ Cm^Three~ 1 × 10
^{twenty two}/ Cm^Three, Preferably 1 × 10²⁰~ 1 × 10^{twenty one}/ C
m^Three, More preferably 5 × 10 ²⁰/ Cm^ThreeHalf containing the concentration of
The conductive film 305 is formed with a thickness of 25 to 250 nm. Teens
Specifically, an amorphous silicon film is selected. This semiconductor film 3
05 is a film with low density because it is removed later.
Is desirable.

Then, a heat treatment is performed as shown in FIG. The heat treatment is performed by a furnace annealing method using an electric furnace or an RTA method using a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, a high-pressure mercury lamp, or the like.

In the case of performing the RTA method, the heating lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds.
It is repeated 1 to 10 times, preferably 2 to 6 times. Although the light emission intensity of the lamp light source is arbitrary, the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably 650 to 75 ° C.
Heat to about 0 ° C. Even at such a high temperature, the semiconductor film is only heated instantaneously, and the substrate 100 itself is not distorted and deformed. When the furnace annealing method is used,
Prior to the heat treatment, heat treatment at 500 ° C. for about 1 hour is performed to release hydrogen contained in the semiconductor film 303 having an amorphous structure. Then, using an electric furnace in a nitrogen atmosphere at 550 to 600 ° C, preferably at 580 ° C for 4 hours.
A heat treatment is performed for a long time to perform crystallization.

By this heat treatment, the catalyst element seeps into the semiconductor film 303 having an amorphous structure, and diffuses toward the semiconductor film 305 (in the direction of the arrow in FIG. 8D) while being crystallized. Thereby, crystallization and gettering are performed simultaneously by one heat treatment.

After that, the semiconductor film 305 is selectively etched and removed. As an etching method, ClF
_{3 can be performed} by dry etching without using plasma, or wet etching with an alkali solution such as an aqueous solution containing hydrazine or tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH). At this time, the barrier layer 304 functions as an etching stopper. The barrier layer 304 may be removed with hydrofluoric acid thereafter.

Thus, as shown in FIG. 8E, a semiconductor film (first semiconductor film) 306 having a crystal structure in which the concentration of the catalytic element is reduced to 1 × 10 ¹⁷ / cm ³ or less can be obtained. . In order to increase the crystallinity of the crystalline semiconductor film 306, laser light irradiation may be performed as in the first embodiment.

The crystalline semiconductor film 306 thus formed
Is formed as a thin rod-shaped or flat rod-shaped crystal by the action of a catalytic element, and each crystal grows in a specific direction when viewed macroscopically. Such a crystalline semiconductor film 306 can be applied not only to an active layer of a TFT but also to a photoelectric conversion layer of a photosensor or a solar cell.

[0083]

(Embodiment 1) An embodiment of the present invention will be described with reference to FIGS. Here, a pixel portion and a TFT (n-channel type TFT) of a driver circuit provided around the pixel portion are provided over the same substrate.
A method for simultaneously manufacturing an FT and a p-channel TFT will be described in detail.

In FIG. 1A, a substrate 100 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Then, as shown in FIG.
A base insulating film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is formed on the substrate 0. A typical example is the base insulating film 101.
And has a two-layer structure, SiH ₄ , NH ₃ , and N ₂ O
Silicon oxynitride film 1 formed by using as a reaction gas
50~100nm the 01a, SiH _4, and N ₂ O and the second silicon oxynitride film 101b which is formed as a reaction gas
Is formed in a thickness of 100 to 150 nm.

The semiconductor film used as the active layer is obtained by crystallizing the amorphous semiconductor film formed on the base film 101. The amorphous semiconductor film is formed to have a thickness of 30 to 60 nm, and then a metal element having a catalytic action for promoting crystallization (nickel in this embodiment) is converted to a weight on the surface of the amorphous semiconductor film 102. Then, a nickel acetate salt solution containing 1 to 100 ppm of nickel is applied by a spinner to form a catalyst-containing layer 103 (FIG. 1B).

Amorphous Semiconductor Film 102 and Catalyst Element-Containing Layer 1
A heat treatment for crystallization is performed while maintaining the state of contact with No. 03. In this embodiment, the heat treatment is performed by the RTA method. The heating lamp light source is used for 1 to 60 seconds, preferably 30 seconds.
Light up for ~ 60 seconds and turn it on 1 to 10 times, preferably 2 to
Repeat 6 times. The light emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably to about 650 to 750 ° C. Even at such a high temperature, the semiconductor film is only heated instantaneously, and the substrate 100 itself is not distorted and deformed. Thus, the amorphous semiconductor film is crystallized to obtain the crystalline semiconductor film 104 shown in FIG.

In order to further increase the crystallization ratio (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, as shown in FIG.
04 is irradiated with a laser beam. For the laser light irradiation treatment, a pulse oscillation type or continuous oscillation type gas laser or solid laser may be used. Examples of the gas laser include an excimer laser, an Ar laser, and a Kr laser, and examples of the solid-state laser include a YAG laser, a YVO ₄ laser, and a YLF laser.
Laser, YAlO ₃ laser, glass laser, ruby laser, alex hydride laser, Ti: sapphire laser, and the like. In the case of using these lasers, a laser beam emitted from a laser oscillator may be condensed into a linear, rectangular, or elliptical shape by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 100 nm.
800 mJ / cm ² (typically 200 to 700 mJ / c
m ² ). When a YAG laser is used, the second harmonic is used, the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ /.
cm ² (typically 350 to 800 mJ / cm ² ). And a width of 100 to 1000 μm, for example 400 μ
The laser beam condensed linearly at m may be irradiated over the entire surface of the substrate. When a YVO ₄ laser is used, the output 1
A laser beam emitted from a 0 W continuous oscillation YVO ₄ laser is converted into a harmonic by a non-linear optical element, and a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a harmonic. Good. At this time, irradiation may be performed in a rectangular or elliptical shape using an optical system.
About 01 to 100 MW / cm ² (preferably 0.1 to
10 MW / cm ² ) is required. And 0.5-2
Irradiation may be performed by moving the semiconductor film relatively to laser light at a speed of about 000 cm / s. In any case, using a laser as described above, the laser light is focused to 100 to 400 mJ / cm ² by an optical system,
The crystalline semiconductor film 104 has an overlap ratio of 5%.
May be subjected to laser processing.

Next, gettering is performed to remove the catalytic element contained in the crystalline semiconductor film 105.
As shown in FIG. 2A, a barrier layer 106 is formed on the crystalline semiconductor film 105. As the barrier layer 106, a porous film that allows a catalyst element (nickel) to penetrate the gettering site and that does not permeate the etchant used in the step of removing the gettering site is formed. For example, a chemical oxide film or a silicon oxide film (SiOx) formed by treatment with ozone water may be used. In the present specification, a film having such properties is particularly called a porous film.

Next, a semiconductor film 107 containing a rare gas element is formed as a gettering site. In this embodiment,
The flow rate of Ar was 50 sccm, the deposition pressure was 0.2 Pa, the power was 3 kW, the substrate temperature was 150 ° C., and the rare gas element was 1 ×
10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ to
1 × 10 ²¹ / cm ³ , more preferably 5 × 10 ²⁰ / cm ³
The semiconductor film 107 containing a concentration of is formed.

After that, heat treatment is performed by using the RTA method,
The catalyst element is moved vertically to the gettering site.
As the heating conditions, a lamp light source for heating is used for 1 to 60 seconds,
It is preferably turned on for 30 to 60 seconds, and it is turned on 1 to 10 times,
Preferably, it is repeated 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is
The temperature is set to about 000 ° C, preferably about 700 to 750 ° C.

After completion of the gettering step, the amorphous semiconductor 1
07 is selectively etched away. As an etching method, dry etching without plasma using ClF ₃ , hydrazine, tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NO
It can be performed by wet etching using an alkaline solution such as an aqueous solution containing H). At this time, the barrier layer 106 functions as an etching stopper. Also, barrier layer 1
06 may then be removed with hydrofluoric acid.

In order to improve the crystallization, after the crystallization step,
Irradiation with laser light may be performed. After that, the obtained crystalline semiconductor film is etched into a desired shape to form semiconductor layers 1102 to 1106 separated into islands.

After the formation of the semiconductor layers 1102 to 1106, an impurity element imparting p-type may be added in order to control the threshold (Vth) of the n-channel TFT. Boron (B), aluminum (Al), gallium (Ga) are the impurity elements that impart p-type to the semiconductor.
For example, Group 13 elements of the periodic rule are known.

Next, the semiconductor layer 110 separated in an island shape
A gate insulating film 1107 covering the layers 2 to 1106 is formed.
The gate insulating film 1107 is formed by a plasma CVD method or a sputtering method, and has a thickness of 40 to 150 nm and is formed of an insulating film containing silicon. Of course, as the gate insulating film, an insulating film containing silicon can be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after formation.

The gate insulating film 1107 has a thickness of 20 to 1
Tantalum nitride (TaN) as the first conductive film of 00 nm
1108 and tungsten (W) 1109 as a second conductive film having a thickness of 100 to 400 nm are stacked. As a conductive material for forming the gate electrode, Ta,
It is formed of an element selected from W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the aforementioned element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a tantalum (TaN) film. , An Al film, a first conductive film formed of a tantalum nitride (TaN) film, and a second conductive film formed of a Cu film.

Next, as shown in FIG. 3B, masks 1101 to 1115 made of resist are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. ICP (Inductivel)
y Coupled Plasma (inductively coupled plasma) etching method is preferably used. There is no limitation on the etching gas used, but it is suitable to use CF ₄ , Cl ₂ and O ₂ for etching W or TaN. Each gas flow ratio is 2
At 5:25:10 sccm, 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

After that, the etching conditions were changed to the second etching conditions, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30:30 sccm, and 500 W RF was applied to the coil-type electrode at a pressure of 1 Pa. (13.56 MHz) Power is supplied to generate plasma, and etching is performed for about 30 seconds. 20W RF on substrate side (sample stage)
(13.56 MHz) Power is applied and a substantially negative self-bias voltage is applied. _Second mixture of CF ₄ and Cl 2
Under the above etching conditions, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, by the first etching process, the first shape conductive layers 1117 to 1122 (the first conductive layer) including the first conductive layer and the second conductive layer are formed.
Conductive layers 1117a to 1122a and second conductive layer 111
7b to 1122b) are formed. Reference numeral 1116 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 1117 to 1122 is etched by about 20 to 50 nm to form a thinned region.

Next, a mask 11010 made of resist is used.
Without removing 1115, as shown in FIG.
Performs a switching process. CF for etching gas_FourAnd Cl_Two
And O _TwoAnd the respective gas flow ratios are 20:20:
20 sccm and 5 Pa on the coil type electrode at a pressure of 1 Pa.
00W RF (13.56 MHz) power
Etching is performed by generating gaps. Substrate side (sample stay
20) RF (13.56 MHz) power
Lower self-bias voltage than the first etching process.
Is applied. The W film is etched under the third etching condition.
Switch. Thus, the third etching condition
Anisotropically etching the W film to form the second shape conductive layer 1
124 to 1129 (first conductive layers 1124a to 1129)
a and second conductive layers 1124b to 1129b) are formed.
You. Reference numeral 1123 denotes a gate insulating film, which is a first shape conductive film.
The area not covered by the layers 1117 to 1122 is 20 to 50 n
A region thinned by etching by about m is formed.

The etching reaction of the W film or the TaN film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressures of the fluorides of W and TaN with the chlorides, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , and TaCl ₅ are comparable. Therefore, with the mixed gas of CF ₄ and Cl ₂ , both the W film and the TaN film are etched. However, an appropriate amount of O
_{When 2} is added, CF ₄ and O ₂ react to become CO and F,
F radicals or F ions are generated in large quantities. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in TaN, the increase in the etching rate is relatively small even if the F increases. Further, since TaN is more easily oxidized than W, the surface of TaN is slightly oxidized by adding O ₂ . Since the oxide of TaN does not react with fluorine or chlorine, the etching rate of the TaN film is further reduced. Therefore, it is possible to make a difference in the etching rate between the W film and the TaN film, and the etching rate of the W film is made to be Ta.
It can be made larger than the N film.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1.5 × 10 ¹⁴ atoms.
/ Cm ² and an acceleration voltage of 60 to 100 KV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. In this case, the second shape conductive layers 1124 to 1128 serve as a mask for the impurity element imparting n-type, and first impurity regions 1130 to 1134 are formed in a self-aligned manner. The first impurity regions 1130 to 1134 have 1 × 1
An impurity element imparting n-type is added in a concentration range of 0 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .

Next, as shown in FIG. 4A, masks 1135 and 1136 made of resist are formed, and a second doping process is performed. The mask 1135 is a mask for protecting a channel formation region of a semiconductor layer forming a p-channel TFT of a driver circuit and a peripheral region thereof.
Reference numeral 36 denotes a mask for protecting a channel forming region of a semiconductor layer forming a TFT of a pixel portion and a peripheral region thereof.

The ion doping in the second doping process
The condition of the step method is that the dose amount is 1.5 × 10¹⁵atoms / c
m^TwoAnd an acceleration voltage of 60 to 100 KV
(P) is doped. Here, the second shape conductive layer
1124 to 1128 and the thickness of the gate insulating film 1123.
An impurity region is formed in each semiconductor layer using the difference. Of course,
Phosphorus (P) is placed in the area covered by the disks 1135 and 1136.
Is not added. Thus, the second impurity region 1180
To 1182 and the third impurity regions 1137 to 1141 are formed.
Is done. The third impurity regions 1137 to 1141 have 1
× 10²⁰~ 1 × 10 ^{twenty one}/ Cm^ThreeN type in the concentration range of
Impurity element is added. Also, the second impurity
The region is different from the third impurity region due to the thickness difference of the gate insulating film.
1 × 10¹⁸~ 1 × 10¹⁹/ Cm
^ThreeN-type impurity element is added in the concentration range of
Will be.

Next, a new mask 1 made of resist is used.
142 to 1144 are formed, and a third doping process is performed as shown in FIG. By the third doping treatment, a fourth impurity region 1147 and a fifth impurity region 1145, 114 in which an impurity element imparting p-type conductivity is added to a semiconductor layer forming a p-channel TFT.
6 is formed. The fourth impurity region is formed in a region overlapping with the second shape conductive layer, and is 1 × 10 ¹⁸ to 1 ×
An impurity element imparting p-type conductivity is added in a concentration range of 10 ²⁰ / cm ³ . Further, the fifth impurity region 11
To 45 and 1146, an impurity element imparting p-type conductivity is added in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Although the fifth impurity region 1146 is a region to which phosphorus (P) is added in the previous step, the concentration of the impurity element imparting p-type is 1.5 to 3 times that of the fifth impurity region 1146, and the conductivity type Is p-type.

The fifth impurity regions 1148 and 114
The ninth and fourth impurity regions 1150 are formed in a semiconductor layer forming a storage capacitor in the pixel portion.

In the above steps, each semiconductor layer has n
An impurity region having a conductivity type of p-type or p-type is formed. The second shape conductive layers 1124 to 1127 serve as gate electrodes. The second shape conductive layer 1128 serves as one electrode forming a storage capacitor in the pixel portion. Further, the second shape conductive layer 1129 forms a source wiring in the pixel portion.

Next, a first interlayer insulating film 1151 covering almost the entire surface is formed. This first interlayer insulating film 1151
Is formed of an insulating film containing silicon and hydrogen with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. A preferable example is a 150-nm-thick silicon oxynitride film formed by a plasma CVD method. Needless to say, the first interlayer insulating film 1151 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Thereafter, a step of activating the impurity element added to each semiconductor layer is performed. This activation is realized by performing a heat treatment using a furnace annealing furnace or a clean oven. The temperature of the heat treatment is 400 to 700 ° C in a nitrogen atmosphere, typically 410 to 50 ° C.
Perform at 0 ° C. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

At the same time as the activation treatment, nickel used as a catalyst at the time of crystallization is gettered by the third impurity regions 1137, 1139, 1140 and the fifth impurity regions 1146, 1149 containing a high concentration of phosphorus. In addition, the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. As a result, a TFT having a channel formation region
Since the off-state current value is low and the crystallinity is good, high field-effect mobility can be obtained, and good characteristics can be achieved.

Next, as shown in FIG. 5, a second interlayer insulating film 1174 made of an organic insulating material is formed on the first interlayer insulating film 1151. Next, the source wiring 1127
And a contact hole reaching each impurity region.

After that, wirings and pixel electrodes are formed using Al, Ti, Mo, W or the like. For example, a film thickness of 50 to 2
A laminated film of a 50 nm Ti film and an alloy film (alloy film of Al and Ti) having a thickness of 300 to 500 nm is used. Thus, the source or drain wirings 1153 to 1158, the gate wiring 1160, the connection wiring 1159, the pixel electrode 116
1 is formed.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03, a driving circuit 406 having
04 and the pixel portion 407 having the storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience. still,
The TFT of the pixel portion 407 may be a p-channel TFT.

The n-channel TFT 40 of the drive circuit 406
1 (second n-channel TFT) is a channel forming region 1
162, conductive layer 11 of second shape forming gate electrode
24, and a third impurity region 1164 functioning as a source region or a drain region. The p-channel TFT 402 includes a channel formation region 1165, a fourth impurity region 1166 which partially overlaps the second shape conductive layer 1125 which forms a gate electrode, and a fifth impurity region 1167 which functions as a source or drain region. Have. In the n-channel TFT 403 (a second n-channel TFT), a channel formation region 1168, a second impurity region 1169 which partially overlaps the second shape conductive layer 1126 which forms a gate electrode, and a source or drain region And has a third impurity region 1170 functioning as. With such an n-channel TFT and a p-channel TFT, a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed. In particular, in a buffer circuit having a high drive voltage, an n-channel TFT 401 or 4 is provided for the purpose of preventing deterioration due to the hot carrier effect.
03 is suitable.

The pixel TFT 404 (first n-channel TFT) of the pixel portion 407 has a channel forming region 1171,
First impurity region 1172 formed outside second shape conductive layer 1128 forming a gate electrode and third impurity region 1 functioning as a source region or a drain region
173. Further, a fourth impurity region 117 is provided in the semiconductor layer functioning as one electrode of the storage capacitor 405.
6. A fifth impurity region 1177 is formed. The storage capacitor 405 includes a second shape electrode 1129 and a semiconductor layer 110 using an insulating film (the same film as the gate insulating film) as a dielectric.
6 are formed.

FIG. 6 shows a top view of such a pixel portion 407. FIG. FIG. 6 shows a top view of substantially one pixel, and the reference numerals assigned are the same as those in FIG. Further, the cross-sectional structure taken along line AA ′ and line BB ′ corresponds to FIG. In the pixel structure in FIG. 6, by forming the gate wiring and the gate electrode on different layers, the gate wiring and the semiconductor layer can be overlapped, and a function as a light-blocking film is added to the gate wiring. Further, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light, so that formation of a light-shielding film (black matrix) can be omitted. As a result, it is possible to improve the aperture ratio as compared with the related art.

According to the present invention, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel portion and the driving circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, the n-channel type TFT has a change in the LDD structure according to the circuit specifications. As described above, the n-channel TFT of the driver circuit has an LDD structure in which part of the TFT overlaps with the gate electrode, so that the TFT is mainly prevented from being deteriorated due to the hot carrier effect. The n-channel TFT in the pixel portion is an LD which does not overlap with the gate electrode.
The D structure is a structure that mainly focuses on reducing off-state current. The present invention provides a technique for forming a p-channel TFT on the same substrate, in addition to an n-channel TFT having such a different structure, so that it can be manufactured using six photomasks. Further, when the pixel electrode is formed using a transparent conductive film, a transmissive display device can be formed although the number of photomasks is increased by one.

(Embodiment 2) In this embodiment, the present invention can be applied to a manufacturing process of a bottom gate type TFT. A manufacturing process of a bottom-gate TFT will be briefly described with reference to FIGS.

On a substrate 50, an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like is formed (not shown), and a conductive film is formed to form a gate electrode.
The gate electrode 51 is obtained by patterning into a desired shape.
As the conductive film, a conductive film mainly containing an element selected from Ta, Ti, W, Mo, Cr, or Al or any element may be used (FIG. 15A).

Next, a gate insulating film 52 is formed. The gate insulating film may have a single-layer structure of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a stacked structure of any of the films (FIG. 15B).

Next, an amorphous silicon film 53 is formed as an amorphous semiconductor film by thermal CVD, plasma CVD, low pressure CVD, vapor deposition or sputtering.
It is formed to a thickness of about 1150 nm. The gate insulating film 52
Since the amorphous silicon film 53 and the amorphous silicon film 53 can be formed by the same film forming method, both may be continuously formed. The continuous formation eliminates exposure to the atmosphere once, prevents surface contamination, and reduces variation in characteristics of the TFT to be manufactured and fluctuation in threshold voltage (FIG. 15C).

Next, a catalytic element for promoting crystallization is applied to the amorphous silicon film 53 to form a catalytic element-containing layer 5.
4 is formed. Subsequently, heat treatment is performed to form a crystalline silicon film 55.

After the crystallization step, a barrier layer 56 is formed on the crystalline silicon film 55. As the barrier layer 56, a film as described in Embodiment 1 may be used. In this embodiment, the catalyst element (nickel) can be penetrated into the gettering site, and furthermore, a porous film that does not permeate the etching solution used in the step of removing the gettering site, or a treatment with ozone water is performed. A chemical oxide film to be formed is formed (FIG. 15
(D)).

Next, a semiconductor film 57 containing a rare gas element is formed as a gettering site. In this embodiment, A
The flow rate of r was 50 sccm, the deposition pressure was 0.2 Pa, the power was 3 kW, the substrate temperature was 150 ° C., and the rare gas element was 1 × 1.
0 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ to 1
A semiconductor film 57 containing a concentration of × 10 ²¹ / cm ³ , more preferably 5 × 10 ²⁰ / cm ³ is formed.

Next, heat treatment for moving (gettering) the catalytic element from the crystalline semiconductor film 55 to the gettering site 57 is performed. The heat treatment is performed by the RTA method,
Any of the furnace annealing methods may be used. By this heat treatment, the catalytic element concentration of the crystalline semiconductor film 55 is reduced to 1
× can be reduced to 10 ¹⁷ / cm ³ or less.
After the end of the gettering step, the gettering site 57 and the barrier layer 56 are removed.

Next, an insulating film 5 for protecting the crystalline silicon film (channel forming region) in a later impurity doping step.
8 is formed with a thickness of 100 to 400 nm. This insulating film
It is formed to prevent the crystalline silicon film from being directly exposed to plasma when adding an impurity element and to enable fine concentration control.

Next, an impurity element for imparting n-type to a crystalline silicon film to be an active layer of an n-channel TFT later and a crystalline material to be an active layer of a p-channel TFT later are formed by using a resist mask. A p-type impurity element is added to the silicon film to form a source region, a drain region, and an LDD region.

Next, a step of activating the impurity element added to the crystalline silicon film is performed. Subsequently, after removing the insulating film on the crystalline silicon film and patterning the crystalline silicon film into a desired shape, an interlayer insulating film 59 is formed. The interlayer insulating film is a silicon oxide film, a silicon nitride film,
500 to 1500n from insulating film such as silicon oxynitride film
It is formed with a thickness of m. Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed, and a wiring 60 for electrically connecting each TFT is formed.

As described above, the present invention can be applied regardless of the shape of the TFT.

(Embodiment 3) FIG. 10 is an example showing a structure of a light emitting device of an active matrix drive system. The n-channel TFT 652, p of the driving circuit portion 650 shown here
The channel type TFT 653, the switching TFT 654 of the pixel portion 651, and the current controlling TFT 655 are manufactured in the same manner as in the first embodiment by using the present invention.

A first interlayer insulating film 618 made of silicon nitride or silicon oxynitride is formed over the gate electrodes 608 to 611 and used as a protective film. Further, as a planarizing film, a second interlayer insulating film 619 made of an organic resin material such as polyimide or acrylic is formed.

The circuit configuration of the drive circuit section 650 differs between the gate signal side drive circuit and the data signal side drive circuit, but is omitted here. Wirings 612 and 613 are connected to the n-channel TFT 652 and the p-channel TFT 653, and a shift register, a latch circuit, a buffer circuit, and the like are formed using these TFTs.

In the pixel portion 651, the data line 614 is connected to the source side of the switching TFT 654, and the drain side line 615 is connected to the gate electrode 611 of the current control TFT 655. The current control TFT 65
The source side of No. 5 is connected to the power supply wiring 617, and the electrode 616 on the drain side is connected to the anode of the light emitting element.

On these wires, a third interlayer insulating film 620 made of an organic insulating material such as silicon nitride is formed. The organic resin material has a hygroscopic property and has a property of absorbing H ₂ O. Part H ₂ O is oxygen is supplied to the organic compound if it is re-emitted, so causing degradation of the organic light emitting device, in order to prevent occlusion and re-emission of H ₂ O, 3
A fourth insulating film 621 made of silicon nitride or silicon oxynitride is formed on the interlayer insulating film 620 of FIG. Alternatively, the third interlayer insulating film 620 is omitted, and the fourth insulating film 6
It is also possible to form this layer with only one of the layers 21.

The organic light emitting element 627 is formed on the fourth insulating film 621, and is formed of a transparent conductive material such as ITO (indium tin oxide), an anode 622, a hole injection layer, a hole transport layer, a light emitting layer, and the like. Compound layer 624 containing Mg, MgA
and a cathode 625 formed using a material such as an alkali metal or an alkaline earth metal such as g or LiF. The detailed structure of the organic compound layer 624 is arbitrary.

Since the organic compound layer 624 and the cathode 625 cannot be subjected to wet processing (such as etching with a chemical solution or washing with water), they are formed of a photosensitive resin material on the fourth insulating film 621 in accordance with the anode 622. Partition layer 62
3 is provided. The partition layer 623 is formed so as to cover an end of the anode 622. Specifically, the partition layer 623 is formed by applying a negative resist and having a thickness of about 1 to 2 μm after baking. Thereafter, exposure is performed by irradiating ultraviolet rays using a photomask provided with a predetermined pattern. If a negative resist material having poor transmittance is used, the ratio of exposure in the thickness direction of the film changes, and when this is developed, the end of the pattern can be formed into an inverted tapered shape. Of course, such a partition layer can also be formed using photosensitive polyimide or the like.

For the cathode 625, a material containing magnesium (Mg), lithium (Li) or calcium (Ca) having a small work function is used. Preferably, MgAg (M
An electrode made of a material obtained by mixing g and Ag at a ratio of Mg: Ag = 10: 1) may be used. In addition, MgAgAl electrode, Li
An Al electrode and a LiFAl electrode are mentioned. Further thereon, a fifth insulating film 626 is formed of silicon nitride or a DLC film to a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film can be formed by a plasma CVD method, and can be formed to cover the edge of the partition layer 623 with good coverage even at a temperature of 100 ° C. or lower.
The internal stress of the DLC film can be reduced by mixing a small amount of oxygen or nitrogen, and can be used as a protective film. And the DLC film contains oxygen,
It is known that gas barrier properties of CO, CO ₂ , H ₂ O and the like are high. After the cathode 625 is formed, the fifth insulating film 626 is preferably formed continuously without opening to the atmosphere. This is because the state of the interface between the cathode 625 and the organic compound layer 624 greatly affects the luminous efficiency of the organic light emitting device.

As described above, by forming the organic compound layer 624 and the cathode layer 625 without contacting the partition layer 623 to form an organic light-emitting device, it is possible to prevent cracks due to thermal stress. In addition, since the organic compound layer 624 most dislikes oxygen and H ₂ O, a silicon nitride film, a silicon oxynitride film, or a DLC film 626 is formed to block them. In addition, they also have a function of keeping the alkali metal element included in the organic compound layer 624 from coming outside.

In FIG. 10, the switching TFT 654 has a multi-gate structure, and the current controlling TFT 655 has a low concentration drain (LD) overlapping the gate electrode.
D) is provided. TFT using polycrystalline silicon,
Because of high operation speed, deterioration such as hot carrier injection is likely to occur. Therefore, forming a TFT having a different structure (a switching TFT having a sufficiently low off-state current and a current control TFT having a high resistance to hot carrier injection) having different structures in a pixel has high reliability, and This is very effective in manufacturing a display device capable of displaying an excellent image (having high operation performance).

As shown in FIG. 10, the TFTs 654, 65
On the lower layer side (substrate 601 side) of the semiconductor film forming
A base insulating film 602 is formed. On the opposite upper layer side, a first interlayer insulating film 618 is formed. on the other hand,
A fourth insulating film 621 is formed below the organic light emitting element 627. A fifth insulating film 626 is formed on the upper layer side. Alkali metals such as sodium, which the TFTs 654 and 655 dislike most, can be a substrate 601 or an organic light-emitting element 627 as a contamination source. On the other hand, since the organic light emitting element 627 dislikes oxygen and H ₂ O most, the fourth insulating film 62
First, a fifth insulating film 626 is formed. These also have a function of keeping the alkali metal element included in the organic light-emitting element 627 from outside.

In an organic light-emitting device having a structure as shown in FIG.
1. Anode 6 made of a transparent conductive film represented by ITO
A step of continuously forming film 22 by sputtering can be employed. A sputtering method is suitable for forming a dense silicon nitride film or a silicon oxynitride film without significantly damaging the surface of the second interlayer insulating film 619 formed of an organic insulating film.

As described above, the pixel portion is formed by combining the TFT and the organic light emitting device, and the light emitting device can be completed. In such a light-emitting device, a driver circuit can be formed over the same substrate using a TFT. The semiconductor film, the gate insulating film, and the gate electrode, which are the main components of the TFT, have their lower and upper layers surrounded by a blocking layer made of silicon nitride or silicon oxynitride and a protective film to prevent contamination of alkali metals and organic substances. It has a structure to prevent it. On the other hand, an organic light-emitting element contains an alkali metal as a part, is surrounded by a protective film made of silicon nitride or silicon oxynitride, and a gas barrier layer made of an insulating film containing silicon nitride or carbon as a main component. _Two
It has a structure to prevent O from entering.

As described above, a good crystalline semiconductor film can be formed by applying the gettering method of the present invention. By manufacturing a TFT using such a semiconductor film, a TFT having good characteristics can be obtained. Can be produced. In addition, by applying the present invention, TFTs having different characteristics required in the driving circuit and the pixel portion can be separately formed.
A light-emitting device that can perform favorable display can be completed.

Embodiment 4 In this embodiment, an example of a manufacturing process of a light emitting device which is different from that of Embodiment 3 will be described with reference to FIGS.

By applying the present invention, as in the third embodiment, the first
Is formed. Subsequently, a second interlayer insulating film 701 is formed. As the second interlayer insulating film, an inorganic insulating material may be formed with an average thickness of 1.0 to 2.0 μm. As the inorganic resin material, a silicon oxide film or a silicon oxynitride film may be formed by a known sputtering method or a plasma CVD method. Further, when a silicon nitride oxide film is used, the film formation conditions are as follows using a plasma CVD apparatus using SiH ₄ and N ₂ O as source gases.
Pressure 0.3 torr, substrate temperature 400 ° C, RF output 10
0 W, source gas flow rate was ₄ sccm for SiH ₄ , and 4 for N ₂ O.
It may be formed at 00 sccm. Further, an SOG film may be used as the second interlayer insulating film. Further, the second interlayer insulating film may be formed using an organic insulating film such as acrylic.

In the case where the second interlayer insulating film is formed using an inorganic insulating film, the surface of the second interlayer insulating film is formed by CMP.
It is preferable that the interlayer insulating film is polished and flattened by a technique called (Chemical Mechanical Polish) method. The CMP method is a method of flattening the surface chemically or mechanically based on the surface of the workpiece. Generally, a polishing cloth or a polishing pad (hereinafter, collectively referred to as a “pad”) is attached on a platen (Platen or Polishing Plate), and a slurry is placed between the workpiece and the pad. In this method, the surface of the workpiece is polished by a combined chemical and mechanical action by rotating or oscillating the surface plate and the workpiece while supplying the wafer. After the planarization process by the CMP method is completed, the average thickness of the second interlayer insulating film 701 is 1.0 to 2.0.
It should be about 0 μm.

Subsequently, according to the third embodiment, the third insulating film 70 is formed.
2. A fourth insulating film 703 is formed. The fourth insulating film 703 made of silicon nitride or silicon oxynitride serves to protect a semiconductor film which is a main component of the TFT from contamination of an alkali metal or an organic substance contained in the organic compound layer 706, and is deteriorated by oxygen or moisture. Organic compound layer 70
6 is playing a protective role.

Next, a transparent conductive film is formed on the fourth insulating film 703 to a thickness of 80 to 120 nm, and the anode 704 is formed by etching. In this embodiment, indium tin oxide (ITO) is used as the transparent electrode.
2-20% zinc oxide (Zn) in the film or indium oxide
O) is used.

Subsequently, in order to form the partition layer 705,
Resist, polyimide, polyamide, acrylic, BCB
(Benzocyclobutene), a film such as a silicon oxide film is formed. The partition layer may be either an organic substance or an inorganic substance as long as the substance has an insulating property. In the case where the partition layer is formed using photosensitive acrylic, it is preferable to perform heat treatment at 180 to 350 ° C. after etching the photosensitive acrylic film. In the case of using a non-photosensitive acrylic film, it is preferable to form a partition layer 705 by performing heat treatment at 180 to 350 ° C. and then etching. Also,
In the case where a silicon oxide film is used, it may be formed by a CVD method or the like.

Next, an organic compound layer 706 and a cathode 707 are formed on the anode 704 and the partition layer 705 by a vapor deposition method. In this embodiment, Mg is used as the cathode of the light emitting element.
Although an Ag electrode is used, other known materials may be used.
Note that the organic compound layer 706 is formed by combining and stacking a plurality of layers such as a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and a buffer layer, in addition to the light emitting layer. Note that the detailed structure of the organic compound layer 706 is arbitrary.

Thus, an organic light emitting device 708 comprising the anode 704, the organic compound layer 706 and the cathode 707 is formed.

Subsequently, according to the third embodiment, the fifth insulating film 70
9, an insulating film such as a DLC film is formed. In this way,
A light-emitting device having a tapered partition wall layer as illustrated in FIG. 18 can be manufactured.

As described above, a good crystalline semiconductor film can be formed by applying the gettering method of the present invention, and a TFT having good characteristics can be formed by using such a semiconductor film. A TFT can be manufactured. In addition, by applying the present invention, TFTs having different characteristics can be separately formed in a driver circuit and a pixel portion, so that a light-emitting device which can perform favorable display can be completed.

Example 5 This example shows the results of measuring the reliability and electrical characteristics of a TFT manufactured by applying the present invention.

FIG. 19A shows the result of measuring the reliability of an n-channel TFT.

The present applicant has evaluated reliability by examining a 10-year guaranteed voltage. The 10-year guaranteed voltage means that the maximum mobility ( _{μFE (max)} ) of the TFT is 10%.
When the time until the change is defined as the lifetime, the reciprocal of the stress voltage is plotted on a semilogarithmic graph, and the stress voltage having a lifetime of 10 years is estimated and obtained from the obtained linear relationship. When measurement was performed on a TFT (drive circuit) manufactured by applying the present invention, as shown in FIG. 19A, the 10-year guarantee voltage was 17.7 V when the Lov length was 1.0 μm, 19. When the Lov length is 1.7 μm.
It showed high reliability of 0V.

FIG. 19B shows an Id-Vg curve of a TFT manufactured by applying the present invention. The measurement was performed at a source voltage (Vs) of 0 V and a drain voltage (Vd) of 1 V or 14 V. The measured values show that the pixel TFT has a channel length (L) of 4.5 × 2 μm and a channel width (W) of 3 μm.
m.

The pixel TFT has an off current (Ioff) of 1 pA
It was suppressed below, and the jump of Ioff when Vg was high was suppressed. In addition, the field effect mobility is 100 to
130 (cm ² / Vs), S value 0.174 to 0.185
A good characteristic of (V / dec) could be obtained.

According to the above results, by applying the present invention, a TF having high reliability and required performance can be obtained.
It can be seen that T can be divided without increasing the number of steps.

(Embodiment 6) A CMOS circuit or a pixel portion formed by implementing the present invention can be used for an active matrix type liquid crystal display (liquid crystal display device). That is, the present invention can be applied to all electric appliances in which the liquid crystal display devices are incorporated in the display unit.

Examples of such electric appliances include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggle type display), a personal computer, a portable information terminal (mobile computer, a mobile phone or an electronic book). Etc.). Examples of these are shown in FIGS.
And FIG.

FIG. 11A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like.

FIG. 11B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6 and so on.

FIG. 11C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like.

FIG. 11D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on.

FIG. 11E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display unit 2402, and a speaker unit 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games and the Internet.

FIG. 11F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like.

FIG. 12A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like.

FIG. 12B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like.

FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9, the projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 12D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 12, a case where a transmission type electro-optical device is used is shown, and an application example of a reflection type liquid crystal display device is not shown.

FIG. 13A shows a mobile phone,
, A display panel; and 3002, an operation panel. The display panel 3001 and the operation panel 3002 are connected to
003. The angle θ between the surface of the connection panel 3003 where the display portion 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 where the operation keys 3006 are provided can be arbitrarily changed. Further, an audio output unit 3005, operation keys 301
0, a power switch 3007, a voice input unit 3008, and an antenna 3009.

FIG. 13B shows a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, and an antenna 3106.
And so on.

FIG. 13C shows a display, which includes a main body 3201, a support 3202, a display portion 3203, and the like.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in various fields. Further, the electric appliance of this embodiment can be realized by combining Embodiments 1 to 4 and Embodiments 1 and 2.

[0178]

As described above, the first problem relating to the method for removing a catalytic element from a crystalline semiconductor film obtained by performing a heat treatment at a low temperature using a catalytic element that promotes crystallization is as follows.
By using the gettering method using a rare gas element of the present invention, the catalytic element can be effectively removed from the semiconductor film or the concentration can be reduced, which can be solved. In addition, since the rare gas element used for gettering is inactive in the semiconductor film, there is no adverse effect such as a change in the threshold voltage of the TFT.

The second problem of complicating the manufacturing process when the TFT structures that meet the driving conditions of the pixel portion and the driving circuit is different is that according to the present invention, the LDD structure is formed on the same substrate. Since the n-channel TFT and the p-channel TFT different from each other can be formed by using six photomasks, this can be solved. Using such an active matrix substrate, a liquid crystal display device or a display device having a light-emitting layer over the same substrate can be formed. Although the reduction in the number of photomasks leads to an improvement in productivity, the present invention is not limited to this.
By optimizing the LDD structure of T, the reliability and operation characteristics of the active matrix substrate can be improved at the same time.

Further, if the first invention for solving the first problem and the second invention for solving the second problem are applied together, the first problem and the second problem can be solved simultaneously. The characteristics of the TFT are improved by using a semiconductor film in which the concentration of the catalyst element is sufficiently reduced for the active layer, and a semiconductor device having high performance by manufacturing the TFT by the method disclosed in the present invention. A liquid crystal display device can be realized.

[Brief description of the drawings]

FIG. 1 illustrates an example of an embodiment of the present invention.

FIG. 2 illustrates an example of an embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing an embodiment of the present invention.

FIG. 5 is a diagram showing an embodiment of the present invention.

FIG. 6 is a diagram showing an embodiment of the present invention.

FIG. 7 illustrates an example of an embodiment of the present invention.

FIG. 8 illustrates an example of an embodiment of the present invention.

FIG. 9 is a graph showing the result of measuring the concentration of Ar contained in a semiconductor film.

FIG. 10 illustrates an example of a light-emitting device manufactured according to the present invention.

FIG. 11 illustrates an example of an electric appliance using a liquid crystal display device manufactured according to the present invention for a display portion.

FIG. 12 illustrates an example of an electric appliance using a liquid crystal display device manufactured according to the present invention for a display portion.

FIG. 13 illustrates an example of an electric appliance using a liquid crystal display device manufactured according to the present invention for a display portion.

FIG. 14 illustrates an example of an embodiment of the present invention.

FIG. 15 is a diagram showing an example of the present invention.

FIG. 16 is a diagram showing an example of the present invention.

FIG. 17 illustrates an example of an embodiment of the present invention.

FIG. 18 illustrates an example of a light-emitting device manufactured according to the present invention.

FIG. 19 is a graph showing the results of measuring the reliability and characteristics of a TFT manufactured by applying the present invention.

[Explanation of symbols]

401 first n-channel TFT 402 p-channel TFT 403 second n-channel TFT 1162, 1165, 1168 channel formation region 1163, 1169 second impurity region 1164, 1170 third impurity region (source region or drain) 1166 Fourth impurity region 1167 Fifth impurity region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) H01L 27/08 331 H01L 27/08 321E 27/092 29/78 627Z 29/786 613A 627G (72) Inventor Osamu Nakamura 398 Hase, Atsugi-shi, Kanagawa Pref.Semiconductor Energy Laboratory Co., Ltd. (72) Inventor Masayuki Kajihara 398 Hase, Atsugi-shi, Kanagawa Pref. Address Semiconductor Energy Laboratory Co., Ltd. (72) Inventor Tohru Takayama 398 Hase, Atsugi-shi, Kanagawa Prefecture Semiconductor Energy Laboratory Co., Ltd.F-term (reference) BA04 BA07 BB01 BB02 BB05 BB07 DA02 DA03 DB02 DB03 DB07 EA16 FA06 FA19 JA01 5F110 AA06 AA16 BB02 BB04 CC02 CC06 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE23 EE28 EE44 EE45 FF02 FF03 FF04 FF09 FF12 GG28 GG13 GG33 GG33 GG33 GG33 GG01 HJ13 HJ23 HL03 HL04 HL06 HL11 HM15 NN02 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN72 NN78 PP01 PP02 PP03 PP04 PP06 PP13 PP26 PP29 PP34 PP35 PP38 QQ04 QQ05 QQ11 QQ28

Claims (26)

[Claims] 1. A semiconductor device comprising a first n-channel TFT, a second n-channel TFT, and a p-channel TFT on a same substrate, wherein the first n-channel TFT is
The second impurity region and the third impurity region formed in the T semiconductor layer are provided outside the gate electrode, and the second impurity region formed in the semiconductor layer of the second n-channel TFT is A third impurity region which is provided so as to partially overlap with the gate electrode, and which is provided outside the gate electrode;
A fourth impurity region formed in the semiconductor layer of the p-channel TFT is provided so as to partially overlap the gate electrode, and a fifth impurity region is provided outside the gate electrode. Semiconductor device. 2. A semiconductor device comprising a first n-channel TFT, a second n-channel TFT, and a p-channel TFT on the same substrate, wherein the first n-channel TFT is
The second impurity region formed in the semiconductor layer of T and serving as an LDD region and the third impurity region serving as a source or drain region are provided outside a gate electrode, and the second n region is formed.
The second impurity region formed in the semiconductor layer of the channel type TFT and serving as an LDD region is provided so as to partially overlap with the gate electrode, and the third impurity region serving as a source or drain region is provided outside the gate electrode. And the p
A fourth impurity region formed in the semiconductor layer of the channel type TFT and serving as an LDD region is provided so as to partially overlap with the gate electrode, and a fifth impurity region serving as a source or drain region is provided outside the gate electrode. A semiconductor device characterized by being provided in a semiconductor device. 3. A first n-channel type T provided in a pixel portion.
FT and a second n-channel type TF provided in the drive circuit
A semiconductor device comprising a T and a p-channel TFT on the same substrate, wherein a second impurity region and a third impurity region formed in a semiconductor layer of the first n-channel TFT are formed by a gate electrode. , The second impurity region formed in the semiconductor layer of the second n-channel TFT is provided so as to partially overlap with the gate electrode, and the third impurity region is provided on the gate electrode. The fourth impurity region provided on the outside and formed in the semiconductor layer of the p-channel TFT is provided so as to partially overlap the gate electrode, and the fifth impurity region is provided on the outside of the gate electrode. A semiconductor device, comprising: 4. A first n-channel type T provided in a pixel portion
FT and a second n-channel type TF provided in the drive circuit
A semiconductor device including a T and a p-channel TFT on the same substrate, wherein the second impurity region is formed in a semiconductor layer of the first n-channel TFT and serves as an LDD region;
The third impurity region serving as a source or drain region is provided outside the gate electrode, is formed in the semiconductor layer of the second n-channel TFT, and the second impurity region serving as an LDD region is connected to the gate electrode. The third impurity region which is provided so that the portions overlap and which is to be a source or drain region is provided outside the gate electrode and is formed in the semiconductor layer of the p-channel TFT, and the fourth impurity region which becomes the LDD region is formed.
Wherein the impurity region is provided so as to partially overlap with the gate electrode, and the fifth impurity region serving as a source or drain region is provided outside the gate electrode. 5. The semiconductor device according to claim 1, wherein the second n-channel type TFT is provided in a buffer circuit. 6. A step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalytic element for promoting crystallization to the amorphous semiconductor film, and performing a first heat treatment. A step of forming a crystalline semiconductor film, a step of forming a barrier layer on the crystalline semiconductor film, and a step of forming a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²² / cm ³ . A semiconductor device including a step of forming a semiconductor film containing the semiconductor element at a concentration, a step of moving the catalyst element to the semiconductor film by a second heat treatment, and a step of removing the semiconductor film. Method of manufacturing. 7. A step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalyst element for promoting crystallization to the amorphous semiconductor film, and performing a first heat treatment. A step of forming a crystalline semiconductor film, a step of irradiating the crystalline semiconductor film with laser light, a step of forming a barrier layer on the crystalline semiconductor film, and a step of forming a rare gas element by 1 × on the barrier layer. Forming a semiconductor film containing a concentration of 10 ¹⁹ / cm ³ to 1 × 10 ²² / cm ³ , and transferring the catalyst element to the semiconductor film by a second heat treatment;
Removing the semiconductor film. 8. A step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface, and adding a catalytic element for promoting crystallization to the amorphous semiconductor film, and performing a first heat treatment. A step of forming a crystalline semiconductor film, a step of forming a barrier layer on the crystalline semiconductor film, and a step of forming a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²² / cm ³ . Forming a semiconductor film containing the semiconductor element at a concentration, transferring the catalytic element to the semiconductor film by a second heat treatment, removing the semiconductor film, and irradiating the crystalline semiconductor film with laser light. A method for manufacturing a semiconductor device. 9. A step of forming an amorphous semiconductor film containing silicon as a main component on an insulating surface; a step of adding a catalytic element for promoting crystallization to the amorphous semiconductor film; Forming a barrier layer on the film, and applying a rare gas element on the barrier layer at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²² / cm ³
A step of forming a semiconductor film containing the semiconductor element at a concentration of, and a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film and moving the catalytic element to the semiconductor film. A method for manufacturing a semiconductor device, comprising: removing a film; and irradiating the crystalline semiconductor film with laser light. 10. A step of adding a catalytic element for promoting crystallization to an insulating surface; a step of forming an amorphous semiconductor film containing silicon as a main component on the insulating surface; forming a barrier layer, the noble gas element on the amorphous semiconductor film ^{1 × 10 19 / cm 3 ~1} × 10 22 /
a step of forming a semiconductor film containing a concentration of ³ cm, and a step of heat treatment, crystallizing the amorphous semiconductor film to form a crystalline semiconductor film and transferring the catalytic element to the semiconductor film, A method for manufacturing a semiconductor device, comprising: a step of removing the semiconductor film; and a step of irradiating the crystalline semiconductor film with laser light. 11. A step of adding a catalytic element for promoting crystallization to an insulating surface; a step of forming an amorphous semiconductor film containing silicon as a main component on the insulating surface; forming a barrier layer, the noble gas element on the amorphous semiconductor film ^{1 × 10 19 / cm 3 ~1} × 10 22 /
a step of forming a semiconductor film containing a concentration of ³ cm ³ , a step of adding a rare gas element to the semiconductor film, and a heat treatment to crystallize the amorphous semiconductor film to form a crystalline semiconductor film. A method for manufacturing a semiconductor device, comprising: a step of moving the catalyst element to the semiconductor film; a step of removing the semiconductor film; and a step of irradiating the crystalline semiconductor film with laser light. 12. The method for manufacturing a semiconductor device according to claim 6, wherein the barrier layer is a chemical oxide film formed with ozone water. 13. The method for manufacturing a semiconductor device according to claim 6, wherein the barrier layer is formed by oxidizing a surface of the amorphous semiconductor film by plasma treatment. . 14. The barrier layer according to claim 6, wherein the barrier layer is formed by irradiating ultraviolet rays in an atmosphere containing oxygen to generate ozone and oxidize the surface of the amorphous semiconductor film. A method for manufacturing a semiconductor device. 15. The barrier layer according to claim 6, wherein the barrier layer is formed with a film thickness of 1 to 10 nm.
A method for manufacturing a semiconductor device, which is a porous film. 16. The rare gas element according to claim 6, wherein the rare gas element is He, Ne, Ar, Kr, X
e. one or more kinds of semiconductor devices selected from the group consisting of: 17. The method according to claim 6, wherein the first heat treatment is selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp. A method for manufacturing a semiconductor device, which is performed by radiation from one or more kinds. 18. The method for manufacturing a semiconductor device according to claim 6, wherein the first heat treatment is performed using an electric furnace. 19. The method according to claim 6, wherein the second heat treatment is selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp. A method for manufacturing a semiconductor device, which is performed by radiation from one or more kinds. 20. The method for manufacturing a semiconductor device according to claim 6, wherein the second heat treatment is performed using an electric furnace. 21. The method according to claim 6, wherein the catalyst element is Fe, Ni, Co, Ru, R
A method for manufacturing a semiconductor device, which is one or more kinds selected from h, Pd, Os, Ir, Pt, Cu, and Au. 22. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and forming a first shape conductive layer on the insulating film. A third step, a fourth step of forming a second-shape conductive layer from the first-shape conductive layer, and an impurity element of one conductivity type in the semiconductor layer using the second-shape conductive layer as a mask. A fifth step of adding the first impurity region to form a first impurity region, and adding a second conductivity type impurity element to a selected region of the semiconductor layer using the second shape conductive layer as a mask. A sixth step of forming an impurity region of No. 3; and adding an impurity element opposite to one conductivity type to a selected region of the semiconductor layer using the conductive layer of the second shape as a mask. And a seventh step of forming an impurity region of the semiconductor device. Manufacturing method. 23. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and forming a first shape conductive layer on the insulating film. A third step, a fourth step of forming a second-shape conductive layer from the first-shape conductive layer, and a first dose to the semiconductor layer using the second-shape conductive layer as a mask. A fifth step of forming a first impurity region by adding an impurity element of a conductivity type, and using a conductive layer of the second shape as a mask to form a first conductive region with a second dose in a selected region of the semiconductor layer. A sixth step of forming second and third impurity regions by adding an impurity element of a negative conductivity type, and opposing one conductivity type to a selected region of the semiconductor layer using the conductive layer of the second shape as a mask. A seventh step of forming fourth and fifth impurity regions by adding an impurity element of The method for manufacturing a semiconductor device which is characterized in that. 24. The method according to claim 22, wherein
The method for manufacturing a semiconductor device, wherein the one conductivity type impurity is an impurity imparting n-type. 25. The method according to claim 22, wherein
A step of forming a barrier layer on the crystalline semiconductor film, wherein the semiconductor layer is made of a crystalline semiconductor film formed by performing a first heat treatment by adding a catalytic element to an amorphous semiconductor film; A rare gas element is applied on the barrier layer in an amount of 1 × 10 ¹⁹ to 1 × 1
Forming a semiconductor film containing at a concentration of 0 ²² / cm ³ ;
Transferring the catalyst element to the semiconductor film by a second heat treatment. 26. The method for manufacturing a semiconductor device according to claim 25, wherein the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.