JP2006179878A - Method of preparing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of preparing a semiconductor device adaptable for a large-area device by forming gate electrodes or wiring lines using metal films having low resistance. <P>SOLUTION: A first conductive layer containing aluminum as a major component is formed on a substrate, a second conductive layer is formed including a material different from the relevant first conductive layer on the first conductive layer, and the first and second conductive layers are patterned to form gate electrodes. The first conductive layer contains at least one of carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. The second conductive layer contains at least one of chromium, tantalum, tungsten, molybdenum, titanium, silicon, nickel, and a nitride of each of them. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device having an inverted staggered thin film transistor having a crystalline semiconductor film.

  In recent years, a flat panel display (FPD) represented by a liquid crystal display (LCD) and an EL (Electro Luminescence) display has been attracting attention as a display device replacing a conventional CRT. In particular, the development of large-screen liquid crystal televisions equipped with large liquid crystal panels driven by an active matrix has become an important issue for LCD panel manufacturers to focus on. In recent years, a large screen EL television has been developed following the liquid crystal television.

  In a conventional liquid crystal display device or EL display device (hereinafter referred to as “light emitting display device”), a thin film transistor (hereinafter referred to as “TFT”) using an amorphous semiconductor film (amorphous silicon) as a semiconductor element for driving each pixel. ")" Is used.

  On the other hand, in the conventional liquid crystal television, image blurring due to the limitation of viewing angle characteristics and the limitation of high-speed operation due to liquid crystal materials and the like has been a drawback, but as a new display mode to solve this in recent years, OCB (Optically A Compensated Bend) mode has been proposed (for example, see Non-Patent Document 1).

Nagahiro Yasuaki et al., “Nikkei Microdevices separate volume flat panel display 2002”, Nikkei BP, October 2001, P102-109

  In order to improve the image quality of the LCD, a switching element capable of high-speed operation is required. However, a TFT using an amorphous semiconductor film has a limit. For example, it is difficult to realize an OCB mode liquid crystal display device.

  In addition, when a TFT using an amorphous semiconductor film is DC-driven, the threshold value tends to shift, and the characteristics of the TFT tend to vary accordingly. For this reason, luminance unevenness occurs in a light-emitting display device in which a TFT using an amorphous semiconductor film is used for pixel switching. Such a phenomenon becomes more conspicuous as the screen TV has a diagonal size of 30 inches or more (typically 40 inches or more), and the deterioration of image quality is a serious problem.

  In the conventional TFT, it has been actively attempted to use aluminum for the gate electrode. Aluminum is characterized by a low resistance value and good adhesion to the silicon oxide film. Another advantage is that the cost is very low.

  However, aluminum has a problem in heat resistance. For example, in the TFT process, when heat treatment is performed at 250 ° C. or higher, a phenomenon called a hillock or a void or a worm-like hole may be generated. The occurrence of hillocks (voids) causes a short circuit between wires, disconnection, and a decrease in reliability.

  The present invention has been made in view of such a situation, and provides a method for manufacturing a semiconductor device that can cope with a large area device by forming a gate electrode and a wiring using a low-resistance metal film. . In addition, a method for manufacturing a semiconductor device including a TFT which is less likely to cause variation in characteristics of the TFT and can operate at high speed is provided. In addition, a method for manufacturing a semiconductor device having a TFT with a small number of photomasks is provided. In addition, a method for manufacturing a semiconductor device with high switching characteristics and capable of display with excellent contrast is provided.

  In the present invention, as a gate electrode of a TFT, a laminated structure of a conductive film (or metal film) containing Al as a main component and a cap film formed on the conductive film is used, and a non-catalytic element is used. An inverted staggered TFT is formed using a technique for crystallizing a crystalline semiconductor film and a technique for gettering a catalytic element after crystallizing the amorphous semiconductor film.

  As the conductive film containing Al as a main component, specifically, aluminum containing carbon (C), aluminum containing carbon, and any of Cr, Ta, W, Mo, Ti, Si, Ni Those containing one or more of them can be used.

  Note that in this specification, the “cap film” refers to a conductive film (or metal film) provided in order to suppress generation of hillocks in a conductive film containing Al as a main component. Specifically, Cr, Ta, W, Mo, Ti, Ni, and nitrides thereof can be used as the cap film. It is also possible to use silicon.

The structure of the invention related to the method for manufacturing a semiconductor device disclosed in this specification is as follows.
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form an island-shaped semiconductor region;
Forming a third conductive layer on the island-shaped semiconductor region;
A source electrode and a drain electrode are formed by patterning the third conductive layer, and the second semiconductor film is etched in the island-shaped semiconductor region using the source electrode and the drain electrode as a mask, A part of the semiconductor film is exposed and a source region and a drain region are formed.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form an island-shaped semiconductor region;
Of the island-shaped semiconductor regions, the second semiconductor film is etched to form a source region and a drain region,
A source electrode and a drain electrode in contact with the source region and the drain region are formed.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming the second semiconductor film containing a rare gas element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film,
Removing the second semiconductor film;
Forming a conductive third semiconductor film on the first semiconductor film;
Patterning the first semiconductor film and the third semiconductor film to form an island-shaped first semiconductor film and an island-shaped second semiconductor film;
Forming a third conductive layer on the island-shaped second semiconductor film;
The third conductive layer is partially etched to form a source electrode and a drain electrode, and the island-shaped second semiconductor film is etched using the source electrode and the drain electrode as a mask to form the island-shaped first A part of the semiconductor film is exposed and a source region and a drain region are formed.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming the second semiconductor film containing a rare gas element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film,
Removing the second semiconductor film;
Forming a conductive third semiconductor film on the first semiconductor film;
Patterning the first semiconductor film and the third semiconductor film to form an island-shaped semiconductor region;
Of the island-shaped semiconductor regions, the third semiconductor film is etched to form a source region and a drain region,
A source electrode and a drain electrode in contact with the source region and the drain region are formed.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a first mask, and a part of the second island-shaped semiconductor region is covered with a second mask, and then a second impurity element is selectively added. And
Removing the first mask and the second mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The third conductive layer is patterned to form a source electrode and a drain electrode in contact with the second semiconductor film of the first island-shaped semiconductor region, and the second island-shaped semiconductor region of the second island-shaped semiconductor region. Forming a source electrode and a drain electrode in contact with the semiconductor film;
The exposed portion of the second semiconductor film in the first island-shaped semiconductor region is etched to form a first source region and a drain region, and the second semiconductor film in the second island-shaped semiconductor region The exposed portion is etched to form a second source region and a drain region.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a first mask, and a part of the second island-shaped semiconductor region is covered with a second mask, and then a second impurity element is selectively added. And
Removing the first mask and the second mask;
Among the first island-shaped semiconductor regions, the second semiconductor film is etched to form a first source region and a first drain region, and at the same time, among the second island-shaped semiconductor regions, Etching the second semiconductor film to form a second source region and a second drain region;
Forming a first source electrode and a first drain electrode in contact with the first source region and the first drain region, and a second in contact with the second source region and the second drain region; The source electrode and the second drain electrode are formed.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Patterning the first semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
A part of the first island-shaped semiconductor region is covered with a first mask, and a part of the second island-like semiconductor region is covered with a second mask, and then the first impurity element is selected. Added
Removing the first mask and the second mask;
Heating the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a third mask, and a part of the second island-shaped semiconductor region is covered with a fourth mask, and then a second impurity element is selectively added. And
Removing the third mask and the fourth mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
Patterning the third conductive layer to form a source electrode and a drain electrode in contact with the first island-shaped semiconductor region, and a source electrode and a drain electrode in contact with the second island-shaped semiconductor region; Features.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film containing a rare gas element on the first semiconductor film;
Heating the first semiconductor film and the second semiconductor film;
Removing the second semiconductor film;
Patterning the first semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
A portion of the first island-shaped semiconductor region is covered with a first mask, and the second island-shaped semiconductor region is covered with a second mask, and then a first impurity element is selectively added. And
Removing the first mask and the second mask;
The first island-shaped semiconductor region is covered with a third mask, and a part of the second island-shaped semiconductor region is covered with a fourth mask, and then a second impurity element is selectively added. And
Removing the third mask and the fourth mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
Patterning the third conductive layer to form a source electrode and a drain electrode in contact with the first island-shaped semiconductor region, and a source electrode and a drain electrode in contact with the second island-shaped semiconductor region; Features.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
After covering the first island-shaped semiconductor region with a mask, a second impurity element is added to the second island-shaped semiconductor region;
Removing the mask,
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The third conductive layer is patterned to form a source electrode and a drain electrode in contact with the second semiconductor film of the first island-shaped semiconductor region, and the second island-shaped semiconductor region of the second island-shaped semiconductor region. Forming a source electrode and a drain electrode in contact with the semiconductor film;
A source region and a drain region are formed by etching the exposed portion of the second semiconductor film in the first island-shaped semiconductor region and the exposed portion of the second semiconductor film in the first island-shaped semiconductor region. It is characterized by doing.

Further, another structure of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is as follows:
Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
After covering the first island-shaped semiconductor region with a mask, a second impurity element is added to the second island-shaped semiconductor region;
Removing the mask,
Among the first island-shaped semiconductor regions, the second semiconductor film is etched to form the first source region and the first drain region, and at the same time, among the second island-shaped semiconductor regions, Etching the second semiconductor film to form a second source region and a second drain region;
Forming a first source electrode and a first drain electrode in contact with the first source region and the first drain region, and simultaneously forming a second source electrode in contact with the second source region and the second drain region; The source electrode and the second drain electrode are formed.

  In the configuration of the above invention, the heating is performed by rapid thermal annealing (RTA).

  In the structure of the above invention, the rare gas element is one or more of He, Ne, Ar, Kr, and Xe.

  In the structure of the above invention, the first impurity element is one or more of phosphorus, nitrogen, arsenic, antimony, and bismuth.

  In the structure of the above invention, the second impurity element is boron.

  In the structure of the above invention, the catalyst element is one or more of tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, and platinum.

  In the structure of the above invention, the first conductive layer contains carbon and one or more of chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel.

  Moreover, in the structure of the above invention, the carbon is contained in an amount of 0.1 to 10 atomic%.

  In the structure of the above invention, the second conductive layer is made of one or more of chromium, tantalum, tungsten, molybdenum, titanium, nickel, or a nitride thereof. It is also possible to use silicon.

  Another invention of a method for manufacturing a semiconductor device disclosed in this specification is a liquid crystal television or an EL television including the semiconductor device.

  In the present invention, examples of the semiconductor device include an integrated circuit including a semiconductor element, a display device, a wireless tag, and an IC tag. Typical examples of the display device include a liquid crystal display device, a light emitting display device, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display). And display devices such as electrophoretic display devices (electronic paper).

  In the present invention, the display device refers to a device using a display element, that is, an image display device. In addition, a connector, for example, a module in which a flexible printed wiring (FPC), TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to the display panel, and a printed wiring board is attached to the end of the TAB tape or TCP. It is assumed that the display device includes all provided modules or modules in which an IC (Integrated Circuit) or a CPU is directly mounted on a display element by a COG (Chip On Glass) method.

  In this specification, “patterning” refers to etching into a desired shape.

  In the conventional single-layer structure of a film containing aluminum as a main component (including a film containing carbon or the like), sufficient heat resistance and hillock suppression effects could not be obtained. The subject can be solved by forming another conductive film over the main film. That is, an inverted staggered TFT having a crystalline semiconductor film can be formed using a low-resistance, high-reliability, and low-cost gate electrode, and can be applied to a large-area device.

  Further, according to the present invention, a TFT can be formed with a small number of masks. In addition, since the TFT formed according to the present invention is formed using a crystalline semiconductor film, it has higher mobility than an inverted staggered TFT formed using an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured. Typically, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, in comparison with an EL display device using a TFT formed of an amorphous semiconductor film as a switching element, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured. It is.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. Therefore, the contrast can be improved by using such a TFT as a switching element of a display device, for example, a liquid crystal display device.

  Further, after the second semiconductor film having the first impurity element is formed over the first semiconductor film, the first semiconductor film and the second semiconductor film are heated to thereby form the first semiconductor film. The catalyst element contained therein is moved (gettered) into the second semiconductor film, and the second semiconductor film is also used as a film functioning as a source region and a drain region. For this reason, it is not necessary to newly provide films functioning as a source region and a drain region. That is, a thin film transistor having a crystalline semiconductor film can be manufactured without increasing the number of steps compared to the conventional method.

  Further, a liquid crystal television and an EL television each including the semiconductor device formed by the above manufacturing process can be manufactured with high throughput and yield at low cost.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment, a manufacturing process of an inverted staggered TFT having a crystalline semiconductor film will be described with reference to FIGS.

  As shown in FIG. 1A, a first conductive film 102a is formed over a substrate 101, and a second conductive film 102b is formed thereover. Next, the first insulating film 103 and the second insulating film 104 are formed over the second conductive film 102b. Next, a first semiconductor film 105 is formed over the second insulating film 104, and a layer 106 containing a catalytic element is formed over the first semiconductor film 105.

  Note that a base film may be formed between the substrate 101 and the first conductive film 102a as necessary in order to prevent diffusion of impurities and the like from the substrate side. As the base film, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy (x> y)), silicon nitride oxide (SiNxOy (x> y)), or the like can be used as appropriate.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a silicon wafer, a metal plate, or the like can be used. In the present invention, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm is used as the substrate 101. Can do.

  The first conductive film 102a and the second conductive film 102b function as gate electrodes. As a formation method of the first conductive film 102a and the second conductive film 102b, a first conductive layer and a second conductive layer are sequentially formed, a mask is formed by a photolithography step, and the mask is used. And patterning (etching) at the same time. In this case, since the mask process may be performed once, there is an advantage in terms of reducing the number of processes. In this embodiment, the first conductive film 102a and the second conductive film 102b are formed to have the same taper angle; however, the first conductive film 102a and the second conductive film 102b are tapered. You may change the corner. Further, if coverage (step coverage) does not become a problem, it is not necessary to be tapered. Alternatively, the side surfaces of the first conductive film 102a may be oxidized after the second conductive film 102b is formed.

  Alternatively, the gate electrode may have a structure in which the second conductive film 102b is formed so as to cover the first conductive film 102a. Specifically, the first conductive layer is formed and then patterned to form the first conductive layer 102a. At this time, it is preferable to form a taper in consideration of coverage (step coverage). Next, a second conductive layer is formed so as to cover the surface of the first conductive film 102a, and then patterned to form the second conductive film 102b. At this time, the second conductive film 102b may be formed to have the same taper angle as the first conductive film 102a, or may be formed to have a different taper angle. With the structure in which the second conductive film 102b is formed so as to cover the first conductive film 102a, the effect of suppressing hillocks in the first conductive film 102a containing aluminum as a main component can be significantly obtained. .

  The first conductive film 102a and the second conductive film 102b are formed by a known method such as a printing method, an electroplating method, a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), or an evaporation method. That's fine.

  As the material for the first conductive film 102a, a material containing aluminum as its main component and containing one or more of carbon and chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel can be used. . Specifically, carbon is preferably contained in an amount of 0.1 to 10 atomic%. By using a film made of such a material as the first conductive film 102a, an effect of higher heat resistance than that of pure aluminum can be obtained while taking advantage of low resistance and low cost of aluminum.

  If the second conductive film 102b described below can sufficiently suppress generation of hillocks, which is a problem of the conductive film containing aluminum as a main component, caused by high temperature heating, only carbon ( A film containing aluminum as a main component and containing 0.1 to 10 atom% may be used as the first conductive film 102a.

  In addition, the functions required as the second conductive film 102b are required to have a function of suppressing hillocks and improving heat resistance of the first conductive film 102a containing aluminum. Examples of the material having such a function include one made of chromium, tantalum, tungsten, molybdenum, titanium, nickel, or a nitride thereof. It is also possible to use silicon.

  In order to further suppress hillocks in the first conductive film containing aluminum, the first conductive layer is formed and patterned to form the first conductive film 102a. The second conductive film 102b may be formed so as to cover the entire surface of the conductive film 102a.

  Further, although the number of steps is increased, the gate electrode may be formed so that the film containing aluminum as a main component is completely covered with the upper and lower conductive films. As an example of a specific formation method, a first conductive layer functioning as a cap film and a layer containing aluminum as a main component are formed using a known film formation method, and then patterned simultaneously. Next, a second conductive layer functioning as a cap film is formed so as to cover the patterned first conductive layer and a layer containing aluminum as a main component, and then etched into a desired shape. Since the three-layer gate electrode formed in this way has a structure in which the upper and lower sides of a film containing aluminum as a main component are covered with a cap film, the effect of suppressing generation of hillocks can be sufficiently obtained.

  The first insulating film 103 and the second insulating film 104 function as a gate insulating film. The first insulating film 103 and the second insulating film 104 include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy (x> y)), and silicon nitride oxide (SiNxOy (x> y)). Etc. can be used as appropriate. Note that in order to prevent diffusion of impurities and the like from the substrate side, the first insulating film 103 is preferably formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy (x> y)), or the like. The second insulating film may be formed using silicon oxide (SiOx) or silicon oxynitride (SiOxNy (x> y)) because of interface characteristics with the first semiconductor film 105 to be formed later. desirable. However, the present invention is not limited to this step, and it is formed of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy (x> y)), silicon nitride oxide (SiNxOy (x> y)), and the like. It may be formed of a single layer. Note that the second insulating film contains hydrogen.

  As the first semiconductor film 105, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm are formed in the amorphous semiconductor. A film having any state selected from a microcrystalline semiconductor and a crystalline semiconductor that can be observed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor film whose main component is silicon, silicon germanium, or the like can be a semiconductor film having a thickness of 10 to 200 nm, preferably 50 to 100 nm.

Note that in order to obtain a semiconductor film having a high-quality crystal structure by subsequent crystallization, an impurity concentration of oxygen, nitrogen, or the like contained in the first semiconductor film 105 is set to 5 × 10 ¹⁸ / cm ³ (hereinafter referred to as “concentration”). All concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

  As a method of forming the layer 106 having a catalytic element, a method of forming a thin film of a catalytic element or a silicide of a catalytic element on the surface of the first semiconductor film 105 by a PVD method, a CVD method, a vapor deposition method, or the like, 105 includes a method of applying a solution containing a catalytic element on the surface. Examples of catalyst elements include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of nickel (Ni), platinum (Pt), and the like. Further, the catalyst element may be directly added to the semiconductor film by an ion doping method or an ion implantation method. Further, the surface of the semiconductor film may be subjected to plasma treatment using an electrode formed of the above catalytic element. Here, the catalytic element is an element that promotes or promotes crystallization of the semiconductor film.

  Next, the first semiconductor film 105 is heated to form a first crystalline semiconductor film 111 as shown in FIG. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Examples of the crystallization method include a heat treatment (furnace annealing method) using an electric furnace after a heat treatment for dehydrogenation. The heating conditions at this time may be 550 ° C. to 650 ° C. for 4 to 24 hours. More preferably, crystallization is performed by a rapid thermal annealing (hereinafter referred to as “RTA”) method using a gas, a halogen lamp, or an electron beam as a heating source. In this embodiment, crystallization is performed by this RTA. The heating conditions by RTA may be 3 to 10 minutes at 500 to 700 ° C.

  By crystallizing the semiconductor film without using laser light as a heating means, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed. Further, RTA is characterized in that it can be heated in a very short time compared to furnace annealing. Therefore, as in the present embodiment, in addition to forming the second conductive film 102b on the first conductive film 102a, by forming the first crystalline semiconductor film 111 of the semiconductor film by RTA, A synergistic effect for suppressing generation of hillocks in the first conductive film 102a containing aluminum as a main component can be obtained.

Next, a channel doping process for adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT is performed entirely or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used. Note that the channel doping step may be performed before the crystallization step.

Next, a second semiconductor film 112 containing a Group 15 element (hereinafter referred to as a “donor element”) is formed over the first crystalline semiconductor film 111. The film may be formed by a plasma CVD method in which a gas containing a donor element such as phosphorus or arsenic is added to a silicide gas. By forming the second semiconductor film by such a method, an interface between the first crystalline semiconductor film and the second semiconductor film is formed. In addition, the second semiconductor film 112 containing a donor-type element is formed by forming a semiconductor film similar to the first semiconductor film and then adding the donor-type element by an ion doping method or an ion implantation method. Can do. In this case, the second semiconductor film 112 preferably has a phosphorus concentration of 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ .

  FIG. 9 shows a model diagram (not an actual measurement result) of the impurity profile of the second semiconductor film containing the donor element at this time. FIG. 9A shows a donor-type element profile 140a when a second semiconductor film containing a donor-type element is formed on the first crystalline semiconductor film 111 by a plasma CVD method. A donor-type element having a constant concentration is distributed in the depth direction of the film.

On the other hand, FIG. 9B illustrates a case where a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed over the first crystalline semiconductor film 111. A donor-type element profile 140b is shown when a second semiconductor film is formed by forming and adding a donor-type element to the semiconductor film by ion doping or ion implantation. As shown in FIG. 9B, the donor-type element concentration is relatively high in the vicinity of the surface of the second semiconductor film. A region having a donor-type element concentration of 1 × 10 ¹⁹ / cm ³ or more is denoted as n + region 134a. On the other hand, as the first crystalline semiconductor film 111 is approached, the donor-type element concentration is relatively decreased. A region having a donor-type element concentration of 5 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ is referred to as an n-region 134b. The n + region 134a functions as a source region and a drain region later, and the n− region 134b functions as an LDD region. Note that there is no interface between the n + region and the n− region, and the interface varies depending on the relative concentration of the donor-type element. Thus, the second semiconductor film containing the donor element formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the film thicknesses of the n + region and the n− region Can be appropriately controlled.

Next, the first crystalline semiconductor film 111 and the second semiconductor film 112 are heated, and the catalyst element contained in the first crystalline semiconductor film 111 is added to the first crystalline semiconductor film 111 as indicated by an arrow in FIG. The second semiconductor film 112 is moved to getter the catalyst element. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ^3. It can be as follows. Such a film is hereinafter referred to as a second crystalline semiconductor film 121. Further, since the second semiconductor film 112 to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is hereinafter referred to as a third crystalline semiconductor film 122. In the present embodiment, the donor-type element in the third crystalline semiconductor film 122 is activated together with the gettering step.

  Note that in this embodiment, the second semiconductor film 112 containing a donor-type element is used as a gettering site and also as a film that functions as a later source region and drain region. For this reason, it is not necessary to newly provide films functioning as a source region and a drain region. That is, a thin film transistor having a crystalline semiconductor film can be manufactured without increasing the number of steps compared to the conventional method.

Next, as illustrated in FIG. 1D, the second crystalline semiconductor film 121 and the third crystalline semiconductor film 122 are etched using a mask formed by a photolithography process, and the first crystalline semiconductor film 122 is etched. A semiconductor region 131 and a second semiconductor region 132 are formed. Note that the second crystalline semiconductor film 121 and the third crystalline semiconductor film 122 are formed of chlorine-based gas such as Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , CF ₄ , SF ₆ , NF ₃ , Etching can be performed using a fluorine-based gas typified by CHF ₃ or the like, or O ₂ .

  Note that in the photolithography processes of the following embodiments and examples, an insulating film having a thickness of about several nm is preferably formed on the surface of the semiconductor film 122 before applying a resist. By this step, it is possible to avoid direct contact between the semiconductor film and the resist, and impurities can be prevented from entering the semiconductor film. Note that examples of a method for forming the insulating film include a method of applying an oxidizing solution such as ozone water, a method of irradiating oxygen plasma, ozone plasma, and the like.

  Next, a third conductive layer is formed. Next, a mask is formed over the third conductive layer by a photolithography process. Next, the third conductive layer is etched into a desired shape using the mask to form a third conductive film 133. The third conductive film 133 functions as a source electrode and a drain electrode.

  In the conductive film forming process of the embodiment and the example below, when an insulating film is formed on the surface of the semiconductor film during the photolithography process, it is preferable to etch the insulating film before forming the conductive film.

  As a material of the third conductive film, a metal such as Al, Ti, Mo, W, or an alloy thereof can be used. Moreover, you may form as these single layer or multilayer structure. Typically, Ti, Al, and Ti may be sequentially stacked from the substrate side, or Mo, Al, and Mo may be sequentially stacked.

  Next, as illustrated in FIG. 1E, the exposed portion of the second semiconductor region is etched using the third conductive film 133 as a mask, so that a source region and a drain region 142 are formed. At this time, a part of the first semiconductor region 131 may be over-etched. The over-etched first semiconductor region at this time is hereinafter referred to as a third semiconductor region 141. The third semiconductor region 141 functions as a channel formation region.

  Next, it is preferable to form a passivation film over the surfaces of the third conductive film 133 and the third semiconductor region 141. The passivation film contains silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), and nitrogen using a thin film formation method such as plasma CVD or sputtering. It can be formed using carbon or other insulating material. Note that the passivation film may be a single layer or a laminated structure. Here, in consideration of the interface characteristics of the third semiconductor region 141, silicon oxide or silicon oxynitride is preferably formed as the third insulating film 140. The fourth insulating film 144 is preferably formed using silicon nitride or silicon nitride oxide in order to prevent impurities from the outside from entering the semiconductor element.

  After that, the third semiconductor region 141 is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case of heating in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed in the third insulating film or the fourth insulating film.

  Through the above steps, an inverted staggered TFT having a crystalline semiconductor film can be formed. The TFT formed in this embodiment can form an inverted staggered TFT having a crystalline semiconductor film using a gate electrode or wiring which is a low-resistance metal film, and can also be used for a large area device. Can do. Further, since the TFT formed in this embodiment is formed of a crystalline semiconductor film, the mobility is higher than that of a TFT formed of an amorphous semiconductor film. Further, the source region and the drain region contain a catalyst element in addition to the donor element. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured. Typically, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, in comparison with an EL display device using a TFT formed of an amorphous semiconductor film as a switching element, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured. It is.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a display device, for example, a liquid crystal display device.

(Embodiment 2)
In this embodiment, a process for forming a TFT by gettering a catalytic element using a semiconductor film containing a rare gas element instead of a semiconductor film containing a donor element will be described with reference to FIGS.

  As shown in FIGS. 2A and 2B, a first crystalline semiconductor film 111 is formed by a process similar to that of Embodiment Mode 1. After this, a channel doping process may be performed. Next, an oxide film with a thickness of 1 to 5 nm may be formed on the surface of the first crystalline semiconductor film. Here, ozone water is applied to the surface of the crystalline semiconductor film to form an oxide film.

  Next, a second semiconductor film 212 containing a rare gas element is formed over the first crystalline semiconductor film 111 by a known method such as a PVD method or a CVD method. The second semiconductor film 212 is preferably an amorphous semiconductor film.

Next, the first crystalline semiconductor film 111 and the second semiconductor film 212 are heated by a method similar to that of Embodiment Mode 1, and the first crystalline semiconductor film is indicated by an arrow in FIG. The catalytic element contained in 111 is moved to the second semiconductor film 212 to getter the catalytic element. By this step, as in Embodiment 1, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the concentration of the catalytic element in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably It can be set to 1 × 10 ¹⁷ / cm ³ or less. Such a film is referred to as a second crystalline semiconductor film 221. Further, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 222.

  Next, as shown in FIG. 2D, after the third crystalline semiconductor film 222 is removed, a conductive second semiconductor film 223 is formed. Here, the second semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or 15 group element such as boron, phosphorus, or arsenic is added to a silicide gas. Note that the second semiconductor film may be formed using a film having any state selected from an amorphous semiconductor, a SAS, a crystalline semiconductor, and a microcrystalline semiconductor (μc). Note that in the case where the second semiconductor film is any one of a conductive amorphous semiconductor film, a SAS, and a microcrystalline semiconductor (μc), heat treatment for activating impurities is performed thereafter. On the other hand, when the second semiconductor film is a crystalline semiconductor having conductivity, heat treatment is not necessarily performed. Here, an amorphous silicon film containing phosphorus with a thickness of 100 nm is formed by plasma CVD, and then heated at 550 ° C. for 2 hours to activate the impurities.

  Next, as illustrated in FIG. 2E, a first semiconductor region 232 and a second semiconductor region 231 are formed by the same process as that in the first embodiment.

  Next, as illustrated in FIG. 2F, a source electrode and a drain electrode 133 are formed. Next, in a process similar to that in Embodiment 1, the first semiconductor region can be etched to form the source and drain regions 242, and the third semiconductor region 241 functioning as a channel formation region.

  Thereafter, an inverted staggered TFT can be formed by the same process as in the first embodiment. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

(Embodiment 3)
In this embodiment, the step of forming the n-channel TFT and the p-channel TFT on the same substrate is formed using FIG.

  As shown in FIG. 3A, a gate electrode 301 (consisting of a first conductive film 301a and a second conductive film 301b) and a gate electrode 302 (first film) are formed over a substrate 101 as in the first embodiment. A conductive film 302 a and a second conductive film 302 b are formed, and a first insulating film 103 and a second insulating film 104 are formed over the gate electrode 301 and the gate electrode 302. Next, by a process similar to that in Embodiment 1, a first crystalline semiconductor film and a second semiconductor film containing a donor element are formed thereon. Next, using the mask formed by a photolithography process, the first crystalline semiconductor film is etched into a desired shape to form a first semiconductor region, and the second semiconductor film is formed into a desired shape. Etching forms a second semiconductor region.

  Next, the first semiconductor region and the second semiconductor region are heated to move the catalytic element included in the first semiconductor region to the second semiconductor region as indicated by arrows in FIG. And gettering the catalytic element. Here, the first semiconductor region in which the metal element concentration is reduced is referred to as third semiconductor regions 311 and 312, and the second semiconductor region to which the catalytic element after gettering has moved is the fourth semiconductor regions 313 and 314. It shows. Note that the third semiconductor region and the fourth semiconductor region are each crystallized by heating in the gettering step.

  In this embodiment, the gettering process is performed after forming each semiconductor region, but after the gettering process of each semiconductor film is performed as in Embodiment 1, the semiconductor film is etched into a desired shape, Each semiconductor region may be formed.

  Next, after forming oxide films on the surfaces of the third semiconductor regions 311 and 312 and the fourth semiconductor regions 313 and 314, masks 321 and 322 are formed by a photolithography process as shown in FIG. To do. The mask 321 covers all of the third semiconductor region 311 and the fourth semiconductor region 313 that will be n-channel TFTs later. On the other hand, the mask 322 covers part of the fourth semiconductor region 314 that will later become a p-channel TFT. At this time, the first mask 322 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, a group 13 element (hereinafter referred to as an “acceptor type element”) is added to the exposed portion of the fourth semiconductor region 314 to form a p-type impurity region 324. At this time, the region covered with the mask 322 remains as the n-type impurity region 325. By adding an acceptor type element to the exposed portion of the fourth semiconductor region 314 so as to have a concentration 2 to 10 times that of the fourth semiconductor region 314 having a donor type element, a p-type impurity region is formed. be able to.

FIG. 10 shows a model diagram (not an actual measurement result) of the profile of the impurity element in the p-type impurity region. 10A, after forming a second semiconductor film containing a donor-type element by a CVD method and performing a gettering step, an acceptor-type element (boron is used in this embodiment). 5 shows the profile of each element in the p-type impurity region 601 when. The donor-type element profile 140a shows a constant concentration with respect to the depth direction of the region, as in FIG. 9A. The acceptor-type element profile 603 has a high concentration in the vicinity of the surface of the p-type impurity region 601, and the concentration decreases as it approaches the fourth semiconductor region 312. Incidentally, a region having a acceptor element 2 to 10 times the concentration of the donor element contained in the n ⁺ region indicated as p ⁺ region 602a, n ^- acceptor 2-10 times the concentration of the donor element of the region A region having an element is referred to as a p ⁻ region 602b.

FIG. 10B illustrates a case where a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed, and is formed by an ion doping method or an ion implantation method. A profile of each element in the p-type impurity region 611 when a donor-type element is added to the semiconductor film to form a second semiconductor film, a gettering process is performed, and then an acceptor-type element is added is shown. The donor-type element profile 140b is similar to the donor-type element profile 140b of FIG. 9B. The acceptor-type element profile 613 shows the same tendency as the acceptor-type element profile 603 in FIG. 10A, and the concentration is high in the vicinity of the surface of the p-type impurity region 611, and as it approaches the fourth semiconductor region 312. , The concentration is decreasing. Incidentally, a region having a acceptor element 2 to 10 times the concentration of the donor element contained in the n ⁺ region indicated as p ⁺ region 612a, n ^- acceptor 2-10 times the concentration of the donor element of the region A region having an element is referred to as a p ⁻ region 612b.

  In the second semiconductor film containing the donor element, a rare gas element (typically, argon) is added to form a distortion of the crystal lattice. Further gettering is possible.

  Next, after removing the first masks 321 and 322, the third semiconductor region 313 and the first semiconductor region 314 to which one acceptor element is added are heated to activate the impurity element. As a heating method, Rapid Thermal Annealing (RTA), furnace annealing, or the like using a gas, a halogen lamp, or an electron beam as a heat source can be used as appropriate. Here, RTA is used and heated at 675 ° C. for 3 minutes.

  Next, as shown in FIG. 3C, third conductive films 331 and 332 are formed as in the first embodiment. Next, source and drain regions 343 and 344 are formed using the third conductive films 331 and 332 as masks. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the third conductive films 331 and 332 and the fifth semiconductor regions 341 and 342.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, it is possible to form a CMOS that can be driven at a lower voltage than a drive circuit formed of a single channel TFT. Furthermore, since an acceptor element (eg, boron) has a smaller atomic radius than a donor element (eg, phosphorus), the acceptor element is added to the semiconductor film at a relatively low acceleration voltage and concentration. Is possible.

(Embodiment 4)
In this embodiment, an n-channel TFT and a p-channel manufacturing process including a crystalline semiconductor film formed by a different gettering process from that in Embodiment 3 will be described with reference to FIGS.

  In accordance with Embodiment Mode 1, a gate electrode 301 (consisting of a first conductive film 301a and a second conductive film 301b) and a gate electrode 302 (first conductive film 302a and second conductive film 302b are formed on the substrate 101. Is formed). Next, in accordance with Embodiment 1, after forming a first crystalline semiconductor film having a catalytic element as shown in FIG. 1B, an insulating film having a thickness of several nm is formed on the surface of the first crystalline semiconductor film. To do. Next, a first mask is formed by a photolithography process, and the first crystalline semiconductor film is etched into a desired shape, so that first semiconductor regions 401 and 402 are formed.

  Next, as shown in FIG. 4B, second masks 403 and 404 are formed over the first semiconductor regions 401 and 402 by a photolithography process, and then donors are formed on the exposed portions of the first semiconductor regions. Add type elements. At this time, regions to which the donor element is added are denoted as n-type impurity regions 406 and 407. Here, phosphorus is added by an ion doping method. Note that the first semiconductor region covered with the second mask does not contain phosphorus but contains a catalytic element.

  Next, the first semiconductor region is heated, and the catalyst element contained in the first semiconductor region is moved to the n-type impurity regions 406 and 407 as shown by arrows in FIG. Gettering elements. Here, the first semiconductor region to which the metal catalyst after gettering has moved is referred to as a source region and drain regions 413 and 414, and the first semiconductor region in which the metal element concentration is reduced is referred to as a channel formation region 411. Note that the third semiconductor region and the fourth semiconductor region are each crystallized by heating in the gettering step, and the donor-type element contained in the n-type impurity regions 406 and 407 is activated. Yes.

  Next, as shown in FIG. 4D, third masks 421 and 422 are formed by a photolithography process. The third mask 421 covers all of the channel formation region 411 and the n-type impurity region 413 that will later become n-channel TFTs. On the other hand, the third mask 422 covers part or all of the channel formation region 412 to be a p-channel TFT later. At this time, the third mask 422 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element is added to the exposed portions of the n-type impurity region 414 and the channel formation region 412 to form a p-type impurity region 424. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the n-type impurity region 414.

  Next, after the third masks 421 and 422 are removed, the n-type impurity region 414 and the p-type impurity region 424 are heated to activate the impurity element. As a heating method, Rapid Thermal Annealing (RTA), furnace annealing, or the like using a gas, a halogen lamp, or an electron beam as a heat source can be used as appropriate. Here, RTA is used and heated at 675 ° C. for 3 minutes.

  Next, as shown in FIG. 4D, third conductive films 331 and 332 are formed as in the first embodiment. Thereafter, part of the channel formation regions 411 and 412 may be etched. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the third conductive films 331 and 332 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, since the number of film formation steps can be reduced as compared with Embodiment Mode 3, throughput can be improved.

(Embodiment 5)
In the present embodiment, a step of forming an n-channel TFT and a p-channel TFT on the same substrate using the crystalline semiconductor film subjected to the gettering step using Embodiment Mode 2 is formed using FIG.

  In accordance with the steps of Embodiment Mode 1, a gate electrode 301 (consisting of a first conductive film 301a and a second conductive film 301b), 302 (a first conductive film 302a and a second conductive film 302b) is formed over the substrate 101. To form). Next, a first crystalline semiconductor film and a second semiconductor film containing a rare gas element are formed according to the steps of Embodiment Mode 2. Next, the first crystalline semiconductor film and the second semiconductor film are heated by a method similar to that in Embodiment 1 and are included in the first crystalline semiconductor film as indicated by arrows in FIG. The catalytic element is moved to the second semiconductor film to getter the catalytic element. The first crystalline semiconductor film in which the catalytic element is gettered is referred to as a second crystalline semiconductor film 501. In addition, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 502.

  Next, as shown in FIG. 5B, after the third crystalline semiconductor film 502 is etched, an insulating film having a thickness of several nm is formed on the surface of the second crystalline semiconductor film 501. Next, a first mask is formed by a photolithography process, and the second crystalline semiconductor film is etched to form first semiconductor regions 511 and 512. Next, second masks 513 and 514 are formed by a photolithography process. The second mask 513 covers a portion that later becomes a channel formation region of the n-channel TFT. On the other hand, the second mask 514 covers the entire first semiconductor region 512 that will later become a p-channel TFT. Next, a donor-type element is added to the exposed portion of the first semiconductor region 511. At this time, a region to which the donor element is added is referred to as an n-type impurity region 516. The region covered with the second mask 513 functions as a channel formation region 517.

  Next, after the second masks 513 and 514 are etched, new third masks 521 and 522 are formed. The third mask 521 covers all of the channel formation region 411 and the n-type impurity region 413 that will be n-channel TFTs later. On the other hand, the third mask 422 covers a region to be a channel formation region of the p-channel TFT later.

  Next, an acceptor element is added to the exposed portion of the semiconductor region 512 to form a p-type impurity region 524. Further, the region covered with the third mask 522 functions as a channel formation region 525. Next, after removing the third masks 521 and 522, the n-type impurity region 516 and the p-type impurity region 524 are heated to activate the impurity element. As a heating method, Rapid Thermal Annealing (RTA), furnace annealing, or the like using a gas, a halogen lamp, or an electron beam as a heat source can be used as appropriate.

  Next, as illustrated in FIG. 5D, third conductive films 331 and 332 are formed as in Embodiment 1. Thereafter, part of the channel formation regions 517 and 525 may be etched. Next, it is preferable to form passivation films 140 and 144 on the surfaces of the third conductive films 331 and 332 and the channel formation regions 517 and 525.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

(Embodiment 6)
In this embodiment, a process of forming an n-channel TFT and a p-channel TFT on the same substrate using a modification of the third embodiment is formed using FIG.

  According to Embodiment 3, as shown in FIG. 6A, third semiconductor regions 313 and 314 and fourth semiconductor regions 311 and 312 having a catalyst element and a donor element are formed. Next, as illustrated in FIG. 6B, after the first mask 321 is formed, an acceptor element is added to the third semiconductor region 314 to form a p-type impurity region 601. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the n-type impurity region 314. Further, when boron is used as the acceptor element, the molecular radius is small, so that it is added deeper than the third semiconductor regions 313 and 314. For this reason, boron is added above the fourth semiconductor regions 311 and 312 depending on the addition conditions. Thereafter, the third semiconductor region 313 and the p-type impurity region 601 are heated to activate the acceptor-type element and the donor-type element.

  Next, third conductive films 331 and 332 are formed according to the third embodiment. Next, the exposed portions of the third semiconductor region 313 and the p-type impurity region 601 are etched using the third conductive films 331 and 332 as a mask, so that a source region and a drain region 343 as illustrated in FIG. 622 and fifth semiconductor regions 341 and 611 functioning as channel formation regions can be formed. After that, it is preferable to form passivation films 140 and 144 on the surfaces of the third conductive films 331 and 332 and the channel formation regions 341 and 611.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

(Embodiment 7)
In this embodiment, the positional relationship between the end portions of the gate electrode, the source electrode, and the drain electrode, that is, the relationship between the width of the gate electrode and the size of the channel length in the above embodiment will be described with reference to FIGS. To do.

In FIG. 7A, the end portions of the source electrode and the drain electrode overlap each other on the gate electrode 102 by z1. Here, a region where the gate electrode 102 overlaps with the source electrode and the drain electrode is referred to as an overlap region. That is, the width y1 of the gate electrode is larger than the channel length x1. The width z1 of the overlap region is represented by (y1-x1) / 2. An n-channel TFT having such an overlap region has an n ⁺ region 134a and an n ⁻ region 134b as shown in FIG. 9B between the source and drain electrodes and the semiconductor region. preferable. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

  In FIG. 7B, the end portion of the gate electrode 102 is aligned with the end portions of the source electrode and the drain electrode. That is, the gate electrode width y2 is equal to the channel length x2.

  In FIG. 7C, the gate electrode 102 and the end portions of the source electrode and the drain electrode are separated by z3. Here, a region where the gate electrode 102 is separated from the source electrode and the drain electrode is referred to as an offset region. That is, the width y3 of the gate electrode is smaller than the channel length x3. The width z3 of the offset area is represented by (x3-y3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  In FIG. 8A, the width y4 of the gate electrode is larger than the channel length x4. In addition, the first end portion of the gate electrode 102 and one end portion of the source electrode or the drain electrode coincide with each other, and the second end portion of the gate electrode 102 and the other end portion of the source electrode or the drain electrode correspond to z4. Only overlap. The width z4 of the overlap region is represented by (y4-x4).

  In FIG. 8B, the width y5 of the gate electrode is smaller than the channel length x5. In addition, the first end portion of the gate electrode 102 and one end portion of the source electrode or the drain electrode coincide with each other, and the second end portion of the gate electrode 102 and the other end portion of the source electrode or the drain electrode become z5. Just away. The width z5 of the offset area is represented by (x5-y5). By using the electrode having the first end portion and the end portion of the gate electrode 102 as the source electrode and the electrode having the offset region as the drain electrode, electric field relaxation in the vicinity of the drain electrode can be achieved.

  In FIG. 8C, the first end portion of the gate electrode 102 overlaps with one end portion of the source electrode or the drain electrode by z6, and the second end portion of the gate electrode 102 and the other end of the source electrode or drain electrode overlap with each other. Is separated by z7. By using the electrode having the overlap region of the gate electrode 102 as the source electrode and the electrode having the offset region as the drain electrode, electric field relaxation in the vicinity of the drain electrode can be achieved.

  Further, a TFT having a so-called multi-gate structure in which a semiconductor region covers a plurality of gate electrodes may be used. A multi-gate TFT can also reduce off-state current.

(Embodiment 8)
In Embodiments 1 to 3 and 6, the semiconductor film containing a donor-type element includes a semiconductor film 145 containing a low-concentration donor-type element and a high-concentration donor-type element as shown in FIG. A two-layer structure of the semiconductor film 142 may be used. With such a stacked structure, a TFT having an LDD region 145 can be formed as shown in FIG. As a result, the effect of relaxing the electric field is increased, and it is possible to form a TFT with improved hot carrier resistance.

(Embodiment 9)
In the above-described embodiment, the source electrode and the drain electrode having end portions perpendicular to the surface of the channel formation region are shown; As shown in FIG. 26 (A), it may be an end portion that is larger than 90 degrees and smaller than 180 degrees, preferably 95 to 135 degrees with respect to the surface of the channel formation region. Further, if the angle between the source electrode and the channel formation region surface is θ1, and the angle between the drain electrode and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

  On the other hand, as shown in FIG. 26 (B), it may be an end portion that is larger than 0 degree and smaller than 90 degrees, preferably 45 to 85 degrees with respect to the channel formation region surface. Further, if the angle between the source electrode and the channel formation region surface is θ3, and the angle between the drain electrode and the channel formation region surface is θ4, θ3 and θ4 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a wet etching method.

(Embodiment 10)
In this embodiment, a semiconductor film crystallization process applicable to the above embodiment will be described with reference to FIGS. As shown in FIG. 22A, a semiconductor film may be crystallized by forming a mask 2701 formed of an insulating film over the semiconductor film 106 and selectively forming a catalytic element layer 2705. When the semiconductor film is heated, crystal growth occurs in a direction parallel to the surface of the substrate from a contact portion between the catalytic element layer and the semiconductor film, as indicated by an arrow in FIG. Note that crystallization is not performed in a portion considerably away from the catalyst element layer 2705, and an amorphous portion remains.

  Alternatively, as shown in FIG. 23A, the crystallization may be performed by selectively forming the catalyst element layer 2805 by a droplet discharge method without using a mask. FIG. 23B is a top view of FIG. FIG. 23D is a top view of FIG. When the semiconductor film is crystallized, crystal growth occurs in the direction parallel to the surface of the substrate from the contact portion between the catalytic element layer and the semiconductor film, as shown in FIGS. Again, crystallization is not performed at a portion far away from the catalyst element layer 2705, and an amorphous portion 2807 remains.

  Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth. Since large crystal grains can be formed by lateral growth, a TFT having higher mobility can be formed.

  In this embodiment, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. In this embodiment, a liquid crystal display device is used as a display device. FIGS. 14 and 16 are plan views of the active matrix substrate. FIGS. 11 to 13 schematically show the longitudinal cross-sectional structures corresponding to the drive circuit portion A-A ′ and the pixel portion B-B ′.

  First, a first conductive layer containing aluminum as a main component and having a thickness of 50 to 100 nm is formed over the substrate 800. Here, a glass substrate is used as the substrate 800, and a film containing aluminum as a main component and containing carbon and titanium is formed as a first conductive layer over the surface so as to have a thickness of 50 nm by a sputtering method.

  Next, a second conductive layer with a thickness of 50 to 100 nm is formed over the first conductive layer. Here, a titanium nitride film with a thickness of 50 nm is formed as the second conductive layer by a sputtering method.

  Next, as illustrated in FIG. 11A, the first conductive layer and the second conductive layer are etched using the first photomask to form gate electrodes 801 to 803 (each of the first conductive layers). 801a to 803a and second conductive films 801b to 803b). Here, the first conductive layer and the second conductive layer are etched by a dry etching method. Note that the second conductive films 801b to 803b function as protective films (cap films) that suppress generation of hillocks in the first conductive films 801a to 803a containing aluminum as a main component.

  Next, a first insulating film 805 and a second insulating film 806 are formed over the surface of the substrate 800 and the gate electrodes 801 to 803. Here, a 50-nm-thick silicon nitride film is stacked as the first insulating film 805, and a 100-nm-thick silicon oxynitride film (SiOxNy (x> y)) is stacked as the second insulating film 806 by a CVD method. Let it form. Note that the first insulating film 805 and the second insulating film 806 function as gate insulating films. At this time, it is preferable that the first insulating film 805 and the second insulating film 806 be continuously formed by only switching the source gas without being released to the atmosphere.

  Next, an amorphous semiconductor film 807 with a thickness of 10 to 100 nm is formed over the first insulating film. Here, an amorphous silicon film with a thickness of 100 nm is formed by a CVD method. Next, a solution 808 containing a catalytic element is applied over the surface of the amorphous semiconductor film 807. Here, a solution containing 100 ppm of nickel catalyst is applied by spin coating. Next, the amorphous semiconductor film 807 is heated to form a crystalline semiconductor film 811 as shown in FIG. Note that the crystalline semiconductor film 811 contains a catalyst element. In this embodiment, RTA is used and heated at 650 ° C. for 6 minutes to form a crystalline silicon film containing nickel. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively.

  Next, a semiconductor film 812 containing a donor-type element with a thickness of 100 nm is formed over the surface of the crystalline semiconductor film 811 containing a catalytic element. Here, an amorphous silicon film containing phosphorus is formed using silane gas and 0.5 vol% phosphine gas (flow rate ratio: silane / phosphine = 10/17).

  Next, the crystalline semiconductor film 811 and the semiconductor film 812 containing a donor element are heated to getter the catalytic element and activate the donor element. In this embodiment, RTA is used and heated at 650 ° C. for 6 minutes to move the catalytic element in the crystalline semiconductor film 811 containing the catalytic element to the semiconductor film 812 containing the donor-type element. A crystalline semiconductor film thus formed with reduced concentration of the catalytic element is denoted by reference numeral 813 in FIG. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film 814 containing a catalyst element and a donor element is formed. In this embodiment, a crystalline silicon film containing nickel and phosphorus is formed.

  Next, the crystalline semiconductor film 813 and the crystalline semiconductor film 814 containing a catalyst element and a donor element are etched into a desired shape using a second photomask. The etched crystalline semiconductor film 813 is referred to as first semiconductor regions 821 to 823, and the etched crystalline semiconductor film containing a catalytic element and a donor element is referred to as second semiconductor regions 824 to 826.

  Next, in the driver circuit, one of the first insulating film 805 and the second insulating film 806 is formed using a third photomask in order to connect the gate electrode and the source electrode or the drain electrode of some TFTs. The portion is etched to form a contact hole 850 as shown in FIG.

  Next, as illustrated in FIG. 12B, a third conductive layer functioning as a pixel electrode is formed over the second insulating film 806 formed over the substrate. As a material for the third conductive layer, a light-transmitting conductive film or a reflective conductive film can be given. As a material for the light-transmitting conductive film, indium tin oxide (ITO), zinc oxide, indium zinc oxide (IZO), zinc oxide added with gallium (GZO), and indium tin oxide containing silicon oxide ( ITSO). In addition, as a material for the conductive film having reflectivity, a metal such as aluminum (Al), titanium (Ti), silver (Ag), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal is used. A metal material containing nitrogen, titanium nitride which is a nitride of the metal, tantalum nitride, aluminum containing 1 to 20 atomic% nickel, or the like can be given. Next, the third conductive layer 851 is formed by etching the third conductive layer into a desired shape. As a formation method of the third conductive film 851, a sputtering method, an evaporation method, a CVD method, a coating method, or the like is appropriately used. In this embodiment, indium tin oxide (ITSO) containing silicon oxide with a thickness of 110 nm is formed and etched into a desired shape, so that the third conductive film 851 is formed.

  Next, a fourth conductive film with a thickness of 100 to 300 nm is in contact with the first semiconductor regions 821 to 823, the second semiconductor regions 824 to 826, the second insulating film 806, and the third conductive film 851. Deposit layers. Here, a molybdenum film with a thickness of 200 nm is formed by a sputtering method. Next, using the fourth photomask, the fourth conductive layer is etched into a desired shape, so that fourth conductive films 830 to 835 are formed. In this embodiment, the molybdenum film is etched by a wet etching method using a solution containing phosphoric acid, acetic acid, and nitric acid (mixed acid), so that fourth conductive films 830 to 835 are formed. Note that the fourth conductive films 830 to 835 function as a source electrode and a drain electrode.

  Next, the second semiconductor regions 824 to 826 are etched using the fourth conductive films 830 to 835 as masks to form source and drain regions 836 to 839. At this time, part of the first semiconductor regions 821 to 823 is also etched. The etched first semiconductor regions (third semiconductor regions) 840 to 842 function as channel formation regions.

  Next, as illustrated in FIG. 12C, the third insulating film 852 is in contact with the surfaces of the second insulating film 806, the fourth conductive films 830 to 835, and the third semiconductor regions 840 to 842, and A fourth insulating film 853 is formed. In this embodiment, as the third insulating film 852, a 150-nm-thick silicon oxynitride film containing hydrogen is formed by a CVD method. In addition, as the fourth insulating film, a silicon nitride film having a thickness of 200 nm is formed by a CVD method. Note that the silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, although not shown, the silicon nitride film and the silicon oxynitride film formed on the wiring in the connection terminal portion are etched to expose the wiring surface so as to be connected to the external terminal.

  Next, the third semiconductor regions 840 to 842 are heated and hydrogenated. Here, by heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the third insulating film 852 is added to the third semiconductor regions 840 to 842 and hydrogenated.

  Note that the planar structure of the vertical cross-sectional structure B-B ′ of the pixel portion in FIG. 12C is shown in FIG.

  Through the above steps, an active matrix substrate of a liquid crystal display device including a driver circuit formed using n-channel TFTs 861 and 862 and a pixel portion including an n-channel TFT 863 having a double gate 803 can be formed. . In this embodiment, since the drive circuit is formed of n-channel TFTs, it is not necessary to form p-channel TFTs, and the number of processes can be reduced.

  Next, as illustrated in FIG. 13, an insulating film is formed by a printing method or a spin coating method so as to cover the fourth insulating film 853, and rubbing is performed to form an alignment film 871. Note that by forming the alignment film 871 by an oblique deposition method, the alignment film 871 can be formed at a low temperature, and the alignment film can be formed over a plastic having low heat resistance.

  A second pixel electrode (counter electrode) 873 and an alignment film 874 are formed over the counter substrate 872. Next, a closed loop sealing material is formed over the counter substrate 872. At this time, the sealing material is formed in a region around the pixel portion by using a droplet discharge method. Next, a liquid crystal material is dropped inside the closed loop formed of the sealing material by a dispenser type (dropping type).

  A filler may be mixed in the sealing material, and a color filter, a shielding film (black matrix), or the like may be formed on the counter substrate 872.

  Next, the counter substrate 872 provided with the alignment film 874 and the second pixel electrode (counter electrode) 873 and the active matrix substrate are bonded to each other in a vacuum, and ultraviolet curing is performed, so that a liquid crystal filled with a liquid crystal material is obtained. Layer 875 is formed. Note that as a method for forming the liquid crystal layer 875, a dip type (pumping type) in which a liquid crystal material is injected using a capillary phenomenon after the counter substrate is bonded can be used instead of the dispenser type (dropping type).

  Through the above process, a liquid crystal display panel can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (gate wiring) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above-described TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain or source wiring layer of the diode.

  Through the above process, a liquid crystal display device can be formed. Note that any of Embodiment Modes 1 to 10 can be applied to this example.

  In this embodiment, the appearance of a liquid crystal display device panel, which is one embodiment of the semiconductor device of the present invention, will be described with reference to FIG. FIG. 15A is a top view of a panel in which a space between the first substrate 1600 and the second substrate 1604 is sealed with the first sealant 1605 and the second sealant 1606. FIG. FIG. 15B corresponds to a cross-sectional view taken along lines AA ′ and BB ′ in FIG. The active matrix substrate formed in Embodiment 1 can be used for the first substrate 1600.

  In FIG. 15A, 1602 indicated by a dotted line is a pixel portion, and 1603 is a scanning line driver circuit. Reference numeral 1601 indicated by a solid line is a signal line (gate line) drive circuit. In this embodiment, the pixel portion 1602 and the scan line driver circuit 1603 are in a region sealed with a first sealant and a second sealant. Reference numeral 1601 denotes a signal line (source line) driver circuit, and a chip-like signal line driver circuit is provided on the first substrate 1600.

  Reference numeral 1600 denotes a first substrate, 1604 denotes a second substrate, and 1605 and 1606 denote a first sealing material and a second sealing material each containing a gap material for maintaining a space between the sealed spaces. is there. The first substrate 1600 and the second substrate 1604 are sealed with a first sealant 1605 and a second sealant 1606, and a liquid crystal material is filled therebetween.

  Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1600 and have a plurality of semiconductor elements typified by TFTs. A color filter 1621 is provided on the surface of the second substrate 1604. A scan line driver circuit 1603 and a pixel portion 1602 are shown as driver circuits. Note that as the scan line driver circuit 1603, a CMOS circuit in which an n-channel TFT 1612 and a p-channel TFT 1613 are combined is formed. Note that the driver circuit may be formed of a single channel TFT as in the first embodiment.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the display device can be reduced.

  A plurality of pixels are formed in the pixel portion 1602, and a liquid crystal element 1615 is formed in each pixel. The liquid crystal element 1615 is a portion where the first electrode 1616, the second electrode 1618, and the liquid crystal material 1619 filled therebetween overlap. A first electrode 1616 included in the liquid crystal element 1615 is electrically connected to the TFT 1611 through a wiring 1617. Although the first electrode 1615 is formed after the wiring 1617 is formed here, the wiring 1617 may be formed after the first electrode 1616 is formed as shown in Embodiment 1. The second electrode 1618 of the liquid crystal element 1615 is formed on the second substrate 1604 side. In addition, alignment films 1630 and 1631 are formed on the surface of each pixel electrode.

  Reference numeral 1622 denotes a columnar spacer, which is provided to control the distance (cell gap) between the first electrode 1616 and the second electrode 1618. The insulating film is formed by etching into a desired shape. A spherical spacer may be used. Various signals and potentials supplied to the signal line driver circuit 1601 or the pixel portion 1602 are supplied from the FPC 1609 through the connection wiring 1623. Note that the connection wiring 1623 and the FPC are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1627. Note that a conductive paste such as solder may be used instead of the anisotropic conductive film or the anisotropic conductive resin.

  Although not illustrated, a polarizing plate is fixed to one or both surfaces of the first substrate 1600 and the second substrate 1604 with an adhesive. Note that a circularly polarizing plate or an elliptically polarizing plate provided with a retardation plate may be used as the polarizing plate.

  Next, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. In this embodiment, a light-emitting display device is used as the display device. FIG. 19 is a plan view of the active matrix substrate, and a longitudinal sectional structure corresponding to B-B ′ of the pixel portion is schematically shown in FIGS. 17 and 18. Although not shown in a plan view, the longitudinal sectional structure of the drive circuit is schematically shown in A-A ′ of FIGS. 17 and 18.

  As shown in FIG. 17A, after the first conductive layer having a thickness of 50 to 100 nm and the second conductive layer having a thickness of 50 to 100 nm are sequentially formed over the substrate 900 as in Example 1, Etching is performed to form gate electrodes 901 to 904 (each of which includes first conductive films 901a to 904a and second conductive films 901b to 904b).

  Next, a first insulating film 905 and a second insulating film 906 are formed over the surface of the substrate 900 and the gate electrodes 901 to 904.

  Next, an amorphous semiconductor film with a thickness of 10 to 100 nm is formed over the first insulating film, and a solution containing a catalytic element is applied over the surface of the amorphous semiconductor film. Next, the amorphous semiconductor film is heated to form a crystalline semiconductor film. Note that the crystalline semiconductor film contains a catalytic element. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively.

  Next, a semiconductor film 908 containing a donor-type element with a thickness of 100 nm is formed over the surface of the crystalline semiconductor film 907 containing a catalytic element. Next, the crystalline semiconductor film and the semiconductor film 812 containing the donor element are heated to getter the catalyst element and activate the donor element. That is, the catalyst element in the crystalline semiconductor film 907 containing the catalyst element is moved to the semiconductor film containing the donor element. A crystalline semiconductor film in which the concentration of the catalytic element is reduced at this time is indicated by reference numeral 907 in FIG. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by reference numeral 908 in FIG.

  Next, the crystalline semiconductor film 907 and the crystalline semiconductor film 908 containing a catalyst element and a donor element are etched into a desired shape using a second photomask. At this time, the etched crystalline semiconductor film 908 containing the catalytic element and the donor-type element is referred to as a first semiconductor region 915 to 918, and the etched crystalline semiconductor film 907 is referred to as a second semiconductor region 911 to 914.

  Next, as illustrated in FIG. 17C, first masks 920 to 923 are formed using a third photomask. The first mask 920 covers the entire first semiconductor region 915 and the second semiconductor region 911. Further, the first mask 921 covers the entire first semiconductor region 917 and the second semiconductor region 913. These semiconductor regions later function as n-channel TFTs. In addition, the first masks 922 and 923 cover parts of the first semiconductor regions 916 and 918, respectively. At this time, the first masks 922 and 923 are preferably narrower than the channel length of a TFT to be formed later. Note that the first semiconductor regions 916 and 918 and the second semiconductor regions 912 and 914 covered by the first semiconductor regions 916 and 918 later function as p-channel TFTs.

  Next, an acceptor element is added to the exposed portions of the first semiconductor regions 912 and 914 to form p-type impurity regions 925, 926, 928, and 930. At this time, regions covered with the first masks 922 and 923 remain as n-type impurity regions 927 and 923.

  Next, after the first masks 920 to 923 are removed, the first semiconductor regions 915 and 917 and the first semiconductor regions 916 and 918 to which the acceptor element is added are heated to activate the impurity element. . Here, heating is performed at 550 degrees for 1 hour.

  Through the above steps, the pixel circuit includes a driver circuit formed of an n-channel TFT 952 and a p-channel TFT 953, a switching TFT 954 formed of an n-channel TFT, and a driver TFT 955 formed of a p-channel TFT. An active matrix substrate of a light emitting display device can be formed.

  Next, a third conductive layer is formed. The third conductive layer is formed by stacking a reflective conductive film and a transparent conductive film. Here, a titanium nitride film and indium tin oxide containing silicon oxide (ITSO) are stacked by a sputtering method. Next, the third conductive layer is etched using the fourth photomask to form a third conductive film 951 functioning as a pixel electrode.

  Next, a part of the first insulating films 905 and 906 formed on the surface of the gate electrode 904 in FIG. 19 is etched using a fifth photomask (not shown) to form a contact hole 909. Then, a part of the gate electrode 904 is exposed.

  Next, as shown in FIG. 18A, as in Example 1, after the fourth conductive layer is formed, the fourth conductive layer is etched into a desired shape using a sixth photomask. Conductive films 931 to 938 are formed. The fourth conductive film 936 is connected to the gate electrode 904. Note that the fourth conductive films 931 to 938 function as a source electrode and a drain electrode.

  Next, the first semiconductor region is etched using the fourth conductive films 931 to 938 as masks to form source and drain regions 941 to 948. At this time, a part of the second semiconductor region is also etched. The third semiconductor region which is the etched second semiconductor region functions as a channel formation region.

  Next, as illustrated in FIG. 12C, a third insulating film 852 and a fourth insulating film 853 are formed over the surfaces of the third conductive film, the fourth conductive film, and the third semiconductor region. To do. Here, a 150-nm-thick silicon oxynitride film containing hydrogen is formed by a CVD method as the fourth insulating film. Further, a silicon nitride film with a thickness of 200 nm is formed as the fifth insulating film by a CVD method. Note that the silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, the third semiconductor region is heated and hydrogenated. Here, by heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the third insulating film is added to the third semiconductor region and hydrogenated.

  Next, after a fifth insulating film is formed over the entire surface, the fifth insulating film, the fourth insulating film, and the third insulating film are etched using a seventh photomask, and the fifth insulating film is etched. The insulating layer 961, the fourth insulating layer 966, and the third insulating layer 965 are formed. In the case where the third to fifth insulating layers are formed, processing is performed so that the first pixel electrode 951 and the connection terminal portion are exposed.

  As a material for the fifth insulating film, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide ( Among the compounds consisting of silicon, oxygen and hydrogen formed from a heat-resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane polymer material typified by silica glass, Si— Hydrogen on silicon typified by inorganic siloxane polymer containing O-Si bond, alkylsiloxane polymer, alkylsilsesquioxane polymer, hydrogenated silsesquioxane polymer, hydrogenated alkylsilsesquioxane polymer is methyl or phenyl. It may be an organic siloxane polymer based insulating material which is substituted by an organic group such as. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the second insulating layer can be planarized by being formed by a coating method. Note that by using an organic material in which a material that absorbs visible light, such as a black pigment or a dye, is used as the fifth insulating layer, stray light absorption of a light-emitting element to be formed later can be prevented from occurring in the fifth insulating layer. It is absorbed by the layer, and the contrast of each pixel can be improved. Further, it is preferable to form the fifth insulating layer using a photosensitive material because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. Here, the fifth insulating film is formed by applying and baking an acrylic resin by a coating method.

  Through the above steps, an active matrix substrate of a light-emitting display device can be formed.

  Next, an electroluminescent layer 963 is formed over the surface of the third conductive film 951 and the end portion of the fifth insulating layer 961 by an evaporation method, a coating method, a droplet discharge method, or the like. Next, a fifth conductive film 964 functioning as a second pixel electrode is formed over the electroluminescent layer 963. Here, indium tin oxide containing silicon oxide (ITSO) is formed by a sputtering method. As a result, a light-emitting element can be formed using the third conductive film, the electroluminescent layer, and the fifth conductive film. Each material of the conductive film and the electroluminescent layer constituting the light-emitting element is appropriately selected, and each film thickness is also adjusted.

  Note that before the electroluminescent layer 963 is formed, heat treatment is performed at 200 to 350 ° C. under atmospheric pressure to remove moisture adsorbed in or on the surface of the fifth insulating layer 961. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and the electroluminescent layer 963 is directly exposed to the air without being exposed to the atmosphere, or a liquid droplet ejection method under atmospheric pressure or reduced pressure, Is preferably formed by a coating method or the like.

  The electroluminescent layer 963 is formed of a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light emitting material, and has a low molecular weight organic compound and a medium molecular weight organic compound (a molecule that does not have sublimation and is chained based on the number of molecules thereof. Including organic compounds having a length of 10 μm or less, typically dendrimers, oligomers, etc.), including one or more layers selected from high molecular organic compounds, and having an electron injection / transport property or hole injection It may be combined with a transporting inorganic compound.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, by providing a filter (colored layer) that transmits light in the emission wavelength band on the light emission side of the pixel, the color purity is improved and the pixel portion is mirrored (reflected). Prevention can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

  On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the high molecular weight organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used, and the cathode, the electroluminescent layer, and the anode are sequentially formed from the substrate side. However, when forming an electroluminescent layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. Become. Specifically, the structure is a cathode, an electroluminescent layer, a hole transport layer, and an anode in order from the substrate side.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting material.

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. Moreover, when forming a light emitting layer by the apply | coating method using spin coating, after apply | coating, it is preferable to bake by vacuum heating.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material.

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the electroluminescent layer listed above are examples, and the functionality such as a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emitting layer, an electron block layer, a hole block layer, etc. A light emitting element can be formed by appropriately stacking these layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  Next, a transparent protective layer 964 that covers the light-emitting element and prevents moisture from entering is formed. As the transparent protective layer 964, a silicon nitride film, a silicon oxide film, a silicon oxynitride film (SiNO film (composition ratio N> O) or SiON film (composition ratio N <O)) obtained by sputtering or CVD, carbon A thin film (for example, a DLC film or a CN film) whose main component is can be used.

  Through the above process, a light-emitting display panel can be manufactured. Note that a protective circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring layer (gate wiring layer) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above-described TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain wiring layer or the source wiring layer of the diode.

  Note that any of Embodiment Modes 1 to 10 can be applied to this example. Further, in the first and second embodiments, the liquid crystal display device and the light-emitting display device have been described as examples in the first and second embodiments. However, the present invention is not limited to this, and a DMD (Digital Micromirror Device) may be used. The present invention can be appropriately applied to an active display panel such as a plasma display panel (PDP), a field emission display (FED), and an electrophoretic display device (electronic paper).

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIGS.

  In FIG. 21A, the first pixel electrode 11 is formed using a light-transmitting conductive film having a high work function, and the second pixel electrode 17 is formed using a conductive film having a low work function. It is an example. The first pixel electrode 11 is formed of a light-transmitting oxide conductive material, and is typically formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. An electroluminescent layer 16 in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked thereon is provided. The second pixel electrode 17 is formed of a first electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or MgAg and a second electrode layer 34 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 11 side as indicated by an arrow in the figure.

In FIG. 21B, the first pixel electrode 11 is formed using a conductive film having a high work function, and the second pixel electrode 17 is formed using a light-transmitting conductive film having a low work function. It is an example. The first pixel electrode 11 includes a first electrode layer 35 formed of a metal such as aluminum or titanium, or a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of the metal, and silicon oxide 1-15. It is formed in a stacked structure with the second electrode layer 32 formed of an oxide conductive material containing at a concentration of atomic%. An electroluminescent layer 16 in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked thereon is provided. The second pixel electrode 17 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF ₂ and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting any layer of the second electrode to a thickness of 100 nm or less so that light can be transmitted, it is possible to emit light from the second electrode 17 as indicated by an arrow in the figure. Become.

In FIG. 21C, the first pixel electrode 11 is formed using a light-transmitting conductive film having a low work function, and the second pixel electrode 17 is formed using a conductive film having a high work function. It is an example. The structure in which the electroluminescent layer is laminated in the order of the electron transport layer or electron injection layer 43, the light emitting layer 42, the hole injection layer or the hole transport layer 41 is shown. The second pixel electrode 17 includes a second electrode layer 32 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the electroluminescent layer 16 side, a metal such as aluminum or titanium, or the The first electrode layer 35 is formed of a stacked structure formed using a metal material containing nitrogen at a concentration equal to or less than the stoichiometric composition ratio of metal. The first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF ₂ and a fourth electrode layer 34 formed of a metal material such as aluminum. This layer is also set to a thickness of 100 nm or less so that light can be transmitted, so that light can be emitted from the first pixel electrode 11 as indicated by an arrow in the figure.

  In FIG. 21D, the first pixel electrode 11 is formed using a conductive film having a low work function, and the second pixel electrode 17 is formed using a light-transmitting conductive film having a high work function. It is an example. The structure in which the electroluminescent layer is laminated in the order of the electron transport layer or electron injection layer 43, the light emitting layer 42, the hole injection layer or the hole transport layer 41 is shown. The first pixel electrode 11 has a structure similar to that shown in FIG. 21C, and is formed so as to reflect the light emitted from the electroluminescent layer. The second pixel electrode 17 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, the hole injection layer 41 is formed of an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), so that oxygen introduced when the second electrode layer 32 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered. In addition, by forming the second pixel electrode 17 from a light-transmitting conductive film, light can be emitted from the second electrode 17 as indicated by arrows in the drawing.

FIG. 21E illustrates an example in which light is emitted from both directions, that is, the first electrode and the second electrode. A conductive film having a light-transmitting property and a high work function is provided on the first pixel electrode 11. In addition, a conductive film having translucency and a small work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 17 is formed of LiF having a thickness of 100 nm or less. As shown by the arrows in the figure, the third electrode layer 33 containing an alkali metal or alkaline earth metal such as CaF ₂ and the fourth electrode layer 34 formed of a metal material such as aluminum are used. Thus, light can be emitted from both sides of the first pixel electrode 11 and the second electrode 17.

FIG. 21F illustrates an example in which light is emitted from both directions, that is, the first pixel electrode and the second pixel electrode, and the first pixel electrode 11 has a light-transmitting property and has a small work function. A film is used, and a conductive film having translucency and a large work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF _{2 having} a thickness of 100 nm or less and a metal material such as aluminum. The fourth electrode layer 34 may be formed, and the second pixel electrode 17 may be formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  As described above, various pixel circuits can be employed.

  In this embodiment, as an example of a display panel, the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 20A is a top view of a panel in which a space between a first substrate and a second substrate is sealed with a first sealant 1205 and a second sealant 1206. FIG. ) Corresponds to cross-sectional views taken along lines AA ′ and BB ′ in FIG.

  In FIG. 20A, 1202 indicated by a dotted line is a pixel portion, and 1203 is a scanning line (gate line) driving circuit. In this embodiment, the pixel portion 1202 and the scanning line driver circuit 1203 are in a region sealed with a first sealing material and a second sealing material. Reference numeral 1201 denotes a signal line (source line) drive circuit, and a chip-like signal line drive circuit is provided on the first substrate 1200. As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. As the second sealing material, it is preferable to use an epoxy resin having a low viscosity. In addition, the first sealing material 1205 and the second sealing material are desirably materials that do not transmit moisture and oxygen as much as possible.

Further, a desiccant may be provided between the pixel portion 1202 and the sealant 1205. Further, in the pixel portion, a desiccant may be provided on the scan line or the signal line. As the desiccant, it is preferable to use a substance that adsorbs water (H ₂ O) by chemical adsorption such as an alkaline earth metal oxide such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  In addition, the resin can be fixed to the second substrate 1204 in a state where a highly moisture-permeable resin contains a granular material of a desiccant. Further, instead of a highly moisture-permeable resin, an inorganic substance such as a siloxane polymer, polyimide, PSG (phosphorus glass), or BPSG (phosphorus glass) may be used.

  Further, a desiccant may be provided in a region overlapping with the scanning line. Furthermore, you may fix to the 2nd board | substrate in the state which included the granular substance of the desiccant in resin with high moisture permeability. By providing these desiccants, it is possible to suppress the intrusion of moisture into the display element and the deterioration caused thereby without reducing the aperture ratio. For this reason, it is possible to suppress variations in deterioration of the light emitting elements in the peripheral portion and the central portion of the pixel portion 1202.

  Note that reference numeral 1210 denotes a connection region for transmitting signals input to the signal line driver circuit 1201 and the scanning line driver circuit 1203, from an FPC (flexible printed wiring) 1209 serving as an external input terminal via a connection wiring 1208. Receive video and clock signals.

  Next, a cross-sectional structure will be described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1200, and includes a plurality of semiconductor elements typified by TFTs. A signal line driver circuit 1201 and a pixel portion 1202 are shown as driver circuits. Note that as the signal line driver circuit 1201, a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined is formed.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the light emitting display device can be reduced.

  The pixel portion 1202 is formed of a plurality of pixels including a switching TFT 1211, a driving TFT 1212, and a first pixel electrode (anode) 1213 made of a reflective conductive film electrically connected to the drain thereof. .

  In addition, insulators (called banks, partition walls, barriers, banks, or the like) 1214 are formed at both ends of the first pixel electrode (anode) 1213. In order to improve the coverage (coverage) of the film formed over the insulator 1214, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 1214. The surface of the insulator 1214 may be covered with a protective film formed of an aluminum nitride film, an aluminum nitride oxide film, a thin film containing carbon as its main component, or a silicon nitride film. Further, by using an organic material obtained by dissolving or dispersing a material that absorbs visible light, such as a black pigment or a dye, as the insulator 1214, stray light from a light-emitting element to be formed later can be absorbed. As a result, the contrast of each pixel is improved.

  Further, an organic compound material is deposited on the first pixel electrode (anode) 1213 to selectively form the electroluminescent layer 1215. Further, a second pixel electrode (cathode) is formed on the electroluminescent layer 1215.

  The structure shown in Embodiment 3 can be used as appropriate for the electroluminescent layer 1215.

  In this manner, a light emitting element 1217 including the first pixel electrode (anode) 1213, the electroluminescent layer 1215, and the second pixel electrode (cathode) 1216 is formed. The light-emitting element 1217 emits light toward the second substrate 1204 side.

  In addition, a protective stack 1218 is formed in order to seal the light emitting element 1217. The protective laminate includes a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film. Next, the protective laminate 1218 and the second substrate 1204 are bonded with the first sealant 1205 and the second sealant 1206. Note that the second sealant is preferably dropped using a device for dropping the sealant. After the sealing material is dropped or discharged from the dispenser and applied onto the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum, and the sealing material is cured and sealed. be able to.

  Note that an antireflection film 1226 is provided on the surface of the second substrate 1204 to prevent external light from being reflected by the substrate surface. One or both of a polarizing plate and a retardation plate may be provided between the second substrate and the antireflection film. By providing the retardation plate and the polarizing plate 1225, it is possible to prevent external light from being reflected by the pixel electrode. Note that the first pixel electrode 1213 and the second pixel electrode 1216 are formed using a light-transmitting conductive film or a semi-transparent conductive film, and the interlayer insulating film 1214 absorbs visible light, or When an organic material formed by dissolving or dispersing a material that absorbs visible light is used, external light is not reflected by each pixel electrode, so that a retardation plate and a polarizing plate may not be used.

  The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Note that a space filled with an inert gas such as nitrogen gas may be provided between the second substrate 1204 and the protective laminate 1218 instead of the second sealant 1206. It is possible to enhance prevention of moisture and oxygen from entering.

  In addition, a colored layer can be provided between the second substrate and the polarizing plate 1225. In this case, a full color display can be performed by providing a light emitting element capable of emitting white light in the pixel portion and separately providing a colored layer showing RGB. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Furthermore, each pixel portion, a light emitting element that emits red, green, and blue light can be formed, and a colored layer can be used. Such a display module has high color purity of each RBG and enables high-definition display.

  Alternatively, the light-emitting display module may be formed using one of the first substrate 1200 and the second substrate 1204, or a substrate such as a film or resin. When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

  Further, an IC chip such as a controller, a memory, and a pixel driver circuit may be provided on the surface or end of an FPC (flexible printed wiring) 1209 that serves as an external input terminal to form a light emitting display module.

  Note that any of Embodiment Modes 1 to 10 can be applied to this example. Moreover, although the example of the liquid crystal display module and the light emission display module was shown as a display module, it is not restricted to this, DMD (Digital Micromirror Device; Digital micromirror device), PDP (Plasma Display Panel; Plasma display panel), The present invention can be appropriately applied to display modules such as FED (Field Emission Display) and electrophoretic display devices (electronic paper).

  As an electronic device in which the display device described in the above embodiment is incorporated in a housing, a television device (also simply referred to as a TV, a television, or a television receiver), a camera (such as a video camera or a digital camera), a goggle type display, Navigation system, sound playback device (car audio, audio component, etc.), computer, game machine, portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), image playback device (including a recording medium) Specifically, DVD (digital versatile disc), HD DVD (High Definition DVD), Blu-ray Disc (Blu-ray Disc) and other recording media playback device that can display the image), other display Have part Such as electrical appliances and the like that. A specific example of the electronic device is illustrated in FIG.

  A portable information terminal illustrated in FIG. 24A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a highly reliable portable information terminal can be provided at low cost.

  A digital video camera shown in FIG. 24B includes a display portion 9701, a display portion 9702, and the like. As the display portion 9701, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a highly reliable digital video camera can be provided at low cost.

  A portable terminal illustrated in FIG. 24C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, the display modes in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a highly reliable portable terminal can be provided at low cost.

  A portable television device shown in FIG. 24D includes a main body 9301, a display portion 9302, and the like. As the display portion 9302, the display portions shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a highly reliable portable television device can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 24E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a portable computer having high reliability can be provided at low cost.

  A television device illustrated in FIG. 24F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, the display portions shown in Embodiment Modes 1 to 10 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a highly reliable television device can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

  In addition to the electronic devices described above, the projector can be used for a front or rear projector.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. Sectional drawing explaining the element profile in the semiconductor film of the semiconductor device which concerns on this invention. Sectional drawing explaining the element profile in the semiconductor film of the semiconductor device which concerns on this invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 10 is a top view illustrating a structure of a semiconductor device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a semiconductor device according to the invention. The top view explaining the drive circuit applicable to this invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. FIG. 10 is a top view illustrating a structure of a semiconductor device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a semiconductor device according to the invention. 4A and 4B each illustrate a mode of a light-emitting element that can be applied to the present invention. Sectional drawing explaining the crystallization process applicable to this invention. Sectional drawing and top view explaining the crystallization process applicable to this invention. 10A and 10B each illustrate an example of an electronic device. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention. FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device according to the invention.

Explanation of symbols

101 substrate 102a first conductive film 102b second conductive film 102 gate electrode 103 first insulating film 104 second insulating film 105 first semiconductor film 106 layer 111 containing a catalytic element first crystalline semiconductor film 112 Second semiconductor film 121 Second crystalline semiconductor film 122 Third crystalline semiconductor film 131 First semiconductor region 132 Second semiconductor region 133 Third conductive film (source electrode, drain electrode)
140 Third insulating film 141 Third semiconductor region (channel formation region)
142 Source region, drain region 144 Fourth insulating film

Claims (19)

Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form an island-shaped semiconductor region;
Forming a third conductive layer on the island-shaped semiconductor region;
A source electrode and a drain electrode are formed by patterning the third conductive layer, and the second semiconductor film is etched in the island-shaped semiconductor region using the source electrode and the drain electrode as a mask, A method for manufacturing a semiconductor device, comprising exposing a part of the semiconductor film and forming a source region and a drain region. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element on the first semiconductor film and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form an island-shaped semiconductor region;
Of the island-shaped semiconductor regions, the second semiconductor film is etched to form a source region and a drain region,
A method for manufacturing a semiconductor device, comprising forming a source electrode and a drain electrode in contact with the source region and the drain region. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming the second semiconductor film containing a rare gas element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film,
Removing the second semiconductor film;
Forming a conductive third semiconductor film on the first semiconductor film;
Patterning the first semiconductor film and the third semiconductor film to form an island-shaped first semiconductor film and an island-shaped second semiconductor film;
Forming a third conductive layer on the island-shaped second semiconductor film;
The third conductive layer is partially etched to form a source electrode and a drain electrode, and the island-shaped second semiconductor film is etched using the source electrode and the drain electrode as a mask to form the island-shaped first A method for manufacturing a semiconductor device, comprising exposing a part of the semiconductor film and forming a source region and a drain region. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a gate electrode;
Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming the second semiconductor film containing a rare gas element on the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film,
Removing the second semiconductor film;
Forming a conductive third semiconductor film on the first semiconductor film;
Patterning the first semiconductor film and the third semiconductor film to form an island-shaped semiconductor region;
Of the island-shaped semiconductor regions, the third semiconductor film is etched to form a source region and a drain region,
A method for manufacturing a semiconductor device, comprising forming a source electrode and a drain electrode in contact with the source region and the drain region. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a first mask, and a part of the second island-shaped semiconductor region is covered with a second mask, and then a second impurity element is selectively added. And
Removing the first mask and the second mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The third conductive layer is patterned to form a source electrode and a drain electrode in contact with the second semiconductor film in the first island-shaped semiconductor region, and the second island-shaped semiconductor region in the second island-shaped semiconductor region. Forming a source electrode and a drain electrode in contact with the semiconductor film;
The exposed portion of the second semiconductor film in the first island-shaped semiconductor region is etched to form a first source region and a drain region, and the second semiconductor film in the second island-shaped semiconductor region And a second source region and a drain region are formed by etching the exposed portion of the semiconductor device. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a first mask, and a part of the second island-shaped semiconductor region is covered with a second mask, and then a second impurity element is selectively added. And
Removing the first mask and the second mask;
Among the first island-shaped semiconductor regions, the second semiconductor film is etched to form the first source region and the first drain region, and at the same time, among the second island-shaped semiconductor regions, Etching the second semiconductor film to form a second source region and a second drain region;
Forming a first source electrode and a first drain electrode in contact with the first source region and the first drain region, and a second in contact with the second source region and the second drain region; Forming a source electrode and a second drain electrode of the semiconductor device. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Patterning the first semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
A part of the first island-shaped semiconductor region is covered with a first mask, and a part of the second island-like semiconductor region is covered with a second mask, and then the first impurity element is selected. Added
Removing the first mask and the second mask;
Heating the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The first island-shaped semiconductor region is covered with a third mask, and a part of the second island-shaped semiconductor region is covered with a fourth mask, and then a second impurity element is selectively added. And
Removing the third mask and the fourth mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
Patterning the third conductive layer to form a source electrode and a drain electrode in contact with the first island-shaped semiconductor region, and a source electrode and a drain electrode in contact with the second island-shaped semiconductor region; A method for manufacturing a semiconductor device. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film containing a rare gas element on the first semiconductor film;
Heating the first semiconductor film and the second semiconductor film;
Removing the second semiconductor film;
Patterning the first semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
A portion of the first island-shaped semiconductor region is covered with a first mask, and the second island-shaped semiconductor region is covered with a second mask, and then a first impurity element is selectively added. And
Removing the first mask and the second mask;
The first island-shaped semiconductor region is covered with a third mask, and a part of the second island-shaped semiconductor region is covered with a fourth mask, and then a second impurity element is selectively added. And
Removing the third mask and the fourth mask;
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
Patterning the third conductive layer to form a source electrode and a drain electrode in contact with the first island-shaped semiconductor region, and a source electrode and a drain electrode in contact with the second island-shaped semiconductor region; A method for manufacturing a semiconductor device. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
After covering the first island-shaped semiconductor region with a mask, a second impurity element is added to the second island-shaped semiconductor region;
Removing the mask,
Forming a third conductive layer on the first island-shaped semiconductor region and the second island-shaped semiconductor region;
The third conductive layer is patterned to form a source electrode and a drain electrode in contact with the second semiconductor film of the first island-shaped semiconductor region, and the second island-shaped semiconductor region of the second island-shaped semiconductor region. Forming a source electrode and a drain electrode in contact with the semiconductor film;
A source region and a drain region are formed by etching the exposed portion of the second semiconductor film in the first island-shaped semiconductor region and the exposed portion of the second semiconductor film in the first island-shaped semiconductor region. A method for manufacturing a semiconductor device. Forming a first conductive layer mainly composed of aluminum on a substrate;
Forming a second conductive layer made of a material different from that of the first conductive layer on the first conductive layer;
Patterning the first conductive layer and the second conductive layer to form a first gate electrode and a second gate electrode;
Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Heating after introducing a catalytic element into the first semiconductor film;
Forming a second semiconductor film having a first impurity element over the first semiconductor film, and then heating the first semiconductor film and the second semiconductor film;
Patterning the first semiconductor film and the second semiconductor film to form a first island-shaped semiconductor region and a second island-shaped semiconductor region;
After covering the first island-shaped semiconductor region with a mask, a second impurity element is added to the second island-shaped semiconductor region;
Removing the mask,
Among the first island-shaped semiconductor regions, the second semiconductor film is etched to form the first source region and the first drain region, and at the same time, among the second island-shaped semiconductor regions, Etching the second semiconductor film to form a second source region and a second drain region;
Forming a first source electrode and a first drain electrode in contact with the first source region and the first drain region, and a second in contact with the second source region and the second drain region; Forming a source electrode and a second drain electrode of the semiconductor device.   9. The method for manufacturing a semiconductor device according to claim 3, wherein the rare gas element is one or more of He, Ne, Ar, Kr, and Xe.   11. The method for manufacturing a semiconductor device according to claim 1, wherein the first impurity element is one or more of phosphorus, nitrogen, arsenic, antimony, and bismuth. .   The method for manufacturing a semiconductor device according to claim 5, wherein the second impurity element is boron.   The catalyst element according to any one of claims 1 to 13, wherein the catalyst element is any one or more of tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, and platinum. A method for manufacturing a semiconductor device.   15. The method according to claim 1, wherein the first conductive layer contains carbon and one or more of chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. A method for manufacturing a semiconductor device.   16. The method for manufacturing a semiconductor device according to claim 15, wherein the carbon is contained in an amount of 0.1 to 10 atomic%.   17. The semiconductor device according to claim 1, wherein the second conductive layer is made of one or more of chromium, tantalum, tungsten, molybdenum, titanium, nickel, or a nitride thereof. Manufacturing method.   An EL television having the semiconductor device manufactured according to any one of claims 1 to 17. A liquid crystal television having a semiconductor device manufactured according to any one of claims 1 to 17.

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