JP2006128666A - Method for manufacturing display - Google Patents

Method for manufacturing display Download PDF

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JP2006128666A
JP2006128666A JP2005285804A JP2005285804A JP2006128666A JP 2006128666 A JP2006128666 A JP 2006128666A JP 2005285804 A JP2005285804 A JP 2005285804A JP 2005285804 A JP2005285804 A JP 2005285804A JP 2006128666 A JP2006128666 A JP 2006128666A
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electrode
gate
formed
insulating film
forming
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JP2006128666A5 (en
JP4801407B2 (en
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Shinji Maekawa
Shunpei Yamazaki
慎志 前川
舜平 山崎
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Semiconductor Energy Lab Co Ltd
株式会社半導体エネルギー研究所
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Abstract

An object of the present invention is to provide a method for manufacturing a display device having an inverted staggered TFT that is unlikely to cause a threshold shift and can operate at high speed. In addition, a method for manufacturing a display device with high switching characteristics and capable of display with high contrast is provided.
The present invention provides a layer having a catalytic element that promotes crystallization of an amorphous semiconductor film, an amorphous semiconductor film, and a donor-type element or a rare element after a gate electrode is formed using a material having high heat resistance. A layer containing a gas element is formed and heated to crystallize the amorphous semiconductor film, and after removing the catalytic element from the crystalline semiconductor film, a semiconductor region is formed using a part of the crystalline semiconductor film. Then, a source electrode and a drain electrode that are in electrical contact with the semiconductor region are formed, a gate wiring connected to the gate electrode is formed, and an inverted staggered TFT is formed.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a display device having an inverted staggered thin film transistor formed of a crystalline semiconductor film.

  In recent years, a flat panel display (FPD) typified by a liquid crystal display (LCD) or an EL display has attracted attention as a display device that replaces a conventional CRT. In particular, the development of large-screen liquid crystal televisions equipped with large liquid crystal panels driven by an active matrix has become an important issue for LCD panel manufacturers to focus on. In recent years, a large screen EL television has been developed following the liquid crystal television.

In a display device having a conventional light emitting element, a thin film transistor (hereinafter referred to as TFT) using amorphous silicon is used as a semiconductor element for driving each pixel (Patent Document 1).
JP-A-5-35207

  However, when a TFT using an amorphous semiconductor film is DC-driven, the threshold value tends to shift, and the TFT characteristics tend to vary accordingly. For this reason, luminance unevenness occurs in a display device in which a TFT using an amorphous semiconductor film is used for pixel switching. Such a phenomenon becomes more conspicuous as the screen TV has a diagonal size of 30 inches or more (typically 40 inches or more), and the deterioration of image quality is a serious problem.

  The present invention has been made in view of such a situation, and provides a method for manufacturing a TFT which is less likely to cause a threshold shift with a small number of steps. In addition, a method for manufacturing a display device including an inverted staggered TFT capable of high-speed operation is provided.

  In the present invention, after forming a gate electrode with a material having high heat resistance, an amorphous semiconductor film is formed, a catalytic element layer in contact with the amorphous semiconductor film is formed, and a donor element is formed on the catalytic element layer Alternatively, a layer containing a rare gas element or a layer containing a donor element and a rare gas element is formed and heated to form a crystalline semiconductor film, and after removing the catalytic element from the crystalline semiconductor film, the crystalline semiconductor film A semiconductor region is formed using a part of the source region, a source electrode and a drain electrode that are in electrical contact with the semiconductor region, a scanning line connected to the gate electrode is formed, an inverted staggered TFT is formed, The gist is to form a display device by forming a first electrode connected to a source electrode or a drain electrode and forming a layer containing a light-emitting substance and a second electrode over the first electrode.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor film on the first semiconductor film, forming a second semiconductor film having an impurity element on the first semiconductor film, and then heating the first conductive layer in contact with the heated second semiconductor film And forming a source region and a drain region by etching a part of the first conductive layer, forming a source electrode and a drain electrode, etching a part of the second semiconductor film, Forming an insulating film on the gate insulating film, the source electrode, and the drain electrode; etching a part of the insulating film and the gate insulating film to expose a part of the gate electrode; Form the gate wiring to be connected A portion of the insulating film is etched to expose a portion of the source or drain electrode, and then a first electrode connected to the source or drain electrode is formed, and the first electrode is formed on the first electrode. A method for manufacturing a display device is characterized in that a layer containing a light-emitting substance and a second electrode are formed.

  According to one embodiment of the present invention, a gate electrode is formed over an insulating surface, a gate insulating film is formed over the gate electrode, a first semiconductor film is formed over the gate insulating film, and the first semiconductor film is formed Forming a layer having a catalytic element on the first conductive layer, forming a second semiconductor film having an impurity element on the layer having the catalytic element, and then heating the first conductive layer in contact with the heated second semiconductor film And forming a source region and a drain region by etching a part of the first conductive layer, forming a source electrode and a drain electrode, etching a part of the second semiconductor film, Forming an insulating film on the gate insulating film, the source electrode, and the drain electrode; etching a part of the insulating film and the gate insulating film to expose a part of the gate electrode; Form the gate wiring to be connected A portion of the insulating film is etched to expose a portion of the source or drain electrode, and then a first electrode connected to the source or drain electrode is formed, and the first electrode is formed on the first electrode. A method for manufacturing a display device is characterized in that a layer containing a light-emitting substance and a second electrode are formed.

According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed A first semiconductor film is formed, and a protective layer is formed on a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap, and the first semiconductor film and the protective layer are formed. A second semiconductor film having an impurity element is formed thereon and then heated to form a first conductive layer in contact with the heated second semiconductor film, and a part of the first conductive layer is etched. Then, a source electrode and a drain electrode are formed, a part of the second semiconductor film is etched to form a source region and a drain region, and an insulating film is formed over the gate insulating film and the source electrode and the drain electrode. Forming the insulating film and the front After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode is formed, and a part of the insulating film is etched to etch the source electrode or the drain electrode. A first electrode connected to the source electrode or the drain electrode is formed, and a layer containing a light-emitting substance and a second electrode are formed on the first electrode. This is a method for manufacturing a display device.

  According to one embodiment of the present invention, a gate electrode is formed over an insulating surface, a gate insulating film is formed over the gate electrode, a first semiconductor film is formed over the gate insulating film, and the first semiconductor film is formed Forming a layer having a catalytic element on the gate electrode, forming a protective layer in a region where the first semiconductor film and the layer having the catalytic element overlap, and forming a protective layer on the protective layer and the layer having the catalytic element After forming the second semiconductor film having an impurity element, heating, forming a first conductive layer in contact with the heated second semiconductor film, etching a part of the first conductive layer, A source electrode and a drain electrode are formed, a part of the second semiconductor film is etched to form a source region and a drain region, and an insulating film is formed over the gate insulating film and the source electrode and the drain electrode. , The insulating film and the gate After etching a part of the insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode is formed, and a part of the insulating film is etched to form the source electrode or the drain electrode. A first electrode connected to the source electrode or the drain electrode is formed, and a layer containing a light-emitting substance and a second electrode are formed on the first electrode. This is a method for manufacturing a display device.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor film is formed, a second semiconductor film having an impurity element is formed over the first semiconductor film, and then heated, and the heated second semiconductor film is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region Forming an electrode, forming an insulating film on the gate insulating film, the gate wiring, the source electrode and the drain electrode, etching a part of the insulating film to expose a part of the gate wiring And forming a conductive layer connected to the gate wiring, etching a part of the insulating film to expose a part of the source electrode or drain electrode, and then forming a first electrode in contact with the source electrode or drain electrode. A method for manufacturing a display device is characterized in that a layer containing a light-emitting substance and a second electrode are formed over the first electrode.

  According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor film is formed over the gate insulating film, and the first semiconductor film is formed over the first semiconductor film. A layer having a catalytic element is formed, a second semiconductor film having an impurity element is formed on the layer having the catalytic element, and then heated, and the heated second semiconductor film is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region Forming an electrode, forming an insulating film on the gate insulating film, the gate wiring, the source electrode and the drain electrode, etching a part of the insulating film to expose a part of the gate wiring And forming a conductive layer connected to the gate wiring, etching a part of the insulating film to expose a part of the source electrode or drain electrode, and then forming a first electrode in contact with the source electrode or drain electrode. A method for manufacturing a display device is characterized in that a layer containing a light-emitting substance and a second electrode are formed over the first electrode.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor film is formed, a protective layer is formed over a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap, and the first semiconductor film and the protective layer are formed. A second semiconductor film having an impurity element is formed and then heated; the heated second semiconductor film is etched to form a source region and a drain region; and a part of the gate insulating film is etched Forming a gate wiring connected to the gate electrode, a source electrode and a drain electrode in contact with the source region and the drain region, and exposing the gate insulating film, the gate wiring, Forming an insulating film on the source electrode and the drain electrode, etching a part of the insulating film to expose a part of the gate wiring, and then forming a conductive layer connected to the gate wiring; A portion of the film is etched to expose a portion of the source or drain electrode, and then a first electrode in contact with the source or drain electrode is formed, and a layer containing a luminescent material is formed on the first electrode And a second electrode. A method for manufacturing a display device.

  According to one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor film is formed over the gate insulating film, and the first semiconductor film is formed over the first semiconductor film. A layer having a catalytic element is formed, a protective layer is formed in a region where the gate electrode, the first semiconductor film, and the layer having the catalytic element overlap, and impurities are formed on the protective layer and the layer having the catalytic element. After the second semiconductor film having an element is formed and heated, the heated second semiconductor film is etched to form a source region and a drain region, and a part of the gate insulating film is etched, After exposing a part of the gate electrode, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed, and the gate insulating film, the gate wiring, and the source electrode are formed. Forming an insulating film on the electrode and the drain electrode; etching a part of the insulating film to expose a part of the gate wiring; and forming a conductive layer connected to the gate wiring; Etching a part to expose a part of the source or drain electrode, forming a first electrode in contact with the source or drain electrode, and a layer containing a luminescent material on the first electrode; and A display device manufacturing method is characterized in that a second electrode is formed.

  Note that after forming the first electrode in contact with the source or drain electrode, a gate wiring connected to the gate electrode may be formed. In addition, after forming a gate wiring connected to the gate electrode, a first electrode in contact with the source electrode or the drain electrode may be formed.

  The gate wiring may be connected to three or more gate electrodes. The gate wiring may be connected to the two gate electrodes.

  Note that an insulating film which covers a part of the source electrode or the drain electrode may be formed instead of the insulating film formed over the gate insulating film, the gate wiring, the source electrode, and the drain electrode.

  In addition, the gate electrode is formed by forming a conductive film on an insulating surface, discharging or applying a photosensitive resin onto the conductive film, irradiating a part of the photosensitive resin with ultraviolet light or light having a wavelength close to the gate electrode, and developing. After the mask is formed, the conductive film is etched using the mask.

  The gate electrode is formed of a heat-resistant conductive layer. Typically, tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, platinum or phosphorus-containing crystalline silicon film, indium tin oxide, zinc oxide, indium zinc oxide, gallium added Zinc oxide or indium tin oxide containing silicon oxide.

  The catalytic element is one or more selected from tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, copper, titanium, nickel, and platinum.

  The first electrode is a pixel electrode.

  In the present invention, the display device refers to a device using a light emitting element, that is, an image display device. In addition, a module in which a connector such as a flexible printed circuit (FPC) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to a light-emitting display panel, a printed wiring board at the end of a TAB tape or TCP The display device also includes a module in which an IC (integrated circuit) or a CPU is directly mounted on a light emitting element by a COG (Chip On Glass) method.

  Another embodiment of the present invention is an EL television including the above display device.

  According to the present invention, an inverted staggered TFT formed of a crystalline semiconductor film can be formed with a small number of photomasks. The inversely staggered TFT of the present invention can simultaneously perform a crystallization process of an amorphous semiconductor film and a gettering process of a metal catalyst for promoting crystallization of the amorphous semiconductor film. The number of steps can be reduced, and throughput can be improved. In addition, since the number of heat treatments can be reduced, energy saving can be achieved.

  In addition, the inverted staggered TFT of the present invention uses a material having high heat resistance for the gate electrode, and after performing heat treatment in the crystallization process and the gettering process, the signal line is formed using a low resistance material. Wiring such as scanning lines is formed. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the display device including the light-emitting element of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  A TFT formed of a crystalline semiconductor film has a mobility of about 10 to 50 times that of an inverted staggered TFT formed of an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a display device including a light-emitting element that requires high-speed operation can be manufactured.

  In addition, a scan line driver circuit can be formed at the same time as the TFT in the pixel region in the peripheral portion of the display device having a light emitting element. Therefore, a miniaturized display device can be manufactured.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, display unevenness can be reduced as compared with a display device having a light-emitting element using a TFT formed of an amorphous semiconductor film as a switching element.

  Furthermore, the gettering process performed together with the crystallization process also getters the metal element mixed in the semiconductor film in the film formation stage, so that the off-current can be reduced, typically 6 digits. It is possible to form a TFT having the above ON / OFF ratio. By providing the switching element of a display device having such a TFT, the contrast can be improved.

  Further, the throughput and yield of a television set (referred to as an EL (electroluminescence) television set) including a display device having a light-emitting element formed by the above manufacturing process can be improved. It can be manufactured at a low cost.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment, the steps of manufacturing an active matrix substrate having an element for driving a light emitting element of a bottom gate structure channel etch type TFT having a crystalline semiconductor film are shown in FIGS. 1 to 2, 20, and 39. It explains using. In this embodiment, a light emitting element having a switching TFT and a driving TFT is shown as a representative example as an element for driving the light emitting element. FIG. 7 is a top view of a light emitting element having an element for driving the light emitting element, and FIGS. 1 and 2 are cross sections showing a connection portion between a gate electrode of a switching TFT and a scanning line, a driving TFT, and the light emitting element. FIG.

  As shown in FIG. 1A, a first conductive layer 102 is formed on a substrate 101, and a normal lithography process is performed on the first conductive layer 102 to form first masks 103 and 104. .

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a silicon wafer, a metal plate, or the like can be used. Further, as the substrate 101, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm can be used.

  The first conductive layer 102 is formed over the entire surface of the substrate by a sputtering method having a thickness of 100 to 1000 nm, a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), an evaporation method, or the like.

  The first conductive layer 102 is preferably formed using a high melting point material. By using the high melting point material, a heating process such as a subsequent crystallization process, gettering process, activation process or the like can be performed. High melting point materials include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni), titanium (Ti), platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, from the substrate surface side, a tantalum nitride film and a tungsten film formed thereon, a tantalum nitride film, molybdenum formed thereon, a titanium nitride film, a tungsten film formed thereon, and a titanium nitride film And it is good also as laminated structure, such as a molybdenum film | membrane formed on it. In addition, a silicon film containing phosphorus (including an amorphous semiconductor film and a crystalline semiconductor film), indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide added with gallium, or indium tin oxide containing silicon oxide is used. It can also be used.

  As a material of the first masks 103 and 104 formed by the lithography process, a negative photosensitive material or a positive photosensitive material that is sensitive to ultraviolet light to infrared light is used. As a representative example of the photosensitive material, a resin material exhibiting photosensitivity such as an epoxy resin, a cryl resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, organic materials exhibiting photosensitivity such as benzocyclobutene, parylene, flare, and polyimide can be used. Moreover, as a typical positive type photosensitive resin, there can be mentioned a novolak resin and a photosensitive resin having a naphthoquinonediazide compound as a photosensitive agent, and as a negative type photosensitive resin, a base resin, diphenylsilanediol, an acid generator and the like can be mentioned. The photosensitive resin which has. Here, a positive photosensitive material is used.

  Next, as illustrated in FIG. 1B, the first conductive layer 102 is etched using the first mask to form second conductive layers 111 and 112. The second conductive layer 111 functions as a gate electrode of the driving TFT, and the second conductive layer 112 functions as a gate electrode of the switching TFT.

  Next, after removing the first mask, a first insulating film 113 with a thickness of 10 to 200 nm, preferably 50 to 100 nm, is formed, and a thickness of 50 to 250 nm, preferably with respect to the first insulating film 113 is formed. A second insulating film 114 with a thickness of 100 to 200 nm is formed, and a third insulating film 115 with a thickness of 0.1 to 10 nm, preferably 1 to 3 nm, is formed over the second insulating film 114.

  The first insulating film 113 functions as a gate insulating film and plays a role of preventing the diffusion of movable ions from the glass substrate. For the first insulating film 113, silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate. The second insulating film 114 functions as a gate insulating film. For the second insulating film 114, silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like can be used as appropriate. As the third insulating film 115, silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate. In this embodiment mode, a catalyst element that promotes crystallization is used for the semiconductor layer, and thereafter, gettering treatment is performed to remove it. The interface state between the silicon oxide and the silicon film is good, but the metal element in the silicon film reacts with oxygen in the silicon oxide at the interface and easily becomes a metal oxide (in this embodiment, nickel oxide (NiOx)). The catalyst element may be difficult to getter. Further, the silicon nitride film may adversely affect the interface state with the semiconductor layer due to the stress of the silicon nitride film and the influence of traps. Therefore, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.1 to 10 nm is formed as the uppermost layer of the insulating layer in contact with the semiconductor layer. In this embodiment mode, the gate insulating film has a three-layer structure. With such a structure, the gettering efficiency of the catalytic element in the semiconductor layer is increased, and the adverse effect of the silicon nitride film on the semiconductor layer can be reduced. The insulating film to be laminated is preferably formed continuously while switching the reaction gas at the same temperature without breaking the vacuum in the same chamber. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

  Note that silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), silicon nitride (SiNx), and silicon nitride oxide (SiNxOy) (x> y) contain hydrogen. The first, second, and third insulating films 113, 114, and 115 are formed by a known method such as a CVD method or a PVD method.

A layer 119 including a catalytic element is formed over the third insulating film 115. As a method for forming the layer 119 having a catalytic element, a method of forming a thin film of a catalytic element or a silicide of the catalytic element on the surface of the third insulating film 115 by a PVD method, a CVD method, a vapor deposition method, or the like, There is a method of applying a solution containing a catalytic element to the surface of the film 115. Examples of catalyst elements include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of copper (Cu), titanium (Ti), nickel (Ni), platinum (Pt) and the like. Further, the catalytic element may be implanted shallowly from the surface of the insulating film by ion doping such as NiCl 2 or ion implantation. Further, the surface of the semiconductor film may be subjected to plasma treatment using an electrode formed of the above catalytic element. Here, a nickel film having a thickness of 1 to 100 nm is formed by an evaporation method. Here, the catalytic element is an element that promotes or promotes crystallization of the semiconductor film.

  Next, as illustrated in FIG. 1D, a first semiconductor film 131 with a thickness of 50 to 200 nm, preferably 100 to 150 nm, is formed over the layer 119 containing a catalytic element.

Next, a group 3 element (Group 13 element, hereinafter referred to as an acceptor type element) or a Group 5 element (Group 15 element, hereinafter referred to as a donor type element) has a low concentration in a region to be a channel region of the TFT. The channel doping process to be added to is performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which diborane (B 2 H 6 ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used.

Next, a second semiconductor film and a third semiconductor film are formed without breaking the vacuum. The thickness of the second semiconductor film 132 is 30 to 200 nm, preferably 50 to 100 nm. The thickness of the third semiconductor film 133 is 30 to 200 nm, preferably 50 to 100 nm. The second semiconductor film has a stacked structure of a low concentration region (hereinafter referred to as an n region), and the third semiconductor film has a stacked structure of a high concentration region (hereinafter referred to as an n + region).

  As the first semiconductor film 131, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed, and a crystal grain having a thickness of 0.5 nm to 20 nm can be observed in the amorphous semiconductor. A film having any state selected from a crystalline semiconductor and a crystalline semiconductor is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used.

Note that in order to obtain a semiconductor film having a high-quality crystal structure by subsequent crystallization, an impurity concentration of oxygen, nitrogen, or the like contained in the first semiconductor film 131 is set to 5 × 10 18 / cm 3 (hereinafter referred to as “the semiconductor film”). All concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

The second semiconductor film 132 and the third semiconductor film 133 are semiconductors containing a donor element. The film is formed by a plasma CVD method in which a gas containing a donor element such as phosphorus or arsenic is added to a silicide gas. By forming the second semiconductor film 132 and the third semiconductor film 133 by such a method, the first semiconductor film 131, the second semiconductor film 132, and the third semiconductor film 133 are less contaminated. A clean interface is formed. Further, as the second semiconductor film 132 and the third semiconductor film 133 containing a donor-type element, a semiconductor film similar to the first semiconductor film 131 is formed, and then the donor-type element is ion-doped or ion-implanted. It can be added by the method. In this case, the second semiconductor film 132 preferably has a phosphorus concentration of 1 × 10 16 to 1 × 10 18 / cm 3 . The third semiconductor film 133 preferably has a phosphorus concentration of 1 × 10 19 to 1 × 10 21 / cm 3 .

  FIG. 20 shows impurity profiles of the second semiconductor film 132 and the third semiconductor film 133 containing donor-type elements at this time. FIG. 20A shows a profile of a donor-type element when the second semiconductor film 132 and the third semiconductor film 133 containing a donor-type element are formed over the first semiconductor film 131 by a plasma CVD method. 150a is shown. Note that in the third semiconductor film 133, a donor-type element having a constant concentration (first concentration) is distributed in the depth direction of the film. In the second semiconductor film 132, a donor-type element having a constant concentration (second concentration) is distributed in the depth direction of the film. At this time, the first concentration is higher than the second concentration.

On the other hand, FIG. 20B illustrates a semiconductor film having a state selected from an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, and a crystalline semiconductor over the first semiconductor film 131. A donor-type element profile 150b is shown when the second semiconductor film 132a is formed by forming and adding a donor-type element to the semiconductor film by ion doping or ion implantation. At this time, the third semiconductor film 133 is not necessarily formed. As shown in FIG. 20B, the donor-type element concentration is relatively high in the vicinity of the surface of the second semiconductor film 132a. This region is denoted as n + region 144a. On the other hand, as it approaches the first semiconductor film 131, the donor-type element concentration decreases. This region is referred to as an n-region 144b. The concentration of the donor-type element in the n + region 144a is 10 to 100 times that of the donor-type element in the n region 144b.

The third semiconductor film 133 and the n + region 144a later function as a source region and a drain region, and the second semiconductor film 132 and the n region 144b function as an LDD region. Note that there is no interface between the n + region and the n region, and the interface varies depending on the relative donor element concentration. As described above, the second semiconductor film containing the donor-type element formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the n + region and n region films The thickness can be appropriately controlled.

  Note that the second semiconductor film 132, the third semiconductor film 133, and the second semiconductor film 132a containing a donor-type element are doped with a rare gas element, typically argon, so that distortion of the crystal lattice is increased. It is possible to getter the catalyst element more in the gettering step performed later.

  The layer 119 including the catalytic element, the first semiconductor film 131, the second semiconductor film 132, and the third semiconductor film 133 are heated to crystallize the first semiconductor film 131, whereby the first crystalline semiconductor film 141 is obtained. In addition, as indicated by an arrow in FIG. 1E, the catalytic element contained in the first crystalline semiconductor film 141 is moved to the second semiconductor film 132 and the third semiconductor film 133, and the catalytic element is moved. Gettering.

  The heat treatment is a heat treatment for dehydrogenation (400 to 550 ° C., 0.5 to 2 hours) followed by a heat treatment for crystallization (550 to 650 ° C. for 1 to 24 hours). Further, crystallization may be performed by RTA (Rapid Thermal Anneal) or GRTA (Gas Rapid Thermal Anneal). In crystallization, silicide is formed in the portion of the semiconductor film in contact with the catalytic element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. At the same time, gettering is performed, and the catalyst element is moved to the second semiconductor film 132 and the third semiconductor film 133 where the solid solubility of the catalyst element is high to getter the catalyst element.

By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 18 / cm 3 or less, preferably 1 × 10 17 / cm 3. It can be as follows. Such a film is referred to as a first crystalline semiconductor film 141. In addition, since the second semiconductor film 132 and the third semiconductor film 133 to which the catalytic element after gettering has moved are crystallized in the same manner, they are collectively referred to as a second crystalline semiconductor film 142. In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Next, as illustrated in FIG. 1F, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second crystalline semiconductor film 142 are formed using the second mask. One crystalline semiconductor film 141 is etched to form a first semiconductor region 151 and a second semiconductor region 152 as shown in FIG.

  In the mask formation process of the following embodiments and examples, before applying a photosensitive material on a film or region formed of a semiconductor material, a film thickness of about several nanometers is formed on the surface of the semiconductor film or region. It is preferable to form an insulating film. This step can avoid direct contact between the semiconductor material and the photosensitive material, and can prevent impurities from entering the semiconductor film. Note that examples of a method for forming the insulating film include a method of applying an oxidizing solution such as ozone water, a method of irradiating oxygen plasma, ozone plasma, and the like.

The first crystalline semiconductor film 141 and the second crystalline semiconductor film 142 are made of chlorine gas such as Cl 2 , BCl 3 , SiCl 4, or CCl 4 , CF 4 , SF 6 , NF 3 , and CHF 3. it can be etched using a fluorine-based gas or O 2, the like typified.

  Next, after removing the second mask, a third conductive layer 153 having a thickness of 200 to 1000 nm, preferably 500 to 1000 nm is formed. Next, a photosensitive material such as a resist is applied over the third conductive layer 153, and after exposure and development, a third mask 161 as shown in FIG. 2B is formed.

  The third conductive layer 153 is formed over the entire surface of the substrate by sputtering, PVD, CVD, vapor deposition, or the like. As a material, a plurality of metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, and Ti can be used in combination. In addition, a third conductive layer can be formed by stacking conductive layers formed of these materials. The third conductive layer functions as a wiring. In order to reduce the wiring resistance, it is preferable to use a low resistance material. Here, Al having a thickness of 500 nm and Mo having a thickness of 50 nm are stacked on Mo having a thickness of 100 nm. Al tends to cause spiking at a temperature of 250 ° C. or higher. Therefore, in order to prevent Al diffusion, the upper and lower sides of the Al film are sandwiched between refractory metal Mo. Mo and Al can be etched with a mixture of phosphoric acid: nitric acid: acetic acid: water = 72: 2: 10: 16. In addition, dry etching may be performed by selecting various gases.

  Here, as a barrier film in the case of using copper as a wiring, an insulating or conductive substance containing nitrogen such as silicon nitride, silicon oxynitride, aluminum nitride, titanium nitride, or tantalum nitride may be used.

  Next, the third conductive layer is etched into a desired shape using the third mask 161, and the fourth conductive layers 162 and 163, FIG. 7B and FIG. Fourth conductive layers 167 and 169 shown in FIG. The fourth conductive layer 162 functions as a power supply line and a capacitor wiring, and the fourth conductive layer 163 functions as a source electrode or a drain electrode of the driving TFT. In addition, the fourth conductive layer 167 illustrated in FIG. 7C functions as a signal line, and the fourth conductive layer 169 functions as a switching source region or a drain region. At this time, the third conductive layer is divided to form each wiring and each electrode, and etching is performed so that the width of the source wiring or the drain wiring is narrowed. It is possible to increase the rate.

  Next, the exposed portion of the first semiconductor region 152 is etched using the third mask 161 to form third semiconductor regions 164 and 165 that function as a source region and a drain region. At this time, part of the second semiconductor region 151 may be over-etched. The over-etched second semiconductor region at this time is referred to as a fourth semiconductor region 166. The fourth semiconductor region 166 functions as a channel formation region of the driving TFT. On the other hand, a fourth semiconductor region 168 that functions as a channel formation region of the switching TFT is also formed by the same process.

  Next, after removing the third mask 161, as shown in FIG. 2C, a film thickness 50 that functions as a passivation film over the surfaces of the fourth conductive layers 162 and 163 and the fourth semiconductor region 166 is obtained. A fourth insulating film 171 with a thickness of ˜300 nm is preferably formed. The passivation film is formed using a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used. Note that the passivation film may be a single layer or a laminated structure. Here, silicon oxide or silicon oxynitride is preferably formed from the interface characteristics of the fourth semiconductor region 166, and a silicon nitride film or a silicon nitride oxide film is preferably formed thereover.

  Thereafter, the fourth semiconductor region 166 is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case where heating is performed in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed as the third insulating film 115.

  Through the above steps, a bottom gate channel etch TFT having a crystalline semiconductor film can be formed.

  Next, a fifth insulating film 172 having a thickness of 500 to 1500 nm is formed over the fourth insulating film 171. As the fifth insulating film 172, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide (polyimide) ), Aromatic polyamide, polybenzimidazole (polybenzimidazole), or a siloxane polymer-based material typified by silica glass as a starting material, Si—O among compounds composed of silicon, oxygen, and hydrogen -Inorganic siloxane polymer containing Si bond, alkyl siloxane polymer, alkyl silsesquioxane polymer, hydrogenated silsesquioxane polymer, hydrogen on silicon represented by hydrogenated alkyl silsesquioxane polymer is methyl or phenyl. It may be an organic siloxane polymer based insulating material which is substituted by an organic group such as. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the fifth insulating film 172 can be planarized by the application method. Here, the fifth insulating film 172 is formed by applying and baking an acrylic resin by a coating method.

  Note that when the fourth insulating film 171 has a thickness such that parasitic capacitance is not generated between the sixth conductive layer 175 and the fourth conductive layers 162 and 163 to be formed later, The film 172 is not necessarily required.

  Next, after a fourth mask (not shown) is formed over the fifth insulating film 172, the fifth insulating film 172 and a part of the fourth insulating film 171 are etched to form the switching TFT. The second conductive layers 112 (FIG. 2C) and 122a (FIG. 7A) functioning as gate electrodes are exposed. Next, after removing the fourth mask, a fifth conductive layer 173 having a thickness of 500 to 1500 nm, preferably 500 to 1000 nm is formed. The fifth conductive layer 173 functions as a scan line.

  For the fourth mask, a method and a material similar to those of the second mask 143 can be used as appropriate. As a material and a formation method of the fifth conductive layer 173, a material and a formation method similar to those of the third conductive layer 153 may be selected as appropriate. In order to suppress wiring resistance, it is preferable to use a low resistance material.

  Through the above steps, the second conductive layer 111 or the second conductive layer 121 as illustrated in FIGS. 2C, 7A, and 7C and the first conductive layer that functions as a gate insulating film. The insulating film 113, the second insulating film 114, the third insulating film 115, or the first insulating film 123, the fourth semiconductor region 166 functioning as a channel formation region, and the third functioning as a source region or a drain region A driving TFT 191 including the semiconductor regions 164 and 165, the fourth conductive layer 162 functioning as a power supply line, and the fourth conductive layer 163 functioning as a source electrode or a drain electrode can be formed.

  Further, as shown in FIGS. 7B and 7C, the second conductive layer 122a, the first insulating film 123 functioning as a gate insulating film, and the fourth semiconductor region 168 functioning as a channel formation region. , A switching TFT 192 including third semiconductor regions 164 and 165 functioning as a source region or a drain region, a fourth conductive layer 167 functioning as a signal line, and a fourth conductive layer 169 functioning as a source electrode or a drain electrode Form.

  Note that the second conductive layer 169 functioning as a source electrode or a drain electrode of the switching TFT 192 is connected to the second conductive layer 121 functioning as a gate electrode of the driving TFT 191. In addition, 122a functioning as a gate electrode of the switching TFT 192 is connected to a fifth conductive layer 173 functioning as a scanning line.

  Next, a sixth insulating film 174 is formed over the fifth conductive layer 173 and the fifth insulating film 172. As the sixth insulating film 174, a material similar to that of the fifth insulating film 172 can be used as appropriate.

  Next, after a fifth mask (not shown) is formed over the sixth insulating film 174, the sixth insulating film 174, the fifth insulating film 172, and a part of the fourth insulating film 171 are etched. Then, a part of the fourth conductive layer 163 is exposed. Next, after removing the fifth mask, a sixth conductive layer 175 having a thickness of 100 to 200 nm which functions as a pixel electrode is formed. As the fifth mask, a method and a material similar to those of the second mask 143 can be used as appropriate.

  As a method for forming the sixth conductive layer 175, a sputtering method, an evaporation method, a CVD method, a coating method, or the like is appropriately used.

  Note that although a conductive layer functioning as a scan line is formed as the fifth conductive layer 173 and a conductive layer functioning as the first pixel electrode is formed as the sixth conductive layer 175 here, the invention is not limited to this. . After the conductive layer functioning as the pixel electrode is formed, the conductive layer functioning as the scanning line may be formed.

  Through the above steps, an active matrix substrate can be formed.

  Next, as illustrated in FIG. 2D, a seventh insulating film 181 is formed over the sixth conductive layer 175 and the sixth insulating film 174. The seventh insulating film 181 functions as a partition layer surrounding the end portion of the sixth conductive layer 175. The seventh insulating film 181 is made of an organic material, but may be either photosensitive or non-photosensitive. However, when a photosensitive material is used, the side wall has a shape in which the radius of curvature continuously changes, and a layer containing a light-emitting substance to be formed later can be formed without being cut off. In particular, when a negative photosensitive material is used, a curved surface having a first radius of curvature at the upper end portion of the seventh insulating film 181 and a curved surface having a second radius of curvature at the lower end portion of the seventh insulating film 181. Is provided. The first and second curvature radii are preferably 0.2 to 3 μm, and the angle of the seventh insulating film 181 is preferably 35 degrees or more. In addition, when a positive photosensitive material is used, a curved surface having a radius of curvature is provided only at the upper end portion of the seventh insulating film 181. The cross-sectional structure shown in the figure shows a case where a negative photosensitive material is used.

  Next, a layer 182 containing a light-emitting substance and a seventh conductive layer 183 are formed over the sixth conductive layer 175 and the seventh insulating film 181. The seventh conductive layer 183 functions as a second pixel electrode. The materials of the sixth conductive layer 175 functioning as the first pixel electrode and the seventh conductive layer 183 functioning as the second pixel electrode need to be selected in consideration of the work function. However, each of the first pixel electrode and the second pixel electrode can be an anode or a cathode depending on the pixel configuration. When the polarity of the driving TFT is a p-channel type, the first pixel electrode may be an anode and the second pixel electrode may be a cathode. In the case where the polarity of the driving TFT is an n-channel type, it is preferable that the first pixel electrode be a cathode and the second pixel electrode be an anode.

As an anode material, it is preferable to use a conductive material having a large work function. If the anode side is the light extraction direction, a transparent conductive material (indium tin oxide (ITO), indium tin oxide containing silicon oxide, zinc oxide (ZnO), tin oxide (SnO 2 )), indium oxide Zinc (IZO), zinc oxide added with gallium (GZO), or the like may be used. In addition, if the anode side is made light-shielding, a laminate of titanium nitride and a film mainly composed of aluminum in addition to a single layer film such as TiN, ZrN, Ti, W, Ni, Pt, Cr, Al, A three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Or the method of laminating | stacking the transparent conductive material mentioned above on the film | membrane which has said light-shielding property may be sufficient.

  Moreover, it is preferable to use a conductive material having a small work function as the material of the cathode. Specifically, alkaline metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and these are used. In addition to alloys including Mg (Ag, Al: Li, etc.), rare earth metals such as Yb and Er can also be used. Further, a metal material such as Au (gold), Cu (copper), W (tungsten), Al (aluminum), Ti (titanium), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal material. It is also possible to use a metal material containing nitrogen, or titanium nitride (TiN), tantalum nitride (TaN), or aluminum containing 1 to 20 at% nickel which is a nitride of the metal.

When the cathode side is the light extraction direction, an ultrathin film containing an alkali metal such as Li or Cs and an alkaline earth metal such as Mg, Ca, or Sr, a transparent conductive film (transparent conductive material (indium tin Oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO 2 )), indium zinc oxide (IZO), zinc oxide with gallium added (GZO), etc.) A stacked structure may be used. Alternatively, an electron injection layer in which an alkali metal or alkaline earth metal and an electron transport material are co-evaporated may be formed, and a transparent conductive film may be stacked thereon.

  Note that ITO containing silicon oxide, which can be used as the sixth conductive layer 175 or the seventh conductive layer 183, is a material that is difficult to crystallize by energization or heat treatment and has high surface flatness.

  Here, since an n-channel TFT is used as the driving TFT, the sixth conductive layer 175 is formed with a stacked structure of a lower layer made of tantalum nitride and an upper layer made of ITO containing silicon oxide. The seventh conductive layer 183 is formed using ITO containing silicon oxide.

  Here, since an n-channel TFT is used as the driving TFT, the layer 182 containing a light-emitting substance has an EIL (electron injection layer) ETL (electron transport layer) sequentially from the sixth conductive layer 175 (cathode) side. ), EML (light emitting layer), HTL (hole transport layer), and HIL (hole injection layer). Note that the layer containing a light-emitting substance can have a single-layer structure or a mixed structure in addition to a stacked structure.

In addition, in order to protect the light-emitting element from damage due to moisture or degassing, it is preferable to provide a protective film 185 that covers the seventh conductive layer 183. As the protective film 185, a dense inorganic insulating film (SiN x : x> 0, SiN x O y : x>y> 0, etc.) by a PCVD method, or a dense inorganic insulating film (SiN x : x> by a sputtering method). 0, SiN x O y: x >y> 0, etc.), thin film mainly containing carbon (DLC (diamond-like carbon) film, CN film, an amorphous carbon film), a metal oxide film (WO 2, CaF 2 It is preferable to use Al 2 O 3 or the like.

  Note that the light-emitting element 184 is formed of a sixth conductive layer 175 functioning as a first pixel electrode, a layer 182 containing a light-emitting substance, and a seventh conductive layer 183 functioning as a second pixel electrode.

  The channel etch type TFT formed in this embodiment uses a material having high heat resistance for the gate electrode, and after performing the heat treatment in the activation process, the gettering process, and the crystallization process at the same time, the low resistance Wirings such as signal lines and scanning lines are formed using a material. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the display device of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  For this reason, it is formed of a crystalline semiconductor film and has higher mobility than a bottom gate channel etch TFT formed of an amorphous semiconductor film. Further, the source region and the drain region contain a catalyst element in addition to the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, compared to a display device using a TFT formed using an amorphous semiconductor film as a switching element, display unevenness can be reduced and a highly reliable display device can be manufactured. is there.

  Furthermore, the off-current can be reduced because the metal element mixed in the semiconductor film in the film formation stage is also gettered by one-time heating for simultaneously performing the crystallization, activation, and gettering steps. . By providing such a TFT in a switching element of a display device, contrast can be improved.

(Embodiment 2)
In this embodiment mode, a manufacturing process different from that of the bottom gate structure channel etch type TFT having the crystalline semiconductor film shown in Embodiment Mode 1 will be described with reference to FIGS.

  As shown in FIG. 3A, a first conductive layer 102 is formed over a substrate 101, and a normal lithography process is performed on the first conductive layer, whereby first masks 103 and 104 are formed.

  Next, as illustrated in FIG. 3B, the first conductive layer 102 is etched using the first masks 103 and 104 to form second conductive layers 111 and 112. The second conductive layer 111 functions as a gate electrode of the driving TFT, and the second conductive layer 112 functions as a gate electrode of the switching TFT.

  Next, after removing the first mask, a first insulating film 113 with a thickness of 10 to 200 nm, preferably 50 to 100 nm, is formed, and a thickness of 50 to 250 nm, preferably with respect to the first insulating film 113 is formed. A second insulating film 114 with a thickness of 100 to 200 nm is formed, and a third insulating film 115 with a thickness of 0.1 to 10 nm, preferably 1 to 3 nm, is formed over the second insulating film 114.

  A first semiconductor film 116 is continuously formed on the first, second, and third insulating films 113, 114, and 115 while maintaining a vacuum state. Next, a layer 117 including a catalytic element is formed over the first semiconductor film 116. The first semiconductor film 116 is formed using the same material and method as the first semiconductor film 131 of the first embodiment, and the layer 117 having a catalytic element is the same as the layer 117 having the catalytic element of the first embodiment. can do.

  Next, a group 3 element (Group 13 element, hereinafter referred to as an acceptor type element) or a Group 5 element (Group 15 element, hereinafter referred to as a donor type element) has a low concentration in a region to be a channel region of the TFT. A channel doping process to be added to the entire surface or selectively.

Next, as illustrated in FIG. 3D, the second semiconductor film 132 and the third semiconductor film 133 are formed over the layer 117 including the catalytic element while maintaining a vacuum state. The second semiconductor film 132 has a thickness of 30 to 200 nm, preferably 50 to 100 nm. The third semiconductor film 133 is 30 to 200 nm, preferably 50 to 100 nm. A second semiconductor film 132 which is a low concentration impurity region (hereinafter referred to as an n region) and a third semiconductor region 133 which is a high concentration impurity region (hereinafter referred to as an n + region) are stacked thereover. Structure. Note that the second semiconductor film 132 and the third semiconductor film 133 are semiconductors containing a donor-type element.

  Note that the third semiconductor film 133 containing the donor element is added with a rare gas element, typically argon, so that distortion of the crystal lattice is formed, and the third semiconductor film 133 is more effective in the gettering step performed later. In particular, it is possible to getter the catalytic element.

  The first semiconductor film 116, the layer 117 having a catalytic element, the second semiconductor film 132, and the third semiconductor film 133 are heated to crystallize the first semiconductor film 116, whereby the first crystalline semiconductor film 141, and as indicated by an arrow in FIG. 3E, the catalyst element contained in the first crystalline semiconductor film 141 is moved to the second semiconductor film 132 and the third semiconductor film 133, thereby Gettering elements. The heat treatment can be performed in the same manner as in the first embodiment.

By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 18 / cm 3 or less, preferably 1 × 10 17 / cm 3. It can be as follows. Such a film is referred to as a first crystalline semiconductor film 141. In addition, since the second semiconductor film 132 and the third semiconductor film 133 to which the catalytic element after gettering has moved are crystallized in the same manner, they are collectively referred to as a second crystalline semiconductor film 142. In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Next, as illustrated in FIG. 3F, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second mask 143 are used to form the second mask 143. The first crystalline semiconductor film 141 is etched to form a second semiconductor region 151 and a third semiconductor region 152 as shown in FIG.

  Thereafter, a bottom gate channel etch TFT can be formed by the same process as in the first embodiment.

(Embodiment 3)
In this embodiment, a manufacturing process of an active matrix substrate having an element for driving a light emitting element of a bottom gate structure channel protection type TFT having a crystalline semiconductor film will be described with reference to FIGS. To do. In this embodiment, a light emitting element having a switching TFT and a driving TFT is shown as a representative example as an element for driving the light emitting element. 4 and 5 are cross-sectional views showing a connection portion between a gate electrode of a switching TFT and a scanning line, a driving TFT, and a light emitting element.

  As shown in FIG. 4A, a first conductive layer 102 is formed over a substrate 101, and a normal lithography process is performed on the first conductive layer to form first masks 103 and 104.

  Next, as illustrated in FIG. 4B, the first conductive layer 102 is etched using the first mask to form second conductive layers 111 and 112. The second conductive layer 111 functions as a gate electrode of the driving TFT, and the second conductive layer 112 functions as a gate electrode of the switching TFT.

  Next, after removing the first mask, a first insulating film 113 with a thickness of 10 to 200 nm, preferably 50 to 100 nm, is formed, and a thickness of 50 to 250 nm, preferably with respect to the first insulating film 113 is formed. A second insulating film 114 with a thickness of 100 to 200 nm is formed, and a third insulating film 115 with a thickness of 0.1 to 10 nm, preferably 1 to 3 nm, is formed over the second insulating film 114.

  A layer 119 including a catalytic element is formed over the third insulating film 115. For the layer 119 having a catalytic element, the same catalytic element as in Embodiment 1 can be used.

  Next, as illustrated in FIG. 4C, a first semiconductor film 131 with a thickness of 50 to 200 nm, preferably 100 to 150 nm, is formed over the layer 119 containing a catalytic element. Next, an insulating film is formed over the first semiconductor film 131 while maintaining a vacuum state, and is selectively etched to have a film thickness of 50 to 300 nm, preferably 100 to 200 nm, immediately above the first conductive film. The channel protective insulating film 128 is formed. The channel protective insulating film 128 is made of silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like. It can be used as appropriate.

  A channel doping process may be performed on the entire surface or selectively after the formation of the first semiconductor film 131.

Next, as illustrated in FIG. 4D, the second semiconductor film 132 and the third semiconductor film 133 are formed over the channel protection insulating film 128. The second semiconductor film 132 is 30 to 200 nm, preferably 50 to 100 nm. The third semiconductor film 133 is 30 to 200 nm, preferably 50 to 100 nm. A second semiconductor film 132 which is a low concentration impurity region (hereinafter referred to as an n region) and a third semiconductor film 133 which is a high concentration impurity region (hereinafter referred to as an n + region) are stacked thereover. It is a structure.

  The second semiconductor film 132 and the third semiconductor film 133 are semiconductors containing a donor element and can be formed in a manner similar to that of Embodiment 1.

The layer 119 having a catalytic element, the first semiconductor film 131, the second semiconductor film 132, and the third semiconductor film 133 are heated to crystallize the first semiconductor film 131, thereby causing the first crystalline semiconductor film 141 to be crystallized. 4E, the catalyst element contained in the first crystalline semiconductor film 141 is moved to the second semiconductor film 132 and the third semiconductor film 133, so that the catalyst element Gettering. The heat treatment can be performed in the same manner as in the first embodiment. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 18 / cm 3 or less, preferably 1 × 10 17 / cm 3. It can be as follows. Such a film is referred to as a first crystalline semiconductor film 141. In addition, since the second semiconductor film 132 and the third semiconductor film 133 to which the catalytic element after gettering has moved are crystallized in the same manner, they are collectively referred to as a second crystalline semiconductor film 142. In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Next, as illustrated in FIG. 4F, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second crystalline semiconductor film 142 are formed using the second mask. One crystalline semiconductor film 141 is etched to form a first semiconductor region 151 and a second semiconductor region 152 as shown in FIG.

  The first crystalline semiconductor film 141 and the second crystalline semiconductor film 142 can be etched similarly to Embodiment Mode 1.

  Next, after removing the second mask, a third conductive layer 153 having a thickness of 200 to 1000 nm, preferably 500 to 1000 nm is formed. Next, a photosensitive material such as a resist is applied over the third conductive layer 153, and after exposure and development, a third mask 161 as shown in FIG. 5A is formed.

  The third conductive layer 153 can be formed in a manner similar to that of Embodiment 1.

  Next, the third conductive layer is etched into a desired shape using the third mask 161 to form fourth conductive layers 162 and 163. The fourth conductive layer 162 functions as a power supply line and a capacitor wiring, and the fourth conductive layer 163 functions as a source electrode or a drain electrode of the driving TFT.

  Next, the exposed portion of the second semiconductor region 152 is etched using the third mask 161 to form third semiconductor regions 164 and 165 that function as a source region and a drain region. At this time, the channel protection insulating film 128 is partially etched when the exposed portion of the first semiconductor region 152 is etched. Therefore, the second semiconductor region 151 is not over-etched. In addition to being not etched, plasma damage during etching can be prevented, and variations in TFT characteristics and abnormal points can be eliminated. The second semiconductor region thus formed is referred to as a fourth semiconductor region 166. The fourth semiconductor region 166 functions as a channel formation region of the driving TFT.

  Next, after removing the third mask, as shown in FIG. 5C, a film thickness of 100 to 100 that functions as a passivation film is formed on the surfaces of the fourth conductive layers 162 and 163 and the fourth semiconductor region 166. A fourth insulating film 171 with a thickness of 300 nm is preferably formed.

  Thereafter, the fourth semiconductor region 166 is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case where heating is performed in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed as the fourth insulating film 171.

  Through the above process, a channel protective TFT having a crystalline semiconductor film can be formed.

  After that, by the same process as in Embodiment Mode 1, an active matrix substrate can be formed by forming a fifth conductive layer 173 connected to the second conductive layer 122a as shown in FIG. 5C. It is.

  Next, as illustrated in FIG. 5D, a seventh insulating film 181 is formed over the sixth conductive layer 175 and the sixth insulating film 174 by the same process as that in Embodiment 1, and is formed thereon. A light-emitting element 184 can be formed.

  The channel protection type TFT formed in this embodiment uses a material having high heat resistance for the gate electrode, and after performing heat treatment for simultaneously performing the activation process, the gettering process, and the crystallization process, Wirings such as signal lines and scanning lines are formed using a resistance material. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the display device of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

(Embodiment 4)
In this embodiment mode, a manufacturing process different from that of the channel protection type TFT having the crystalline semiconductor film described in Embodiment Mode 3 will be described with reference to FIGS.

  As shown in FIG. 6A, as in the first embodiment, a first conductive layer 102 is formed over a substrate 101, a normal lithography process is performed on the first conductive layer, and a first mask is formed. 103 and 104 are formed.

  Next, as illustrated in FIG. 6B, the first conductive layer 102 is etched using the first mask to form second conductive layers 111 and 112. The second conductive layer 111 functions as a gate electrode of the driving TFT, and the second conductive layer 112 functions as a gate electrode of the switching TFT.

  Next, after removing the first mask, a first insulating film 113 with a thickness of 10 to 200 nm, preferably 50 to 100 nm, is formed, and a thickness of 50 to 250 nm, preferably with respect to the first insulating film 113 is formed. A second insulating film 114 with a thickness of 100 to 200 nm is formed, and a third insulating film 115 with a thickness of 0.1 to 10 nm, preferably 1 to 3 nm, is formed over the second insulating film 114.

  A first semiconductor film 116 is continuously formed on the first, second, and third insulating films 113, 114, and 115 while maintaining a vacuum state.

  Next, a group 3 element (Group 13 element, hereinafter referred to as an acceptor type element) or a Group 5 element (Group 15 element, hereinafter referred to as a donor type element) has a low concentration in a region to be a channel region of the TFT. A channel doping process to be added to the entire surface or selectively.

  A layer 117 including a catalytic element is formed over the first semiconductor film 116. As a method for forming the layer 117 having a catalytic element, a method of forming a thin film of a catalytic element or a silicide of a catalytic element on the surface of the first semiconductor film 116 by a PVD method, a CVD method, a vapor deposition method, or the like, a first semiconductor There is a method of applying a solution containing a catalytic element to the surface of the film 116.

  Next, an insulating film is formed over the layer 117 containing a catalytic element, and selectively etched to form the channel protective insulating film 128 in the same manner as in the third embodiment. The channel protective insulating film 128 serves to protect the first semiconductor film 116 over the first conductive layer 111 when the second semiconductor film 132 and the third semiconductor film 133 described below are etched.

  Next, as illustrated in FIG. 6D, the second semiconductor film 132 and the third semiconductor film 133 are formed over the fourth insulating film 128 in the same manner as in Embodiment Mode 1.

The first semiconductor film 116, the layer 117 having a catalytic element, the second semiconductor film 132, and the third semiconductor film 133 are heated to crystallize the first semiconductor film 116 and the first crystalline semiconductor film 141. In addition, as indicated by an arrow in FIG. 6E, the catalytic element contained in the first crystalline semiconductor film 141 is moved to the second semiconductor film 132 and the third semiconductor film 133, and the catalytic element is moved. Gettering. The heat treatment can be performed in the same manner as in the first embodiment. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 18 / cm 3 or less, preferably 1 × 10 17 / cm 3. It can be as follows. Such a film is referred to as a first crystalline semiconductor film 141. In addition, since the second semiconductor film 132 and the third semiconductor film 133 to which the catalytic element after gettering has moved are crystallized in the same manner, they are collectively referred to as a second crystalline semiconductor film 142. In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Next, as illustrated in FIG. 6F, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second crystalline semiconductor film 142 are formed using the second mask. One crystalline semiconductor film 141 is etched to form a first semiconductor region 151 and a second semiconductor region 152 as shown in FIG.

  Thereafter, a channel protection type inverted staggered TFT can be formed by the same process as in the third embodiment.

(Embodiment 5)
In this embodiment mode, a stacked structure of a power supply line, a signal line, a source or drain electrode, a scan line, and a pixel electrode of the active matrix substrate described in Embodiment Mode 1 is described with reference to FIGS. In the following embodiments, a longitudinal sectional view and a top view corresponding to FIG. 2C before forming a light emitting element are shown.

  FIG. 7A is a diagram illustrating a stacked structure of a driving TFT 191 and a fifth conductive layer 173 functioning as a scanning line of the switching TFT 192. The cross-sectional structure taken along the line AB in FIG. Equivalent to.

  FIG. 7B illustrates a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG. 7C.

  Hereinafter, a fourth conductive layer functioning as a power supply line and a capacitor wiring is a power supply line 162, a fourth conductive layer functioning as a signal line is a signal line 167, a fourth conductive layer 163 functioning as a source electrode or a drain electrode, 169, the fifth conductive layer functioning as a scan line is the scan line 173, the second conductive layer functioning as the gate electrode is the gate electrodes 121 and 122a, and the sixth conductive layer functioning as the pixel electrode is the pixel electrode 175. Show.

  As shown in FIG. 7A, a first insulating film 123 is formed over the gate electrode 121 of the driving TFT 191 and the gate electrode 122 a of the switching TFT 192, and the signal line 167 is formed over the first insulating film 123. The drain electrode 163, the power supply line 162, and the fourth semiconductor region 166 of the driving TFT 191 are formed. In FIG. 7, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  In addition, the fourth insulating film 171 and the fifth insulating film 172 are formed on the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply line 162, the fourth semiconductor region 166, and the first insulating film 123. A scan line 173 connected to the gate electrode 122a of the switching TFT 192 is formed on the fifth insulating film 172. That is, the signal line 167, the power supply line 162 of the driving TFT 191, and the signal line 167 of the switching TFT intersect with the scanning line 173 through the fourth insulating film 171 and the fifth insulating film 172.

  A sixth insulating film 174 is formed over all of the scan lines 173 and the fifth insulating film 172, and a pixel electrode 175 is formed over the sixth insulating film 174. That is, the scanning line 173 and the pixel electrode 175 are formed through the sixth insulating film. Since the sixth insulating film 174 over which the pixel electrode 175 is formed is formed using a planarization layer, it is possible to suppress disconnection of a layer including a light-emitting substance that is formed later, and display with few defects. It is possible to form a device.

  Note that the capacitor 193 is formed by the power supply line 162, the first insulating film 123, and the gate electrode 121.

  As shown in FIG. 7B, a first insulating film 123 is formed over the gate electrode 122a of the switching TFT 192. On the first insulating film 123, a fourth semiconductor region 168, a signal line 167, A drain electrode 169 is formed. The drain electrode 169 of the switching TFT 192 is connected to the gate electrode 121 of the driving TFT 191 through the first insulating film 123. The driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 with the fourth insulating film 171, the fifth insulating film 172, and the sixth insulating film 174 interposed therebetween.

(Embodiment 6)
In the present embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with the fifth embodiment will be described with reference to FIG.

  FIG. 8A is a diagram illustrating a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along line AB in FIG. 8C.

  As in the fifth embodiment, the gate electrode 121 of the driving TFT 191 and the gate electrode 122a of the switching TFT 192 are formed, and a first insulating film 123 is formed on them, and on the first insulating film 123, A signal line 167, a drain electrode 163 of the driving TFT 191, a power supply line 162, and a fourth semiconductor region 166 are formed. In FIG. 8, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  In the present embodiment, the scanning line 1113 is formed on the first insulating film 123.

  In addition, a second insulating film 1114 is formed over the signal line 167, and a scanning line 1113 is formed over the second insulating film 1114. That is, the signal line intersects the scanning line 1113 with the second insulating film 1114 interposed therebetween. In this embodiment, the second insulating film 1114 is provided only in a region where the signal line and the scanning line intersect.

  The third insulating film 1111 functioning as a passivation film over the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply line 162, the fourth semiconductor region 166, the first insulating film 123, and the scanning line 1113. Is formed.

  Further, a fourth insulating film 1112 is formed over the third insulating film 1111, and a pixel electrode 175 connected to the drain electrode 163 is formed through the fourth insulating film 1112.

  FIG. 8B illustrates a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG. 8C.

  As shown in FIG. 8B, a switching TFT is formed as in the second embodiment, and the drain electrode 169 of the switching TFT 192 is connected to the gate of the driving TFT 191 with the first insulating film 123 interposed therebetween. It is connected to the electrode 121. In addition, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

(Embodiment 7)
In the present embodiment, an active matrix substrate having a scanning line structure different from that in the fifth embodiment will be described with reference to FIG.

  FIG. 9A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along line AB of FIG. 9C.

  FIG. 9B illustrates a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG. 9C.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the second embodiment. Note that as illustrated in FIG. 9C, the scanning lines 1123a and 1123b are formed for each pixel and connected to gate electrodes 122a and 122b provided in adjacent pixels. For this reason, the material of the scanning lines 1123a and 1123b does not need to be a particularly low resistance material, and the range of selection of the material is widened.

  In addition, a sixth insulating film 174 is formed over all of the scan lines 1123 a and 1123 b and the fifth insulating film 172, and a pixel electrode 175 is formed over the sixth insulating film 174. That is, the pixel electrode 175 is formed so as to cover part of the scanning lines 1123 a and 1123 b with the sixth insulating film 174 interposed therebetween.

(Embodiment 8)
In the present embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with the sixth embodiment will be described with reference to FIG.

  FIG. 10A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along line AB in FIG.

  FIG. 10B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the third embodiment. As shown in FIG. 10C, as in the seventh embodiment, the scanning lines 1133a and 1133b are formed for each pixel and connected to gate electrodes 122a and 122b provided in adjacent pixels. Yes. For this reason, the material of the scanning lines 1133a and 1133b is not particularly required to be a low-resistance material, and the selection range of the material is widened.

  Note that the second insulating film 1137 is provided only in a region where the signal line 167 intersects with the scanning lines 1133a and 1133b. Therefore, the scanning lines 1133a and 1133b are formed over the second insulating film 1137 and the first insulating film 123. In FIG. 10, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  Further, a third insulating film 1131 is provided as a passivation film over the driving TFT 191, the switching TFT 192, and the capacitor 193, and a fourth insulating film 1112 is formed over the third insulating film. Further, the drain electrode 163 of the driving TFT 191 is covered with the pixel electrode 175 with the third insulating film 1131 and the fourth insulating film 1112 interposed therebetween.

  Further, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1131 and the fourth insulating film 1112.

(Embodiment 9)
In this embodiment mode, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with Embodiment Modes 2 to 5 will be described with reference to FIGS.

  FIG. 11A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, which corresponds to a cross-sectional structure taken along line AB of FIG. 11C.

  FIG. 11B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG.

  In the present embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the fifth embodiment.

  In this embodiment, unlike the fifth to eighth embodiments, the scanning lines 1141a and 1141b are formed simultaneously with the power supply lines 162a and 163a, the signal line 167, and the drain electrodes 163 and 169.

  Specifically, as illustrated in FIG. 10A, a first insulating film 123 is formed over the gate electrodes 121 and 122a, and the signal line 167 and the drain of the driving TFT 191 are formed over the first insulating film 123. Scanning lines 1141a and 1141b are formed together with the electrode 163 and the power supply lines 162a and 162b. In addition, a fourth semiconductor region 166 is formed. In FIG. 11, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  Note that the scanning lines 1141a and 1141b are provided in each pixel and do not intersect with the signal lines.

  Further, a fourth insulating film 171 and a fifth insulating film 172 are formed over the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply lines 162a and 162b, and the scanning lines 1141a and 1141b. Over the insulating film 172, a conductive layer 1143a connected to the scan lines 1141a and 1141b is formed. That is, the power supply lines 162 a and 162 b and the signal line 167 intersect the scanning lines 1141 a and 1141 b and the conductive layers 1143 a and 1143 b through the fourth insulating film 171 and the fifth insulating film 172.

  In addition, a sixth insulating film 174 is formed over the entire surfaces of the conductive layers 1143a and 1143b and the fifth insulating film 172, and a pixel electrode 175 is formed over the sixth insulating film.

(Embodiment 10)
In the present embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with the ninth embodiment will be described with reference to FIG.

  FIG. 12A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along line AB of FIG.

  FIG. 12B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG.

  In the present embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the sixth embodiment.

  Here, as in the ninth embodiment, the scanning lines 1141a and 1141b, the signal line 167, the drain electrode 163 of the driving TFT 191 and the power supply lines 162a and 162b do not intersect each other. In addition, scanning lines 1141a and 1141b are formed for each pixel, and are connected to gate electrodes 122a and 122b provided in adjacent pixels. For this reason, the material of the scanning lines 1141a and 1141b is not particularly required to be a low-resistance material, and the selection range of the material is widened.

  In this embodiment, the second insulating film 1154 is provided only in a region where the signal line 167 and the power supply line 162b intersect with the scanning lines 1141a and 1141b.

  In addition, conductive layers 1153 a and 1153 b are formed over the scan lines 1141 a and 1141 b and the second insulating layer 1154. Note that the conductive layers 1153a and 1153b are connected to the scanning lines 1141a and 1141b.

  Further, a third insulating film 1131 is provided as a passivation film over the driving TFT 191, the switching TFT 192, and the capacitor 193, and a fourth insulating film 1112 is formed over the third insulating film. Further, the drain electrode 163 of the driving TFT 191 is covered with the pixel electrode 175 with the third insulating film 1131 and the fourth insulating film 1112 interposed therebetween.

  Further, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1131 and the fourth insulating film 1112.

(Embodiment 11)
In this embodiment, an active matrix substrate having a different stacked structure of scanning lines and source wirings will be described with reference to FIG.

  FIG. 36A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along line AB in FIG.

  FIG. 36B illustrates a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure taken along line CD in FIG.

  As shown in FIG. 36A, after the first insulating film over the gate electrode 122a of the switching TFT 192 is removed, a second insulating film 1162b is formed over the gate electrode 122a. At this time, the second insulating film 1162b is preferably formed so that both ends of the gate electrode 122a are exposed. In FIG. 36, the three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  In addition, when the second insulating film 1162b over the gate electrode 122a is etched, it is preferable to remove the gate insulating film other than the region where the driving TFT 191, the switching TFT 192, and the capacitor 193 are formed. Specifically, it is preferable that only the gate insulating film in the region surrounded by the broken lines 1163a and 1163b in FIG. 36C be left and the gate insulating film outside the broken lines 1163a and 1163b be etched. By this step, the contact area of each conductive layer is increased, contact resistance can be suppressed, and a switching TFT and a driving TFT capable of high-speed operation can be formed.

  Next, power supply lines 162a and 162b and a signal line 167 are formed over the second insulating film 1162b, and at the same time, scanning lines 1161a and 1161b in contact with the gate electrode 122a are formed. With such a structure, contact resistance between the gate electrode and the scanning line can be suppressed. Further, these power supply lines, signal lines, and scanning lines do not intersect.

  Note that the connection structure between the gate electrode 122a and the scanning lines 1161a and 1161b as in this embodiment can be applied to each of Embodiments 5 to 10.

  In this embodiment, the scanning lines 1161a and 1161b formed for each pixel are electrically connected through the gate electrodes 122a and 122b. In addition, the scan line and the signal line intersect with each other through the second insulating film 1162b formed over the gate electrode 122a.

  In this embodiment, the second insulating film 1162b is provided only in a region where the signal line, the power supply line, and the scanning line intersect.

Embodiment 12
In this embodiment, a process for forming a TFT by gettering a catalytic element using a semiconductor film having a rare gas element instead of a semiconductor film having a donor element will be described with reference to FIGS.

  As shown in FIGS. 13A and 13B, a layer 119 having a catalytic element is formed over the first insulating film 123 by a process similar to that of the first embodiment. In FIG. 13, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in Embodiment Mode 1 are shown. An insulating film 123 is shown.

  Next, the first semiconductor film 131 is formed. After this, a channel doping process may be performed. Next, an oxide film with a thickness of 1 to 5 nm may be formed on the surface of the first semiconductor film. Here, ozone water is applied to the surface of the semiconductor film to form an oxide film.

  Next, a second semiconductor film 232 containing a rare gas element is formed over the first semiconductor film 131 by a known method such as a PVD method or a CVD method. The second semiconductor film 232 is preferably an amorphous semiconductor film.

Next, the first semiconductor film 131 and the second semiconductor film 232 are heated by the same method as in Embodiment 1 to crystallize the first semiconductor film 131 and the second semiconductor film 232, and The catalytic element contained in the semiconductor film 131 is moved to the second semiconductor film 232 to getter the catalytic element. By this step, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics as in the first embodiment, that is, the concentration of the catalytic element in the film is 1 × 10 18 / cm 3 or less, preferably It can be 1 × 10 17 / cm 3 or less. Such a film is referred to as a first crystalline semiconductor film 141. Further, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a second crystalline semiconductor film 242 (FIG. 13C).

  Next, as shown in FIG. 13D, after the second crystalline semiconductor film 242 is removed, a conductive third semiconductor film 243 is formed. Here, the third semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas. Note that the second semiconductor film may be a film having any state selected from an amorphous semiconductor, a semi-amorphous semiconductor, a crystalline semiconductor, and a microcrystal (μc). Note that in the case where the third semiconductor film is any one of a conductive amorphous semiconductor film, a semi-amorphous semiconductor, and a microcrystal (μc), heat treatment for activating impurities is performed thereafter. On the other hand, when the third semiconductor film is a crystalline semiconductor having conductivity, heat treatment is not necessarily performed.

  Next, as illustrated in FIG. 13E, a first semiconductor region 151, a second semiconductor region 152, and a third conductive layer 153 are formed by the same process as that in Embodiment Mode 1. Next, a third mask 161 is formed by a lithography process.

  Next, as illustrated in FIG. 13F, the third conductive layer 153 is etched using a third mask to form fourth conductive layers 162 and 163 that function as a source electrode and a drain electrode. . In addition, by the same process as that in Embodiment 1, the first semiconductor region is etched to form third semiconductor regions 164 and 165 that function as a source region and a drain region, and a fourth semiconductor region 166 that functions as a channel formation region. Can be formed.

  Thereafter, an inverted staggered TFT and an active matrix substrate can be formed by the same process as in the first embodiment. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, the present embodiment can be applied to any one of the first to twelfth embodiments.

(Embodiment 13)
In this embodiment, the step of forming the n-channel TFT and the p-channel TFT on the same substrate is formed using FIG.

  As shown in FIG. 14A, similarly to Embodiment Mode 1, second conductive layers 301 and 302 are formed over a substrate 101, and a first insulating film 123 is formed over the second conductive layer. Next, a layer having a catalytic element, a first semiconductor film, and a second semiconductor film containing a donor-type element are formed thereon by a process similar to that in Embodiment 1. In FIG. 14, three layers of the first insulating film 113, the second insulating film 114, and the third insulating film 115 shown in the first embodiment are shown. An insulating film 123 is shown.

  Next, the layer including the catalytic element, the first semiconductor film, and the second semiconductor film are heated to form the first crystalline semiconductor film and the second crystalline semiconductor film. Thereafter, the first crystalline semiconductor film is etched into a desired shape to form a first semiconductor region, and the second semiconductor film is etched into a desired shape to form a second semiconductor region. . Here, the first semiconductor region to which the metal catalyst after gettering has moved is referred to as third semiconductor regions 311 and 312, and the second semiconductor region in which the metal element concentration is reduced is the fourth semiconductor regions 313 and 314. It shows.

  In the present embodiment, as in the first embodiment, after performing the gettering step of each semiconductor film, the semiconductor film is etched into a desired shape to form each semiconductor region. However, after each semiconductor region is formed, The crystallization and gettering steps may be performed by heating.

  Next, after forming oxide films on the surfaces of the third semiconductor regions 311 and 312 and the fourth semiconductor regions 313 and 314, as shown in FIG. 14B, the first masks 321 and 322 are formed by a photolithography process. Form. The mask 321 covers all of the third semiconductor region 311 and the fourth semiconductor region 313 that will be n-channel TFTs later. On the other hand, the mask 322 covers a part of the third semiconductor region 312 to be a p-channel TFT later. At this time, the first mask 322 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element is added to the exposed portion of the third semiconductor region 312 to form a third semiconductor region 324 exhibiting a p-type. At this time, the region covered with the first mask 322 remains as the n-type impurity region 325. At this time, the p-type impurity region can be formed by adding the acceptor-type element so that the concentration is 2 to 10 times that of the third semiconductor region 312 having the donor-type element.

  FIG. 21 shows a profile of the impurity element in the p-type impurity region.

FIG. 21A shows a profile of each element when an acceptor element is added after the second semiconductor film 601 having an n region concentration and an n + region concentration is formed by a CVD method. The donor-type element profile 150a shows the first concentration and the second concentration, as in FIG. The acceptor-type element profile 603 has a high concentration in the vicinity of the surface of the second semiconductor film, and the concentration decreases as it approaches the fourth semiconductor region 314. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n + region is denoted as p + region 602a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is designated. A region having the same is indicated as a p-region 602b.

FIG. 21B illustrates a case where a semiconductor film having a state selected from an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, and a crystalline semiconductor is formed by an ion doping method or an ion implantation method. A profile of each element when an acceptor element is added after forming a second semiconductor film 611 having an n region concentration and an n + region concentration by adding a donor type element to the semiconductor film is shown. The donor-type element profile 150b is similar to the donor-type element profile 150b of FIG. The acceptor-type element profile 613 is similar to the acceptor-type element profile 603 in FIG. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n + region is indicated as p + region 612a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is indicated. The region having this is indicated as p-region 612b.

  Note that the second semiconductor films 601 and 611 containing the donor element are formed by adding a rare gas element, typically argon, so that distortion of the crystal lattice is formed, and a gettering step performed later is performed. It is possible to getter the catalytic element more effectively.

  Next, after removing the first masks 321 and 322, the third semiconductor region 311 and the third semiconductor region 324 exhibiting p-type and the n-type impurity region 325 are heated to activate the impurity element. As a heating method, LRTA (Lamp Rapid Thermal Anneal), GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 4 hours.

  Next, as shown in FIG. 14C, third conductive layers 331 and 332 are formed as in the first embodiment. Next, a second mask 333 is formed, and as illustrated in FIG. 14D, fourth conductive layers 341 and 342 which function as a source region and a drain region, and fifth semiconductor regions 343 and 344 are formed. Form.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, it is possible to form a CMOS circuit that can be driven at a lower voltage than a drive circuit formed of a single channel TFT. Furthermore, since an acceptor element (eg, boron) has a smaller atomic radius than a donor element (eg, phosphorus), the acceptor element is added to the semiconductor film at a relatively low acceleration voltage and concentration. Is possible. In this embodiment, since only the acceptor element is added to the semiconductor film, it can be manufactured in a shorter time and with less energy compared with the manufacturing process of the conventional COMS circuit. As a result, the cost can be reduced. Is possible.

  Further, the present embodiment can be applied to any one of the first to eleventh embodiments.

(Embodiment 14)
In this embodiment, a manufacturing process of an n-channel TFT and a p-channel TFT having a crystalline semiconductor film formed by a gettering process different from that in Embodiment 13 will be described with reference to FIGS.

  In accordance with Embodiment Mode 1, second conductive layers 301 and 302 are formed over the substrate 101. Next, after forming a layer having a catalytic element and a first semiconductor film as shown in FIG. 1B in accordance with Embodiment Mode 1, an insulating film having a thickness of several nm is formed on the surface of the first semiconductor film. Next, a first mask is formed, and the first semiconductor film is etched into a desired shape, so that first semiconductor regions 401 and 402 and layers 303 and 304 containing a catalytic element are formed.

  Next, as shown in FIG. 15B, second masks 403 and 404 are formed over the first semiconductor regions 401 and 402, and then a donor-type element 405 is formed on the exposed portion of the first semiconductor region. Added. At this time, regions to which the donor element is added are denoted as n-type impurity regions 406 and 407. Here, phosphorus is added by an ion doping method. Note that the first semiconductor region covered with the second masks 403 and 404 does not contain phosphorus but contains a catalytic element.

  Next, the first semiconductor region is heated and crystallized, and the catalyst element contained in the first semiconductor region is moved to the n-type impurity regions 406 and 407 as indicated by arrows in FIG. And gettering the catalytic element. Here, the first semiconductor region in which the metal catalyst after gettering has moved is referred to as a source region and drain regions 413 and 414, and the first semiconductor region in which the metal element concentration is reduced is referred to as channel formation regions 411 and 412. . Note that the source and drain regions 413 and 414 and the channel formation regions 411 and 412 are each crystallized by heating in the gettering step, and the donor element is activated.

  Next, as shown in FIG. 15D, third masks 421 and 422 are formed. The third mask 421 covers the channel formation region 411 and the source and drain regions 413 that will later become n-channel TFTs. On the other hand, the third mask 422 covers part or all of the channel formation region 412 to be a p-channel TFT later. At this time, the third mask 422 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element 423 is added to exposed portions of the source and drain regions 414 and the channel formation region 412 to form p-type source and drain regions 424. At this time, by adding an acceptor element so that the concentration thereof is 2 to 10 times that of the source and drain regions 414, the p-type source and drain regions 424 can be formed.

  Next, after the third masks 421 and 422 are removed, the source and drain regions 414 exhibiting n-type and the source and drain regions 424 exhibiting p-type are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 4 hours.

  Next, as shown in FIG. 15E, fourth conductive layers 341 and 342 are formed in the same manner as in the thirteenth embodiment. Thereafter, part of the channel formation regions 411 and 412 may be etched. Next, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, since the number of film formation steps can be reduced as compared with Embodiment Mode 3, throughput can be improved.

  Note that this embodiment can be applied to any one of Embodiments 1 to 11.

(Embodiment 15)
In this embodiment, a step of forming an n-channel TFT and a p-channel TFT on the same substrate using the crystalline semiconductor film subjected to the gettering step using Embodiment Mode 12 is formed using FIG.

  In accordance with the steps of Embodiment Mode 1, second conductive layers 301 and 302 are formed on the substrate 101. Next, in accordance with the process of Embodiment 12, a layer having a catalytic element, a first semiconductor film, and a second semiconductor film having a rare gas element are formed. Next, the first semiconductor film and the second semiconductor film are heated and crystallized in the same manner as in the first embodiment, and the first crystalline semiconductor film is indicated by an arrow in FIG. The catalyst element contained in is moved to the second semiconductor film to getter the catalyst element. The first crystalline semiconductor film in which the catalytic element is gettered is referred to as a second crystalline semiconductor film 501. In addition, since the second semiconductor film to which the metal catalyst after gettering has moved is also crystallized in the same manner, it is referred to as a third crystalline semiconductor film 502.

  Next, as shown in FIG. 16B, after the third crystalline semiconductor film 502 is etched, an insulating film having a thickness of several nm is formed on the surface of the second crystalline semiconductor film 501. Next, a first mask is formed, and the second crystalline semiconductor film is etched to form first semiconductor regions 511 and 512. Next, second masks 513 and 514 are formed. The second mask 513 covers a portion that later becomes a channel formation region of the n-channel TFT. On the other hand, the second mask 514 covers the entire first semiconductor region 512 that will later become a p-channel TFT. Next, a donor-type element 515 is added to the exposed portion of the first semiconductor region 511. At this time, a region to which the donor element is added is referred to as an n-type impurity region 516. The region covered with the second mask 513 functions as a channel formation region 517.

  Next, after the second masks 513 and 514 are removed, third masks 521 and 522 are formed. The third mask 521 covers all of the semiconductor region that later becomes a channel formation region of the p-channel TFT and the first semiconductor region 511 that exhibits n-type.

  Next, an acceptor element 523 is added to the exposed portion of the first semiconductor region 512 to form a p-type impurity region 524. Further, the region covered with the third mask 522 functions as a channel formation region 525. Next, after removing the third masks 521 and 522, the n-type impurity region 516 and the p-type impurity region 524 are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate.

  Next, as illustrated in FIG. 16D, fourth conductive layers 341 and 342 are formed as in the thirteenth embodiment. Thereafter, part of the channel formation regions 517 and 525 may be etched. Next, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the channel formation regions 517 and 525.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

  Note that this embodiment can be applied to any one of Embodiments 1 to 11.

(Embodiment 16)
In the present embodiment, which is a modification of the thirteenth embodiment, a process of forming an n-channel TFT and a p-channel TFT on the same substrate is formed using FIG.

  In accordance with Embodiment 13, as shown in FIG. 17A, third semiconductor regions 311 and 312 and fourth semiconductor regions 313 and 314 having a catalytic element and a donor element are formed. Next, as illustrated in FIG. 17B, after forming the first mask 321, an acceptor element is added to the third semiconductor region 312 to form a p-type impurity region 620. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the third semiconductor region 312. Further, when boron is used as the acceptor element, the molecular radius is small, so that it is added deeper than the third semiconductor region. For this reason, boron is added to the upper portion of the fourth semiconductor region depending on the addition conditions. Thereafter, the third semiconductor region 311 and the p-type impurity region 620 are heated to activate the acceptor element and the donor element. Note that here, the doping conditions are controlled so that the acceptor element is not added to the fourth semiconductor region 314.

  Next, third conductive layers 331 and 332 are formed according to the fourteenth embodiment. Next, the exposed portions of the third conductive layers 331 and 332, the third semiconductor region 311 and the p-type impurity region 620 are etched using a mask formed by a lithography process, as shown in FIG. Thus, fifth semiconductor regions 343 and 621 functioning as source and drain regions and sixth semiconductor regions 345 and 622 functioning as channel formation regions can be formed. After that, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the sixth semiconductor regions 345 and 622.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Furthermore, since only the acceptor element is added to the semiconductor film as in the thirteenth embodiment, it can be manufactured in a shorter time and with less energy compared to a conventional CMOS circuit manufacturing process. As a result, the cost can be reduced.

  Note that this embodiment can be applied to any one of Embodiments 1 to 11.

(Embodiment 17)
In this embodiment, the positional relationship between the end portions of the gate electrode, the source electrode, and the drain electrode, that is, the relationship between the width of the gate electrode and the size of the channel length in the above embodiment is described with reference to FIGS. To do.

  In FIG. 18A, the end portions of the source electrode and the drain electrode overlap each other by z1 on the gate electrode 121a. Here, a region where the gate electrode 121a overlaps with the source electrode and the drain electrode is referred to as an overlap region. That is, the width y1 of the gate electrode is larger than the channel length x1. The width z1 of the overlap region is represented by (y1-x1) / 2. An n-channel TFT having such an overlap region preferably has an n + region and an n− region between the source and drain electrodes and the semiconductor region. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

    In FIG. 18B, the end portion of the gate electrode 121a is coincident with the end portions of the source electrode and the drain electrode. That is, the gate electrode width y2 is equal to the channel length x2.

  In FIG. 18C, the gate electrode 121a is separated from the end portions of the source electrode and the drain electrode by z3. Here, a region where the gate electrode 121a is separated from the source electrode and the drain electrode is referred to as an offset region. That is, the width y3 of the gate electrode is smaller than the channel length x3. The width z3 of the offset area is represented by (x3-y3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  In FIG. 19A, the width y4 of the gate electrode is larger than the channel length x4. In addition, the first end of the gate electrode 121a and one end of the source or drain electrode coincide with each other, and the second end of the gate electrode 121a and the other end of the source or drain electrode are z4. Only overlap. The width z4 of the overlap region is represented by (y4-x4).

  In FIG. 19B, the width y5 of the gate electrode is larger than the channel length x5. In addition, the first end of the gate electrode 121a and one end of the source or drain electrode coincide with each other, and the second end of the gate electrode 121a and the other end of the source or drain electrode are z5. Just away. The width z5 of the offset area is represented by (x5-y5). When the gate electrode 121a has an electrode whose end matches the first end as a source electrode and an electrode having an offset region as a drain electrode, electric field relaxation near the drain electrode can be achieved.

  Further, a TFT having a so-called multi-gate structure in which the semiconductor region covers a plurality of gate electrodes may be used. A TFT having such a structure can also reduce off-state current.

  It should be noted that this embodiment can be applied to any one of Embodiments 1 to 16.

(Embodiment 18)
In the above embodiment, the source electrode and the drain electrode having end portions perpendicular to the surface of the channel formation region are shown; however, the structure is not limited to this. As shown in FIG. 22, it may be an end portion having an angle of more than 90 degrees and less than 180 degrees, preferably 135 to 145 degrees with respect to the surface of the channel formation region. Further, if the angle between the source electrode and the channel formation region surface is θ1, and the angle between the drain electrode and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

  As shown in FIG. 23, the end portions of the source and drain electrodes 2149a and 2149b may have curved surfaces 2150a and 2150b.

  It should be noted that this embodiment can be applied to any one of Embodiments 1 to 16.

(Embodiment 19)
In the present embodiment, a semiconductor film crystallization process applicable to the above embodiment will be described with reference to FIGS. As shown in FIG. 24A, the catalyst element layer 2805 may be formed by vapor deposition and a lithography process to crystallize the semiconductor. FIG. 24B is a top view of FIG. FIG. 24D is a top view of FIG. When the semiconductor film is heated and crystallized, as shown in FIGS. 24C and 24D, crystal growth occurs in a direction parallel to the surface of the substrate from the contact portion between the catalytic element layer and the semiconductor film. appear. Again, crystallization is not performed at a portion far away from the catalyst element layer 2805, and an amorphous portion 2807 remains.

  Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth. Since large crystal grains can be formed by lateral growth, a TFT having higher mobility can be formed.

  It should be noted that this embodiment can be applied to any of Embodiments 1 to 18.

  Next, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. FIGS. 25 to 27 are longitudinal sectional views of the active matrix substrate. The driving circuit unit AA ′, the driving TFT BB ′ of the pixel unit, the gate electrode of the switching TFT and the connecting unit C of the scanning line -C 'is shown schematically.

  As shown in FIG. 25A, a first conductive film with a thickness of 100 to 200 nm is formed over a substrate 800. Here, a glass substrate is used as the substrate 800, and an indium oxide film containing silicon oxide with a thickness of 150 nm is formed as a first conductive film over the surface by a sputtering method. Next, a photosensitive material is discharged or applied onto the first conductive film, and the photosensitive material is exposed and developed using a stepper or the like to form a first mask. Next, the first conductive film is etched using the first mask to form first conductive layers 801 to 804. Here, the indium oxide film containing silicon oxide is etched by wet etching, so that an indium oxide layer containing silicon oxide which is the first conductive layers 801 to 804 is formed. Note that the first conductive layers 801 and 802 function as a gate electrode of a TFT constituting a driving circuit, the first conductive layer 803 functions as a gate electrode of a driving TFT, and the first conductive layer 804 functions as a gate of a switching TFT. Functions as an electrode.

Next, a first insulating film is formed over the surface of the substrate 800 and the first conductive layers 801 to 804. Here, a silicon nitride film with a thickness of 50 nm to 100 nm is used as the first insulating film 805, and a silicon oxynitride film with a thickness of 100 to 200 nm (SiO x N y : x> y) is used as the first insulating film 806. > 0) are laminated by the CVD method. Although not illustrated here, a silicon nitride oxide film (SiN x O y : x>y> 0) with a thickness of 1 to 5 nm may be formed over the first insulating film 806. Note that the first and second insulating films function as gate insulating films. At this time, it is preferable that the silicon nitride film and the silicon oxynitride film are continuously formed only by switching the source gas without being released to the atmosphere. Further, a three-layer structure may be used as in the first embodiment.

  Next, a nickel film 807 with a thickness of 1 to 100 nm is formed on the second insulating film by vapor deposition. Next, an amorphous semiconductor film 811 having a thickness of 10 to 100 nm is formed. An amorphous silicon film having a thickness of 100 nm is formed by a CVD method. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively.

  Next, a semiconductor film 812 containing a donor-type element with a thickness of 100 nm is formed over the surface of the amorphous semiconductor film 811. Here, an amorphous silicon film containing phosphorus is formed using silane gas and 0.5 vol% phosphine gas (flow ratio silane / phosphine is 10/17).

  Next, the amorphous semiconductor film 811 and the semiconductor film 812 containing a donor element are heated. The heat treatment is performed at 550 ° C. for 4 hours in a furnace. By performing the heat treatment, the amorphous semiconductor film 811 is crystallized by the catalyst element and simultaneously gettered to activate the donor element. That is, the catalyst element is moved to the semiconductor film 812 containing a donor element. A crystalline semiconductor film in which the concentration of the catalytic element is reduced at this time is indicated by reference numeral 813 in FIG. Here, a crystalline silicon film is formed. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by 814 in FIG. Here, a crystalline silicon film containing nickel and phosphorus is formed.

  Next, as illustrated in FIG. 25D, after the second masks 815 to 817 are formed over the crystalline semiconductor film 814 and the crystalline semiconductor film 813 containing a catalytic element and a donor-type element, Etching into a desired shape is performed using masks 815 to 817. The etched crystalline semiconductor film 814 containing the catalyst element and the donor element becomes the first semiconductor regions 824 to 826 shown in FIG. 26A, and the etched crystalline semiconductor film 813 becomes the second semiconductor region. 821-823.

  Next, a third mask 827 is formed in a region to be a later n-channel TFT. Next, an acceptor element 828 is added to the first semiconductor regions 825 and 826 which will be p-channel TFTs later, and semiconductor regions 831 and 832 exhibiting p-type are formed as shown in FIG. .

  Next, although not shown, a part of the first insulating films 805 and 806 formed over the first conductive layer 803 functioning as the gate electrode of the driving TFT is etched to form the first function as the gate electrode. A part of the conductive layer 803 is exposed.

  Next, second conductive layers 833 and 834 with a thickness of 500 to 1000 nm are formed on the surfaces of the first semiconductor region 824, the p-type semiconductor regions 831 and 832, and the second semiconductor regions 821 to 823, respectively. The second conductive layers 833 and 834 are formed over the entire surface by a sputtering method, and a plurality of materials such as Mo, Al, Ti, and W can be used in combination. Here, the second conductive layer is formed as a stacked structure of Ti 100 nm, Al 350 nm, and Ti 50 nm.

  Next, after the fourth mask is formed, the second conductive layer is etched to function as a signal line, a scan line, a power supply line, a source electrode, or a drain electrode as shown in FIG. Three conductive layers 841 to 845 are formed.

  Here, a top view of B-B ′ and C-C ′ of the pixel is shown in FIG. 28 and is referred to simultaneously. Through the above steps, a third conductive layer 901 functioning as a signal line and a third conductive layer 902 functioning as a drain electrode are formed over the source region or the drain region of the later switching TFT. In addition, a third conductive layer 844 that functions as a power supply line and a third conductive layer 845 that functions as a drain electrode are formed over a source region or a drain region of a later driving TFT.

  Note that the third conductive layer 902 that functions as a drain of the switching TFT and the first conductive layer 803 that functions as a gate electrode of the driving TFT are connected to each other through a contact hole 909.

  A top view of the drive circuit A-A ′ is shown in FIG. 29 and is referred to at the same time.

  Further, in this step, the third conductive layer is divided to form each signal line, power supply line, scanning line, and drain electrode, and etching is performed so that the width of the drain wiring is narrowed. It is possible to increase the aperture ratio of the display device.

  Next, the first semiconductor region 824 and the p-type semiconductor regions 831 and 832 are etched while leaving the fourth mask, so that source and drain regions 847 to 852 are formed. At this time, part of the second semiconductor regions 821 to 823 is also etched. The second semiconductor regions that function as etched channel formation regions are referred to as third semiconductor regions 854 to 856.

  Here, the case where the driver circuit is formed using a single-channel structure, typically an n-channel TFT, will be described with reference to FIGS. FIG. 39 shows a top view of an inverter formed by an n-channel TFT and a resistor 860. Note that the resistor 860 is formed by connecting one of a source electrode or a drain electrode of an n-channel TFT and a gate electrode.

  Third semiconductor regions 854 and 855 are formed over the first conductive layers 801 and 802 functioning as gate electrodes with a gate insulating film interposed therebetween. In addition, an n-type semiconductor region is formed in each semiconductor region, and a source electrode and a drain electrode are formed thereon.

  One of source and drain electrodes 836 is formed so as to cover the third semiconductor regions 854 and 855. The two semiconductor regions are connected by one of the source electrode or the drain electrode 836.

  Further, the other of the source electrode and the drain electrode 835 is formed over the third semiconductor region 854. Further, the other of the source electrode and the drain electrode 837 is formed over the third semiconductor region 854. In addition, before forming the source electrode and the drain electrode, part of the gate insulating film is etched to expose the first conductive layer 802 functioning as the gate electrode, and then the source electrode and the drain electrode are formed. The other of the source electrode or the drain electrode 837 and the first conductive layer 802 functioning as a gate electrode are connected to each other through a contact hole 838. For this reason, the resistor 860 can be formed. Therefore, an inverter can be formed by connecting the adjacent TFT 859 and the resistor 860.

  Note that the driver circuit may be formed using a single-channel structure of a p-channel TFT instead of a single-channel structure of an n-channel TFT.

Next, as shown in FIG. 26C, after the fourth mask is removed, the second insulating film 857 and the third insulating film 858 are formed over the surface of the fourth conductive layer and the third semiconductor region. Form. Here, a 100-nm-thick silicon oxynitride film (SiO x N y : x>y> 0) containing hydrogen is formed as the second insulating film 857 by a CVD method. Further, a silicon nitride film with a thickness of 200 nm is formed as the third insulating film 858 by a CVD method. The silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, the third semiconductor regions 854 to 856 are heated and hydrogenated. Here, by performing heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the second insulating film 857 is added to the third semiconductor regions 854 to 856 and hydrogenated.

  Next, as illustrated in FIG. 27A, a fourth insulating film 871 is formed over the third insulating film 858. Here, the fourth insulating film 871 is formed by applying and baking acrylic. Next, after a fifth mask is formed over the fourth insulating film 871, the fourth insulating film 871, the third insulating film 858, and the second insulating film 857 are etched to form the switching TFT. A part of the first conductive layer 804 functioning as a gate electrode is exposed. Next, a fourth conductive layer 872 functioning as a scan line connected to the first conductive layer 804 is formed. Here, the fourth conductive layer 872 is formed by sputtering.

  Through the above steps, the driving circuit AA ′ formed by a CMOS circuit in which the n-channel TFT 861 and the p-channel TFT 862 are connected, the driving TFT formed by the p-channel TFT 863, and the n-channel TFT. A pixel portion having a switching TFT to be formed can be formed. In this embodiment, the driver circuit is formed of an n-channel TFT and a p-channel TFT, but the driver circuit and the pixel portion may be formed of only an n-channel TFT.

  Next, a fifth insulating film 873 is formed. The fifth insulating film 873 can be formed using a material similar to that of the fourth insulating film as appropriate. Here, acrylic is used for the fifth insulating film 873. Next, after a sixth mask is formed over the fifth insulating film 873, the fifth insulating film to the second insulating film are etched to expose part of the third conductive layer 845.

  Next, a fifth conductive layer 874 having a thickness of 100 to 300 nm is formed so as to be in contact with the third conductive layer 845. As a material of the fifth conductive layer 874, a light-transmitting conductive film or a reflective conductive film can be given. As a method for forming the fifth conductive layer 874, a sputtering method, an evaporation method, a CVD method, or the like is appropriately used. After the mask is formed, the conductive film is etched to form a conductive layer. Here, indium tin oxide (ITO) containing aluminum having excellent reflectivity as a main component, an alloy material containing at least one of nickel, cobalt, iron, carbon and silicon as a lower layer and silicon oxide thereon. A fifth conductive layer 874 functioning as a pixel electrode is formed by forming a film by sputtering and etching into a desired shape. In the case of tungsten or titanium, it is not necessary to form a transparent electrode such as ITO.

  A top view of the pixel B-B ′ is shown in FIG. 29 and is referred to at the same time. The fourth conductive layer 872 is connected to the fifth conductive layer 874 functioning as a pixel electrode in the contact hole 911.

  Through the above steps, an active matrix substrate can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (scanning line) or in the pixel portion. In this case, electrostatic breakdown can be prevented by manufacturing the TFT in the same process as the above-described TFT and connecting the scanning line layer of the pixel portion and the drain or source wiring layer of the diode.

  Next, as illustrated in FIG. 27B, a sixth insulating film 881 covering the end portion of the fifth conductive layer 874 is formed. Here, the sixth insulating film 881 is formed using a negative photosensitive material.

  Next, a layer 882 containing a light-emitting substance is formed on the surface of the fifth conductive layer 874 and the end portion of the sixth insulating film 881 by an evaporation method, a coating method, a droplet discharge method, or the like. After that, a sixth conductive layer 883 that functions as a second pixel electrode is formed over the layer 882 containing a light-emitting substance. Here, ITO containing silicon oxide is formed by a sputtering method. As a result, a light-emitting element can be formed using the fifth conductive layer, the layer containing a light-emitting substance, and the sixth conductive layer. The materials of the conductive layer and the layer containing a light-emitting substance that constitute the light-emitting element are appropriately selected, and the thicknesses of the layers are also adjusted.

  Note that before the layer 882 containing a light-emitting substance is formed, heat treatment is performed at 200 to 350 ° C. in atmospheric pressure to remove moisture adsorbed in or on the surface of the sixth insulating film 881. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and the layer 882 containing a light-emitting substance is not exposed to the air as it is, and a layer 882 containing a luminescent material is deposited by a vacuum deposition method or a droplet discharge method at atmospheric pressure or reduced pressure. Furthermore, it is preferable to form by a coating method or the like.

  The layer 882 containing a light-emitting substance is formed of a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light-emitting material. One or a plurality of layers selected from high molecular organic compounds may be included and combined with an inorganic compound having electron injection / transport properties or hole injection / transport properties.

Among the charge injecting and transporting materials, materials having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq 3 ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq 3 ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq 2 ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton.

  As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: Aromatic amine systems such as TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring— Compound having a nitrogen bond).

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF 2 ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq 3 and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injection / transport materials, examples of the material having a high hole injection property include molybdenum oxide (MoO x ), vanadium oxide (VO x ), ruthenium oxide (RuO x ), and tungsten oxide (WO x ). And metal oxides such as manganese oxide (MnO x ). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H 2 Pc) and copper phthalocyanine (CuPc) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, by providing a filter (colored layer) that transmits light in the emission wavelength band on the light emission side of the pixel, the color purity is improved and the pixel portion is mirrored (reflected). Prevention can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various materials for the light emitting material forming the light emitting layer. As a low molecular weight organic light-emitting material, 4- (dicyanomethylene) 2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4- (dicyanomethylene) -2-tert-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB) , Periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq 3), 9,9'-bianthryl, 9,10-diphenyl anthracene (abbreviation : DPA) and 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), or the like can be used. Other substances may also be used.

  On the other hand, the high molecular organic light emitting material has higher physical strength and higher device durability than the low molecular organic light emitting material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of a light emitting element using a high molecular weight organic light emitting material is basically the same as that when a low molecular weight organic light emitting material is used, and includes a cathode, a layer containing a light emitting substance, and an anode. However, when forming a layer containing a light emitting material using a high molecular weight organic light emitting material, it is difficult to form a layered structure as in the case of using a low molecular weight organic light emitting material, and in many cases two layers are formed. It becomes a structure. Specifically, the structure is a cathode, a light emitting layer, a hole transport layer, and an anode.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of the polyparaphenylene vinylene-based light emitting material include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2 '-Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. . Polyparaphenylene-based light emitting materials include polyparaphenylene [PPP] derivatives, poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4). -Phenylene) and the like. Polythiophene-based light-emitting materials include polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3 -Cyclohexyl-4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POP], poly [3- (4-octyl) Phenyl) -2,2bithiophene] [PTOPT] and the like. Examples of the polyfluorene-based luminescent material include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for example, Alq 3, Alq 3 partially doped with Nile red that is a red light emitting pigment, p-EtTAZ, TPD (aromatic diamine) are sequentially stacked by a vapor deposition method Thus, white can be obtained. Moreover, when forming a light emitting layer by the apply | coating method using spin coating, after apply | coating, it is preferable to bake by vacuum heating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, A light-emitting pixel is formed using a singlet excitation light-emitting material. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when a triplet excitation light-emitting material is applied to a red pixel, the amount of current flowing through the light-emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the layer containing the light-emitting substance listed above are examples, and examples thereof include a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emission layer, an electron block layer, and a hole block layer. A light-emitting element can be formed by appropriately stacking functional layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved.

Next, a transparent protective layer that covers the light emitting element and prevents moisture from entering is formed. As the transparent protective layer, a silicon nitride film, a silicon oxide film, a silicon oxynitride film (SiN x O y film (x>y> 0) or SiO x N y film (x>y>) obtained by sputtering or CVD is used. 0)), a thin film mainly containing carbon (for example, a DLC film, a CN film), or the like can be used.

  Through the above steps, an active matrix substrate having a light-emitting element can be manufactured. Note that any of Embodiment Modes 1 to 19 can be applied to this example.

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIGS.

  In FIG. 31A, the first pixel electrode 2011 is formed using a light-transmitting conductive film having a high work function, and the second pixel electrode 2017 is formed using a conductive film having a low work function. It is an example. The first pixel electrode 2011 is formed using a light-transmitting oxide conductive material, and is typically formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. A layer 2016 containing a light-emitting substance in which a hole injection layer or hole transport layer 2041, a light-emitting layer 2042, and an electron transport layer or electron injection layer 2043 are stacked is provided thereover. The second pixel electrode 2017 is formed of a first electrode layer 2033 containing an alkali metal or an alkaline earth metal such as LiF or MgAg and a second electrode layer 2034 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 2011 side as indicated by an arrow in the drawing.

In FIG. 31B, the first pixel electrode 2011 is formed using a conductive film having a high work function, and the second pixel electrode 2017 is formed using a light-transmitting conductive film having a low work function. It is an example. The first pixel electrode 2011 includes a first electrode layer 2035 formed using a metal material such as aluminum or titanium, or a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of the metal, and silicon oxide 1-15. The second electrode layer 2032 is formed using a stacked structure of an oxide conductive material containing at a concentration of atomic%. A layer 2016 containing a light-emitting substance in which a hole injection layer or hole transport layer 2041, a light-emitting layer 2042, and an electron transport layer or electron injection layer 2043 are stacked is provided thereover. The second pixel electrode 2017 is formed of a third electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF 2 and a fourth electrode layer 2034 formed of a metal material such as aluminum. By setting any layer of the second electrode to a thickness of 100 nm or less so that light can be transmitted, light can be emitted from the second electrode 2017 as indicated by the arrows in the figure. Become.

FIG. 31E illustrates an example in which light is emitted from both directions, that is, the first electrode and the second electrode. A conductive film having a light-transmitting property and a high work function is provided on the first pixel electrode 2011. In addition, a conductive film having a light-transmitting property and a low work function is used for the second pixel electrode 2017. Typically, the first pixel electrode 2011 is formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 2017 is formed of LiF having a thickness of 100 nm or less. As shown by the arrows in the figure, the third electrode layer 2033 containing an alkali metal or alkaline earth metal such as CaF 2 and the fourth electrode layer 2034 formed of a metal material such as aluminum are used. Thus, light can be emitted from both sides of the first pixel electrode 2011 and the second pixel electrode 2017.

In FIG. 31C, the first pixel electrode 2011 is formed using a light-transmitting conductive film having a low work function, and the second pixel electrode 2017 is formed using a conductive film having a high work function. It is an example. A structure in which a layer containing a light-emitting substance is stacked in the order of an electron-transport layer or electron-injection layer 2043, a light-emitting layer 2042, a hole-injection layer or a hole-transport layer 2041 is shown. The second pixel electrode 2017 includes a second electrode layer 2032 formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the layer 2016 containing a light-emitting substance, a metal such as aluminum or titanium, Alternatively, the first electrode layer 2035 is formed using a stacked structure of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio to the metal. The first pixel electrode 2011 is formed of a third electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF 2 and a fourth electrode layer 2034 formed of a metal material such as aluminum. This layer is also set to a thickness of 100 nm or less so that light can be transmitted, whereby light can be emitted from the first pixel electrode 2011 as indicated by an arrow in the figure.

  In FIG. 31D, the first pixel electrode 2011 is formed using a conductive film having a low work function, and the second pixel electrode 2017 is formed using a light-transmitting conductive film having a high work function. It is an example. A structure in which a layer containing a light-emitting substance is stacked in the order of an electron-transport layer or electron-injection layer 2043, a light-emitting layer 2042, a hole-injection layer or a hole-transport layer 2041 is shown. The first pixel electrode 2011 has a structure similar to that in FIG. 31A and is formed to have a thickness enough to reflect light emitted from a layer containing a light-emitting substance. The second pixel electrode 2017 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, the hole injection layer 2041 is formed using an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), so that oxygen introduced when the second electrode layer 2032 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered. Further, by forming the second pixel electrode 2017 with a light-transmitting conductive layer, light can be emitted from both sides of the second pixel electrode 2017 as shown by arrows in the drawing. Become.

FIG. 31F illustrates an example in which light is emitted from both directions, that is, the first pixel electrode and the second pixel electrode, and the first pixel electrode 2011 has a light-transmitting property and a small work function. A film is used, and a conductive film having a light-transmitting property and a high work function is used for the second pixel electrode 2017. Typically, the first pixel electrode 2011 is formed using a third electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF 2 having a thickness of 100 nm or less and a metal material such as aluminum. The fourth electrode layer 2034 is formed, and the second pixel electrode 2017 may be formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%.

  A pixel circuit of the light-emitting display panel described in the above embodiment and an operation configuration thereof will be described with reference to FIGS. There are two types of operation configurations of the light-emitting display panel, in which a video signal input to a pixel is defined by voltage and a current is defined by current in a display device in which a video signal is digital. There are two types of video signals defined by voltage, one having a constant voltage applied to the light emitting element (CVCV) and one having a constant current applied to the light emitting element (CVCC). In addition, a video signal is defined by current, there are a constant voltage applied to the light emitting element (CCCV) and a constant current applied to the light emitting element (CCCC). In this embodiment, a pixel that performs CVCV operation will be described with reference to FIGS. A pixel that performs the CVCC operation will be described with reference to FIGS.

  In the pixel shown in FIGS. 32A and 32B, a signal line 3710 and a power supply line 3711 are arranged in the column direction, and a scanning line 3714 is arranged in the row direction. In addition, the pixel includes a switching TFT 3701, a driving TFT 3703, a capacitor element 3702, and a light emitting element 3705.

  Note that the switching TFT 3701 and the driving TFT 3703 operate in a linear region when turned on. The driving TFT 3703 has a role of controlling whether or not a voltage is applied to the light emitting element 3705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. In this embodiment, the switching TFT 3701 is an n-channel TFT and the driving TFT 3703 is a p-channel TFT. The driving TFT 3703 may be a depletion type TFT as well as an enhancement type. The ratio (W / L) of the channel width W to the channel length L (W / L) of the driving TFT 3703 is preferably 1 to 1000 depending on the mobility of the TFT. The larger the W / L, the better the electrical characteristics of the TFT.

  In the pixel shown in FIGS. 32A and 32B, the switching TFT 3701 controls input of a video signal to the pixel. When the switching TFT 3701 is turned on, the video signal is input into the pixel. Then, the voltage of the video signal is held in the capacitor 3702.

  32A, in the case where the power supply line 3711 is Vss and the counter electrode of the light emitting element 3705 is Vdd, that is, in FIGS. 31C and 31D, the counter electrode of the light emitting element is an anode, and the driving TFT 3703 The electrode connected to is a cathode. In this case, luminance unevenness due to characteristic variations of the driving TFT 3703 can be suppressed.

  32A, in the case where the power supply line 3711 is Vdd and the counter electrode of the light emitting element 3705 is Vss, that is, in FIGS. 31A and 31B, the counter electrode of the light emitting element is a cathode, and the driving TFT 3703 The electrode connected to is the anode. In this case, when a video signal having a voltage higher than Vdd is input to the signal line 3710, the voltage of the video signal is held in the capacitor 3702, and the driving TFT 3703 operates in a linear region. It is possible to improve.

  The pixel shown in FIG. 32B has the same pixel structure as that shown in FIG. 32A except that a TFT 3706 and a scanning line 3715 are added.

  The TFT 3706 is controlled to be turned on or off by a newly arranged scanning line 3715. When the TFT 3706 is turned on, the charge held in the capacitor 3702 is discharged, and the driving TFT 3703 is turned off. That is, the arrangement of the TFT 3706 can forcibly create a state in which no current flows through the light emitting element 3705. Therefore, the TFT 3706 can be called an erasing TFT. Therefore, the structure in FIG. 32B can improve the light emission duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. Is possible.

  In the pixel having the above operation configuration, the current value of the light-emitting element 3705 can be determined by the driving TFT 3703 that operates in a linear region. With the above structure, variation in TFT characteristics can be suppressed, and luminance unevenness of a light-emitting element due to variation in TFT characteristics can be improved, so that a display device with improved image quality can be provided.

  Next, a pixel that performs the CVCC operation will be described with reference to FIGS. A pixel illustrated in FIG. 32C is provided with a power supply line 3712 and a current control TFT 3704 in the pixel configuration illustrated in FIG.

  The pixel shown in FIG. 32E is the same as the pixel shown in FIG. 32C except that the gate electrode of the driving TFT 3703 is connected to the power supply line 3712 arranged in the row direction. It is a configuration. That is, both pixels shown in FIGS. 32C and 32E show the same equivalent circuit diagram. However, in the case where the power supply line 3712 is arranged in the column direction (FIG. 32C) and in the case where the power supply line 3712 is arranged in the row direction (FIG. 32E), each power supply line has a different layer. It is formed of a conductive film. Here, attention is paid to the wiring to which the gate electrode of the driving TFT 3703 is connected, and FIGS. 32C and 32E are shown separately to show that the layers for producing these are different.

  Note that the switching TFT 3701 operates in a linear region, and the driving TFT 3703 operates in a saturation region. The driving TFT 3703 has a role of controlling a current value flowing through the light emitting element 3705, and the current controlling TFT 3704 has a role of operating in a saturation region and controlling supply of current to the light emitting element 3705.

  32D and 32F are the same as those shown in FIGS. 32C and 32E, respectively, except that an erasing TFT 3706 and a scanning line 3715 are added. The pixel configuration is the same as shown in (E).

  Note that the CVCC operation can be performed also in the pixels shown in FIGS. 32A and 32B. In addition, in the pixel having the operation configuration shown in FIGS. 32C to 32F, Vdd and Vss are appropriately changed depending on the direction of current flow of the light-emitting element, as in FIGS. 32A and 32B. Is possible.

  In the pixel having the above structure, since the current control TFT 3704 operates in a linear region, a slight change in Vgs of the current control TFT 3704 does not affect the current value of the light emitting element 3705. That is, the current value of the light emitting element 3705 can be determined by the driving TFT 3703 operating in the saturation region. With the above structure, it is possible to provide a display device in which luminance unevenness of a light-emitting element due to variation in TFT characteristics is improved and image quality is improved.

  Note that although a structure including the capacitor 3702 is shown, the present invention is not limited to this, and the capacitor 3702 is not provided in the case where the capacity for holding a video signal can be covered by a gate capacitor or the like. May be.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  As described above, various pixel circuits can be employed.

  In this embodiment, as an example of a display panel, the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 30A is a top view of a panel in which a space between a first substrate and a second substrate is sealed with a first sealant 1205 and a second sealant 1206. FIG. ) Corresponds to cross-sectional views taken along lines AA ′ and BB ′ in FIG.

  In FIG. 30A, reference numeral 1202 indicated by a dotted line denotes a pixel portion, and 1203 denotes a scanning line (gate line) driving circuit. In this embodiment, the pixel portion 1202 and the scan line driver circuit 1203 are in a region sealed with a first sealant 1205. Reference numeral 1201 denotes a signal line (source line) driver circuit, and a chip-like signal line driver circuit is provided over the first substrate 1200. As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. As the second sealing material, it is preferable to use an epoxy resin having a low viscosity. In addition, the first sealing material 1205 and the second sealing material are desirably materials that do not transmit moisture and oxygen as much as possible.

Further, a desiccant may be provided between the pixel portion 1202 and the sealant 1205. Further, in the pixel portion, a desiccant may be provided on the scan line or the signal line. As the desiccant, it is preferable to use a substance that adsorbs water (H 2 O) by chemical adsorption such as an oxide of an alkaline earth metal such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  In addition, the resin can be fixed to the second substrate 1204 in a state where a highly moisture-permeable resin contains a granular material of a desiccant. Here, examples of the highly moisture-permeable resin include acrylic resins such as ester acrylate, ether acrylate, ester urethane acrylate, ether urethane acrylate, butadiene urethane acrylate, special urethane acrylate, epoxy acrylate, amino resin acrylate, and acrylic resin acrylate. Can be used. In addition, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type Epoxy resins such as epoxy resins, glycidyl ester resins, glycidylamine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Further, other substances may be used. Further, for example, inorganic substances such as siloxane polymer, polyimide, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like may be used.

  You may provide a desiccant in the area | region which overlaps with a scanning line. Furthermore, you may fix to the 2nd board | substrate in the state which included the granular substance of the desiccant in resin with high moisture permeability. By providing these desiccants, it is possible to suppress the intrusion of moisture into the display element and the deterioration caused thereby without reducing the aperture ratio. For this reason, it is possible to suppress variations in deterioration of the light emitting elements in the peripheral portion and the central portion of the pixel portion 1202.

  Reference numeral 1210 denotes a connection wiring region for transmitting signals input to the signal line driver circuit 1201 and the scanning line driver circuit 1203. The connection wiring 1208 is connected from an FPC (flexible printed wiring) 1209 serving as an external input terminal. Receive video signals and clock signals.

  Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1200, and includes a plurality of semiconductor elements typified by TFTs. A scan line driver circuit 1203 and a pixel portion 1202 are shown as driver circuits. Note that as the scan line driver circuit 1203, a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined is formed.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the area of the light emitting display panel can be reduced.

  The pixel portion 1202 is formed of a plurality of pixels including a switching TFT 1211, a driving TFT 1212, and a first pixel electrode (anode) 1213 made of a reflective conductive film electrically connected to the drain electrode thereof. The

  Further, the gate electrode 1231 of the switching TFT and the scanning line 1214 are connected through the first insulator 1232 and the gate insulating film. Note that the gate electrodes of the driving TFT and the TFT of the driving circuit are also connected to the scanning line through the first insulator and the gate insulating film, respectively.

  In addition, a second insulator 1233 is formed over the first insulator 1232, and the scan line 1214 and the first pixel electrode 1213 are formed through the second insulator 1233.

  A third insulator (referred to as a partition wall, a barrier, or the like) 1234 is formed at both ends of the first pixel electrode (anode) 1213. In order to improve the coverage (coverage) of the film formed over the third insulator 1234, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the third insulator 1234. The surface of the third insulator 1234 may be covered with an aluminum nitride film, an aluminum nitride oxide film, a thin film containing carbon as its main component, or a protective film made of a silicon nitride film. Further, as the third insulator 1234, an organic material obtained by dissolving or dispersing a material that absorbs visible light such as a black pigment or a dye is used to absorb stray light from a light-emitting element that is formed later. Can do. As a result, the contrast of each element is improved.

  Further, an organic compound material is deposited on the first pixel electrode (anode) 1213 to selectively form a layer 1215 containing a light-emitting substance. Further, a second pixel electrode (cathode) is formed over the layer 1215 containing a light-emitting substance.

  For the layer 1215 containing a light-emitting substance, the structure shown in Embodiment 2 can be used as appropriate.

  In this manner, a light-emitting element 1217 including the first pixel electrode (anode) 1213, the layer 1215 containing a light-emitting substance, and the second pixel electrode (cathode) 1216 is formed.

  In addition, a protective stack 1218 is formed in order to seal the light emitting element 1217. The protective laminate includes a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film. Next, the protective laminate 1218 and the second substrate 1204 are bonded with the first sealant 1205 and the second sealant 1206. Note that the second sealant is preferably dropped using a device for dropping the sealant. After the sealing material is dropped or discharged from the dispenser to apply the sealing material onto the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum and then cured by ultraviolet curing. it can.

  Note that an antireflection film 1226 is provided on the surface of the second substrate 1204 to prevent external light from being reflected by the substrate surface. One or both of a polarizing plate and a retardation plate may be provided between the second substrate and the antireflection film. By providing the retardation plate and the polarizing plate, it is possible to prevent external light from being reflected by the pixel electrode. Note that the first pixel electrode 1213 and the second pixel electrode 1216 are formed using a light-transmitting conductive film or a semi-transparent conductive film, and the second insulator 1233 and the third insulator 1234 are formed. Is formed using a material that absorbs visible light or an organic material that dissolves or disperses a material that absorbs visible light, so that each pixel electrode does not reflect external light. Therefore, a retardation plate and a polarizing plate are used. Not necessary.

  The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Note that a space filled with an inert gas such as nitrogen gas may be provided between the second substrate 1204 and the protective laminate 1218 instead of the second sealant 1206. It is possible to enhance prevention of moisture and oxygen from entering.

  Further, a colored layer can be provided between the second substrate and the polarizing plate. In this case, a full color display can be performed by providing a light-emitting element capable of emitting white light in the pixel portion and separately providing a colored layer indicating RGB on the second substrate 1204. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Further, each pixel portion, a light-emitting element that emits red, green, and blue light can be formed, and a colored layer can be used for the second substrate 1204. Such a display module has high color purity of each RBG and enables high-definition display.

  Alternatively, the light-emitting display module may be formed using one of the first substrate 1200 and the second substrate 1204, or a substrate such as a film or resin. When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

  Further, an IC chip such as a controller, a memory, and a pixel driver circuit may be provided on the surface or end of an FPC (flexible printed wiring) 1209 that serves as an external input terminal to form a light emitting display module.

  Note that any of Embodiment Modes 1 to 19 can be applied to this example.

  In this embodiment, a structure of a scanning line input terminal and a signal line input terminal provided in the periphery of the substrate will be described with reference to FIG. 37 (A), (C) and (E) are top views of the periphery of the substrate, respectively, and FIGS. 37 (B), (D) and (F) are FIGS. 37 (A) and (C), respectively. It is the longitudinal cross-sectional view of KL and MN of (E). In addition, KL shows the longitudinal cross-sectional view of a scanning line input terminal, and MN shows the longitudinal cross-sectional view of a signal line input terminal.

  As shown in FIGS. 37A and 37B, the first substrate 11 and the second substrate 21 are sealed with a sealant 20, and the first substrate 11 and the second substrate 21 are sealed in the first substrate. A pixel portion in which the pixel electrode 19 and the pixel TFT 1 are arranged is formed. In addition, an insulator 27 is formed to cover an end portion of the first pixel electrode 19, and a layer 29 containing a luminescent material and a second pixel electrode 30 are formed on the surfaces of the insulator 27 and the first pixel electrode 19. The light emitting element is formed by the first pixel electrode, the layer 29 containing a light emitting substance, and the second pixel electrode 30.

  In FIGS. 37A and 37B, the scanning line input terminal 13 and the signal line input terminal 26 are formed in the same process as the gate electrode 12 of the TFT 1. The scanning line input terminal 13 is connected to each gate electrode via a scanning line 17 formed on the first interlayer insulating film 16. The signal line input terminal 26 is connected to the power supply lines 14a and 14b and the signal line 14c, respectively.

  The first pixel electrode 19 is formed on the second interlayer insulating film 18 formed on the first interlayer insulating film 16. Note that the first pixel electrode is connected to the drain electrode 15 through the first interlayer insulating film 16 and the second interlayer insulating film 18.

  The scanning line input terminal 13 and the signal line input terminal 26 are connected to the FPCs 24 and 25 via connection layers 22 and 23, respectively. In FIG. 37A, the connection layers 22 and 23 and the FPCs 24 and 25 are indicated by broken lines.

  In FIG. 37C and FIG. 37D, the scanning line input terminal 33 is formed in the same process as the power supply lines 14a and 14b and the signal line 14c, and the signal line input terminal 26 is connected to the power supply lines 14a and 14b, It is a part of each signal line 14c. The scanning line input terminal 33 and the gate electrode 12 are connected by a scanning line 17 formed on the first interlayer insulating film 16.

  Other structures are similar to those in FIGS. 37A and 37B.

  In FIG. 37E and FIG. 37F, the scanning line input terminal is a part of the scanning line 43, and the signal line input terminal 44 is formed simultaneously with the scanning line 43. That is, each input terminal is formed simultaneously with the scanning line 43. The signal line input terminal 44 is formed on the exposed power supply lines 14a, 14b, and signal lines 14c after the first interlayer insulating film formed on the power supply lines 14a, 14b, and signal lines 14c is removed. Is done.

  Other structures are similar to those in FIGS. 37A and 37B.

  Note that although this example is described using the structure of the TFT shown in Embodiment Mode 1, it can be applied to Embodiment Modes 2 to 19 as appropriate.

  An example of a protection circuit included in the display device of the present invention will be described. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, a configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 38A includes P-type TFTs 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit shown in FIG. 38B is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with diodes 7260 and 7270 having rectifying properties. The protection circuit shown in FIG. 38C is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. Further, as a protection circuit having a different structure from the above, the protection circuit illustrated in FIG. 38D includes resistors 7280 and 7290 and an N-type TFT 7300. The protection circuit illustrated in FIG. 38E includes resistors 7280 and 7290, a P-type TFT 7310, and an N-type TFT 7320. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment can be freely combined with the above embodiment modes.

  In this embodiment, mounting of a driver circuit on the light-emitting panel described in the above embodiment will be described with reference to FIGS.

  As shown in FIG. 33A, a signal line driver circuit 1402 and scan line driver circuits 1403 a and 1403 b are mounted around the pixel portion 1401. In FIG. 33A, as a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b, a mounting method using a known anisotropic conductive adhesive and anisotropic conductive film, a COG method, wire bonding, and the like. The IC chip 1405 is mounted on the substrate 1400 by a method, a reflow process using a solder bump, or the like. Here, the COG method is used. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  As shown in FIG. 33B, in the case where a semiconductor element typified by a TFT is formed using a semi-amorphous semiconductor or a crystalline semiconductor, the pixel portion 1401 and the scan line driver circuits 1403a and 1403b are integrally formed over the substrate. In some cases, the signal line driver circuit 1402 and the like are separately mounted as an IC chip. In FIG. 33B, an IC chip 1405 is mounted on a substrate 1400 as a signal line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  Further, as shown in FIG. 33C, the signal line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 33C, the signal line driver circuit is mounted by the TAB method, but the scan line driver circuit may be mounted by the TAB method.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which a circuit is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor film obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor film has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  As an electronic device in which the display device shown in the above embodiment is incorporated in a housing, a television device (also simply referred to as a television or a television receiver), a camera such as a digital camera or a digital video camera, a mobile phone device (simply a mobile phone) Portable information terminals such as PDAs, portable game machines, computer monitors, computers, sound reproduction apparatuses such as car audio, and image reproduction apparatuses equipped with recording media such as home game machines. Can be mentioned. A specific example will be described with reference to FIG.

  A portable information terminal illustrated in FIG. 34A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  A digital video camera shown in FIG. 34B includes a display portion 9701, a display portion 9702, and the like. As the display portions 9701 and 9702, those shown in Embodiment Modes 1 to 16 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a digital video camera capable of high-quality display can be provided at low cost.

  A portable terminal illustrated in FIG. 34C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, any of those shown in Embodiment Modes 1 to 16 and Examples 1 to 7 can be applied. By using the display device which is one embodiment of the present invention, a portable terminal capable of high-quality display can be provided at low cost.

  A portable television device shown in FIG. 34D includes a main body 9301, a display portion 9302, and the like. As the display portion 9302, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable television device capable of high-quality display can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 34E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable computer capable of high-quality display can be provided at low cost.

  A television device illustrated in FIG. 34F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a television device capable of high-quality display can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device by reducing power consumption, and can reduce the frequency of charging the secondary battery.

  A large television device shown in FIG. 35 includes a main body 9601, a display portion 9602, and the like. A wall-supporting body is provided on the back or top of the main body. FIG. 35 shows a wall-mounted television device as a typical example of a large television device. As shown in FIG. 35, the image can be displayed over the wall 9603. In addition, the present invention can be applied to various uses as a display medium having a particularly large area, such as an information display board at a railway station or airport, or an advertisement display board in a street. As the display portion 9602, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a large television device capable of high-quality display can be provided at low cost.

8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a structure of a display device according to the invention. FIG. 6 is a cross-sectional view illustrating a structure of a display device according to the invention. FIG. 6 is a cross-sectional view illustrating impurity concentration in a semiconductor region of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating impurity concentration in a semiconductor region of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a structure of a display device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a top view illustrating a structure of a pixel of a display device according to the present invention. FIG. 6 is a top view illustrating a structure of a driver circuit of a display device according to the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a structure of a light-emitting display panel according to the invention. FIG. 6 is a cross-sectional view illustrating a structure of a light-emitting element of a display device according to the present invention. 4A and 4B each illustrate a circuit of a light-emitting element of a display device according to the present invention. FIG. 6 is a top view illustrating a method for mounting a driver circuit of a display device according to the present invention. 10A and 10B each illustrate an example of an electronic device. 10A and 10B each illustrate an example of an electronic device. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and a cross-sectional view illustrating a structure of a peripheral portion of a display device according to the invention. FIG. 9 is a circuit diagram illustrating a protection circuit. FIG. 6 is a top view illustrating a structure of a driver circuit of a display device according to the present invention.

Explanation of symbols

101 substrate 102 first conductive layer 103 first mask 104 first mask 111 second conductive layer 112 second conductive layer 113 first insulating film 114 second insulating film 115 third insulating film 131 second 1st semiconductor film 132 2nd semiconductor film 133 3rd semiconductor film 141 1st crystalline semiconductor film 142 2nd crystalline semiconductor film 143 2nd mask


Claims (29)

  1.   Forming a gate electrode on the insulating surface; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element And forming a second semiconductor film having an impurity element over the first semiconductor film and heating to form a first conductive layer in contact with the heated second semiconductor film, A portion of the first conductive layer is etched to form a source electrode and a drain electrode; a portion of the second semiconductor film is etched to form a source region and a drain region; An insulating film is formed on the source electrode and the drain electrode, and a part of the insulating film and the gate insulating film is etched to expose a part of the gate electrode, and then a gate wiring connected to the gate electrode is formed. And the insulation A first electrode connected to the source electrode or drain electrode is formed, and a layer containing a light emitting material is formed on the first electrode. And forming a second electrode. A method for manufacturing a display device.
  2.   Forming a gate electrode on the insulating surface; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element And forming a second semiconductor film having an impurity element over the first semiconductor film and heating to form a first conductive layer in contact with the heated second semiconductor film, A part of one conductive layer is etched to form a source electrode and a drain electrode, a part of the second semiconductor film is etched to form a source region and a drain region, and the source electrode or the drain electrode is formed. An insulating film covering a part of the gate electrode, etching a part of the gate insulating film to expose a part of the gate electrode, and then covering the one of the source electrode and the drain electrode and the gate On the insulating film, Forming a gate wiring connected to the gate electrode, forming a first electrode in contact with the other of the source electrode and the drain electrode, and forming a layer containing a light-emitting substance on the first electrode, and a second electrode A manufacturing method of a display device characterized by forming.
  3.   A gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor film is formed on the gate insulating film, and a layer having a catalytic element on the first semiconductor film And forming a second semiconductor film having an impurity element on the layer having the catalytic element and then heating to form a first conductive layer in contact with the heated second semiconductor film, and A portion of the first conductive layer is etched to form a source electrode and a drain electrode; a portion of the second semiconductor film is etched to form a source region and a drain region; An insulating film is formed on the source electrode and the drain electrode, and a part of the insulating film and the gate insulating film is etched to expose a part of the gate electrode, and then a gate wiring connected to the gate electrode is formed. And the insulation A first electrode connected to the source electrode or drain electrode is formed, and a layer containing a light emitting material is formed on the first electrode. And forming a second electrode. A method for manufacturing a display device.
  4.   A gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor film is formed on the gate insulating film, and a layer having a catalytic element on the first semiconductor film And forming a second semiconductor film having an impurity element on the layer having the catalytic element and then heating to form a first conductive layer in contact with the heated second semiconductor film, and A part of one conductive layer is etched to form a source electrode and a drain electrode, a part of the second semiconductor film is etched to form a source region and a drain region, and the source electrode or the drain electrode is formed. An insulating film covering a part of the gate electrode, etching a part of the gate insulating film to expose a part of the gate electrode, and then covering the one of the source electrode and the drain electrode and the gate On the insulating film, Forming a gate wiring connected to the gate electrode, forming a first electrode in contact with the other of the source electrode and the drain electrode, and forming a layer containing a light-emitting substance on the first electrode, and a second electrode A manufacturing method of a display device characterized by forming.
  5.   Forming a gate electrode on the insulating surface; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element And forming a protective layer over a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap, and having an impurity element on the first semiconductor film and the protective layer After forming the second semiconductor film, heating is performed, a first conductive layer in contact with the heated second semiconductor film is formed, a part of the first conductive layer is etched, and a source electrode and a drain are formed. Forming an electrode, etching a part of the second semiconductor film to form a source region and a drain region, forming an insulating film on the gate insulating film, the source electrode, and the drain electrode; And the gate insulating film After etching a part to expose a part of the gate electrode, a gate wiring connected to the gate electrode is formed, and a part of the insulating film is etched to remove a part of the source electrode or the drain electrode. A first electrode connected to the source electrode or the drain electrode is formed after the exposure, and a layer containing a light-emitting substance and a second electrode are formed over the first electrode. Manufacturing method.
  6.   Forming a gate electrode on the insulating surface; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element Forming a protective layer over a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap, and a second layer having an impurity element over the semiconductor film and the protective layer. A semiconductor film is formed and then heated to form a first conductive layer in contact with the heated second semiconductor film, and a part of the first conductive layer is etched to form a source electrode and a drain electrode Then, a part of the second semiconductor film is etched to form a source region and a drain region, an insulating film covering a part of the source electrode or the drain electrode is formed, and a part of the gate insulating film is formed. Etch the gate After exposing a part of the electrode, a gate wiring connected to the gate electrode is formed on the insulating film covering the source electrode or the drain electrode and the gate insulating film, and the source electrode or the drain electrode A method for manufacturing a display device, wherein a first electrode in contact with the other is formed, a layer containing a light-emitting substance, and a second electrode are formed over the first electrode.
  7.   A gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor film is formed on the gate insulating film, and a layer having a catalytic element on the first semiconductor film Forming a protective layer in a region where the gate electrode, the first semiconductor film, and the layer having the catalytic element overlap, and a second layer having an impurity element on the protective layer and the layer having the catalytic element. And forming a first conductive layer in contact with the heated second semiconductor film, etching a part of the first conductive layer, and forming a source electrode and a drain electrode. Forming and etching a part of the second semiconductor film to form a source region and a drain region; forming an insulating film over the gate insulating film and the source electrode and the drain electrode; and One of gate insulating film After etching a portion of the gate electrode, a gate wiring connected to the gate electrode was formed, and a portion of the insulating film was etched to expose a portion of the source or drain electrode Then, a first electrode connected to the source electrode or the drain electrode is formed, and a layer containing a light-emitting substance and a second electrode are formed over the first electrode, and a method for manufacturing a display device .
  8.   A gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor film is formed on the gate insulating film, and a layer having a catalytic element on the first semiconductor film Forming a protective layer in a region where the gate electrode, the first semiconductor film, and the layer having the catalytic element overlap, and a second layer having an impurity element on the protective layer and the layer having the catalytic element. And forming a first conductive layer in contact with the heated second semiconductor film, etching a part of the first conductive layer, and forming a source electrode and a drain electrode. Forming and etching part of the second semiconductor film to form a source region and a drain region, forming an insulating film covering a part of the source electrode or the drain electrode, and part of the gate insulating film; Etch A gate wiring connected to the gate electrode is formed on the insulating film covering the one of the source electrode and the drain electrode and the gate insulating film, and the source electrode or the drain electrode is exposed. A method for manufacturing a display device is characterized in that a first electrode in contact with the other electrode is formed, a layer containing a light-emitting substance, and a second electrode are formed over the first electrode.
  9.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element Forming a second semiconductor film having an impurity element on the first semiconductor film, heating the second semiconductor film, and etching the heated second semiconductor film to form a source region and a drain region; After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed, Forming an insulating film on the gate insulating film, the gate wiring, the source electrode and the drain electrode; etching a part of the insulating film to expose a part of the gate wiring; Forming a conductive layer connected to a line, etching a part of the insulating film to expose a part of the source or drain electrode, and then forming a first electrode in contact with the source or drain electrode; A method for manufacturing a display device, wherein a layer containing a light-emitting substance and a second electrode are formed over the first electrode.
  10.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element Forming a second semiconductor film having an impurity element on the first semiconductor film, heating the second semiconductor film, and etching the heated second semiconductor film to form a source region and a drain region; After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed, An insulating film covering a part of the source electrode or drain electrode is formed, and the conductive film connected to the gate wiring is formed on the insulating film covering one of the source electrode or the drain electrode and the gate electrode. And forming a first electrode in contact with the other of the source electrode and the drain electrode, and forming a layer containing a light-emitting substance and a second electrode on the first electrode. Manufacturing method.
  11.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a first semiconductor film on the gate insulating film; and forming a layer having a catalytic element on the first semiconductor film. Forming a second semiconductor film having an impurity element on the layer having the catalytic element, and then heating, etching the heated second semiconductor film to form a source region and a drain region, After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed, Forming an insulating film on the gate insulating film, the gate wiring, the source electrode and the drain electrode; etching a part of the insulating film to expose a part of the gate wiring; Forming a conductive layer connected to a line, etching a part of the insulating film to expose a part of the source or drain electrode, and then forming a first electrode in contact with the source or drain electrode; A method for manufacturing a display device, wherein a layer containing a light-emitting substance and a second electrode are formed over the first electrode.
  12.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a first semiconductor film on the gate insulating film; and forming a layer having a catalytic element on the first semiconductor film. Forming a second semiconductor film having an impurity element on the layer having the catalytic element, and then heating, etching the heated second semiconductor film to form a source region and a drain region, After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed, An insulating film covering a part of the source electrode or drain electrode is formed, and the conductive film connected to the gate wiring is formed on the insulating film covering one of the source electrode or the drain electrode and the gate electrode. And forming a first electrode in contact with the other of the source electrode and the drain electrode, and forming a layer containing a light-emitting substance and a second electrode on the first electrode. Manufacturing method.
  13.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element Forming a protective layer over a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap with each other, and forming an impurity element over the first semiconductor film and the protective layer. The second semiconductor film is heated after being formed, the heated second semiconductor film is etched to form a source region and a drain region, a part of the gate insulating film is etched, and one of the gate electrodes is etched. A gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region, and the gate insulating film, the gate wiring, the source electrode, and An insulating film is formed on the rain electrode, a part of the insulating film is etched to expose a part of the gate wiring, and then a conductive layer connected to the gate wiring is formed, and a part of the insulating film is formed. Is etched to expose a part of the source or drain electrode, a first electrode in contact with the source or drain electrode is formed, a layer containing a light-emitting substance on the first electrode, and a second A method for manufacturing a display device, characterized by forming an electrode.
  14.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a layer having a catalytic element on the gate insulating film; and forming a first semiconductor film on the layer having the catalytic element Forming a protective layer over a region where the gate electrode, the layer having the catalytic element, and the first semiconductor film overlap with each other, and forming an impurity element over the first semiconductor film and the protective layer. The second semiconductor film is heated after being formed, the heated second semiconductor film is etched to form a source region and a drain region, a part of the gate insulating film is etched, and one of the gate electrodes is etched. An insulating film that forms a gate wiring connected to the gate electrode, a source electrode and a drain electrode in contact with the source region and the drain region, and covers a part of the source electrode or the drain electrode Forming a conductive layer connected to the gate wiring over the insulating film covering the source electrode or the drain electrode and the gate electrode, and forming a first electrode in contact with the other of the source electrode or the drain electrode; And a layer containing a light-emitting substance and a second electrode are formed over the first electrode.
  15.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a first semiconductor film on the gate insulating film; and forming a layer having a catalytic element on the first semiconductor film. Forming a protective layer in a region where the gate electrode, the first semiconductor film, and the layer including the catalytic element overlap, and a second layer including an impurity element on the protective layer and the layer including the catalytic element. After the semiconductor film is formed and heated, the heated second semiconductor film is etched to form a source region and a drain region, a part of the gate insulating film is etched, and a part of the gate electrode is formed. After the exposure, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed, and the gate insulating film, the gate wiring, the source electrode and the drain are formed. Forming an insulating film on the gate electrode, etching a part of the insulating film to expose a part of the gate wiring, and then forming a conductive layer connected to the gate wiring; Is etched to expose a part of the source or drain electrode, a first electrode in contact with the source or drain electrode is formed, a layer containing a light-emitting substance on the first electrode, and a second A method for manufacturing a display device, characterized by forming an electrode.
  16.   Forming a gate electrode on the substrate; forming a gate insulating film on the gate electrode; forming a first semiconductor film on the gate insulating film; and forming a layer having a catalytic element on the first semiconductor film. Forming a protective layer in a region where the gate electrode, the first semiconductor film, and the layer including the catalytic element overlap, and a second layer including an impurity element on the protective layer and the layer including the catalytic element. After the semiconductor film is formed and heated, the heated second semiconductor film is etched to form a source region and a drain region, a part of the gate insulating film is etched, and a part of the gate electrode is formed. After the exposure, a gate wiring connected to the gate electrode, a source electrode and a drain electrode in contact with the source region and the drain region are formed, and an insulating film that covers a part of the source electrode or the drain electrode is formed. And forming a conductive layer connected to the gate wiring on the insulating film covering the source electrode or the drain electrode and the gate electrode, and forming a first electrode in contact with the other of the source electrode or the drain electrode. A method for manufacturing a display device is characterized in that a layer containing a light-emitting substance and a second electrode are formed over the first electrode.
  17.   17. The display device according to claim 1, wherein after the first electrode in contact with the source electrode or the drain electrode is formed, a gate wiring connected to the gate electrode is formed. Manufacturing method.
  18.   18. The display device according to claim 1, wherein after the gate wiring connected to the gate electrode is formed, the first electrode in contact with the source electrode or the drain electrode is formed. Manufacturing method.
  19.   The method for manufacturing a display device according to claim 1, wherein the gate wiring is connected to three or more gate electrodes.
  20.   20. The method for manufacturing a display device according to claim 1, wherein the gate wiring is connected to two of the gate electrodes.
  21.   21. The gate electrode according to any one of claims 1 to 20, wherein the gate electrode includes a conductive film formed on the insulating surface, a photosensitive resin is discharged or applied onto the conductive film, and the photosensitive resin is photo-coated. A method for manufacturing a display device, comprising: forming a mask by exposing and developing using a mask; and etching the conductive film using the mask.
  22.   The method for manufacturing a display device according to claim 1, wherein the gate electrode is formed using a heat-resistant conductive layer.
  23.   23. The crystalline silicon film according to claim 1, wherein the gate electrode includes tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, platinum, or phosphorus. A method for manufacturing a display device, which is formed using indium tin, zinc oxide, indium zinc oxide, zinc oxide to which gallium is added, or indium tin oxide containing silicon oxide.
  24.   24. The method for manufacturing a display device according to any one of claims 1 to 23, wherein the impurity element is an element selected from phosphorus, arsenic, antimony, and bismuth.
  25.   25. The catalyst element according to claim 1, wherein the catalyst element is one selected from tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, titanium, copper, nickel, and platinum. Alternatively, a method for manufacturing a display device including a plurality of display devices.
  26. 26. The method for manufacturing a display device according to any one of claims 1 to 25, wherein the first electrode is a pixel electrode.
  27. 27. The method for manufacturing a display device according to any one of claims 1 to 26, wherein a layer including a silicon nitride film is formed as the gate insulating film.
  28. 28. The layer having the catalytic element or the first semiconductor film is formed so as to be in contact with the silicon nitride film after forming a silicon nitride film as the gate insulating film according to any one of claims 1 to 27. And a manufacturing method of a display device.
  29. 29. The display device according to claim 1, wherein the first semiconductor film is crystallized by the heating and the catalytic element is moved to the second semiconductor film. Manufacturing method.

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