JP4781066B2 - Method for manufacturing display device - Google Patents

Description

  The present invention relates to a method for manufacturing a display device having an inverted staggered thin film transistor formed of a crystalline semiconductor film.

  In recent years, a flat panel display (FPD) typified by a liquid crystal display (LCD) or an EL display has attracted attention as a display device that replaces a conventional CRT. In particular, the development of large-screen liquid crystal televisions equipped with large liquid crystal panels driven by an active matrix has become an important issue for LCD panel manufacturers to focus on. In recent years, a large screen EL television has been developed following the liquid crystal television.

In a display device having a conventional light emitting element, a thin film transistor (hereinafter referred to as TFT) using amorphous silicon is used as a semiconductor element for driving each pixel (Patent Document 1).
JP-A-5-35207

  However, when a TFT using an amorphous semiconductor film is DC-driven, the threshold value tends to shift, and the TFT characteristics tend to vary accordingly. For this reason, luminance unevenness occurs in a display device in which a TFT using an amorphous semiconductor film is used for pixel switching. Such a phenomenon becomes more conspicuous as the screen TV has a diagonal size of 30 inches or more (typically 40 inches or more), and the deterioration of image quality is a serious problem.

  Also, in the process of forming an inverted staggered TFT using a conventional photolithography process, a resist is applied on a film formed on the entire surface of the substrate by CVD, PVD, or the like, exposed and developed, and wiring or A semiconductor region was formed. However, in this case, most of the materials such as films and resists formed on the entire surface of the substrate by the CVD method, the PVD method, and the like are wasted, and the number of steps for forming wirings and semiconductor regions is large, and the throughput is increased. There is a problem that decreases.

  In addition, it is difficult for an exposure apparatus used in the photolithography process to perform exposure processing on a large area substrate at a time. For this reason, in a method for manufacturing a display device using a large-area substrate, a plurality of exposure times are required. For this reason, there is a problem that inconsistency between adjacent patterns occurs, and the yield decreases. This problem is remarkable for a large display device represented by a large television.

  The present invention has been made in view of such circumstances, and provides a method for manufacturing a display device having an inverted staggered TFT that is unlikely to cause a threshold shift and that can operate at high speed. Furthermore, a manufacturing method of a display device which can reduce cost with a small amount of raw materials and has a high yield is provided.

  The present invention includes an amorphous semiconductor film, a layer having a catalytic element that promotes crystallization of the amorphous semiconductor film, and a donor-type element or a rare gas element after the gate electrode is formed using a material having high heat resistance. A layer is formed and heated to crystallize the amorphous semiconductor film and remove the catalytic element from the crystalline semiconductor film, and then form a semiconductor region using a part of the crystalline semiconductor film. The gist is to form an inverted staggered TFT by forming a source electrode and a drain electrode that are in electrical contact with each other and forming a gate wiring connected to the gate electrode.

  The present invention includes forming a gate electrode on an insulating surface, forming a gate insulating film on the gate electrode, forming a layer having a catalytic element on the gate insulating film, and forming a layer on the layer having the catalytic element. 1 semiconductor region is formed, a second semiconductor region having an impurity element is formed on the first semiconductor region, and then heated, and the first conductive layer in contact with the heated second semiconductor region is liquid-treated. Formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region are etched to form a source electrode and a drain electrode, and a source region and a drain region, and the gate insulating film and the An insulating film is formed on the source electrode and the drain electrode, a part of the insulating film and the gate insulating film is etched to expose a part of the gate electrode, and then a gate wiring connected to the gate electrode is liquid-treated. A first electrode connected to the source electrode or drain electrode is formed after etching a part of the insulating film to expose a part of the source electrode or drain electrode. A method for manufacturing a display device in which a layer containing a light-emitting substance and a second electrode are formed over the electrode.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor region is formed on the gate insulating film, and the first semiconductor region is formed on the gate insulating film. Forming a layer having a catalytic element on the first conductive layer, forming a second semiconductor region having an impurity element on the layer having the catalytic element, and then heating the first conductive layer in contact with the heated second semiconductor region Is formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region, and the gate insulating film And forming an insulating film on the source electrode and the drain electrode, etching a part of the insulating film and the gate insulating film to expose a part of the gate electrode, and then connecting to the gate electrode Forming a first electrode connected to the source electrode or drain electrode after etching a part of the insulating film to expose a part of the source electrode or drain electrode; A method for manufacturing a display device in which a layer containing a light-emitting substance and a second electrode are formed over a first electrode.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region, forming a protective layer over the gate electrode, the layer having the catalytic element, and a region where the first semiconductor region overlaps, and the first semiconductor region and the protective layer A second semiconductor region having an impurity element is formed thereon and then heated, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and Etching a part of the second semiconductor region to form a source electrode and a drain electrode, and a source region and a drain region, forming an insulating film on the gate insulating film and the source electrode and the drain electrode, Insulation film And etching a part of the gate insulating film to expose a part of the gate electrode, then forming a gate wiring connected to the gate electrode by a droplet discharge method, and etching a part of the insulating film. A first electrode connected to the source electrode or drain electrode is formed, a layer containing a light-emitting substance is formed on the first electrode, and a second electrode Is a method for manufacturing a display device.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor region is formed on the gate insulating film, and the first semiconductor region is formed on the gate insulating film. A layer having a catalytic element is formed on the gate electrode, the first semiconductor region, and a region where the layer having the catalytic element overlaps, and the protective layer and the layer having the catalytic element are formed on the protective layer. A second semiconductor region having an impurity element is formed and then heated, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and the first conductive layer are formed. A portion of the semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region, an insulating film is formed on the gate insulating film and the source electrode and the drain electrode, and the insulating film as well as After etching a part of the gate insulating film to expose a part of the gate electrode, a gate wiring connected to the gate electrode is formed by a droplet discharge method, and a part of the insulating film is etched. After exposing a part of the source electrode or the drain electrode, a first electrode connected to the source electrode or the drain electrode is formed, a layer containing a light emitting material is formed on the first electrode, and a second electrode is formed This is a method for manufacturing a display device to be formed.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a second semiconductor region having an impurity element is formed on the first semiconductor region, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region An electrode is formed by a droplet discharge method, an insulating film is formed on the gate insulating film, the gate wiring, the source electrode, and the drain electrode, and a part of the insulating film is etched to form the gate. After exposing a part of the gate wiring, a conductive layer connected to the gate wiring is formed by a droplet discharge method, and after etching a part of the insulating film to expose a part of the source electrode or drain electrode , A method for manufacturing a display device, in which a first electrode in contact with the source electrode or the drain electrode is formed, and a layer containing a light-emitting substance and a second electrode are formed over the first electrode.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a second semiconductor region having an impurity element is formed on the layer having the catalytic element, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region An electrode is formed by a droplet discharge method, an insulating film is formed on the gate insulating film, the gate wiring, the source electrode, and the drain electrode, and a part of the insulating film is etched to form the gate. After exposing a part of the gate wiring, a conductive layer connected to the gate wiring is formed by a droplet discharge method, and after etching a part of the insulating film to expose a part of the source electrode or drain electrode , A method for manufacturing a display device, in which a first electrode in contact with the source electrode or the drain electrode is formed, and a layer containing a light-emitting substance and a second electrode are formed over the first electrode.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a protective layer is formed on a region where the gate electrode, the layer having the catalytic element, and the first semiconductor region overlap, and the first semiconductor region and the protective layer are formed. A second semiconductor region having an impurity element is formed and then heated; the heated second semiconductor region is etched to form a source region and a drain region; and a part of the gate insulating film is etched. Then, after exposing a part of the gate electrode, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method, and the gate is formed. An insulating film is formed on the insulating film, the gate wiring, the source electrode and the drain electrode, and a part of the insulating film is etched to expose a part of the gate wiring, and then a conductive layer connected to the gate wiring Forming a first electrode in contact with the source or drain electrode after etching a part of the insulating film to expose a part of the source or drain electrode, A method for manufacturing a display device in which a layer containing a light-emitting substance and a second electrode are formed over a first electrode.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a protective layer is formed in a region where the gate electrode, the first semiconductor region, and the layer having the catalytic element overlap, and impurities are formed on the protective layer and the layer having the catalytic element. After forming the second semiconductor region having an element, heating, etching the heated second semiconductor region to form a source region and a drain region, etching a part of the gate insulating film, After exposing a part of the gate electrode, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method, and the gate insulation is An insulating film is formed on the film, the gate wiring, the source electrode and the drain electrode, and a part of the insulating film is etched to expose a part of the gate wiring, and then a conductive layer connected to the gate wiring is formed. Forming a first electrode in contact with the source electrode or the drain electrode after etching a part of the insulating film to expose a part of the source electrode or the drain electrode; 1 is a method for manufacturing a display device in which a layer containing a light-emitting substance and a second electrode are formed over one electrode.

  Note that instead of the insulating film formed over the gate insulating film, the gate wiring, the source electrode, and the drain electrode, an insulating film that covers part of the source electrode or the drain electrode may be formed.

Alternatively, after forming the first electrode in contact with the drain electrode, a gate wiring connected to the gate electrode may be formed.
In addition, after the gate wiring connected to the gate electrode is formed, the first electrode in contact with the drain electrode may be formed.

  Further, the gate wiring is connected to three or more gate electrodes. In this case, the gate wiring is desirably formed of a low resistance material. On the other hand, the gate wiring may be connected to two gate electrodes. In this case, the material of the gate wiring is not particularly limited.

  The gate electrode is formed by forming a conductive film over an insulating surface, discharging or applying a photosensitive resin over the conductive film, irradiating a part of the photosensitive resin with laser light to form a mask, and then applying the mask. It may be formed by etching the conductive film.

  The gate electrode is formed of a heat-resistant conductive layer, and typically includes tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium (Cr), cobalt, nickel, platinum, and phosphorus. It is formed of a crystalline silicon film, indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide to which gallium is added, or indium tin oxide containing silicon oxide.

  The impurity element is an element selected from phosphorus, arsenic, antimony, and vanadium.

  The catalytic element is one or more selected from tungsten, molybdenum, zirconium, hafnium, bismuth, niobium, tantalum, chromium, cobalt, titanium, copper, nickel, and platinum.

  The first electrode functions as a pixel electrode.

  In addition, a layer including a silicon nitride film may be formed as the gate insulating film.

  In addition, after a silicon nitride film is formed as the gate insulating film, a layer having a catalytic element or the first semiconductor region may be formed in contact with the silicon nitride film.

  In the present invention, the display device refers to a device using a light emitting element, that is, an image display device. In addition, a module in which a connector such as a flexible printed circuit (FPC), a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached to a light emitting display panel, a printed wiring board at the end of a TAB tape or TCP The display device also includes a module in which an IC (integrated circuit) or a CPU is directly mounted on a light emitting element by a COG (Chip On Glass) method.

  Another embodiment of the present invention is an EL television device including the above display device.

  According to the present invention, an inverted staggered TFT formed of a crystalline semiconductor film can be formed. The inversely staggered TFT of the present invention can simultaneously perform a crystallization process of an amorphous semiconductor film and a gettering process of a catalytic element for promoting crystallization of the amorphous semiconductor film. Since the number of steps can be reduced, throughput can be improved. In addition, since the number of heat treatments can be reduced, energy saving can be achieved.

  The inverted staggered TFT of the present invention uses a material having high heat resistance for the gate electrode, and uses a low resistance material after heat treatment such as an activation process, a gettering process, and a crystallization process. Wiring such as signal lines and scanning lines is formed. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the display device including the light-emitting element of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  A TFT formed of a crystalline semiconductor film has a mobility of several tens to 50 times that of an inverted staggered TFT formed of an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a display device having a light-emitting element that requires high-speed operation can be manufactured.

  In addition, a scan line driver circuit can be formed at the same time as the TFT in the pixel region in the peripheral portion of the display device having a light emitting element. Therefore, a miniaturized display device can be manufactured.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, display unevenness can be reduced as compared with a display device having a light-emitting element using a TFT formed of an amorphous semiconductor film as a switching element.

  Furthermore, since the gettering process also getters the metal element mixed in the semiconductor film at the film formation stage, it is possible to reduce the off-current, and typically has an ON / OFF ratio of 6 digits or more. It is possible to form a TFT having By providing the switching element of a display device having such a TFT, the contrast can be improved.

    In the present invention, a thin film material or a resist may be discharged to a predetermined place using a droplet discharge method without forming a thin film on the entire surface of the substrate, and a TFT can be formed without using a photomask. Can do. For this reason, it is possible to improve throughput and yield and to reduce costs.

  Furthermore, a television set including a display device including a light-emitting element formed by the above manufacturing process (referred to as an EL (electroluminescence) television set) can be improved in throughput and yield at low cost. Can be produced.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment, a manufacturing process of an active matrix substrate having an inverted staggered TFT having a crystalline semiconductor film as an element for driving a light emitting element will be described with reference to FIGS. 1 to 3, 16, and 31. . In this embodiment, a light emitting element having a switching TFT and a driving TFT is shown as a representative example as an element for driving the light emitting element. FIG. 3 is a top view of a light emitting element having an element for driving the light emitting element, and FIGS. 1 and 2 are cross-sectional views showing a connection portion between a gate electrode of a switching TFT and a scanning line, a driving TFT, and the light emitting element FIG.

  As shown in FIG. 1A, a first conductive layer 102 is formed over a substrate 101, photosensitive materials 103 and 104 are applied or discharged over the first conductive layer, and then dried and fired. Next, the photosensitive materials 103 and 104 are irradiated with laser beams (hereinafter also referred to as laser beam) 105 and 106 to form first masks 111 and 112 as shown in FIG.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a silicon wafer, a metal plate, or the like can be used. Further, as the substrate 101, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm can be used.

  The first conductive layer 102 is formed in a predetermined region by a droplet discharge method having a thickness of 500 to 1000 nm, a printing method, an electroless plating method, or the like. Alternatively, it may be formed on the entire surface of the substrate by a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), a vapor deposition method, or the like. Note that here, by using a droplet discharge method or a printing method, a predetermined region is formed, so that there are few regions to be removed in a later etching step, so that raw materials can be reduced.

  The first conductive layer 102 is preferably formed using a high melting point material. By using the high melting point material, a heating process such as a subsequent crystallization process, gettering process, activation process or the like can be performed. High melting point materials include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni), titanium (Ti), platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, from the substrate surface side, a tantalum nitride film and a tungsten film formed thereon, a tantalum nitride film, molybdenum formed thereon, a titanium nitride film, a tungsten film formed thereon, and a titanium nitride film And it is good also as laminated structure, such as a molybdenum film | membrane formed on it. In addition, a silicon film containing phosphorus (including an amorphous semiconductor film and a crystalline semiconductor film), indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide added with gallium, or indium tin oxide containing silicon oxide is used. It can also be used.

  As the material of the photosensitive materials 103 and 104, a negative photosensitive material or a positive photosensitive material that is sensitive from ultraviolet light to infrared light is used. As a representative example of the photosensitive material, a resin material exhibiting photosensitivity such as an epoxy resin, a cryl resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, organic materials exhibiting photosensitivity such as benzocyclobutene, parylene, flare, and polyimide can be used. Moreover, as a typical positive type photosensitive resin, there can be mentioned a novolak resin and a photosensitive resin having a naphthoquinonediazide compound as a photosensitive agent, and as a negative type photosensitive resin, a base resin, diphenylsilanediol, an acid generator and the like can be mentioned. The photosensitive resin which has. Here, a negative photosensitive material is used.

  Next, the photosensitive materials 103 and 104 are irradiated with laser beams 105 and 106 using a laser beam direct drawing apparatus.

  A laser beam direct writing apparatus will be described with reference to FIG. As shown in FIG. 31, a laser beam direct drawing apparatus 1001 includes a personal computer (hereinafter referred to as PC) 1002 that executes various controls when irradiating a laser beam, a laser oscillator 1003 that outputs a laser beam, A power source 1004 of the laser oscillator 1003, an optical system (ND filter) 1005 for attenuating the laser beam, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser beam, An optical system 1007 composed of a lens for reducing, a mirror for changing an optical path, a substrate moving mechanism 1009 having an X stage and a Y stage, and D for digital-analog conversion of control data output from the PC / A converter 1010 and the sound according to the analog voltage output from the D / A converter A driver 1011 for controlling the optical modulator 1006, and a driver 1012 for outputting a driving signal for driving the substrate moving mechanism 1009.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. As the laser oscillator, excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He-Cd, Ar, He-Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the first to fifth harmonics of the fundamental wave.

  Next, a method for exposing a photosensitive material using a laser beam direct drawing apparatus will be described. When the substrate 1008 is mounted on the substrate moving mechanism 1009, the PC 1002 detects the position of the marker attached to the substrate by a camera (not shown). Next, the PC 1002 generates movement data for moving the substrate movement mechanism 1009 based on the detected marker position data and drawing pattern data input in advance. Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, whereby the laser beam output from the laser oscillator 1003 is attenuated by the optical system 1005, and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser beam output from the acousto-optic modulator 1006 is changed in optical path and beam shape by the optical system 1007, condensed by the lens, and then irradiated to the photosensitive material applied on the substrate. Photosensitive material is exposed. At this time, according to the movement data generated by the PC 1002, the movement of the substrate moving mechanism 1009 is controlled in the X direction and the Y direction. As a result, the laser beam is irradiated to a predetermined place, and the photosensitive material is exposed.

  As a result, as shown in FIG. 1B, first masks 111 and 112 are formed in the region irradiated with the laser beam. Here, since the negative type is used as the photosensitive material, the region irradiated with the laser beam serves as a resist mask. A part of the energy of the laser beam is converted into heat by the resist and reacts a part of the resist, so that the width of the resist mask is slightly larger than the width of the laser beam. In addition, the shorter the laser beam, the shorter the beam diameter can be focused. Therefore, it is preferable to irradiate the laser beam with a short wavelength in order to form a resist mask with a fine width.

  Further, the spot shape of the laser beam on the surface of the photosensitive material is processed by an optical system so as to be a dot shape, a circle shape, an ellipse shape, a rectangle shape, or a line shape (strictly, an elongated rectangle shape). Note that the spot shape may be circular, but a linear resist mask having a uniform width can be formed.

  The apparatus shown in FIG. 31 shows an example in which exposure is performed by irradiating a laser beam from the front side of the substrate. However, the optical system and the substrate moving mechanism are appropriately changed, and the laser beam is irradiated from the back side of the substrate. It is also possible to use a laser beam direct writing apparatus for exposure.

  Note that here, the laser beam is selectively irradiated by moving the substrate; however, the present invention is not limited to this, and the laser beam can be irradiated by scanning the laser beam in the X and Y axis directions. In this case, it is preferable to use a polygon mirror or a galvanometer mirror for the optical system 1007.

  Next, as illustrated in FIG. 1C, the first conductive layer 102 is etched using the first mask to form second conductive layers 121a and 122a. The second conductive layer 121a functions as a gate electrode, and the second conductive layer 122a is a region connected to a gate wiring in the gate electrode (hereinafter referred to as a gate electrode connection portion). Note that in FIG. 1C, the second conductive layers 121a and 122a are displayed in a separated state, but actually, in the same connected region as shown in FIG. is there.

  Next, after removing the first mask, a first insulating film is formed. Here, an insulating film 123a having a thickness of 50 to 100 nm, an insulating film 123b having a thickness of 50 to 100 nm, and an insulating film 123c having a thickness of 0.3 to 5 nm are stacked as the first insulating film. After that, a layer 125 having a catalytic element is formed over the first insulating film.

  The first insulating films 123a, 123b, and 123c function as gate insulating films. As the first insulating films 123a and 123b, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like is used as appropriate. Can do. Furthermore, the second conductive layers 121a and 122a may be anodized to form an anodized film instead of the first insulating films 123a and 123b. Note that silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like is preferably used as the first insulating film 123a in contact with the substrate side in order to prevent diffusion of impurities and the like from the substrate side. . In addition, in order to reduce the influence of device characteristics due to insulation and defects in the film, the first insulating film 123b is formed using silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like. It is desirable to do. However, the structure is not limited, and any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like is used as appropriate. A laminated structure may be combined. Note that the silicon oxide (SiOx) film contains hydrogen.

  As the first insulating film 123c in contact with the semiconductor film, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.3 nm to 5 nm is preferably formed. In this embodiment mode, a metal element that promotes crystallization (nickel is used in this embodiment mode) is added to the semiconductor film, and then gettering treatment is performed for removal. Although the interface state between the silicon oxide film and the silicon film is good, the metal element in the silicon film reacts with oxygen in the silicon oxide at the interface to react with the metal oxide (in this embodiment, nickel oxide (NiOx)). In some cases, the metal element is difficult to getter. Further, the silicon nitride film may adversely affect the interface state with the semiconductor film due to the stress of the silicon nitride film and the influence of traps. Therefore, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.1 nm to 10 nm, preferably 1 to 3 nm, is formed as the uppermost layer of the insulating layer in contact with the semiconductor film.

  In this embodiment, after a silicon nitride oxide film is stacked as the insulating film 123a and the silicon oxynitride film is stacked as the first insulating film 123b over the substrate 101 and the second conductive layer films 121a and 122a, silicon oxynitride is stacked. Over the film, a silicon nitride oxide film with a thickness of 0.1 nm to 10 nm, preferably 1 to 3 nm, is formed as the first insulating film 123c to have a three-layer structure. With such a structure, the gettering efficiency of the metal element in the semiconductor film is increased, and the adverse effect of the silicon nitride film on the semiconductor film can be reduced. The insulating layers to be stacked are preferably formed continuously at the same temperature without breaking the vacuum in the same chamber while switching the reaction gas. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

  As a method for forming the layer 125 having a catalytic element, a method of forming a thin film of a catalytic element or a silicide of a catalytic element on the surface of the first insulating film by a PVD method, a CVD method, a vapor deposition method, or the like, There is a method of applying a solution containing a catalytic element on the surface. As catalyst elements, tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of nickel (Ni), platinum (Pt), and the like. Further, the surface of the semiconductor film may be subjected to plasma treatment using an electrode formed of the above catalytic element. Here, a solution containing 1 to 200 ppm and 10 to 150 ppm of nickel is applied. Here, the catalytic element is an element that promotes or promotes crystallization of the semiconductor film.

  Next, as illustrated in FIG. 1D, a first semiconductor film 124 with a thickness of 50 to 250 nm is formed over the first insulating film, and the film thickness includes a donor-type element over the first semiconductor film. A second semiconductor film 132 having a thickness of 80 to 250 nm is formed.

  As the first semiconductor film 124, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm are formed in the amorphous semiconductor. A film having any state selected from a microcrystalline semiconductor and a crystalline semiconductor that can be observed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor film can be used for the film thickness mainly composed of silicon, silicon germanium (SiGe), or the like.

Note that in order to obtain a semiconductor film having a high-quality crystal structure by subsequent crystallization, the impurity concentration of oxygen, nitrogen, or the like contained in the first semiconductor film 124 is set to 5 × 10 ¹⁸ / cm ³ (hereinafter referred to as “the semiconductor film”). All concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

The second semiconductor film 132 is formed by a plasma CVD method in which a gas containing a donor element such as phosphorus or arsenic is added to a silicide gas. By forming the second semiconductor film by such a method, an interface between the first semiconductor film and the second semiconductor film is formed. In addition, the second semiconductor film 132 containing a donor-type element is formed by forming a semiconductor film similar to the first semiconductor film and then adding the donor-type element by an ion doping method or an ion implantation method. Can do. At this time, the second semiconductor film 132 preferably has a phosphorus concentration of 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ .

Further, a low concentration region (hereinafter referred to as an n ⁻ region) is formed on the side in contact with the first semiconductor film 124 using the plasma CVD method, ion doping method, or ion implantation method, and a high concentration is formed thereon. A stacked structure of regions (hereinafter referred to as n ⁺ regions) may be employed. At this time, n ^- concentration of donor element ^{region, 1 × 10 17 ~3 × 10} 19 / cm 3, preferably between ^{1 × 10 18 ~1 × 10 19} / cm 3, donor element in the n ⁺ region The concentration of is 10 to 100 times that of the donor element in the n ⁻ region. The film thickness of the n ⁻ region is 50 to 200 nm, and the film thickness of the n ⁺ region is 30 to 100 nm, preferably 40 to 60 nm. Here, as the second semiconductor film 132, a region closer to the first crystalline semiconductor film 131 than the wavy line is an n ⁻ region, and an n ⁺ region is shown on the surface thereof.

FIG. 16 shows an impurity profile of the second semiconductor film containing the donor element at this time. FIG. 16A shows a donor-type element profile 150a when the second semiconductor film 132a containing a donor-type element is formed over the first semiconductor film 124 by a plasma CVD method. Note that in the second semiconductor film 132a, a donor-type element having a constant concentration (first concentration) is distributed in the depth direction of the film from the surface to the interface between the n ⁺ region 144a and the n ⁻ region 144b. ing. In addition, a donor-type element having a constant concentration (second concentration) is distributed from the interface between the n ⁺ region 144a and the n ⁻ region 144b to the interface with the first semiconductor film 124 in the depth direction of the film. ing. At this time, the first concentration is higher than the second concentration.

On the other hand, in FIG. 16B, a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed over the first semiconductor film 124. A donor-type element profile 150b is shown when a second semiconductor film 132b is formed by adding a donor-type element to the semiconductor film by ion doping or ion implantation. As shown in FIG. 16B, the donor-type element concentration is relatively high near the surface of the second semiconductor film. This region is denoted as n ⁺ region 144a. On the other hand, as the first semiconductor film 124 is approached, the donor-type element concentration is relatively decreased. A region having a donor-type element concentration of 1 × 10 ^{17 to} 3 × 10 ¹⁹ / cm ³ , preferably a region of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ is referred to as an n ⁻ region 144b. The concentration of the donor-type element in the n ⁺ region 144a is 10 to 100 times that of the donor-type element in the n ⁻ region.

The n ⁺ region 144a later functions as a source region and a drain region, and the n ⁻ region 144b functions as an LDD region. Note that there is no interface between the n ⁺ region and the n ⁻ region, and the interface varies depending on the relative donor concentration. As described above, the second semiconductor film containing the donor-type element formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the n ⁺ region and n ⁻ region films The thickness can be appropriately controlled.

  Note that the second semiconductor film 132 containing a donor-type element is added with a rare gas element, typically argon, so that distortion of the crystal lattice is formed. It is possible to getter elements.

Note that after formation of the first semiconductor film 124, a region that becomes a channel region of the TFT is a group 3 element (group 13 element, hereinafter referred to as an acceptor element) or a group 5 element (group 15 element, hereinafter referred to as a donor). The channel doping step of adding a low-concentration element) may be performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used.

Next, the first semiconductor film and the second semiconductor film are heated to form a first crystalline semiconductor film 141 as shown in FIG. In this case, silicide is formed in the portion of the semiconductor film in contact with the metal element that promotes crystallization, and the crystallization proceeds using the silicide as a nucleus. As shown by the arrow in FIG. The catalytic element obtained by crystallizing the film is moved to the second semiconductor film 132 to perform gettering of the catalytic element. By this step, the concentration of the catalytic element can be reduced to such an extent that the device characteristics are not affected. That is, the first crystalline semiconductor film 141 having a nickel concentration of 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less can be formed. In addition, since the second semiconductor film to which the catalytic element after gettering has moved is also crystallized in the same manner, it is referred to as a second crystalline semiconductor film 142. In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Here, after the heat treatment for dehydrogenation (400 to 550 ° C., 0.5 to 2 hours), the heat treatment for crystallization (550 to 650 ° C. for 1 to 24 hours) is performed. Further, crystallization may be performed by RTA or GRTA. Here, by performing crystallization without laser light irradiation, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed. In addition, since a ridge (convex concave portion) that grows on the protrusion on the crystal surface is difficult to form, the surface of the semiconductor region is relatively flat, and leakage current flowing between the gate insulating film and the gate electrode is suppressed. It is possible.

  Next, as illustrated in FIG. 1F, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second crystalline semiconductor film 142 are formed using the second mask. One crystalline semiconductor film 141 is etched to form a first semiconductor region 152 and a second semiconductor region 151 as shown in FIG.

  The second mask 143 forms an organic resin in a predetermined region by a droplet discharge method, a printing method, or the like. Further, as in the first mask, after the photosensitive material is applied or discharged, the photosensitive material is irradiated with a laser beam, exposed, and then developed. By forming the second mask by this method, it is possible to reduce the area of a semiconductor region to be formed later, and to increase the integration of semiconductor elements and increase the aperture ratio of a transmissive liquid crystal display device. It is.

  In the mask formation process of the following embodiments and examples, before applying a photosensitive material on a film or region formed of a semiconductor material, a film thickness of about several nanometers is formed on the surface of the semiconductor film or region. It is preferable to form an insulating film. This step can avoid direct contact between the semiconductor material and the photosensitive material, and can prevent impurities from entering the semiconductor film. Note that examples of a method for forming the insulating film include a method of applying an oxidizing solution such as ozone water, a method of irradiating oxygen plasma, ozone plasma, and the like.

The second crystalline semiconductor film and the first crystalline semiconductor film are made of chlorine gas such as Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , CF ₄ , SF ₆ , NF ₃ , CHF _3, etc. Etching can be performed using a representative fluorine-based gas or O ₂ . The second crystalline semiconductor film is etched to form a first semiconductor region 152, and the second crystalline semiconductor film is etched to form a second semiconductor region 151.

  Next, after removing the second mask, a third conductive layer 153 having a thickness of 500 to 1500 nm, preferably 500 to 1000 nm is formed. Next, a photosensitive material 154 is applied or discharged onto the third conductive layer, and the photosensitive material 154 is irradiated with the laser beam 155 by using a laser beam direct drawing apparatus. A third mask 161 as shown in B) is formed. Here, a positive photosensitive material is used as the photosensitive material 154.

  As a material for the third conductive layer 153, a material obtained by dissolving or dispersing a conductor in a solvent is used. As the conductor, Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba or other metals, or halogen Fine particles such as silver halide, or dispersible nanoparticles can be used. Furthermore, you may have multiple types of the said metal fine particles or dispersion | distribution nanoparticle. In addition, a third conductive layer can be formed by stacking conductive layers formed of these materials. The third conductive layer functions as a wiring. In order to reduce the wiring resistance, it is preferable to use a low resistance material.

  In addition, it is preferable to use what dissolved or disperse | distributed the material of either gold | metal | money, silver, and copper in the solvent considering the specific resistance value as the composition discharged from a discharge outlet. More preferably, low resistance and inexpensive silver or copper may be used. However, when copper is used, a barrier film may be provided as a countermeasure against impurities. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone may be used.

  Here, as a barrier film in the case of using copper as a wiring, an insulating or conductive material containing nitrogen such as silicon nitride, silicon oxynitride, aluminum nitride, titanium nitride, or tantalum nitride (TaN) is used. These may be formed by a droplet discharge method.

  The viscosity of the composition used for the droplet discharge method is preferably 5 to 20 mPa · s, which is to prevent the drying from occurring and to smoothly discharge the composition from the discharge port. . The surface tension is preferably 40 m / N or less. Note that the viscosity of the composition may be appropriately adjusted according to the solvent to be used and the application. The viscosity of the composition in which silver is dissolved or dispersed in the solvent is 5 to 20 mPa · s, and the viscosity of the composition in which gold is dissolved or dispersed in the solvent is 10 to 20 mPa · s.

  The step of discharging the composition may be performed under reduced pressure. This is because the solvent of the composition volatilizes before the composition is discharged and landed on the object to be processed, and the subsequent drying and firing steps can be omitted or shortened. After discharging the solution, one or both of drying and baking steps are performed by laser light irradiation, rapid thermal annealing, a heating furnace, or the like under normal pressure or reduced pressure depending on the material of the solution. The drying and firing steps are both heat treatment steps. For example, the drying is performed at 100 degrees for 3 minutes, and the firing is performed at 200 to 350 degrees for 15 minutes to 120 minutes. Time is different. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is 100 to 800 degrees (preferably 200 to 350 degrees). And By this step, the solvent in the solution is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and shrunk to accelerate fusion and fusion. The atmosphere is an oxygen atmosphere, a nitrogen atmosphere or air. However, it is preferable to perform in an oxygen atmosphere in which the solvent in which the metal element is decomposed or dispersed is easily removed.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG or YVO ₄ doped with Cr, Nd, or the like. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. In addition, a so-called hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that emits ultraviolet light or infrared light in an inert gas atmosphere to rapidly increase the temperature from several microseconds to several minutes. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, there is an advantage that only the outermost thin film can be heated substantially without affecting the lower layer film.

    Here, a composition containing Ag (hereinafter referred to as “Ag paste”) is selectively ejected, and drying and firing by laser beam irradiation or heat treatment as described above are performed as appropriate to form a third film having a thickness of 600 to 800 nm. A conductive layer is formed. At this time, the conductive layer is formed by irregularly overlapping fine particles, which are conductors, three-dimensionally. That is, it is composed of three-dimensional aggregate particles. For this reason, the surface has fine unevenness. Further, since the fine particles are fired by the heat of the light absorption layer and the heating time, and the particle size of the particles increases, the layer has a large difference in surface height.

Incidentally, the sintering is performed in an O ₂ atmosphere, organic substances such as binders contained in the Ag paste (thermosetting resin) is decomposed, it is possible to obtain a Ag film containing little organic matter. Further, the film surface can be smoothed using a press machine or the like.

  In the conductive film forming process of the embodiment and examples below, when an insulating film is formed on the surface of the semiconductor film during the photosensitive resin coating or discharging process, the conductive film is formed before the conductive film is formed in order to reduce the contact resistance. It is preferable to etch the insulating film.

  Next, the third conductive layer is etched into a desired shape using the third mask 161, so that the fourth conductive layers 162 and 163 and the fourth conductive layer shown in FIGS. 167 and 169 are formed. The fourth conductive layer 162 functions as a power supply line and a capacitor wiring, and the fourth conductive layer 163 functions as a source electrode or a drain electrode of the driving TFT. In addition, the fourth conductive layer 167 illustrated in FIG. 3C functions as a signal line, and the fourth conductive layer 169 functions as a switching source electrode or a drain electrode. At this time, the third conductive layer is divided to form each wiring and each electrode electrode, and etching is performed so that the width of the source wiring or the drain wiring is narrowed. It is possible to increase the aperture ratio.

    Next, the exposed portion of the first semiconductor region 152 is etched using the third mask 161 to form third semiconductor regions 164 and 165 that function as a source region and a drain region. At this time, part of the second semiconductor region 151 may be over-etched. The over-etched second semiconductor region at this time is referred to as a fourth semiconductor region 166. The fourth semiconductor region 166 functions as a channel formation region of the driving TFT. On the other hand, a fourth semiconductor region 168 that functions as a channel formation region of the switching TFT is also formed by the same process.

  Next, after removing the third mask, as shown in FIG. 2C, a film thickness of 100 to 100 which functions as a passivation film is formed on the surfaces of the fourth conductive layers 162 and 163 and the fourth semiconductor region 166. A second insulating film 171 with a thickness of 300 nm is preferably formed. The passivation film is formed using a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used. Note that the passivation film may be a single layer or a laminated structure. Here, silicon oxide or silicon oxynitride is preferably formed from the interface characteristics of the fourth semiconductor region 166, and a silicon nitride film or a silicon nitride oxide film is preferably formed thereover.

  Thereafter, the fourth semiconductor region is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case of heating in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed as the second insulating film.

  Through the above steps, an inverted staggered TFT having a crystalline semiconductor film can be formed.

  Next, a third insulating film 172 having a thickness of 500 to 1500 nm is formed over the second insulating film 171. As the third insulating film, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide (polyimide) Si—O— among compounds consisting of silicon, oxygen, and hydrogen formed from a heat-resistant polymer such as aromatic polyamide, polybenzimidazole, or a siloxane polymer-based material typified by silica glass. Inorganic siloxane polymers containing Si bonds, alkyl siloxane polymers, alkyl silsesquioxane polymers, hydrogenated silsesquioxane polymers, hydrogenated alkyl silsesquioxane polymers such as hydrogen on silicon such as methyl and phenyl Organosiloxane polymer based insulating material which is substituted by an organic group can be used. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the fourth insulating layer can be planarized by the application method. Here, the fourth insulating film is formed by applying and baking an acrylic resin by a coating method.

  Note that in the case where the second insulating film 171 has a film thickness such that parasitic capacitance is not generated between the sixth conductive layer 175 and the fourth conductive layers 162a and 163 to be formed later, the third insulating film 171 The film 172 is not necessarily required.

    Next, after a fourth mask (not shown) is formed over the third insulating film 172, the third insulating film 172 and a part of the second insulating film 171 are etched to form the switching TFT. The second conductive layer 122a that functions as a gate electrode is exposed. Next, after removing the fourth mask, a fifth conductive layer 173 having a thickness of 500 to 1500 nm, preferably 500 to 1000 nm is formed. The fifth conductive layer 173 functions as a scan line.

  For the fourth mask, a method and a material similar to those of the second mask 143 can be used as appropriate. As a material and a formation method of the fifth conductive layer 173, a material and a formation method similar to those of the third conductive layer 153 may be selected as appropriate. In order to suppress wiring resistance, it is preferable to use a low resistance material. Alternatively, the line width may be reduced by etching the fifth conductive layer 173 with a mask formed using a laser beam direct writing apparatus like the first conductive layer. Through this step, the wiring area in the pixel can be reduced, and the aperture ratio can be improved in the transmissive display device. Here, the fifth conductive layer is formed by discharging an Ag paste and drying and baking it.

    Through the above steps, as shown in FIGS. 3A and 3C, the second conductive layer 121, the first insulating film 123 functioning as a gate insulating film, and the fourth function functioning as a channel formation region are formed. The semiconductor region 166 includes third semiconductor regions 164 and 165 that function as a source region or a drain region, a fourth conductive layer 162 that functions as a power supply line, and a fourth conductive layer 163 that functions as a source electrode or a drain electrode. A driving TFT 191 can be formed.

  In addition, as shown in FIGS. 3B and 3C, the second conductive layer 122a, the first insulating film 123 functioning as a gate insulating film, and the fourth semiconductor region 168 functioning as a channel formation region. , A switching TFT 192 including third semiconductor regions 164 and 165 functioning as a source region or a drain region, a fourth conductive layer 167 functioning as a signal line, and a fourth conductive layer 169 functioning as a source electrode or a drain electrode Form.

  Note that the fourth conductive layer 169 functioning as a source electrode or a drain electrode of the switching TFT 192 is connected to the second conductive layer 121 functioning as a gate electrode of the driving TFT 191. Further, 122a functioning as a gate electrode of the switching TFT 192 is connected to a fifth conductive layer 173 functioning as a scanning line.

Next, a fourth insulating film 174 is formed over the fifth conductive layer 173 and the third insulating film 172. As the fourth insulating film 174, a material similar to that of the third insulating film 172 can be used as appropriate.

  Next, after a fifth mask (not shown) is formed over the fourth insulating film 174, the fourth insulating film 174, the third insulating film 172, and a part of the second insulating film 171 are etched. Then, a part of the fourth conductive layer 163 is exposed. Next, after removing the fifth mask, a sixth conductive layer 175 having a thickness of 100 to 200 nm which functions as a pixel electrode is formed. As the fifth mask, a method and a material similar to those of the second mask 143 can be used as appropriate.

  As a method for forming the sixth conductive layer 175, a droplet discharge method, a sputtering method, a vapor deposition method, a CVD method, a coating method, or the like is appropriately used. By using a droplet discharge method, the sixth conductive layer can be selectively formed. Further, when a sputtering method, a vapor deposition method, a CVD method, a coating method, or the like is used, after forming a mask in the same manner as the second conductive layer, the conductive film is etched using the mask to form a sixth conductive layer. Form.

  Note that although a conductive layer functioning as a scan line is formed as the fifth conductive layer 173 and a conductive layer functioning as the first pixel electrode is formed as the sixth conductive layer 175 here, the invention is not limited to this. . After the conductive layer functioning as the pixel electrode is formed, the conductive layer functioning as the scanning line may be formed.

  Through the above steps, an active matrix substrate can be formed.

  Next, as illustrated in FIG. 2D, a fifth insulating film 181 is formed over the sixth conductive layer 175 and the fourth insulating film 174. The fifth insulating film 181 functions as a partition layer (also referred to as a bank or a bank) surrounding the end portion of the sixth conductive layer 175. The fifth insulating film 181 is made of an organic material, but may be either photosensitive or non-photosensitive. However, when a photosensitive material is used, the side wall has a shape in which the radius of curvature continuously changes, and a layer containing a light-emitting substance to be formed later can be formed without being cut off. In particular, when a negative photosensitive material is used, a curved surface having a first radius of curvature at the upper end portion of the fifth insulating film 181 and a curved surface having a second radius of curvature at the lower end portion of the fifth insulating film 181. Is provided. The first and second curvature radii are preferably 0.2 to 3 μm, and the angle of the fifth insulating film 181 is preferably 35 degrees or more. When a positive photosensitive material is used, a curved surface having a radius of curvature is provided only at the upper end portion of the fifth insulating film 181. The cross-sectional structure shown in the figure shows a case where a negative photosensitive material is used.

  Next, a layer 182 containing a light-emitting substance and a seventh conductive layer 183 are formed over the sixth conductive layer 175 and the fifth insulating film 181. The seventh conductive layer 183 functions as a second pixel electrode. The materials of the sixth conductive layer 175 functioning as the first pixel electrode and the seventh conductive layer 183 functioning as the second pixel electrode need to be selected in consideration of the work function. However, each of the first pixel electrode and the second pixel electrode can be an anode or a cathode depending on the pixel configuration. When the polarity of the driving TFT is a p-channel type, the first pixel electrode may be an anode and the second pixel electrode may be a cathode. In the case where the polarity of the driving TFT is an n-channel type, it is preferable that the first pixel electrode be a cathode and the second pixel electrode be an anode.

As an anode material, it is preferable to use a conductive material having a large work function. If the anode side is the light extraction direction, a transparent conductive material (indium tin oxide (hereinafter “ITO”), indium tin oxide containing silicon oxide, zinc oxide (ZnO), tin oxide (SnO ₂ )) , Indium zinc oxide (IZO), zinc oxide added with gallium (GZO), etc. Further, if the anode side is made light-shielding, TiN, ZrN, Ti, W, Ni, Pt, Cr, In addition to a single layer film of Al or the like, a laminated structure of titanium nitride and a film containing aluminum as a main component, a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film can be used. Or the method of laminating | stacking the transparent conductive material mentioned above on the film | membrane which has said light-shielding property may be sufficient.

    Moreover, it is preferable to use a conductive material having a small work function as the material of the cathode. Specifically, alkaline metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and these are used. In addition to alloys including Mg (Ag, Al: Li, etc.), rare earth metals such as Yb and Er can also be used. Further, a metal material such as Au (gold), Cu (copper), W (tungsten), Al (aluminum), Ti (titanium), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal material. It is also possible to use a metal material containing nitrogen, or titanium nitride (TiN), tantalum nitride (TaN), or aluminum containing 1 to 20% nickel which is a nitride of the metal.

When the cathode side is the light extraction direction, an ultrathin film containing an alkali metal such as Li or Cs and an alkaline earth metal such as Mg, Ca, or Sr, a transparent conductive film (transparent conductive material (indium tin Oxide (ITO), indium tin oxide containing silicon oxide (ITO), zinc oxide (ZnO), tin oxide (SnO ₂ ), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), etc.) and Alternatively, an electron injection layer in which an alkali metal or an alkaline earth metal and an electron transport material are co-evaporated may be formed, and a transparent conductive film may be stacked thereon.

  Note that ITO containing silicon oxide, which can be used as the sixth conductive layer 175 or the seventh conductive layer 183, is a material that is difficult to crystallize by energization or heat treatment and has high surface flatness.

  Here, since the n-channel TFT is used as the driving TFT, the sixth conductive layer 175 is formed with a stacked structure of a lower layer made of tantalum nitride (TaN) and an upper layer made of ITO containing silicon oxide. . The seventh conductive layer 183 is formed using ITO containing silicon oxide.

  Here, since an n-channel TFT is used as the driving TFT, the layer 182 containing a light-emitting substance has an EIL (electron injection layer) ETL (electron transport layer) sequentially from the sixth conductive layer 175 (cathode) side. ), EML (light emitting layer), HTL (hole transport layer), and HIL (hole injection layer). Note that the layer containing a light-emitting substance can have a single-layer structure or a mixed structure in addition to a stacked structure.

In addition, in order to protect the light-emitting element from damage due to moisture or degassing, it is preferable to provide a protective film 185 that covers the seventh conductive layer 183. As the protective film 185, a dense inorganic insulating film (SiN, SiNO film, etc.) by a PCVD method, a dense inorganic insulating film (SiN, SiNO film, etc.) by a sputtering method, a thin film (DLC film, CN) containing carbon as a main component It is preferable to use a film, an amorphous carbon film), a metal oxide film (WO ₂ , CaF ₂ , Al ₂ O ₃ or the like).

  Note that the light-emitting element 184 is formed of a sixth conductive layer 175 functioning as a first pixel electrode, a layer 182 containing a light-emitting substance, and a seventh conductive layer 183 functioning as a second pixel electrode.

  The inverted stagger type TFT formed in this embodiment uses a material having high heat resistance for the gate electrode, and after performing heat treatment for simultaneously performing the activation process, the gettering process, and the crystallization process, the low resistance Wirings such as signal lines and scanning lines are formed using a material. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the display device of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  For this reason, since it is formed of a crystalline semiconductor film, it has higher mobility than an inverted staggered TFT formed of an amorphous semiconductor film. Further, the source region and the drain region contain a catalyst element in addition to the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured as compared with a display device using a TFT formed using an amorphous semiconductor film as a switching element. is there.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. By providing such a TFT in a switching element of a display device, contrast can be improved.

    In the present embodiment, therefore, a thin film material or a resist may be discharged to a predetermined place using a droplet discharge method without forming a thin film on the entire surface of the substrate, and a TFT can be used without using a photomask. Can be formed. For this reason, it is possible to improve throughput and yield and to reduce costs.

(Embodiment 2)
In this embodiment mode, a stacked structure of a power supply line, a signal line, a source or drain electrode, a scan line, and a pixel electrode of the active matrix substrate described in Embodiment Mode 1 is described with reference to FIGS. In the following embodiments, a longitudinal sectional view and a top view corresponding to FIG. 2C before forming a light emitting element are shown.

  3A is a diagram illustrating a stacked structure of a driving TFT 191 and a fifth conductive layer functioning as a scanning line of the switching TFT 192. FIG. 3A illustrates a structure of (A)-(B) in FIG. It corresponds to a cross-sectional structure.

  FIG. 3B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG. Note that in FIG. 3C, the sixth conductive layer (pixel electrode 175) functioning as a pixel electrode is indicated by a broken line.

  Hereinafter, the fourth conductive layer functioning as a power supply line and a capacitor wiring is a power supply line 162, the fourth conductive layer functioning as a signal line is a signal line 167, and the fourth conductive layer functioning as a source electrode or a drain electrode is drained. The electrodes 163 and 169, the fifth conductive layer functioning as a scan line is the scan line 173, the second conductive layer functioning as the gate electrode is the gate electrodes 121 and 122a, and the sixth conductive layer functioning as the pixel electrode is the pixel. This is indicated as an electrode 175.

  As shown in FIG. 3A, a first insulating film 123 is formed over the gate electrode 121 of the driving TFT 191 and the gate electrode 122 a of the switching TFT 192, and the signal line 167 is formed over the first insulating film 123. The drain electrode 163, the power supply line 162, and the fourth semiconductor region 166 of the driving TFT 191 are formed. Note that in FIGS. 3A and 3B, the first insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  Further, the second insulating film 171 and the third insulating film 172 are formed on all of the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply line 162, the fourth semiconductor region 166, and the first insulating film 123. A scanning line 173 connected to the gate electrode 122 a of the switching TFT 192 is formed on the third insulating film 172. That is, the signal line 167, the power supply line 162 of the driving TFT 191, and the signal line 167 of the switching TFT intersect with the scanning line 173 through the second insulating film 171 and the third insulating film 172.

  A fourth insulating film 174 is formed over all of the scanning lines 173 and the third insulating film 172, and a pixel electrode 175 is formed over the fourth insulating film. That is, the scanning line 173 and the pixel electrode 175 are formed through the fourth insulating film. Since the fourth insulating film 174 over which the pixel electrode 175 is formed is formed using a planarization layer, a layer including a light-emitting substance to be formed later can be prevented from being disconnected, and a display with few defects can be achieved. It is possible to form a device.

  Note that the capacitor 193 is formed using the power supply line 162, the first insulating film 123, and the second conductive layer 121.

  As shown in FIG. 3B, a first insulating film 123 is formed over the gate electrode 122a of the switching TFT 192. On the first insulating film 123, a fourth semiconductor region 168, a signal line 167, A drain electrode 169 is formed. The drain electrode 169 of the switching TFT 192 is connected to the gate electrode 121 of the driving TFT 191 through the first insulating film 123. Further, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the second insulating film 171, the third insulating film 172, and the fourth insulating film 174.

(Embodiment 3)
In this embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with Embodiment 2 will be described with reference to FIG.

  FIG. 4A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along lines (A)-(B) in FIG. Note that in FIG. 4C, the pixel electrode 175 is indicated by a broken line.

  On the first insulating film 123, as in the second embodiment, the gate electrode 121 of the driving TFT 191 and the gate electrode 122a of the switching TFT 192 are formed, and the first insulating film 123 is formed thereon. On the first insulating film 123, the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply line 162, and the fourth semiconductor region 166 are formed. Note that in FIGS. 4A and 4B, the first insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  In the present embodiment, the scanning line 1113 is formed on the first insulating film 123.

  In addition, a second insulating film 1114 is formed over the signal line 167, and a scanning line 1113 is formed over the second insulating film 1114. That is, the signal line intersects the scanning line 1113 with the second insulating film 1114 interposed therebetween. Here, the second insulating film 1114 is formed by a droplet discharge method or a printing method.

  In this embodiment, the second insulating film 1114 is provided only in a region where the source wiring, the capacitor wiring, and the scanning line intersect. For this reason, unlike the second embodiment, the second insulating film 1114 is formed only in part, so that raw materials can be reduced and the cost can be reduced.

  The third insulating film 1111 functioning as a passivation film over the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply line 162, the fourth semiconductor region 166, the first insulating film 123, and the scanning line 1113. Is formed.

    Further, a fourth insulating film 1112 is formed over the third insulating film 1111, and a pixel electrode 175 connected to the drain electrode 163 is formed through the fourth insulating film 1112.

  FIG. 4B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG.

  As shown in FIG. 4B, a switching TFT is formed as in the second embodiment, and the drain electrode 169 of the switching TFT 192 is connected to the gate of the driving TFT 191 with the first insulating film 123 interposed therebetween. It is connected to the electrode 121. In addition, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

(Embodiment 4)
In the present embodiment, an active matrix substrate having a scanning line structure different from that in the second embodiment will be described with reference to FIG.

  FIG. 5A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along lines (A)-(B) in FIG.

  FIG. 5B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG. Note that in FIG. 5C, the pixel electrode 175 is indicated by a broken line.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the second embodiment. Note that as illustrated in FIG. 5C, the scanning lines 1123a and 1123b are formed for each pixel and connected to gate electrodes 122a and 122b provided in adjacent pixels. For this reason, the material of the scanning lines 1123a and 1123b does not need to be a particularly low resistance material, and the range of selection of the material is widened.

  In addition, a fourth insulating film 174 is formed over all of the scan lines 1123a and 1123b and the third insulating film 172, and a pixel electrode 175 is formed over the fourth insulating film. That is, the pixel electrode 175 may be formed so as to cover part of the scanning lines 1123a and 1123b with the fourth insulating film interposed therebetween.

(Embodiment 5)
In this embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with Embodiment 3 will be described with reference to FIG.

  FIG. 6A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, which corresponds to the cross-sectional structure of FIGS. 6A to 6B.

  FIG. 6B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG. Note that in FIG. 6C, the pixel electrode 175 is indicated by a broken line.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the third embodiment. As shown in FIG. 6C, as in the fourth embodiment, the scanning lines 1133a and 1133b are formed for each pixel and connected to gate electrodes 122a and 122b provided in adjacent pixels. Yes. For this reason, the material of the scanning lines 1133a and 1133b is not particularly required to be a low-resistance material, and the selection range of the material is widened.

  Note that the second insulating film 1137 is provided only in a region where the signal line 167 intersects with the scanning lines 1133a and 1133b. Therefore, the scanning lines 1133a and 1133b are formed over the second insulating film 1137 and the first insulating film 123. Note that in FIGS. 5A and 5B, the first insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  In the present embodiment, unlike the second and fourth embodiments, the second insulating film 1137 is formed only in part, so that raw materials can be reduced and the cost can be reduced.

  Further, a third insulating film 1131 is provided as a passivation film over the driving TFT 191, the switching TFT 192, and the capacitor 193, and a fourth insulating film 1112 is formed over the third insulating film. In addition, the drain electrode 163 of the driving TFT 191 is covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

  In addition, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

(Embodiment 6)
In this embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with Embodiments 2 to 5 will be described with reference to FIGS.

  FIG. 7A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, which corresponds to the cross-sectional structure of FIGS. 7A to 7B.

  FIG. 7B illustrates a connection structure between the switching TFT 192 and the driving TFT 191, and corresponds to a cross-sectional structure taken along lines (C) to (D) in FIG. Note that in FIG. 7C, the pixel electrode 175 is indicated by a broken line.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the second embodiment.

  In the present embodiment, unlike the second to fifth embodiments, the scanning lines 1141a and 1141b are formed simultaneously with the power supply lines 162a and 163a, the signal line 167, and the drain electrodes 163 and 169.

  Specifically, as illustrated in FIG. 7A, a first insulating film 123 is formed over the gate electrodes 121 and 122a, and the signal line 167 and the drain of the driving TFT 191 are formed over the first insulating film 123. Scanning lines 1141a and 1141b are formed together with the electrode 163 and the power supply lines 162a and 162b. In addition, a fourth semiconductor region 166 is formed. Note that in FIGS. 7A and 7B, the first insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  Note that the scanning lines 1141a and 1141b are provided in each pixel and do not intersect with the signal lines. Therefore, when these electrodes and wirings are formed by a droplet discharge method, they can be formed at the same time, so that mass productivity can be improved.

  In addition, the second insulating film 171 and the third insulating film 172 are formed over all of the signal line 167, the drain electrode 163 of the driving TFT 191, the power supply lines 162a and 162b, the scanning lines 1141a and 1141b, and the signal line 167. On the third insulating film 172, a conductive layer 1143a connected to the scanning lines 1141a and 1141b is formed. That is, the power supply lines 162 a and 162 b and the signal line 167 intersect the scanning lines 1141 a and 1141 b and the conductive layers 1143 a and 1143 b through the second insulating film 171 and the third insulating film 172.

In addition, a fourth insulating film 174 is formed over the entire surfaces of the conductive layers 1143a and 1143b and the third insulating film 172, and a pixel electrode 175 is formed over the fourth insulating film.

(Embodiment 7)
In this embodiment, an active matrix substrate having a stacked structure of scanning lines and signal lines as compared with Embodiment 6 will be described with reference to FIG.

  FIG. 8A illustrates a stacked structure of the driving TFT 191 and the scanning line of the switching TFT 192, and corresponds to the cross-sectional structure of FIGS. 8A to 8B.

  FIG. 8B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191 and corresponds to a cross-sectional structure of (C)-(D) in FIG. Note that in FIG. 8C, the pixel electrode 175 is indicated by a broken line.

  In this embodiment, the structures of the driving TFT 191, the switching TFT 192, and the capacitor 193 are the same as those in the third embodiment.

  Here, as in the sixth embodiment, the scanning lines 1141a and 1141b, the signal line 167, the drain electrode 163 of the driving TFT 191 and the power supply lines 162a and 162b do not intersect each other. For this reason, when forming by a droplet discharge method, since it can form simultaneously, it is possible to improve mass-productivity. In addition, scanning lines 1141a and 1141b are formed for each pixel, and are connected to gate electrodes 122a and 122b provided in adjacent pixels. For this reason, the material of the scanning lines 1141a and 1141b is not particularly required to be a low-resistance material, and the selection range of the material is expanded.

  In this embodiment, the second insulating layer 1154 is provided only in a region where the signal line 167 and the power supply line 162b intersect with the scanning lines 1141a and 1141b. For this reason, unlike Embodiment 2, Embodiment 4, and Embodiment 6, since it forms only in part, it can reduce a raw material and can reduce cost.

  In addition, conductive layers 1153 a and 1153 b are formed over the scan lines 1141 a and 1141 b and the second insulating layer 1154. Note that the conductive layers 1153a and 1153b are connected to the scanning lines 1141a and 1141b.

  Further, a third insulating film 1131 is provided as a passivation film over the driving TFT 191, the switching TFT 192, and the capacitor 193, and a fourth insulating film 1112 is formed over the third insulating film. In addition, the drain electrode 163 of the driving TFT 191 is covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

  In addition, the driving TFT 191 and the switching TFT 192 are covered with the pixel electrode 175 through the third insulating film 1111 and the fourth insulating film 1112.

(Embodiment 8)
In this embodiment, an active matrix substrate having a different stacked structure of scanning lines and source wirings will be described with reference to FIG.

  FIG. 34A is a diagram illustrating a stacked structure of a driving TFT 191 and a scanning line of the switching TFT 192, and corresponds to a cross-sectional structure taken along lines (A)-(B) in FIG.

  FIG. 34B is a diagram illustrating a connection structure between the switching TFT 192 and the driving TFT 191, and corresponds to a cross-sectional structure of (C)-(D) in FIG. Note that in FIG. 34C, the pixel electrode 175 is indicated by a broken line.

  As shown in FIG. 34A, after the first insulating film over the gate electrode 122a of the switching TFT 192 is removed, a second insulating film 1162b is formed over the gate electrode 122a. At this time, the second insulating film 1162b is preferably formed so that both ends of the gate electrode 122a are exposed. Note that in FIGS. 34A and 34B, the first insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  In addition, when the second insulating film 1162b over the gate electrode 122a is etched, it is preferable to remove the gate insulating film other than the region where the driving TFT 191, the switching TFT 192, and the capacitor 193 are formed. Specifically, it is preferable that only the gate insulating film in the region surrounded by the wavy lines 1163a and 1163b in FIG. 34C is left and the gate insulating film outside the wavy lines 1163a and 1163b be etched. By this step, the contact area of each conductive layer is increased, contact resistance can be suppressed, and a switching TFT and a driving TFT capable of high-speed operation can be formed.

  Next, power supply lines 162a and 162b and a signal line 167 are formed over the second insulating film 1162b, and at the same time, scanning lines 1161a and 1161b in contact with the gate electrode 122a are formed. In addition, a drain electrode 169 connected to the gate electrode 121 is formed. With such a structure, contact resistance between the gate electrode and the scanning line can be suppressed. Further, these power supply lines, signal lines, and scanning lines do not intersect. For this reason, when forming by a droplet discharge method, since it can form simultaneously, it is possible to improve mass-productivity.

  Note that the connection structure between the gate electrode 122a and the scanning lines 1161a and 1161b and the connection structure between the gate electrode 121 and the drain electrode 169 as in this embodiment can be applied to Embodiments 2 to 7, respectively. It is.

  In this embodiment, the scanning lines 1161a and 1161b formed for each pixel are electrically connected through the gate electrodes 122a and 122b. In addition, the scan line and the signal line intersect with each other through the second insulating film 1162b formed over the gate electrode 122a.

In this embodiment, the second insulating film 1162b is provided only in a region where the signal line, the power supply line, and the scanning line intersect. For this reason, since it forms only in a part, it is possible to reduce raw materials, and cost reduction is possible.
(Embodiment 9)
In the present embodiment, a modification of the crystallization and gettering steps in Embodiment 1 will be described with reference to FIG.

    As shown in FIG. 20A, first conductive layers 121a and 122a are formed and a first insulating film 123 is formed in accordance with the same steps as in the first embodiment. Here, the first insulating film 123 has the same configuration as the first insulating film of the first embodiment. Note that in FIG. 20, the first insulating films 123 a, 123 b, and 123 c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, as illustrated in FIG. 20B, a first semiconductor film 124, a layer 125 having a catalytic element, and a second semiconductor film 132 are formed through the same steps as in Embodiment Mode 1.

  Note that after the first semiconductor film 124 is formed, a channel doping process may be performed on the entire surface or selectively.

  Next, as illustrated in FIG. 20C, the first semiconductor film and the second semiconductor film are heated by a process similar to that in Embodiment 1, and the first crystalline semiconductor film 141 and the second semiconductor film are heated. A crystalline semiconductor film 142 is formed. In crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus.

  At the same time as the crystallization progresses, as indicated by an arrow in FIG. 20C, the catalytic element that contributes to the crystallization of the first semiconductor film is moved to the second semiconductor film 132 and gettered. The concentration of the catalytic element is reduced to form the first crystalline semiconductor film 141, and the second semiconductor film to which the catalytic element after gettering has moved is crystallized to form the second crystalline semiconductor film 142. It is formed.

In this embodiment, a layer containing a catalytic element is formed on the first semiconductor film. For this reason, unlike Embodiment 1, it is possible to reduce the oxygen concentration in the first semiconductor film by continuously forming the first insulating film and the first semiconductor film. For example, as the first insulating film, a silicon nitride film is formed by a CVD method using silane and ammonia gas as raw materials, and the CVD method silicon oxide film is then formed by switching from ammonia gas to nitrogen oxide (N ₂ O). A first insulating film is formed. Next, only silane gas is allowed to flow into the chamber without generating plasma. This makes it possible to reduce the oxygen concentration in the chamber. Thereafter, the first semiconductor film having a low oxygen concentration can be formed by forming the first semiconductor film by a CVD method using silane gas as a raw material.

Note that this embodiment can be applied to any one of Embodiments 1 to 8.
(Embodiment 10)
In this embodiment, a process of forming a channel protection type TFT through the same gettering process as that of Embodiment 1 will be described with reference to FIG.

  As shown in FIG. 38A, the first conductive layers 121a and 122a are formed, the first insulating film 123 is formed, and the layer 125 containing a catalytic element is formed through the same steps as in Embodiment Mode 1. A first semiconductor film 124 is formed. Next, after a second insulating film 128 is formed over the first semiconductor film, a second mask 119 is formed over the second insulating film. In FIG. 38, the first insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Here, the second insulating film 128 is any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. This is an insulating film formed of a single layer. Alternatively, the insulating films may be combined as appropriate to form a stacked structure.

  The second mask 119 is formed by a droplet discharge method or a laser beam direct writing apparatus.

  Next, the second insulating film 128 is etched using the second mask 119 to form a first insulating region 129. The first insulating region 129 functions as a channel protective layer.

  Next, as illustrated in FIG. 38C, a second semiconductor film 132 is formed over the first semiconductor film and the first insulating region, and the first semiconductor film and the first semiconductor film The second semiconductor film is heated and crystallized, and the catalyst element crystallized from the first semiconductor film is moved to the second crystalline semiconductor film 242 as shown by an arrow in FIG. Gettering the catalytic element. As a result, the first crystalline semiconductor film 141 in which the concentration of the catalytic element is reduced and the second crystalline semiconductor film 142 having the catalytic element are formed.

  Thereafter, a channel protection type TFT can be formed according to the same steps as those in the first embodiment. Note that this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 11)
In this embodiment mode, a method for forming a channel protection type TFT according to the same gettering process as that in Embodiment Mode 9 will be described with reference to FIG.

  As shown in FIG. 39A, the first conductive layers 121a and 122a are formed, the first insulating film 123 is formed, and the first semiconductor film 124 is formed following the same steps as in the first embodiment. Then, a layer 125 containing a catalytic element is formed, a second insulating film 128 is formed, and a second mask 119 is formed by a discharge method or a laser direct drawing apparatus. In FIG. 39, the first insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, the second insulating film 128 is etched using the second mask 119 to form a first insulating region 129. The first insulating region 129 functions as an etching protective film.

  Next, as shown in FIG. 39C, a second semiconductor film 132 is formed over the first semiconductor film and the first insulating region, and the first semiconductor film and the first semiconductor film are formed by a process similar to that in Embodiment 9. By heating the second semiconductor film, the first crystalline semiconductor film 141 and the second crystalline semiconductor film 142 are formed. With the heating, the catalytic element is gettered as shown by the arrow in FIG.

  Thereafter, a channel protection type TFT can be formed by following the same process as in the tenth embodiment. Note that this embodiment can be applied to any one of Embodiments 1 to 8.

Embodiment 12
In this embodiment, a process for forming a TFT by gettering a catalytic element using a semiconductor film containing a rare gas element instead of a semiconductor film containing a donor element will be described with reference to FIGS.

  As shown in FIGS. 9A and 9B, a first conductive layer 121a is formed by a process similar to that of Embodiment Mode 1, a first insulating film 123 is formed, and a layer 125 having a catalytic element is formed. The first semiconductor film 124 is formed. Next, an oxide film with a thickness of 1 to 5 nm may be formed on the surface of the first crystalline semiconductor film. Here, ozone water is applied to the surface of the crystalline semiconductor film to form an oxide film. Note that a channel doping step may be performed after the first semiconductor film 124 is formed. In FIG. 9, the first insulating films 123 a, 123 b, and 123 c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, a second semiconductor film 232 containing a rare gas element is formed over the first semiconductor film 124 by a known method such as a PVD method or a CVD method. The second semiconductor film 232 is preferably an amorphous semiconductor film.

Next, the first semiconductor film 124 and the second semiconductor film 232 are heated by a method similar to that of Embodiment Mode 1 and crystallized together with the first semiconductor film as indicated by an arrow in FIG. 9C. The catalyst element crystallized is moved to the second crystalline semiconductor film 242, and the catalyst element is gettered. As a result, the first crystalline semiconductor film 241 in which the concentration of the catalytic element is reduced and the second crystalline semiconductor film 242 having the catalytic element are formed. By this step, as in the first embodiment, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the concentration of the catalytic element in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably It can be 1 × 10 ¹⁷ / cm ³ or less.

  Next, as illustrated in FIG. 9D, after the second crystalline semiconductor film 242 is removed, a conductive second semiconductor film 243 is formed. Here, the second semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas. Note that the second semiconductor film may be formed using a film having any state selected from an amorphous semiconductor, a SAS, a crystalline semiconductor, and μc. Note that in the case where the second semiconductor film is any one of a conductive amorphous semiconductor film, SAS, and μc, heat treatment for activating impurities is performed thereafter. On the other hand, when the second semiconductor film is a crystalline semiconductor having conductivity, heat treatment is not necessarily performed. Here, an amorphous silicon film containing phosphorus with a thickness of 100 nm is formed by plasma CVD, and then heated at 550 ° C. for 2 hours to activate the impurities.

  Next, as illustrated in FIG. 9E, a first semiconductor region 252, a second semiconductor region 251, and a third conductive layer 153 are formed through the same steps as in Embodiment Mode 1. Next, after the photosensitive material 254 is applied or discharged, part of the photosensitive material is irradiated with laser light 255, so that a mask 260 as illustrated in FIG. 9F is formed.

  Next, as illustrated in FIG. 9F, a source electrode 162a and a drain electrode 163 are formed. In addition, by a process similar to that in Embodiment 1, the first semiconductor region is etched to form a third semiconductor region 262 that functions as a source region and a drain region, and a fourth semiconductor region 261 that functions as a channel formation region. can do.

  Thereafter, an inverted staggered TFT and an active matrix substrate can be formed by the same process as in the first embodiment. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 13)
In this embodiment, the step of forming the n-channel TFT and the p-channel TFT on the same substrate is formed using FIG.

  As shown in FIG. 10A, first conductive layers 301 and 302 are formed on a substrate 101 as in the first embodiment, and a first insulating film 123 is formed on the first conductive layer. The first semiconductor film and the second semiconductor film containing a donor element are formed on the first semiconductor film by the same process as the first process. Next, using a mask formed using a droplet discharge method or a laser beam direct writing apparatus, the first semiconductor film is etched into a desired shape to form a first semiconductor region. The semiconductor film is etched into a desired shape to form a second semiconductor region. Note that in FIG. 10, the first insulating films 123 a, 123 b, and 123 c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, the first semiconductor region and the second semiconductor region are heated to crystallize the second semiconductor region, and are included in the second semiconductor region as indicated by an arrow in FIG. The catalytic element is moved to the first semiconductor region to getter the catalytic element. Here, the first semiconductor region to which the catalytic element after gettering has moved is referred to as third semiconductor regions 311 and 312, and the second semiconductor region in which the metal element concentration is reduced is the fourth semiconductor regions 313 and 314. It shows. Note that the first semiconductor region to the fourth semiconductor region are each crystallized by heating.

  In this embodiment, the heat treatment is performed after forming each semiconductor region. However, as in the first embodiment, after the heat treatment of each semiconductor film, the semiconductor film is etched into a desired shape, and each semiconductor film is etched. A region may be formed.

  Next, after an oxide film is formed on the surfaces of the third semiconductor regions 311 and 312 and the fourth semiconductor regions 313 and 314, a droplet discharge method or a laser beam direct writing apparatus is used, as shown in FIG. Thus, the first masks 321 and 322 are formed. The first mask 321 covers all of the third semiconductor region 311 and the fourth semiconductor region 313 that will be n-channel TFTs later. On the other hand, the first mask 322 covers a part of the third semiconductor region 312 to be a p-channel TFT later. At this time, the first mask 322 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, a Group 3 element (Group 13 element, hereinafter referred to as an acceptor element) is added to the exposed portion of the third semiconductor region 312 to form a p-type third semiconductor region 324. At this time, the region covered with the first mask 322 remains as the n-type impurity region 325. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the fourth semiconductor region 314 to be an n-type impurity region.

  FIG. 17 shows a profile of the impurity element in the p-type impurity region.

FIG. 17A shows a profile of each element when an acceptor element is added after forming a second semiconductor film having an n ⁻ region concentration and an n ⁺ region concentration by a CVD method. The donor-type element profile 150a shows the first concentration and the second concentration, as in FIG. The acceptor-type element profile 603 has a high concentration in the vicinity of the surface of the second semiconductor film, and the concentration decreases as it approaches the fourth semiconductor region 314. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n ⁺ region is denoted as p ⁺ region 602a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is designated. A region having the same is indicated as a p-region 602b.

In FIG. 17B, a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed, and the semiconductor is formed by an ion doping method or an ion implantation method. A profile of each element when an acceptor element is added after forming a second semiconductor film having an n ⁻ region concentration and an n ⁺ region concentration by adding a donor element to the film is shown. The donor-type element profile 150b is similar to the donor-type element profile 150b of FIG. The acceptor-type element profile 613 is similar to the acceptor-type element profile 603 in FIG. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n ⁺ region is indicated as p ⁺ region 612a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is indicated. The region having this is indicated as p-region 612b.

  Note that the second semiconductor film 132 containing a donor-type element is added with a rare gas element, typically argon, so that distortion of the crystal lattice is formed. It is possible to getter elements.

  Next, after removing the first masks 321 and 322, the third semiconductor region 311 and the third semiconductor regions 324 to 325 to which the acceptor element is added are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as shown in FIG. 10C, third conductive layers 331 and 332 are formed as in the first embodiment. Next, a mask 333 is formed using a laser beam direct writing apparatus, and as shown in FIG. 10D, fourth conductive layers 341 and 342 and a fifth semiconductor functioning as a source region and a drain region. Regions 343 and 344 are formed. Next, after the mask 333 is removed, passivation films 140 and 144 are preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the sixth semiconductor regions 345 and 346.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, it is possible to form a CMOS that can be driven at a lower voltage than a drive circuit formed of a single channel TFT. Furthermore, since an acceptor element (eg, boron) has a smaller atomic radius than a donor element (eg, phosphorus), the acceptor element is added to the semiconductor film at a relatively low acceleration voltage and concentration. Is possible. In this embodiment, since only the acceptor element is added to the semiconductor film, it can be manufactured in a shorter time and with less energy compared with the manufacturing process of the conventional COMS circuit. As a result, the cost can be reduced. Is possible.

  In addition, this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 14)
In this embodiment, an n-channel TFT and a p-channel manufacturing process including a crystalline semiconductor film formed by a gettering process different from that in Embodiment 13 will be described with reference to FIGS.

  In accordance with Embodiment Mode 1, as shown in FIG. 11A, first conductive layers 301 and 302 are formed over a substrate 101, and a first insulating film 123 is formed. Next, after a layer containing a catalytic element is formed and a first semiconductor film is formed, an insulating film having a thickness of several nm is formed on the surface of the first semiconductor film. Next, a first mask is formed using a droplet discharge method or a laser beam direct writing apparatus, the first semiconductor film is etched into a desired shape, and the first semiconductor regions 401 and 402, Catalytic element regions 125a and 125b are formed. In FIG. 11, the first insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, as illustrated in FIG. 11B, second masks 403 and 434 are formed over the first semiconductor regions 401 and 402 by using a droplet discharge method or a laser beam direct writing apparatus, A donor-type element 405 is added to the exposed portion of the first semiconductor region. At this time, regions to which the donor element is added are denoted as n-type impurity regions 406 and 407. Here, phosphorus is added by an ion doping method. Note that the first semiconductor region covered with the second mask does not contain phosphorus but contains a catalytic element.

Next, the first semiconductor region is heated to crystallize the first semiconductor regions 401 and 402, and as indicated by an arrow in FIG. 11C, the catalytic element contained in the first semiconductor region is changed. The n-type impurity regions 406 and 407 are moved to getter the catalyst element. Here, the first semiconductor region in which the catalytic element after gettering has moved is referred to as a source region and drain regions 413 and 414, and the first semiconductor region in which the metal element concentration is reduced is referred to as channel formation regions 411 and 412. . Note that the third semiconductor regions 413 and 414 and the fourth semiconductor regions 411 and 412 are crystallized by heating in the gettering step, and the donor type included in the n-type impurity regions 406 and 407 is used. Element is activated

  Next, as shown in FIG. 11D, third masks 421 and 422 are formed using a droplet discharge method or a laser beam direct writing apparatus. The third mask 421 covers all of the channel formation region 411 to be an n-channel TFT later and the third semiconductor region 413 exhibiting n-type. On the other hand, the third mask 422 covers part or all of the channel formation region 412 to be a p-channel TFT later. At this time, the third mask 422 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element 423 is added to exposed portions of the source and drain regions 414 and the channel formation region 412 to form p-type source and drain regions 424. At this time, the p-type source region and the drain region can be formed by adding the acceptor element so that the concentration is 2 to 10 times that of the source region and the drain region 414.

  Next, after the third masks 421 and 422 are removed, the source and drain regions 414 exhibiting n-type and the source and drain regions 424 exhibiting p-type are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as shown in FIG. 11D, fourth conductive layers 341 and 342 are formed as in the thirteenth embodiment. Thereafter, part of the channel formation regions 411 and 412 may be etched. Next, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Furthermore, since the number of film formation steps can be reduced as compared with Embodiment 12, the throughput can be improved.

  Note that this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 15)
In this embodiment, a step of forming an n-channel TFT and a p-channel TFT on the same substrate using the crystalline semiconductor film subjected to the gettering step using Embodiment 12 is formed using FIG.

  First conductive layers 301 and 302 are formed over the substrate 101 in accordance with the steps of Embodiment Mode 1. Next, a first semiconductor film and a second semiconductor film containing a rare gas element are formed according to the steps of Embodiment Mode 8. Next, the first semiconductor film and the second semiconductor film are heated by a method similar to that in Embodiment 1 to crystallize the first semiconductor film as indicated by an arrow in FIG. The catalytic element that promotes crystallization is moved to the second semiconductor film to getter the catalytic element. A first semiconductor film in which the catalytic element is gettered after crystallization is referred to as a first crystalline semiconductor film 501. Further, since the second semiconductor film to which the catalytic element after gettering has moved is also crystallized in the same manner, it is referred to as a second crystalline semiconductor film 502.

  Next, as shown in FIG. 12B, after the second crystalline semiconductor film 502 is etched, an insulating film having a thickness of several nm is formed on the surface of the first crystalline semiconductor film 501. Next, by using a droplet discharge method or a laser beam direct writing apparatus, a first mask is formed, and the first crystalline semiconductor film is etched to form first semiconductor regions 511 and 512. Next, second masks 513 and 514 are formed using a droplet discharge method or a laser beam direct writing apparatus. The second mask 513 covers a portion that later becomes a channel formation region of the n-channel TFT. On the other hand, the second mask 514 covers the entire first semiconductor region 512 that will later become a p-channel TFT. Next, a donor-type element is added to the exposed portion of the first semiconductor region 511. At this time, a region to which the donor element is added is referred to as an n-type impurity region 516. The region covered with the second mask 513 functions as a channel formation region 517.

  Next, after removing the second masks 513 and 514, new third masks 521 and 522 are formed. The third mask 521 covers the entire channel formation region 411 that will be an n-channel TFT later and the third semiconductor region 413 that exhibits n-type. On the other hand, the third mask 422 covers a region to be a channel formation region of the p-channel TFT later.

  Next, an acceptor element is added to the exposed portion of the first semiconductor region 512 to form a p-type impurity region 524. Further, the region covered with the third mask 522 functions as a channel formation region 525. Next, after removing the third masks 521 and 522, the n-type impurity region 516 and the p-type impurity region 524 are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate.

  Next, as shown in FIG. 12D, fourth conductive layers 341 and 342 are formed in the same manner as in the thirteenth embodiment. Thereafter, part of the channel formation regions 517 and 525 may be etched. Next, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the channel formation regions 517 and 525.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

  Note that this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 16)
This embodiment is a modification of Embodiment 13, and the step of forming an n-channel TFT and a p-channel TFT on the same substrate is formed using FIG.

  According to Embodiment 13, as shown in FIG. 13A, third semiconductor regions 311 and 312 and fourth semiconductor regions 313 and 314 having a catalytic element and a donor element are formed. Next, as shown in FIG. 13B, after forming the first mask 321, an acceptor element is added to the third semiconductor region 312 to form a p-type impurity region 601. At this time, a p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the third semiconductor region 312 which is an n-type impurity region. Further, when boron is used as the acceptor element, the molecular radius is small, so that it is added deeper than the fourth semiconductor region. For this reason, boron is added to the upper portion of the fourth semiconductor region depending on the addition conditions. Thereafter, the third semiconductor region 311 and the p-type impurity region 601 are heated to activate the acceptor-type element and the donor-type element. Note that here, the doping conditions are controlled so that the acceptor element is not added to the fourth semiconductor region 314.

  Next, as shown in FIG. 13C, third conductive layers 331 and 332 are formed according to the thirteenth embodiment. Next, the exposed portions of the third conductive layers 331 and 332, the third semiconductor region 313, and the p-type impurity region 601 are etched using a mask formed using a droplet discharge method or a laser beam direct writing apparatus, As shown in FIG. 13D, fifth semiconductor regions 343 and 621 that function as source and drain regions and sixth semiconductor regions 345 and 622 that function as channel formation regions can be formed. After that, a passivation film is preferably formed over the surfaces of the fourth conductive layers 341 and 342 and the sixth semiconductor regions 345 and 622.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Furthermore, since only the acceptor-type element is added to the semiconductor film as in the third embodiment, it can be manufactured in a shorter time and with less energy compared to the manufacturing process of the conventional COMS circuit. As a result, the cost can be reduced.

  Note that this embodiment can be applied to any one of Embodiments 1 to 8.

(Embodiment 17)
In this embodiment, the positional relationship between the end portions of the gate electrode, the source electrode, and the drain electrode, that is, the relationship between the width of the gate electrode and the size of the channel length in the above embodiment is described with reference to FIGS. To do.

  In FIG. 14A, the end portions of the source electrode and the drain electrode are overlapped by z1 on the gate electrode 121a. Here, a region where the gate electrode 121a overlaps with the source electrode and the drain electrode is referred to as an overlap region. That is, the width y1 of the gate electrode is larger than the channel length x1. The width z1 of the overlap region is represented by (y1-x1) / 2. An n-channel TFT having such an overlap region preferably has an n + region and an n− region between the source and drain electrodes and the semiconductor region. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

    In FIG. 14B, the end portion of the gate electrode 121a is coincident with the end portions of the source electrode and the drain electrode. That is, the gate electrode width y2 is equal to the channel length x2.

  In FIG. 14C, the gate electrode 121a is separated from the ends of the source and drain electrodes by z3. Here, a region where the gate electrode 121a is separated from the source electrode and the drain electrode is referred to as an offset region. That is, the width y3 of the gate electrode is smaller than the channel length x3. The width z3 of the offset area is represented by (x3-y3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  In FIG. 15A, the width y4 of the gate electrode is larger than the channel length x4. In addition, the first end of the gate electrode 121a and one end of the source or drain electrode coincide with each other, and the second end of the gate electrode 121a and the other end of the source or drain electrode are z4. Only overlap. The width z4 of the overlap region is represented by (y4-x4).

  In FIG. 15B, the width y5 of the gate electrode is larger than the channel length x5. In addition, the first end of the gate electrode 121a and one end of the source or drain electrode coincide with each other, and the second end of the gate electrode 121a and the other end of the source or drain electrode are z5. Just away. The width z5 of the offset area is represented by (x5-y5). When the gate electrode 121a has an electrode whose end matches the first end as a source electrode and an electrode having an offset region as a drain electrode, electric field relaxation near the drain electrode can be achieved.

  Further, a TFT having a so-called multi-gate structure in which the semiconductor region covers a plurality of gate electrodes may be used. A TFT having such a structure can also reduce off-state current.

  It should be noted that this embodiment can be applied to any of Embodiments 1 to 16.

(Embodiment 18)
In the above embodiment, the source electrode and the drain electrode having end portions perpendicular to the surface of the channel formation region are shown; however, the structure is not limited to this. As shown in FIG. 18, it may be an end portion having a larger angle than 90 degrees and smaller than 180 degrees, preferably 135 to 145 degrees with respect to the surface of the channel formation region. Further, if the angle between the source electrode and the channel formation region surface is θ1, and the angle between the drain electrode and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

  Further, as shown in FIG. 19, the end portions of the source electrode and the drain electrodes 2149a and 2149b may have curved surfaces 2150a and 2150b.

  It should be noted that this embodiment can be applied to any of Embodiments 1 to 16.

(Embodiment 19)
In this embodiment, a semiconductor film crystallization process applicable to the above embodiment will be described with reference to FIGS.

  Further, as shown in FIG. 21A, a catalytic element layer 2805 is selectively formed by a droplet discharge method without using a mask, and then a semiconductor film 132 containing a donor element is formed and crystallized. May be performed. FIG. 21B is a top view of FIG. FIG. 21D is a top view of FIG. When the semiconductor film is heated, crystal growth occurs in a direction parallel to the surface of the substrate from the contact portion between the catalytic element layer and the semiconductor film, as shown by arrows in FIGS. At the same time, the catalytic element is gettered to the semiconductor film containing the donor element according to the direction of the arrow. The above crystallization may be performed. FIG. 21B is a top view of FIG. FIG. 21D is a top view of FIG. When the semiconductor film is crystallized, crystal growth occurs in a direction parallel to the surface of the substrate from the contact portion between the catalytic element layer and the semiconductor film, as shown in FIGS. A crystalline semiconductor film 2806 is formed. Again, crystallization is not performed at a portion far away from the catalyst element layer 2805, and an amorphous portion 2807 remains.

  Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth. Since large crystal grains can be formed by lateral growth, a TFT having higher mobility can be formed.

  It should be noted that this embodiment can be applied to any one of Embodiments 1 to 18.

  Next, a method for manufacturing an active matrix substrate and a display device having the active matrix substrate will be described with reference to FIGS. 22 to 24 are longitudinal sectional views of the active matrix substrate. The driving circuit unit AA ′, the driving TFT B-B ′ of the pixel unit, the gate electrode of the switching TFT and the connecting unit C of the scanning line -C 'is shown schematically.

  As shown in FIG. 22A, a first conductive film with a thickness of 100 to 200 nm is formed over a substrate 800. Here, a glass substrate is used as the substrate 800, and an indium oxide film containing silicon oxide with a thickness of 150 nm is formed as a first conductive film over the surface by a sputtering method. Next, a photosensitive material is discharged or applied onto the first conductive film, and the photosensitive material is exposed and developed using a laser beam direct writing apparatus to form a first mask. Next, the first conductive film is etched using the first mask to form first conductive layers 801 to 804. Here, the tungsten film is etched by a dry etching method to form an indium oxide layer containing silicon oxide which is the first conductive layers 801 to 804. Note that the first conductive layers 801 and 802 function as a gate electrode of a TFT constituting a driving circuit, the first conductive layer 803 functions as a gate electrode of a driving TFT, and the first conductive layer 804 functions as a gate of a switching TFT. Functions as an electrode.

  Next, a first insulating film is formed over the surface of the substrate 800 and the first conductive layers 801 to 804. Here, as the first insulating films 805 and 806, a silicon nitride film with a thickness of 50 nm to 100 nm and a silicon oxynitride film (SiON (O> N) with a thickness of 50 to 100 nm are stacked by a CVD method. Note that the first insulating film functions as a gate insulating film, and at this time, it is preferable that the silicon nitride film and the silicon oxynitride film be continuously formed only by switching the source gas without being released to the atmosphere. As in the first embodiment, a three-layer structure may be used.

Next, a layer 808 having a catalytic element is formed by a known method such as a PVD method, a CVD method, or a vapor deposition method. Here, a solution containing 100 ppm of nickel catalyst is applied by spin coating.

  Next, as illustrated in FIG. 22B, an amorphous semiconductor film 807 with a thickness of 10 to 100 nm is formed. Here, an amorphous silicon film with a thickness of 100 nm is formed by a CVD method. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively. Next, a semiconductor film 812 containing a donor-type element with a thickness of 100 nm is formed. Here, an amorphous silicon film containing phosphorus is formed using silane gas and 0.5% phosphine gas (flow ratio silane / phosphine is 10/17).

  Next, the amorphous semiconductor film 807 is heated to form a crystalline semiconductor film 813 as shown in FIG. Here, using an electric furnace, the semiconductor film is dehydrogenated by heating at 500 ° C. for 1 hour, and then heated at 550 ° C. for 4 hours to form a crystalline silicon film containing nickel.

By this heating, the catalyst element moves to the semiconductor film 812 containing the donor type element and is gettered, and the donor type element is activated. That is, the catalyst element in the crystalline semiconductor film containing the catalyst element is moved to the semiconductor film 812 containing the donor element. A crystalline semiconductor film in which the concentration of the catalytic element is reduced is indicated by 813 in FIG. Here, a crystalline silicon film is formed. In addition, a semiconductor film containing a donor element to which the catalyst element has moved also becomes a crystalline semiconductor film by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by 814 in FIG. Here, a crystalline silicon film containing nickel and phosphorus is formed.

  Next, as illustrated in FIG. 22D, after a second mask is formed over the crystalline semiconductor film 814 containing the catalytic element and the donor-type element and the crystalline semiconductor film 813, the second mask is used. Etch to desired shape. The second masks 815 to 817 can be formed by dropping and drying an organic resin by a droplet discharge method. Further, similarly to the first mask, the photosensitive material can be formed by exposure and development with a laser beam direct drawing apparatus. Here, a second mask is formed by selectively discharging polyimide by a droplet discharging method, followed by drying and baking. The etched crystalline semiconductor film containing the catalyst element and the donor element becomes the first semiconductor regions 824 to 826 shown in FIG. 23A, and the etched crystalline semiconductor film 813 becomes the second semiconductor region 821. To 823.

  Next, a third mask 827 is formed in a region to be a later n-channel TFT. Here, polyimide is discharged by a droplet discharge method and dried to form a third mask 827 that covers the second semiconductor region 821 and the first semiconductor region 824 to be n-channel TFTs later. Although not shown, a third mask 827 is formed in the first semiconductor region and the second semiconductor region to be the switching TFT.

  Next, an acceptor element is added to the first semiconductor regions 825 and 826 which will be p-channel TFTs later, so that p-type semiconductor regions 831 and 832 are formed as shown in FIG.

  Next, although not shown, a part of the first insulating films 805 and 806 formed over the first conductive layer 803 functioning as the gate electrode of the driving TFT is etched to form the first function as the gate electrode. A part of the conductive layer 803 is exposed.

  Next, second conductive layers 833 and 834 having a thickness of 500 to 1000 nm are formed on the surfaces of the first semiconductor region 824, the p-type semiconductor regions 831 and 832, and the second semiconductor regions 821 to 823. Here, an Ag paste is discharged by a droplet discharge method and baked to form a third conductive layer.

  Next, a photosensitive material 835 is applied or ejected, the photosensitive material is irradiated with a laser beam 836 using a laser beam direct drawing apparatus, and the photosensitive material is exposed and developed to form a fourth mask. The third conductive layer is etched to form fourth conductive layers 841 to 845 that function as signal lines, scan lines, power supply lines, source electrodes, or drain electrodes, as shown in FIG.

  Here, a top view of B-B 'and C-C' of the pixel is shown in FIG. Through the above steps, a fourth conductive layer 901 which functions as a signal line and functions as a drain electrode and a fourth conductive layer 902 which is provided over a source region or a drain region of a later switching TFT is formed. Further, a fourth conductive layer 844 that functions as a power supply line and a fourth conductive layer 845 that functions as a drain electrode are formed over a source region or a drain region of a later driving TFT.

  Note that the drain electrode 902 of the switching TFT and the first conductive layer 803 functioning as the gate electrode of the driving TFT are connected through a contact hole 909.

  A top view of the drive circuit A-A 'is shown in FIG.

  Further, in this step, the third conductive layer is divided to form each signal line, power supply line, scanning line, and drain electrode, and etching is performed so that the width of the drain wiring is narrowed. It is possible to increase the aperture ratio of the display device. Here, a positive photosensitive material is used as the photosensitive material 835, and a fourth mask is formed by irradiation with a laser beam 830.

  Next, the first semiconductor regions 824, 831, and 832 are etched while leaving the fourth mask, so that source and drain regions 847 to 852 are formed. At this time, part of the second semiconductor regions 821 to 823 is also etched. The etched third semiconductor regions 854 to 856 function as channel formation regions.

  Here, the case where the driver circuit is formed using a single-channel structure, typically an n-channel TFT, will be described with reference to FIGS. FIG. 37 shows a top view of an inverter formed by an n-type TFT 1855 and a resistor 1856. Note that the resistor 1856 is formed by connecting one of a source electrode or a drain electrode of an n-channel TFT and a gate electrode.

  Semiconductor regions 854 and 855 are formed on the gate electrodes 801 and 802, respectively, via a gate insulating film. In addition, an n-type semiconductor region is formed in each semiconductor region, and fourth conductive layers 841, 842, and 843 are formed thereon.

  A fourth conductive layer 842 is formed to cover the third semiconductor region 854 and the third semiconductor region 855. The fourth semiconductor layer 842 connects the two semiconductor regions.

  A fourth conductive layer 842 is formed over the third semiconductor region 854. Further, a fourth conductive layer 843 is formed over the third semiconductor region 855. Further, before forming the fourth conductive layer, a part of the gate insulating film is etched to expose the gate electrode 802, and then the fourth conductive layer is formed, whereby the fourth conductive layer 843 and A gate electrode 802 is connected through a contact hole 859. For this reason, the resistor 1856 can be formed. Therefore, an inverter can be formed by connecting the n-type TFT 1855 and the resistor 1856 adjacent to each other.

    Note that the driver circuit may be formed using a single-channel structure of a p-channel TFT instead of a single-channel structure of an n-channel TFT.

  Next, as shown in FIG. 23C, after the fourth mask is removed, a second insulating film 857 and a third insulating film 858 are formed over the surface of the fourth conductive layer and the third semiconductor region. Form. Here, a 150-nm-thick silicon oxynitride film (SiON (O> N) containing hydrogen is formed by a CVD method as the second insulating film, and a 200-nm-thick silicon nitride film is formed as the third insulating film. The silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, the third semiconductor regions 854 to 856 are heated and hydrogenated. Here, by performing heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the second insulating film 857 is added to the third semiconductor regions 854 to 856 and hydrogenated.

  Next, as illustrated in FIG. 24A, a fourth insulating film 871 is formed over the third insulating film 858. Here, the fourth insulating film 871 is formed by applying and baking acrylic. Next, after a fifth mask is formed over the fourth insulating film 871, the fourth insulating film 871, the third insulating film 858, and the second insulating film 857 are etched to form the switching TFT. A part of the first conductive layer 804 functioning as a gate electrode is exposed. Next, a fifth conductive layer 872 functioning as a scan line connected to the first conductive layer 804 is formed. Here, after the Ag paste is discharged and fired by a droplet discharge method, a part of the Ag paste is etched using a mask formed by a laser beam direct writing apparatus to reduce the wiring width, and the fifth conductive Layer 872 is formed.

  Through the above steps, a driving circuit (A)-(A ′) formed by a CMOS circuit in which an n-channel TFT 861 and a p-channel TFT 862 are connected, and a driving TFT formed by a p-channel TFT 863, n A pixel portion having a switching TFT formed of a channel type TFT can be formed. In this embodiment, the driver circuit is formed of an n-channel TFT and a p-channel TFT, but the driver circuit and the pixel portion may be formed of only an n-channel TFT.

  Next, a fifth insulating film 873 is formed. The fifth insulating film 873 can be formed using a material similar to that of the fourth insulating film as appropriate. Here, acrylic is used for the fifth insulating film 873. Next, after a sixth mask is formed over the fifth insulating film 873, the fifth insulating film to the second insulating film are etched to expose part of the fourth conductive layer 845.

Next, a sixth conductive layer with a thickness of 100 to 300 nm is formed so as to be in contact with the fourth conductive layer 845. As a material for the sixth conductive layer, a light-transmitting conductive film or a reflective conductive film can be given. As a method for forming the sixth conductive layer, a droplet discharge method, a coating method, a sputtering method, a vapor deposition method, a CVD method, or the like is appropriately used. Note that when a coating method, a sputtering method, a vapor deposition method, a CVD method, or the like is used, a conductive layer is formed by etching a conductive film after forming a mask by a droplet discharge method, exposure using a laser beam direct drawing apparatus, or the like. To do. Here, indium tin oxide (ITO) containing, as a main component, aluminum having excellent reflectivity, an alloy material containing at least one of nickel, cobalt, iron, carbon and silicon as a lower layer and silicon oxide thereon A sixth conductive layer 874 functioning as a pixel electrode is formed by forming a film by sputtering and etching into a desired shape.

  A top view of the pixel B-B 'is shown in FIG. The fifth conductive layer 872 is connected to the sixth conductive layer 874 functioning as a pixel electrode in the contact hole 911.

  Through the above steps, an active matrix substrate can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (scanning line) or in the pixel portion. In this case, the TFT can be manufactured by the same process as the above-described TFT, and can be operated as a diode by connecting the scanning line layer of the pixel portion and the drain or source wiring layer of the diode.

  Next, as illustrated in FIG. 24B, a sixth insulating film 881 that covers an end portion of the sixth conductive layer 874 is formed. Here, the sixth insulating film 881 is formed using a negative photosensitive material.

  Next, a layer 882 containing a light-emitting substance is formed over the surface of the sixth conductive layer 874 and the end portion of the sixth insulating film 881 by an evaporation method, a coating method, a droplet discharge method, or the like. After that, a seventh conductive layer 883 that functions as a second pixel electrode is formed over the layer 882 containing a light-emitting substance. Here, ITO containing silicon oxide is formed by a sputtering method. As a result, a light-emitting element can be formed using the sixth conductive layer, the layer containing a light-emitting substance, and the seventh conductive layer. The materials of the conductive layer and the layer containing a light-emitting substance that constitute the light-emitting element are appropriately selected, and the thicknesses of the layers are also adjusted.

Note that before the layer 882 containing a light-emitting substance is formed, heat treatment is performed at 200 to 350 ° C. in atmospheric pressure to remove moisture adsorbed in or on the surface of the sixth insulating film 881. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and the layer 882 containing a light-emitting substance is not exposed to the air as it is, and a layer 882 containing a luminescent material is deposited by a vacuum deposition method or a droplet discharge method at atmospheric pressure or reduced pressure. Furthermore, it is preferable to form by a coating method or the like.

  The layer 882 containing a light-emitting substance is formed using a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light-emitting material. Based on the number of molecules, the layer 882 is a low molecular organic compound or a medium molecular organic compound (having no sublimation, An organic compound having a molecular length of 10 μm or less, typically a dendrimer, an oligomer, etc.), and one or a plurality of types of layers selected from high molecular organic compounds. You may combine with the inorganic compound of a hole injection transport property.

Among the charge injecting and transporting materials, materials having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton.

As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: Aromatic amine systems such as TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring— Compound having a nitrogen bond).

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, materials having a high hole injecting property include, for example, molybdenum oxide (MoO _x ), vanadium oxide (VO _x ), ruthenium oxide (RuO _x ), and tungsten oxide (WO _x ). And metal oxides such as manganese oxide (MnO _x ). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, by providing a filter (colored layer) that transmits light in the emission wavelength band on the light emission side of the pixel, the color purity is improved and the pixel portion is mirrored (reflected). Prevention can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various materials for the light emitting material forming the light emitting layer. Among the low molecular weight organic light emitting materials, 4-dicyanomethylene-2-methyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DCJT), 4- Dicyanomethylene-2-t-butyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DPA), perifuranthene, 2,5-dicyano-1, 4-bis (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-enyl) benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8 - quinolinolato) aluminum (abbreviation: Alq _3), 9,9'-bianthryl, 9,10-diphenyl anthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthracene ( Abbreviations: DNA) and the like can be used. Other substances may also be used.

  On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the polymer organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used, and is a layer / anode containing a cathode / light emitting substance. However, when forming a layer containing a light emitting material using a high molecular weight organic light emitting material, it is difficult to form a layered structure as in the case of using a low molecular weight organic light emitting material, and in many cases two layers are formed. It becomes a structure. Specifically, the structure is cathode / light-emitting layer / hole transport layer / anode.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. Moreover, when forming a light emitting layer by the apply | coating method using spin coating, after apply | coating, it is preferable to bake by vacuum heating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the layer containing the light-emitting substance listed above are examples, such as a hole injecting and transporting layer, a hole transporting layer, an electron injecting and transporting layer, an electron transporting layer, a light emitting layer, an electron blocking layer, and a hole blocking layer. A light-emitting element can be formed by appropriately stacking functional layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved.

  Next, a transparent protective layer that covers the light emitting element and prevents moisture from entering is formed. As the transparent protective layer, a silicon nitride film, a silicon oxide film, a silicon oxynitride film (SiNO film (composition ratio N> O) or SiON film (composition ratio N <O)) obtained by sputtering or CVD, and carbon are used. A thin film (eg, a DLC film or a CN film) having a main component can be used.

  Through the above steps, an active matrix substrate having a light-emitting element can be manufactured. Note that any of Embodiment Modes 1 to 19 can be applied to this example.

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIG.

  In FIG. 28A, the first pixel electrode 2011 is formed using a light-transmitting conductive film having a high work function, and the second pixel electrode 2017 is formed using a conductive film having a low work function. It is an example. The first pixel electrode 2011 is formed using a light-transmitting oxide conductive material, and is typically formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. A layer 2016 containing a light-emitting substance in which a hole injection layer or hole transport layer 2041, a light-emitting layer 2042, and an electron transport layer or electron injection layer 2043 are stacked is provided thereover. The second pixel electrode 2017 is formed of a first electrode layer 2033 containing an alkali metal or an alkaline earth metal such as LiF or MgAg and a second electrode layer 2034 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 2011 side as indicated by an arrow in the drawing.

  In FIG. 28B, the first pixel electrode 2011 is formed using a conductive film having a high work function, and the second pixel electrode 2017 is formed using a light-transmitting conductive film having a low work function. It is an example. The first pixel electrode 2011 includes a first electrode layer 2035 formed using a metal material such as aluminum or titanium, or a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of the metal, and silicon oxide 1-15. The second electrode layer 2032 is formed using a stacked structure of an oxide conductive material containing at a concentration of atomic%. A layer 2016 containing a light-emitting substance in which a hole injection layer or hole transport layer 2041, a light-emitting layer 2042, and an electron transport layer or electron injection layer 2043 are stacked is provided thereover. The second pixel electrode 2017 is formed of a first electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF and a second electrode layer 2034 formed of a metal material such as aluminum. By setting any layer of the second pixel electrode to a thickness of 100 nm or less so that light can be transmitted, light can be emitted from the second pixel electrode 2017 as indicated by arrows in the drawing. It becomes possible.

  FIG. 28E illustrates an example in which light is emitted from both directions, that is, the first electrode and the second electrode. A conductive film having a light-transmitting property and a high work function is provided on the first pixel electrode 2011. In addition, a conductive film having a light-transmitting property and a low work function is used for the second pixel electrode 2017. Typically, the first pixel electrode 2011 is formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 2017 is formed of LiF having a thickness of 100 nm or less. By forming the first electrode layer 2033 containing an alkali metal or alkaline earth metal such as CaF or the like and the second electrode layer 2034 formed of a metal material such as aluminum, as shown by the arrows in the figure, Light can be emitted from both sides of the first pixel electrode 2011 and the second pixel electrode 2017.

  In FIG. 28C, the first pixel electrode 2011 is formed using a light-transmitting conductive film having a low work function, and the second pixel electrode 2017 is formed using a conductive film having a high work function. It is an example. A structure in which a layer containing a light-emitting substance is stacked in the order of an electron-transport layer or electron-injection layer 2043, a light-emitting layer 2042, a hole-injection layer or a hole-transport layer 2041 is shown. The second pixel electrode 2017 includes a second electrode layer 2032 formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the layer 2016 containing a light-emitting substance, a metal such as aluminum or titanium, Alternatively, the first electrode layer 2035 is formed using a stacked structure of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio to the metal. The first pixel electrode 2011 is formed of a first electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF and a second electrode layer 2034 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the first pixel electrode 2011 as indicated by an arrow in the figure.

  In FIG. 28D, the first pixel electrode 2011 is formed using a conductive film having a low work function, and the second pixel electrode 2017 is formed using a light-transmitting conductive film having a high work function. It is an example. A structure in which a layer containing a light-emitting substance is stacked in the order of an electron-transport layer or electron-injection layer 2043, a light-emitting layer 2042, a hole-injection layer or a hole-transport layer 2041 is shown. The first pixel electrode 2011 has a structure similar to that in FIG. 28A and is formed to have a thickness enough to reflect light emitted from a layer containing a light-emitting substance. The second pixel electrode 2017 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, the hole injection layer 2041 is formed using an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), so that oxygen introduced when the second electrode layer 2032 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered. Further, by forming the second pixel electrode 2017 with a light-transmitting conductive layer, light can be emitted from both sides of the second pixel electrode 2017 as shown by arrows in the drawing. Become.

  FIG. 28F illustrates an example in which light is emitted from both directions, that is, from the first pixel electrode and the second pixel electrode. The first pixel electrode 2011 has a light-transmitting property and has a small work function. A film is used, and a conductive film having a light-transmitting property and a high work function is used for the second pixel electrode 2017. Typically, the first pixel electrode 2011 is formed using a first electrode layer 2033 containing an alkali metal or alkaline earth metal such as LiF or CaF having a thickness of 100 nm or less and a metal material such as aluminum. The second pixel electrode 2017 may be formed using an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%.

  A pixel circuit of the light-emitting display panel described in the above embodiment and an operation configuration thereof will be described with reference to FIGS. There are two types of operation configurations of the light-emitting display panel in which a video signal input to a pixel is defined by a voltage and a current is defined by a current in a display device in which a video signal is digital. There are two types of video signals defined by voltage, one having a constant voltage applied to the light emitting element (CVCV) and one having a constant current applied to the light emitting element (CVCC). In addition, a video signal is defined by current, there are a constant voltage applied to the light emitting element (CCCV) and a constant current applied to the light emitting element (CCCC). In this embodiment, a pixel performing a CVCV operation will be described with reference to FIGS. A pixel that performs the CVCC operation will be described with reference to FIGS.

  In the pixel shown in FIGS. 29A and 29B, a signal line 3710 and a power supply line 3711 are arranged in the column direction, and a scanning line 3714 is arranged in the row direction. In addition, the pixel includes a switching TFT 3701, a driving TFT 3703, a capacitor element 3702, and a light emitting element 3705.

  Note that the switching TFT 3701 and the driving TFT 3703 operate in a linear region when turned on. The driving TFT 3703 has a role of controlling whether or not a voltage is applied to the light emitting element 3705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. In this embodiment, the switching TFT 3701 is an n-channel TFT and the driving TFT 3703 is a p-channel TFT. The driving TFT 3703 may be a depletion type TFT as well as an enhancement type. The ratio (W / L) of the channel width W to the channel length L (W / L) of the driving TFT 3703 is preferably 1 to 1000 depending on the mobility of the TFT. The larger the W / L, the better the electrical characteristics of the TFT.

  In the pixels shown in FIGS. 29A and 29B, the switching TFT 3701 controls input of a video signal to the pixel. When the switching TFT 3701 is turned on, the video signal is input into the pixel. Then, the voltage of the video signal is held in the capacitor 3702.

  In FIG. 29A, when the power supply line 3711 is Vss and the counter electrode of the light emitting element 3705 is Vdd, that is, in FIGS. 29C and 29D, the counter electrode of the light emitting element is an anode, and the driving TFT 3703 The electrode connected to is a cathode. In this case, luminance unevenness due to characteristic variations of the driving TFT 3703 can be suppressed.

  In FIG. 29A, when the power supply line 3711 is Vdd and the counter electrode of the light emitting element 3705 is Vss, that is, in FIGS. 29A and 29B, the counter electrode of the light emitting element is a cathode, and the driving TFT 3703 The electrode connected to is the anode. In this case, when a video signal having a voltage higher than Vdd is input to the signal line 3710, the voltage of the video signal is held in the capacitor 3702, and the driving TFT 3703 operates in a linear region. It is possible to improve.

  The pixel shown in FIG. 29B has the same pixel structure as that shown in FIG. 29A except that a TFT 3706 and a scanning line 3715 are added.

  The TFT 3706 is controlled to be turned on or off by a newly arranged scanning line 3715. When the TFT 3706 is turned on, the charge held in the capacitor 3702 is discharged, and the driving TFT 3703 is turned off. That is, the arrangement of the TFT 3706 can forcibly create a state in which no current flows through the light emitting element 3705. Therefore, the TFT 3706 can be called an erasing TFT. Therefore, the structure in FIG. 29B can improve the light emission duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. Is possible.

  In the pixel having the above operation configuration, the current value of the light-emitting element 3705 can be determined by the driving TFT 3703 that operates in a linear region. With the above structure, variation in TFT characteristics can be suppressed, and luminance unevenness of a light-emitting element due to variation in TFT characteristics can be improved, so that a display device with improved image quality can be provided.

  Next, a pixel that performs the CVCC operation will be described with reference to FIGS. The pixel illustrated in FIG. 29C is provided with a power supply line 3712 and a current control TFT 3704 in the pixel configuration illustrated in FIG.

  The pixel shown in FIG. 29E is different from the pixel shown in FIG. 29C except that the gate electrode of the driving TFT 3703 is connected to the power supply line 3712 arranged in the row direction. It is a configuration. That is, both pixels shown in FIGS. 29C and 29E show the same equivalent circuit diagram. However, in the case where the power supply line 3712 is arranged in the row direction (FIG. 29C) and in the case where the power supply line 3712 is arranged in the column direction (FIG. 29E), each power supply line has a different layer. It is formed of a conductive film. Here, attention is paid to the wiring to which the gate electrode of the driving TFT 3703 is connected, and FIGS. 29C and 29E are shown separately in order to show that the layers for producing these are different.

  Note that the switching TFT 3701 operates in a linear region, and the driving TFT 3703 operates in a saturation region. The driving TFT 3703 has a role of controlling a current value flowing through the light emitting element 3705, and the current controlling TFT 3704 has a role of operating in a saturation region and controlling supply of current to the light emitting element 3705.

  29D and 29F are the same as those shown in FIGS. 29C and 29E, respectively, except that an erasing TFT 3706 and a scanning line 3715 are added. The pixel configuration is the same as shown in (E).

Note that the CVCC operation can also be performed in the pixels shown in FIGS. 29A and 29B. In addition, in the pixel having the operation configuration shown in FIGS. 29C to 29F, Vdd and Vss are appropriately changed depending on the direction of current flow of the light-emitting element, as in FIGS. 29A and 29B. Is possible.

  In the pixel having the above structure, since the current control TFT 3704 operates in a linear region, a slight change in Vgs of the current control TFT 3704 does not affect the current value of the light emitting element 3705. That is, the current value of the light emitting element 3705 can be determined by the driving TFT 3703 operating in the saturation region. With the above structure, it is possible to provide a display device in which luminance unevenness of a light-emitting element due to variation in TFT characteristics is improved and image quality is improved.

  Note that although a structure including the capacitor 3702 is shown, the present invention is not limited to this, and the capacitor 3702 is not provided in the case where the capacity for holding a video signal can be covered by a gate capacitor or the like. May be.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

As described above, various pixel circuits can be employed.

  In this embodiment, as an example of a display panel, the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 27A is a top view of a panel in which a space between a first substrate and a second substrate is sealed with a first sealant 1205 and a second sealant 1206. FIG. ) Corresponds to cross-sectional views taken along lines AA ′ and BB ′ in FIG.

  In FIG. 27A, reference numeral 1202 indicated by a dotted line denotes a pixel portion, and 1203 denotes a scanning line (gate line) driving circuit. In this embodiment, the pixel portion 1202 and the scanning line driver circuit 1203 are in a region sealed with a first sealing material and a second sealing material. Reference numeral 1201 denotes a signal line (source line) driver circuit, and a chip-like signal line driver circuit is provided over the first substrate 1200. As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. As the second sealing material, it is preferable to use an epoxy resin having a low viscosity. In addition, the first sealing material 1205 and the second sealing material are desirably materials that do not transmit moisture and oxygen as much as possible.

Further, a desiccant may be provided between the pixel portion 1202 and the first sealant 1205. Further, in the pixel portion, a desiccant may be provided on the scan line or the signal line. As the desiccant, it is preferable to use a substance that adsorbs water (H ₂ O) by chemical adsorption such as an oxide of an alkaline earth metal such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  In addition, the resin can be fixed to the second substrate 1204 in a state where a highly moisture-permeable resin contains a granular material of a desiccant. Here, examples of the highly moisture-permeable resin include acrylic resins such as ester acrylate, ether acrylate, ester urethane acrylate, ether urethane acrylate, butadiene urethane acrylate, special urethane acrylate, epoxy acrylate, amino resin acrylate, and acrylic resin acrylate. Can be used. In addition, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type Epoxy resins such as epoxy resins, glycidyl ester resins, glycidylamine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Further, other substances may be used. Further, for example, inorganic substances such as siloxane polymer, polyimide, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like may be used.

  You may provide a desiccant in the area | region which overlaps with a scanning line. Furthermore, you may fix to the 2nd board | substrate in the state which included the granular substance of the desiccant in resin with high moisture permeability. By providing these desiccants, it is possible to suppress the intrusion of moisture into the display element and the deterioration caused thereby without reducing the aperture ratio. For this reason, it is possible to suppress variations in deterioration of the light emitting elements in the peripheral portion and the central portion of the pixel portion 1202.

  Reference numeral 1210 denotes a connection wiring region for transmitting signals input to the signal line driver circuit 1201 and the scanning line driver circuit 1203. The connection wiring 1208 is connected from an FPC (flexible printed wiring) 1209 serving as an external input terminal. Receive video signals and clock signals.

  Next, a cross-sectional structure will be described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1200, and includes a plurality of semiconductor elements typified by TFTs. A scan line driver circuit 1203 and a pixel portion 1202 are shown as driver circuits. Note that as the scan line driver circuit 1203, a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined is formed.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the display device can be reduced.

  The pixel portion 1202 is formed of a plurality of pixels including a switching TFT 1211, a driving TFT 1212, and a first pixel electrode (anode) 1213 made of a reflective conductive film electrically connected to the drain electrode thereof. The

  Further, the gate electrode 1231 of the switching TFT and the scanning line 1214 are connected through the first insulator 1232 and the gate insulating film. Note that the switching TFT and the gate electrode of the TFT of the driver circuit are also connected to the scanning line through the first insulator and the gate insulating film, respectively.

  In addition, a second insulator 1233 is formed over the first insulator 1232, and the scan line 1214 and the first pixel electrode 1213 are formed through the second insulator 1233.

  A third insulator (called a bank, a partition, a barrier, a bank, or the like) 1234 is formed at both ends of the first pixel electrode (anode) 1213. In order to improve the coverage (coverage) of the film formed over the third insulator 1234, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the third insulator 1234. The surface of the third insulator 1234 may be covered with an aluminum nitride film, an aluminum nitride oxide film, a thin film containing carbon as its main component, or a protective film made of a silicon nitride film. Further, as the third insulator 1234, an organic material obtained by dissolving or dispersing a material that absorbs visible light such as a black pigment or a dye is used to absorb stray light from a light-emitting element that is formed later. Can do. As a result, the contrast of each element is improved.

  Further, an organic compound material is deposited on the first pixel electrode (anode) 1213 to selectively form a layer 1215 containing a light-emitting substance. Further, a second pixel electrode (cathode) is formed over the layer 1215 containing a light-emitting substance.

  For the layer 1215 containing a light-emitting substance, the structure shown in Embodiment 2 can be used as appropriate.

  In this manner, a light-emitting element 1217 including the first pixel electrode (anode) 1213, the layer 1215 containing a light-emitting substance, and the second pixel electrode (cathode) 1216 is formed.

In addition, a protective stack 1218 is formed in order to seal the light emitting element 1217. The protective laminate includes a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film. Next, the protective laminate 1218 and the second substrate 1204 are bonded with the first sealant 1205 and the second sealant 1206. Note that the second sealant is preferably dropped using a device for dropping the sealant. After the sealing material is dropped or discharged from the dispenser to apply the sealing material onto the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum and then cured by ultraviolet curing. it can.

  Note that an antireflection film 1226 is provided on the surface of the second substrate 1204 to prevent external light from being reflected by the substrate surface. One or both of a polarizing plate and a retardation plate may be provided between the second substrate and the antireflection film. By providing the retardation plate and the polarizing plate, it is possible to prevent external light from being reflected by the pixel electrode. Note that the first pixel electrode 1213 and the second pixel electrode 1216 are formed using a light-transmitting conductive film or a semi-transparent conductive film, and the second insulator 1233 and the third insulator 1234 are formed. When using a material that absorbs visible light or an organic material that dissolves or disperses a material that absorbs visible light, external light is not reflected by each pixel electrode, so a retardation plate and a polarizing plate are not used. Good.

  The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Note that a space filled with an inert gas such as nitrogen gas may be provided between the second substrate 1204 and the protective laminate 1218 instead of the second sealant 1206. It is possible to enhance prevention of moisture and oxygen from entering.

Further, a colored layer can be provided between the second substrate and the polarizing plate. In this case, a full color display can be performed by providing a light emitting element capable of emitting white light in the pixel portion and separately providing a colored layer showing RGB. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Furthermore, each pixel portion, a light emitting element that emits red, green, and blue light can be formed, and a colored layer can be used. Such a display module has high color purity of each RBG and enables high-definition display.

  Alternatively, the light-emitting display module may be formed using one of the first substrate 1200 and the second substrate 1204, or a substrate such as a film or resin. When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

  Further, an IC chip such as a controller, a memory, and a pixel driver circuit may be provided on the surface or end of an FPC (flexible printed wiring) 1209 that serves as an external input terminal to form a light emitting display module.

  Note that any of Embodiment Modes 1 to 19 can be applied to this example.

    In this embodiment, a structure of a scanning line input terminal and a signal line input terminal provided in the periphery of the substrate will be described with reference to FIG. 35 (A), (C) and (E) are top views of the periphery of the substrate, respectively, and FIGS. 35 (B), (D) and (F) are FIGS. 35 (A) and (C), respectively. It is a longitudinal cross-sectional view of (K)-(L) and (M)-(N) of (E). Note that (K)-(L) is a longitudinal sectional view of the scanning line input terminal, and (M)-(N) is a longitudinal sectional view of the signal line input terminal.

  As shown in FIGS. 35A and 35B, the first substrate 11 and the second substrate 21 are sealed with a sealant 20, and the first substrate 11 and the second substrate 21 are sealed in the first substrate. A pixel portion in which the pixel electrode 19 and the pixel TFT 1 are arranged is formed. In addition, an insulator 27 is formed to cover an end portion of the first pixel electrode 19, and a layer 29 containing a luminescent material and a second pixel electrode 30 are formed on the surfaces of the insulator 27 and the first pixel electrode 19. The light emitting element is formed by the first pixel electrode, the layer 29 containing a light emitting substance, and the second pixel electrode 30.

  In FIGS. 35A and 35B, the scanning line input terminal 13 and the signal line input terminal 26 are formed by the same process as the gate electrode 12 of the TFT 1. The scanning line input terminal 13 is connected to each gate electrode via a scanning line 17 formed on the first interlayer insulating film 16. The signal line input terminal 26 is connected to the power supply lines 14a and 14b and the signal line 14c, respectively.

  The first pixel electrode 19 is formed on the second interlayer insulating film 18 formed on the first interlayer insulating film 16. Note that the first pixel electrode is connected to the drain electrode 15 through the first interlayer insulating film 16 and the second interlayer insulating film 18.

  The scanning line input terminal 13 and the signal line input terminal 26 are connected to the FPCs 24 and 25 via connection layers 22 and 23, respectively. In FIG. 35A, the connection layers 22 and 23 and the FPCs 24 and 25 are indicated by broken lines.

  35C and 35D, the scanning line input terminal 33 is formed in the same process as the power supply lines 14a, 14b and the signal line 14c, and the signal line input terminal 26 is connected to the power supply lines 14a, 14b, It is a part of each signal line 14c. The scanning line input terminal 33 and the gate electrode 12 are connected by a scanning line 17 formed on the first interlayer insulating film 16.

  Other structures are similar to those in FIGS. 35A and 35B.

  In FIGS. 35E and 35F, the scanning line input terminal is a part of the scanning line 43, and the signal line input terminal 44 is formed simultaneously with the scanning line 43. That is, each input terminal is formed simultaneously with the scanning line 43. The signal line input terminal 44 is formed on the exposed power supply lines 14a, 14b, and signal lines 14c after the first interlayer insulating film formed on the power supply lines 14a, 14b, and signal lines 14c is removed. Is done.

  Other structures are similar to those in FIGS. 35A and 35B.

  Note that although this example is described using the structure of the TFT shown in Embodiment Mode 1, it can be appropriately applied to Embodiment Modes 2 to 19.

  An example of a protection circuit included in the display device of the present invention will be described. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, a configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 36A includes P-type TFTs 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit shown in FIG. 36B is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with diodes 7260 and 7270 having rectifying properties. The protection circuit shown in FIG. 36C is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. In addition, as a protection circuit having a different structure from the above, the protection circuit illustrated in FIG. 36D includes resistors 7280 and 7290 and an N-type TFT 7300. The protection circuit illustrated in FIG. 36E includes resistors 7280 and 7290, a P-type TFT 7310, and an N-type TFT 7320. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment can be freely combined with the above embodiment modes.

  In this embodiment, mounting of a driver circuit on the light-emitting panel described in the above embodiment will be described with reference to FIGS.

  As shown in FIG. 30A, a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b are mounted around the pixel portion 1401. In FIG. 30A, as a signal line driver circuit 1402 and scanning line driver circuits 1403a and 1403b, a mounting method using a known anisotropic conductive adhesive and anisotropic conductive film, a COG method, wire bonding, and the like. The IC chip 1405 is mounted on the substrate 1400 by a method, a reflow process using a solder bump, or the like. Here, the COG method is used. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  As shown in FIG. 30B, when a semiconductor element typified by a TFT such as a SAS or a crystalline semiconductor is formed, the pixel portion 1401 and the scan line driver circuits 1403a and 1403b are integrally formed over the substrate. In some cases, the signal line driver circuit 1402 or the like is separately mounted as an IC chip. In FIG. 30B, an IC chip 1405 is mounted on a substrate 1400 as a signal line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  Further, as shown in FIG. 30C, the signal line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 30C, the signal line driver circuit is mounted by a TAB method; however, the scan line driver circuit may be mounted by a TAB method.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which an IC is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor film obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor film has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  As an electronic device in which the display device described in the above embodiment is incorporated in a housing, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (simply a mobile phone or a mobile phone) Also, a portable information terminal such as a PDA, a portable game machine, a computer monitor, a computer, an audio reproduction device such as a car audio, and an image reproduction device including a recording medium such as a home game machine. A specific example thereof will be described with reference to FIG.

  A portable information terminal illustrated in FIG. 32A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  A digital video camera shown in FIG. 32B includes a display portion 9701, a display portion 9702, and the like. As the display portion 9701, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a digital video camera capable of high-quality display can be provided at low cost.

  A portable terminal illustrated in FIG. 32C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be applied. By using the display device which is one embodiment of the present invention, a portable terminal capable of high-quality display can be provided at low cost.

  A portable television device shown in FIG. 24D includes a main body 9301, a display portion 9302, and the like. As the display portion 9302, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable television device capable of high-quality display can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 32E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a portable computer capable of high-quality display can be provided at low cost.

  A television device illustrated in FIG. 32F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a television device capable of high-quality display can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

  A large television shown in FIG. 33 includes a main body 9601, a display portion 9602, and the like. A wall-supporting body is provided on the back or top of the main body. In FIG. 33, a wall-mounted television is shown as a typical example of a large television. As shown in FIG. 33, the image can be displayed over the wall 9603. In addition, the present invention can be applied to various uses as a display medium having a particularly large area, such as an information display board at a railway station or airport, or an advertisement display board in a street. As the display portion 9602, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the display device which is one embodiment of the present invention, a large television capable of high-quality display can be provided at low cost.

  According to the present invention, a semiconductor device that functions as a wireless chip (also referred to as a wireless processor, a wireless memory, or a wireless tag) can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 40A), packaging containers (wrapping paper, Bottle, etc., see FIG. 40 (C)), recording medium (DVD software, video tape, etc., see FIG. 40 (B)), vehicles (bicycles, etc., see FIG. 40 (D)), personal items (bags, glasses, etc.) ), Foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 40E and 40F) for use. be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The wireless chip is fixed to the article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing wireless chips on banknotes, coins, securities, bearer bonds, certificates, etc. In addition, by providing wireless chips in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. The wireless chip that can be formed according to the present invention is small, thin, and lightweight because it is provided on a cover material after a thin film integrated circuit formed over a substrate is peeled off by a known peeling process, and is mounted on an article. However, the design is not impaired. Furthermore, since it has flexibility, it can be used for a bottle or pipe having a curved surface.

  Further, by applying a wireless chip that can be formed according to the present invention to an object management or distribution system, it is possible to increase the functionality of the system. For example, by reading the information recorded on the wireless chip provided on the tag with a reader / writer provided on the side of the belt conveyor, information such as the distribution process and delivery destination is read, and inspection of goods and distribution of goods Can be done easily.

    A structure of a wireless chip that can be formed according to the present invention will be described with reference to FIGS. The wireless chip is formed with a thin film integrated circuit 9303 and an antenna 9304 connected thereto. Further, the thin film integrated circuit and the antenna are sandwiched between cover materials 9301 and 9302. The thin film integrated circuit 9303 may be bonded to the cover material with an adhesive. In FIG. 41, one thin film integrated circuit 9303 is bonded to a cover material 9301 with an adhesive 9305 interposed therebetween.

  The thin film integrated circuit 9303 is formed using the TFT shown in any of Embodiments 1 to 19, and then peeled off by a known peeling step and provided on the cover material. The semiconductor element used for the thin film integrated circuit 9303 is not limited to this. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used in addition to the TFT.

  As shown in FIG. 41, an interlayer insulating film 9311 is formed over the TFT of the thin film integrated circuit 9303, and an antenna 9304 connected to the TFT through the interlayer insulating film 9311 is formed. A barrier film 9312 made of a silicon nitride film or the like is formed over the interlayer insulating film 9311 and the antenna 9304.

  A method and material for forming the antenna 9304 will be described. As a method for forming the antenna 9304, a droplet discharge method, a dispenser method, a plating method, a printing method such as screen printing or gravure printing, a CVD method, a sputtering method, or the like can be used. By forming the antenna by a droplet discharge method, the number of steps can be reduced, and the cost can be reduced accordingly. As a material for the antenna 9304, aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum ( An element selected from Ta) and molybdenum (Mo), or an alloy material or a compound material containing these elements as main components can be used. Further, fine particles mainly composed of solder (preferably lead-free solder) may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder has the advantage of low cost. Moreover, ceramic, ferrite, or the like can be applied to the antenna.

  Cover materials 9301 and 9302 are a laminated film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), a paper made of a fibrous material, a base film (polyester, polyamide, an inorganic vapor deposition film, paper) Etc.) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The bonded film is one to be bonded to the object to be processed by thermocompression bonding. When performing the bonding process, the bonding film provided on the outermost surface of the bonded film or the outermost layer is used. The provided layer (not the adhesive layer) is melted by heat treatment and bonded by pressure.

In addition, by using an incineration-free pollution material such as paper, fiber, and carbon graphite for the cover material, the used wireless chip can be incinerated or cut. Further, wireless chips using these materials are non-polluting because they do not generate toxic gas even when incinerated.

  Note that in FIG. 41, the wireless chip is provided on the cover material 9301 with the adhesive 9305. However, instead of the cover material 9301, a wireless chip may be attached to an article and used.

8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating the structure of part of a display device according to the invention. FIG. 6 is a cross-sectional view illustrating the structure of part of a display device according to the invention. FIG. 6 is a cross-sectional view illustrating impurity concentration in a part of a semiconductor region of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating impurity concentration in a part of a semiconductor region of a display device according to the present invention. FIG. 6 is a cross-sectional view illustrating the structure of part of a display device according to the invention. FIG. 6 is a cross-sectional view illustrating the structure of part of a display device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a display device according to the present invention. FIG. 6 is a top view illustrating a structure of a pixel of a display device according to the present invention. FIG. 6 is a top view illustrating a structure of a driver circuit of a display device according to the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a structure of a light-emitting display panel according to the invention. FIG. 6 is a cross-sectional view illustrating a structure of a light-emitting element of a display device according to the present invention. 4A and 4B each illustrate a circuit of a light-emitting element of a display device according to the present invention. FIG. 6 is a top view illustrating a method for mounting a driver circuit of a display device according to the present invention. The figure explaining the laser beam direct writing apparatus applicable to this invention. 6A and 6B illustrate examples of electronic devices. 6A and 6B illustrate examples of electronic devices. 4A and 4B are a top view and cross-sectional views illustrating a structure of a display device according to the invention. 4A and 4B are a top view and a cross-sectional view illustrating a structure of a peripheral portion of a display device according to the invention. FIG. 6 is a circuit diagram illustrating a protection circuit. FIG. 6 is a top view illustrating a structure of a driver circuit of a display device according to the present invention. Sectional drawing explaining the manufacturing process of the display apparatus which concerns on this invention Sectional drawing explaining the manufacturing process of the display apparatus which concerns on this invention 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention.

Claims (4)

Forming a gate insulating film on the gate electrode;
Forming a first semiconductor film on the gate insulating film;
Forming a catalytic element layer having a catalytic element for promoting crystallization of a semiconductor on the first semiconductor film;
Forming a second semiconductor film to which an impurity element imparting n-type is added on the first semiconductor film and the catalytic element layer;
Heat-treating the first semiconductor film and the second semiconductor film;
Etching the second semiconductor film to form a first semiconductor region, and etching the first semiconductor film to form a second semiconductor region overlapping the first semiconductor region;
Forming a source electrode and a drain electrode on the first semiconductor region, and forming a signal line on the gate insulating film;
Etching the first semiconductor region to form a source region and a drain region;
Forming a first insulating film on the source electrode, the drain electrode, and the signal line;
Forming a first contact hole in the first insulating film and the gate insulating film;
Forming a scanning line electrically connected to the gate electrode through the first contact hole on the first insulating film;
Forming a second insulating film on the scanning line;
Forming a second contact hole in the second insulating film and the first insulating film;
Forming a pixel electrode of a display element electrically connected to one of the source electrode or the drain electrode through the second contact hole on the second insulating film;
The heat treatment causes the catalytic element to move from the catalytic element layer to the first semiconductor film to crystallize the first semiconductor film, and from the first semiconductor film to the second semiconductor film, the catalyst. Moving the element to crystallize the second semiconductor film;
The source region and the drain region have crystallinity and contain the catalytic element;
The gate electrode formed before the heat treatment is composed of a single layer or a stack of refractory material films,
The signal line formed after the heat treatment has gold, silver, copper, or aluminum,
The method for manufacturing a display device, wherein the scan line formed after the signal line is formed and after the heat treatment includes gold, silver, copper, or aluminum. In claim 1,
The method for manufacturing a display device, wherein the catalyst element layer is selectively formed. In claim 1 or claim 2,
The gate insulating film is composed of a stack of a silicon nitride film and a silicon oxide film provided on the silicon nitride film,
A first step of forming the silicon nitride film by a CVD method using silane gas and ammonia gas as raw materials in a chamber;
After the first step, a second step of forming the silicon oxide film by a CVD method using silane gas and nitrogen oxide as raw materials in the chamber;
After the second step, a third step of flowing only the silane gas into the chamber without generating plasma;
After the third step, a fourth step of forming the first semiconductor film by a CVD method using silane gas as a raw material,
The method for manufacturing a display device, wherein the first to fourth steps are continuously performed. In any one of Claims 1 thru | or 3,
A manufacturing method of a display device, wherein the second semiconductor film contains a rare gas.

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