JP2014030014A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits immersion of an impurity possibly causing variation in electrical characteristics into a semiconductor layer, and has stable electrical characteristics; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device having a structure (so-called top-contact structure) having a source electrode and a drain electrode on a semiconductor layer comprises a structure in which a semiconductor layer at a position which does not overlap the source electrode or the drain electrode is made thinner than a semiconductor layer at a position which overlaps the source electrode or the drain electrode; a recess is provided in the semiconductor layer; and a rising part from a bottom face to a lateral face of the recess has a curved shape. In the structure, a lateral face of the source electrode or the drain electrode and the lateral face of the recess have no level difference.

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, for example, a thin film transistor (TFT) or a display device including a TFT as a component (for example, a liquid crystal display device or an EL device). A display device and the like, and an electronic circuit (for example, a central processing unit (CPU)) including a TFT as a constituent element.

A technique for forming a semiconductor layer (at least a channel formation region) of a transistor by using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as a display device (for example, a liquid crystal display device and an EL display device) and an integrated circuit (for example, an LSI and a CPU). As a semiconductor material applicable to a semiconductor layer of a transistor, a silicon-based semiconductor material is widely known.

In recent years, an oxide semiconductor material has attracted attention as a semiconductor material that can be used for a semiconductor layer of a transistor. For example, an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) (In A transistor using a thin film formed of a (—Ga—Zn—O-based amorphous oxide) material as a semiconductor layer is disclosed (see Patent Document 1).

JP 2006-165527 A

In a transistor in which a semiconductor layer is formed using an oxide semiconductor material, an impurity (eg, moisture or hydrogen) from the outside enters the semiconductor layer, so that a change in electrical characteristics (eg, a decrease in mobility or a threshold) Value voltage fluctuation).

Similarly, in a transistor in which a semiconductor layer is formed using a silicon-based semiconductor material, the electrical characteristics fluctuate due to the entry of impurities from the outside into the semiconductor layer.

In view of the above contents, an object of this specification is to provide a semiconductor device having stable electrical characteristics in which impurities that may cause variation in electrical characteristics are prevented from entering the semiconductor layer. Another object is to provide a method for manufacturing the semiconductor device.

Impurity intrusion into the semiconductor layer is usually performed when there is a low-density portion or a portion where no film is formed (hereinafter also referred to as “po” in this specification) in the film covering the semiconductor layer. Most of the intrusions are through the void. Therefore, in order to suppress the intrusion of impurities into the semiconductor layer, it is effective to prevent the formation of voids in the semiconductor layer.

Therefore, in one embodiment of the present invention, in a semiconductor device having a structure including a source electrode and a drain electrode on a semiconductor layer (a so-called top contact structure), the semiconductor layer at a position not overlapping with the source electrode and the drain electrode is formed The structure is thinner than the semiconductor layer in a position overlapping with the drain electrode. That is, a portion of the semiconductor layer that does not overlap with the source electrode and the drain electrode is a recess, and a rising portion from the bottom surface to the side surface of the recess has a curved shape. Further, there is no step between the side surface of the source or drain electrode and the side surface of the recess.

The concept of the above contents will be described with reference to FIG.

One of the causes of the generation of the void 1005 in the insulating film 1006 is the shape of the surface for forming the insulating film 1006. 10 shows a top contact structure having a semiconductor layer 1002 over a substrate 1000, a source electrode 1003 and a drain electrode 1004 over the semiconductor layer 1002, and an insulating film 1006 covering the semiconductor layer 1002, the source electrode 1003 and the drain electrode 1004. It is a semiconductor element. For example, as in a region 1008 in FIG. 10A, when a source electrode and a drain electrode are formed, an oxide semiconductor film is over-etched to form a corner, so that the source electrode 1003, the drain electrode 1004, and the semiconductor layer are formed. When the insulating film 1006 is formed over 1002, a void 1005 is likely to be generated in the insulating film 1006 from the vicinity of the region 1008 toward the surface of the insulating film 1006.

On the other hand, in the structure of the semiconductor device described in this specification and the like, as illustrated in FIG. 10B, the recessed portion of the semiconductor layer 1002 has a curved shape from the bottom to the side. The semiconductor device has a structure in which there is no step between the side surface of the source electrode 1003 or the drain electrode 1004 and the side surface of the recess. Accordingly, generation of voids in the insulating film 1006 caused by unevenness at a boundary portion between the source electrode 1003 and the drain electrode 1004 and the semiconductor layer 1002 or a corner portion of the semiconductor layer 1002 can be suppressed.

That is, according to one embodiment of the present invention, a gate electrode over an insulating surface, a gate insulating layer in contact with the gate electrode, a semiconductor layer in contact with the gate insulating layer, a source electrode and a drain electrode in contact with the semiconductor layer, a semiconductor layer, and a source An insulating film in contact with the electrode and the drain electrode, and the semiconductor layer has a recess where the thickness of the portion that does not overlap with the source or drain electrode is smaller than the thickness of the portion that overlaps with the source or drain electrode The semiconductor device is characterized in that the rising portion from the bottom surface to the side surface of the recess has a curved shape, and there is no step between the side surface of the source or drain electrode and the side surface of the recess.

When the semiconductor device has the above structure, generation of voids in the insulating film caused by unevenness at the boundary portion between the source electrode or drain electrode and the semiconductor layer or a corner portion of the semiconductor layer can be suppressed. Therefore, a semiconductor device having stable electrical characteristics in which impurities that can cause variation in electrical characteristics are suppressed from entering the semiconductor layer can be provided.

Note that in the above structure, when the angle formed by the side surface of the source electrode or the side surface of the drain electrode with respect to the surface of the semiconductor layer is 30 ° or more and 80 ° or less, generation of voids in the insulating film can be further suppressed.

The source electrode and the drain electrode may have a stacked structure including a plurality of conductive films. In that case, generation of voids in the insulating film can be effectively suppressed by providing a structure in which there is no step between the side surface of the first layer of the conductive film and the side surface of the second layer of the conductive film. Can do. In addition, when the angle formed by the side surface of the conductive film with respect to the semiconductor layer surface is 30 ° or more and 80 ° or less, generation of voids in the insulating film can be further suppressed.

Note that in the above semiconductor device, a metal oxide film containing one or more elements selected from In, Ga, Sn, and Zn is preferably used as the semiconductor layer.

By using the above-described oxide semiconductor film as a semiconductor layer, a semiconductor device formed using the film can have higher mobility than the case where an amorphous silicon film is used as a semiconductor layer. Further, it does not require high temperature processing such as formation of a polycrystalline silicon film. Therefore, it can be used for various devices that require high-speed operation, ease of formation, and formation over a large area.

In the case where the above oxide semiconductor film is used as the semiconductor layer, the insulating film includes an oxygen-releasing film that can release oxygen of 1 × 10 ¹⁹ [atoms / cm ³ ] or more by heat treatment. desirable.

In an oxide semiconductor film, when oxygen vacancies exist in the film, part of the oxygen vacancies functions as a donor to adversely affect the characteristics of the semiconductor device (for example, a channel exists even when a gate voltage is not applied to the transistor). Current may flow, so-called transistor normally on). By forming the above oxygen-releasing film as the insulating film and performing heat treatment on the film, oxygen can be supplied to the oxide semiconductor film. Accordingly, oxygen vacancies in the oxide semiconductor film can be reduced, so that electrical characteristics of a semiconductor device using the oxide semiconductor film as a semiconductor layer can be improved.

Note that the above-mentioned “release oxygen by heat treatment” means that the amount of released oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more in TDS (Thermal Desorption Spectroscopy). It is preferably 3.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 1.0 × 10 ²⁰ molecules / cm ³ or more.

One embodiment of the present invention includes a step of forming a gate electrode over an insulating surface, a step of forming a gate insulating layer in contact with the gate electrode, a step of forming a semiconductor layer in contact with the gate insulating layer, Forming a conductive film on the semiconductor layer and selectively removing the conductive film and the semiconductor layer to form a source electrode and a drain electrode on the semiconductor layer and from the bottom surface to the side surface of the semiconductor layer. A step of forming a concave portion having a curved shape at a rising portion thereof, and a step of forming an insulating film covering the concave portion of the semiconductor layer and the source electrode and the drain electrode, and the side surface of the source electrode or the drain electrode and the side surface of the concave portion A method for manufacturing a semiconductor device is characterized in that there is no step between them.

By adopting the above-described method, there can be a structure in which there is no step between the side surface of the source or drain electrode and the side surface of the recess, and the insulating film that covers the recess and the source and drain electrodes of the semiconductor layer can be obtained. Generation of voids can be suppressed. Therefore, it is possible to manufacture a semiconductor device having stable electrical characteristics in which impurities that can cause variation in electrical characteristics are suppressed from entering the semiconductor layer.

Note that the film thickness at which the semiconductor layer is removed per minute by the removal treatment is preferably 1/10 or more and 1/3 or less of the film thickness of the semiconductor layer. Thereby, a product (for example, a reaction product of a constituent element of the semiconductor layer and a constituent element of the gas used for the removal process) generated by the removal process of the semiconductor layer is formed in order from the upper end of the side surface of the recess. The side surface of the recess is curved.

In the above manufacturing method, it is preferable to use a metal oxide film including one or more elements selected from In, Ga, Sn, and Zn as the semiconductor layer.

By using the above oxide semiconductor film as a semiconductor layer, a transistor having higher mobility than that in the case where an amorphous silicon film is used as a semiconductor layer can be formed. Further, the high temperature treatment as in the case of forming a polycrystalline silicon film as the semiconductor layer is not required.

In the case where the above oxide semiconductor film is used as the semiconductor layer, it is preferable to use an oxygen-releasing film that can release oxygen on 1 × 10 ¹⁹ [atoms / cm ³ ] by heat treatment as the insulating film.

In the oxide semiconductor film, when oxygen vacancies exist in the film, part of the oxygen vacancies may function as a donor and adversely affect the characteristics of the semiconductor device. Therefore, oxygen can be supplied to the oxide semiconductor film by forming the above-described oxygen release film as an insulating layer and performing heat treatment on the film after the oxygen release film is formed. Accordingly, oxygen vacancies in the oxide semiconductor film can be reduced.

In the semiconductor layer, a recess is formed in a portion that does not overlap with the source electrode or the drain electrode, and a rising portion from the bottom surface to the side surface of the recess has a curved shape, and the side surface of the source electrode and the drain electrode and the side surface of the recess The structure has no step between the two. With this structure, the semiconductor layer and the insulating film over the source and drain electrodes can be a film in which the generation of voids is suppressed, so that impurities that can cause fluctuations in electrical characteristics are prevented from entering the semiconductor layer. In addition, a semiconductor device having stable electrical characteristics can be provided.

In addition, a semiconductor film provided with a recess having a curved shape in which the rising portion from the bottom surface to the side surface is necessary for the semiconductor device, and a structure in which there is no step between the side surface of the source electrode and the drain electrode and the side surface of the recess. Therefore, a method for manufacturing a semiconductor device can be provided.

2A and 2B are a plan view and a cross-sectional view illustrating a structure of a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 10 is a plan view illustrating one embodiment of a semiconductor device. FIG. 6 is a plan view illustrating the structure of a display device. FIG. 14 is a cross-sectional view illustrating a structure of a display device. FIG. 14 is a cross-sectional view illustrating a structure of a display device. The top view and sectional drawing explaining the structure of an apparatus. 10A and 10B each illustrate an electronic device. FIG. 10 is a cross-sectional view illustrating the structure of a semiconductor device. FIG. 10 is a cross-sectional view illustrating the structure of a semiconductor device. STEM observation result photograph of the sample.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that in the embodiments described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

In addition, ordinal numbers such as “first”, “second”, and “third” in this specification and the like are added to avoid confusion of components, and are not limited numerically. To do.

Further, in this specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, if the expression “B on A” is used, an expression including another component between A and B is not excluded.

In this specification, “oxynitride” is a substance having a higher oxygen content than nitrogen as a composition, and “nitride oxide” is a composition containing nitrogen more than oxygen as nitrogen. It means a substance with a high content.

(Embodiment 1)
In this embodiment, an example of a structure of the semiconductor device is described with reference to FIGS. 1A to 1C, and an example of a method for manufacturing the semiconductor device is described with reference to FIGS.

<Configuration example of semiconductor device>
As an example of a semiconductor device, in this embodiment, a transistor 150 having a bottom-gate / top-contact structure is described with reference to FIGS. Note that FIG. 1 includes a wiring 114 which functions as a pixel electrode and is electrically connected to the transistor 150 and can be used for manufacturing a display device.

1A is a plan view of a structure including the transistor 150, and FIG. 1B is a cross-sectional view taken along one-dot chain line A1-A2 in FIG.

Note that in this embodiment, a structure of a transistor using an oxide semiconductor material as a semiconductor layer is described. Needless to say, the semiconductor layer is not limited to one using an oxide semiconductor material, but may be one using another semiconductor material (for example, a silicon-based semiconductor material).

In FIG. 1A, some components (for example, the substrate 100 and the partition 112) are not illustrated in order to facilitate understanding of positions of the components of the transistor 150.

As illustrated in FIG. 1, the transistor 150 using an oxide semiconductor material as a semiconductor layer includes a gate electrode 102 over a substrate 100, a gate insulating layer 104 over the gate electrode 102, and a semiconductor layer 106 over the gate insulating layer 104. The source electrode 108 and the drain electrode 109 on the semiconductor layer 106, and the first insulating film 110 and the second insulating film 111 that cover the semiconductor layer 106 and the source electrode 108 and drain electrode 109. Further, over the transistor 150, the drain electrode 109 is electrically connected to the partition 112 over the second insulating film 111 and the first insulating film 110, the second insulating film 111, and the opening provided in the partition 112. Connected wirings 114 are provided. Note that the wiring 114 can function as a pixel electrode.

As the semiconductor layer 106, various semiconductor films such as a silicon-based semiconductor film, a compound semiconductor film, and an oxide semiconductor film can be used; in this embodiment, an oxide semiconductor film is used as the semiconductor layer 106. Will be described.

In this embodiment mode, as illustrated in FIG. 1, the gate insulating layer 104 has a three-layer structure including a first gate insulating film 104a, a second gate insulating film 104b, and a third gate insulating film 104c. This is because an oxide semiconductor film is used as the semiconductor layer 106 in this embodiment.

First, in order to ensure the withstand voltage of the gate insulating layer 104, it is necessary to provide a film with an excellent withstand voltage (corresponding to the first gate insulating film 104a).

Examples of the film having an excellent withstand voltage include a silicon nitride film and a silicon oxynitride film.

However, these films are generally formed by a CVD method (for example, a plasma CVD method) using silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) as film formation gas species. It contains a large amount of hydrogen atoms.

In the case where an oxide semiconductor film is used as the semiconductor layer 106, when an oxygen vacancy occurs in the oxide semiconductor film, part of the oxygen vacancy functions as a donor, which adversely affects the characteristics of the transistor (for example, the transistor is normally May be turned on). Therefore, when a film containing a large amount of hydrogen atoms as described above is used for the gate insulating layer, the film is released from the film containing a large amount of hydrogen atoms by heat treatment or the like performed in the manufacturing process of the transistor 150. There is a possibility that hydrogen atoms are combined with oxygen in the oxide semiconductor film to be water, and are desorbed from the oxide semiconductor film to increase oxygen vacancies in the oxide semiconductor film.

Therefore, an insulating film having excellent hydrogen blocking properties (corresponding to the second gate insulating film 104b) is provided over the first gate insulating film 104a, and the semiconductor layer 106 and the second gate insulating film 104b are provided. An insulating film (corresponding to the third gate insulating film 104c) for reducing the interface state is provided.

The above three-layer structure in the gate insulating layer 104 is an example of a gate insulating layer that can be used when the semiconductor layer 106 is an oxide semiconductor film. A structure of the gate insulating layer 104 is described below. The user may select as appropriate in consideration of the material of the semiconductor layer 106, characteristics required for the transistor 150, and the like.

For example, in the case where dielectric breakdown resistance is sufficiently ensured only by the third gate insulating film 104c, the first gate insulating film 104a and the second gate insulating film 104b are not necessarily provided.
In the case where a silicon-based semiconductor material is used for the semiconductor layer 106, the main purpose is to suppress entry of hydrogen into the third gate insulating film 104 c and the semiconductor layer 106 which are mainly used for supplying oxygen to the semiconductor layer 106. Alternatively, the second gate insulating film 104b may be omitted.

In this embodiment mode, as illustrated in FIG. 1, the source electrode 108 and the drain electrode 109 are formed of the same conductive film as the first conductive film 108a, the second conductive film 108b, and the third conductive film 108c. Although the three-layer structure is used, there is a problem with a laminated structure or a single-layer structure other than the three-layer structure. Further, different conductive films may be used for the source electrode 108 and the drain electrode 109.

The structure of the source electrode 108 and the drain electrode 109 may be appropriately selected by the practitioner in consideration of various factors such as a required wiring resistance value, contact resistance with the semiconductor layer, and reliability. .

In this embodiment mode, as illustrated in FIG. 1, the first insulating film 110 covering the semiconductor layer 106 and the source electrode 108 and the drain electrode 109 is formed of two layers of a first region 110 a and a second region 110 b. In addition, a second insulating film 111 is formed on the first insulating film 110. This is because an oxide semiconductor film is used as the semiconductor layer 106 in this embodiment.

As described above, when an oxygen defect occurs in the oxide semiconductor film, carriers can be generated due to oxygen vacancies. Therefore, the oxide semiconductor film is in contact with the semiconductor layer 106 and releases oxygen by heat treatment (hereinafter referred to as oxygen). It is preferable to form (also referred to as a release film).

However, when the oxygen supply film is formed with strong energy over the oxide semiconductor film, the oxide semiconductor film may be damaged (for example, the crystal state of the oxide semiconductor film is disturbed and defects are generated).

Further, the first insulating film 110 in contact with the semiconductor layer 106 may be damaged.

Therefore, as illustrated in FIG. 1B, first, over the semiconductor layer 106, a first region that plays a role of mitigating damage applied to the semiconductor layer 106 and damage to the first insulating film 110 in contact with the semiconductor layer 106. 110a is formed on the semiconductor layer 106 with weak energy (at least less energy than that when the second region 110b is formed), and then the second region 110b (oxygen supply film) responsible for supplying oxygen to the semiconductor layer 106 is formed. Can be expressed on the first region 110a with a stronger energy than the formation of the first region 110a.

Then, the second insulating film 111 is formed on the first insulating film 110 for the purpose of preventing impurities from entering from the upper layer (for example, moisture from the partition 112).

The above structure is an example of an insulating film that can be used when the semiconductor layer 106 is an oxide semiconductor film, and the structure of the first insulating film 110 and the second insulating film 111 is as follows. The user may select as appropriate in consideration of the material of the semiconductor layer 106, the structure above the second insulating film 111, the reliability required for the transistor 150, and the like.

<Method for Manufacturing Semiconductor Device>
An example of a method for manufacturing the semiconductor device illustrated in FIG. 1 will be described with reference to the following text and FIGS.

First, the gate insulating layer 104 including the gate electrode 102, the first gate insulating film 104a, the second gate insulating film 104b, and the third gate insulating film 104c is formed over the substrate 100 (see FIG. 2A). ).

The substrate 100 is required to have at least heat resistance that can withstand a subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a substrate such as a ceramic substrate, or a quartz substrate can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or the like can be used as long as it has an insulating surface.

Note that the substrate 100 is preferably subjected to heat treatment at a temperature lower than the strain point of the substrate 100 in advance to shrink the substrate 100 (also referred to as heat shrinkage). Thus, the amount of shrinkage generated in the substrate 100 can be suppressed by heat treatment performed in the manufacturing process of the semiconductor device. Therefore, for example, it is possible to suppress a pattern shift or the like in an exposure process or the like. In addition, moisture, organic matter, or the like attached to the surface of the substrate 100 can be removed by the heat treatment.

The gate electrode 102 is made of, for example, a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium using a physical vapor deposition (PVD) method such as a vacuum evaporation method or a sputtering method. Alternatively, a conductive film having a single layer structure of an alloy material containing these as a main component or a stacked structure using these materials is formed, and a mask is formed over the conductive film using a photolithography method, a printing method, an inkjet method, or the like. The conductive film can be formed by selectively removing a part of the conductive film using the mask.

Although there is no particular limitation on the thickness of the gate electrode 102, the thinner the gate electrode 102, the higher the resistance of the gate electrode 102, which may affect the electric characteristics of the transistor 150. The thicker the gate electrode 102, the more the gate electrode 102 is formed. Since the time required increases, the film thickness is preferably 50 nm or more and 500 nm or less.

As described above, the first gate insulating film 104a is a film with an emphasis on increasing the dielectric breakdown resistance of the gate insulating layer 104, and a chemical vapor deposition (CVD) method such as a plasma CVD method. Oxide films such as silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, hafnium oxide film, hafnium oxynitride film, hafnium oxide silicate film, hafnium oxynitride film, oxynitride film, etc. Can be formed as a single layer or stacked layers. For example, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method using a gas containing silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) as a deposition gas species may be used. Note that the first gate insulating film 104 a also serves to prevent impurities included in the substrate 100 from entering the semiconductor layer 106.

Since the breakdown resistance of the film depends on the defect state of the film, the first gate insulating film 104a desirably has reduced defects in the film. Specifically, in the case where a defect state in a film is measured using an electron spin resonance (ESR) method, a signal resulting from a bond defect between a metal and oxygen in the first gate insulating film 104a. (Specifically, the signal in the vicinity of g = 1.93) is desirably 1 × 10 ¹⁷ [spins / cm ³ ] or less.

Note that in order to reduce defects in the first gate insulating film 104a, it is preferable to form the first gate insulating film 104a with the substrate temperature raised. Specifically, the first gate insulating film 104a is formed at a substrate temperature of 250 ° C. or higher, preferably 350 ° C. or higher, more preferably 450 ° C. or higher.

There is no particular limitation on the thickness of the first gate insulating film 104a; however, the thinner the gate insulating layer 104, the lower the dielectric breakdown resistance of the gate insulating layer 104, which may adversely affect the electrical characteristics of the transistor 150. As the time required for forming the first gate insulating film 104a increases, the thickness is preferably greater than or equal to 100 nm and less than or equal to 500 nm.

The second gate insulating film 104b can be formed using a method and a material similar to those of the first gate insulating film 104a. However, as described above, a hydrogen semiconductor desorbed from the first gate insulating film 104a is used. The film is intended to suppress intrusion into the layer 106, and is required to have a higher density than the first gate insulating film 104a.

As a method for making the film density of the second gate insulating film 104b higher than the film density of the first gate insulating film 104a, for example, a gas containing silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) as film forming gas species And a silicon nitride film, a silicon oxynitride film, etc. formed by a CVD method with a smaller amount of ammonia gas (NH ₃ ) added (also referred to as a gas flow rate) than when the first gate insulating film 104a is formed May be used. Alternatively, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method using a gas containing silane gas (SiH ₄ ) but not ammonia gas (NH ₃ ) may be used as a deposition gas species.

In order to examine the difference in film density between the first gate insulating film 104a and the second gate insulating film 104b, for example, STEM (Scanning Transmission Electron Microscope) observation may be performed to confirm the color of the film. Since the second gate insulating film 104b having a high film density is darker than the first gate insulating film 104a having a low film density, the stacked state of both can be confirmed.

In addition, there is a method of performing a wet etching process (for example, dilute hydrofluoric acid process) to check a difference in etching rate. Since the second gate insulating film 104b having a high film density has an etching rate slower than that of the first gate insulating film 104a having a low film density, the stacked state of both can be confirmed.

The second gate insulating film 104b preferably has a small amount of hydrogen released from the film. Specifically, when TDS measurement is performed by heating the film, the peak of the amount of hydrogen molecules released from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 4.0 × A film having 10 ²¹ [molecules / cm ³ ] or less, more preferably 1.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

As a method for accurately measuring the amount of released hydrogen molecules from the second gate insulating film 104b, a sample in which a film used for the second gate insulating film 104b is formed over a substrate with low impurities such as a silicon substrate. Is prepared, TDS measurement is performed on the sample, and desorbed hydrogen molecules (H ₂ ) are measured. However, in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above-described hydrogen molecule emission amount range is not necessarily satisfied.

Note that, similarly to the first gate insulating film 104a, the second gate insulating film 104b is preferably formed in a state where the substrate temperature is increased in order to reduce defects in the film. The substrate temperature is in accordance with that described in the first gate insulating film 104a.

There is no particular limitation on the thickness of the second gate insulating film 104b; however, if it is too thin, the effect of suppressing hydrogen penetration into the semiconductor layer 106 is reduced, which may adversely affect the electrical characteristics of the transistor 150. Since the time required for forming the second gate insulating film 104b increases as the thickness increases, the thickness is preferably greater than or equal to 10 nm and less than or equal to 150 nm.

The third gate insulating film 104c is a film for reducing the interface state with the semiconductor layer 106, and can be formed using a method and a material similar to those of the first gate insulating film 104a. . In this embodiment, an oxide semiconductor material is used for the semiconductor layer 106; therefore, for example, a silicon oxide film or a silicon oxynitride film may be formed by a CVD method.

The third gate insulating film 104c is in direct contact with the semiconductor layer 106, and it is desirable that the amount of released hydrogen molecules from the film be small. Specifically, when TDS measurement is performed by heating the film, the peak of the amount of hydrogen molecules released from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 4.0 × A film having 10 ²¹ [molecules / cm ³ ] or less, more preferably 1.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

As a method for accurately measuring the amount of hydrogen molecules released from the third gate insulating film 104c, the method described for the second gate insulating film 104b may be used. However, in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above-described hydrogen molecule emission amount range is not necessarily satisfied.

In the case where an oxide semiconductor material is used for the semiconductor layer 106, when nitrogen is bonded to the oxide semiconductor, part of the nitrogen may serve as a donor to generate electrons that are carriers. Therefore, it is preferable that the third gate insulating film 104c contain as little nitrogen as possible. When TDS measurement is performed by heating the third gate insulating film 104c, the release amount of ammonia molecules from the film is increased. Peak of 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 1.0 × 10 ²¹ [molecules / cm ³ ] or less, more preferably 8.0 × 10 ²¹ [molecules / cm ³ ] or less. A certain film is used. However, in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above-described ammonia molecule emission amount range is not necessarily satisfied.

Note that, similarly to the first gate insulating film 104a, the third gate insulating film 104c is preferably formed in a state where the substrate temperature is increased in order to reduce defects in the film. The substrate temperature is in accordance with that described in the first gate insulating film 104a.

Although there is no particular limitation on the thickness of the third gate insulating film 104c, the amount of oxygen desorbed from the third gate insulating film 104c decreases as the thickness decreases, so that oxygen vacancies in the semiconductor layer 106 cannot be sufficiently filled. In addition, since the time required for forming the third gate insulating film 104c increases as the thickness increases, the thickness is preferably greater than or equal to 10 nm and less than or equal to 150 nm.

In addition, as the thickness of the gate insulating layer 104 including the first gate insulating film 104a to the third gate insulating film 104c increases, the electric field applied from the gate electrode 102 to the semiconductor layer 106 becomes weaker, and the electric characteristics of the transistor 150 are reduced. In order to decrease (for example, mobility decreases), a film thickness of 120 nm to 800 nm is preferable.

Oxygen released from the gate insulating layer 104 by heat treatment after the formation of the semiconductor layer 106 not only compensates for oxygen vacancies in the semiconductor layer 106 but also reduces the interface state density between the gate insulating layer 104 and the semiconductor layer 106. There is also an effect. Therefore, carriers can be prevented from being trapped at the interface between the semiconductor layer 106 and the gate insulating layer 104, and a highly reliable transistor can be obtained.

Note that after the gate insulating layer 104 is formed, treatment for increasing surface flatness of the gate insulating layer 104 (hereinafter, treatment for increasing surface flatness of the film is referred to as planarization treatment) may be performed. As the treatment, for example, a chemical mechanical polishing (CMP) treatment or a dry etching method may be used.

Note that the gate insulating layer 104 described in this embodiment has a three-layer structure of the first gate insulating film 104a to the third gate insulating film 104c as described above; however, the gate insulating layer 104 necessarily has a three-layer structure. There is no need.

For example, in order to suppress a metal component contained in the gate electrode 102 from entering the semiconductor layer 106 through the gate insulating layer 104, the metal component from the gate electrode 102 is interposed between the gate electrode 102 and the first gate insulating film 104a. Alternatively, a structure provided with a film (which can also be expressed as a fourth gate insulating film) for suppressing intrusion of silicon may be employed.

Next, the semiconductor layer 106 is formed over the gate insulating layer 104, and the first conductive film 108a, the second conductive film 108b, and the third conductive film 108c are formed over the gate insulating layer 104 and the semiconductor layer 106. (See FIG. 2B).

For example, the semiconductor layer 106 is formed by forming a semiconductor film using a PVD method, a CVD method, or the like, and forming a resist mask on the film by a photolithography method or the like, and then using a dry etching method, a wet etching method, or the like. What is necessary is just to form by selectively removing a semiconductor film. As the semiconductor film, for example, a film formed using a material such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide may be used. In addition to the above materials, an oxide semiconductor material may be used as a material for forming the semiconductor film. In this embodiment, an oxide semiconductor material is used for the semiconductor layer 106.

Examples of the oxide semiconductor material include indium oxide, tin oxide, zinc oxide, In—Zn oxide, In—Mg oxide, In—Ga oxide, and In—Ga—Zn oxide (also referred to as IGZO). In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In -Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide Oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In- Lu—Zn-based oxide, In—Sn—Ga—Zn-based oxide, In—Hf— a-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide Can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor material. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 and n is an integer) may be used as the oxide semiconductor material.

Hereinafter, the structure of the oxide semiconductor film is described.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is classified roughly into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, or the like.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. An oxide semiconductor film which has no crystal part even in a minute region and has a completely amorphous structure as a whole is typical.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, a microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is also included. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface can have a higher degree of crystallinity than the region near the formation surface. is there. In addition, in the case where an impurity is added to the CAAC-OS film, the crystallinity of a region to which the impurity is added changes, and a region having a different degree of crystallinity may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

For example, the CAAC-OS film is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved with the ab plane serving as a boundary, and as sputtering particles in the form of flat or pellets having a plane parallel to the ab plane. May peel from the target. In that case, the CAAC-OS film can be formed when the flat (or pellet-like) sputtered particles reach the substrate while maintaining a crystalline state.

In order to form the semiconductor layer 106 as a CAAC-OS film, it is preferable to apply the following conditions.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) existing in the deposition chamber may be reduced. In addition, the impurity concentration in the deposition gas (hydrogen, water, carbon dioxide, nitrogen, or the like) may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of the sputtered particles occurs after the substrate adheres. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature at the time of film formation, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume. By increasing the proportion of oxygen in the deposition gas, excess atoms (eg, rare gas atoms) are not included in the CAAC-OS film, so that the CAAC-OS film is easily formed.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-Ga-Zn which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder at a predetermined mol number ratio, and after heat treatment at a temperature of 1000 ° C. to 1500 ° C. -O compound target. X, Y and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3 or 3: 1: 2. Note that the type of powder and the mol number ratio to be mixed may be changed as appropriate depending on the sputtering target to be manufactured.

Note that in order to reduce oxygen vacancies in the oxide semiconductor film as much as possible, it is preferable to form a film with a high proportion of oxygen gas in the gas species in the film formation atmosphere, and oxygen may be introduced into the apparatus. It can be said that it is preferable to use a sputtering apparatus that can adjust the gas flow rate. When the gas introduced into the film formation chamber of the sputtering apparatus is 90% or more of the whole as oxygen gas and other gas is used in addition to oxygen gas, it is desirable to use a rare gas. More preferably, it is desirable to use only oxygen gas as the gas introduced into the film formation chamber, and to make the ratio of oxygen gas in the gas species in the film formation atmosphere as close to 100% as possible.

Further, when the oxide semiconductor film contains a large amount of hydrogen, the oxide semiconductor film is bonded to the oxide semiconductor, so that part of the hydrogen serves as a donor and an electron serving as a carrier is generated. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, in the oxide semiconductor film 620, the hydrogen concentration is less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, and still more preferably. Is 1 × 10 ¹⁶ atoms / cm ³ or less. Note that the hydrogen concentration in the oxide semiconductor film 620 is measured by secondary ion mass spectrometry (SIMS).

Therefore, when an oxide semiconductor film is formed as the semiconductor layer 106, it is preferable that an impurity such as water, hydrogen, a hydroxyl group, or hydride is not included as a gas used for the film formation, and the purity is preferably 6N or more. A gas having 7N or more (that is, an impurity concentration in the gas of 1 ppm or less, preferably 0.1 ppm or less) is used. In order to remove moisture (including water, water vapor, hydrogen, hydroxyl group, or hydroxide) in the deposition chamber, an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is used. preferable. The exhaust means may be a turbo molecular pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities such as hydrogen and moisture contained in the oxide semiconductor film formed in the chamber can be reduced.

In addition, it is desirable that the film in contact with the semiconductor layer 106 contain as little hydrogen as possible. Specifically, when TDS measurement is performed by heating a film in contact with the semiconductor layer, the peak of the amount of released hydrogen molecules from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 4 A film having a size of 0.0 × 10 ²¹ [molecules / cm ³ ] or less, more preferably 1.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

Further, it is preferable that the film in contact with the semiconductor layer 106 contain as little nitrogen as possible. This is because, as in the case of hydrogen, by bonding with an oxide semiconductor, part of nitrogen becomes a donor and an electron which is a carrier is generated. Therefore, when TDS measurement is performed by heating the film in contact with the semiconductor layer, the peak of the amount of ammonia molecules released from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 1.0. A film having × 10 ²¹ [molecules / cm ³ ] or less, more preferably 8.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

Further, when an oxide semiconductor film is formed as the semiconductor layer 106, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film is 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 2 × 10. ¹⁶ atoms / cm ³ or less. This is because, as in the case of hydrogen and nitrogen described above, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which causes an increase in off-state current of the transistor.

Note that the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked.

For example, the oxide semiconductor film may be a stack of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film, and each may have a different composition. For example, a ternary metal oxide is used for the first oxide semiconductor film and the third oxide semiconductor film, and a binary metal oxide is used for the second oxide semiconductor film. A binary metal oxide is used for the oxide semiconductor film and the third oxide semiconductor film, and a ternary metal oxide is used for the second oxide semiconductor film.

Further, the constituent elements of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film may be the same and may have different compositions. For example, the atomic ratio of the first oxide semiconductor film and the third oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor film is In: Ga. : Zn = 3: 1: 2 may be used. The atomic ratio of the first oxide semiconductor film and the third oxide semiconductor film is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor film is In: Ga. : Zn = 3: 1: 2 may be used.

At this time, the content ratio of In and Ga in the second oxide semiconductor film is preferably In> Ga. In addition, the In and Ga contents in the first oxide semiconductor film and the third oxide semiconductor film may be In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

Note that when a film different from the oxide semiconductor film is formed in contact with the oxide semiconductor film, impurities may diffuse into the oxide semiconductor film from the film formed in contact with the oxide semiconductor film. For example, when silicon, carbon, or the like contained in a film in contact with the oxide semiconductor film diffuses into the oxide semiconductor film, the electrical characteristics of the transistor may be adversely affected.

However, as described above, the oxide semiconductor film has a stacked structure and has a high mobility (that is, an oxide semiconductor film having a composition of In> Ga, which is the second oxide semiconductor in this embodiment). An oxide semiconductor film having a stable characteristic with less oxygen deficiency than that of the oxide semiconductor film (that is, an oxide semiconductor film having a composition of In ≦ Ga, which is the first embodiment in this embodiment). Transistor corresponding to the first oxide semiconductor film and the third oxide semiconductor film), and the oxide semiconductor film having high mobility is separated from the film in contact with the oxide semiconductor film. Adverse effects of electrical characteristics (for example, mobility reduction) can be suppressed. Accordingly, the mobility and reliability of the transistor can be increased.

As a material for the first conductive film 108a to the third conductive film 108c, a material which can withstand heat treatment performed in the manufacturing process of the transistor 150 may be used. For example, using a PVD method, a metal film containing an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or a metal nitride film containing the above elements as a component (a titanium nitride film, a molybdenum nitride film) A single-layer film or a laminated film of a tungsten nitride film or the like may be formed.

In the case where the source electrode 108 and the drain electrode 109 to be formed in a later process have a stacked structure as in this embodiment mode, for example, in order to achieve both low resistance and heat resistance of the electrode, resistivity such as aluminum and copper is used. Of a refractory metal film such as titanium, molybdenum, tungsten, or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) on one or both of the lower and upper metal films And it is sufficient.

Alternatively, the first conductive film 108a to the third conductive film 108c may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

Next, the first conductive film 108 a to the third conductive film 108 c and the semiconductor layer 106 are selectively removed, so that the source electrode 108 and the drain electrode 109 which are electrically connected to the semiconductor layer 106 are formed. In addition to the formation, the semiconductor layer 106 is formed with a recess 130 having a curved shape from the bottom to the side (see FIG. 2C).

Note that from the viewpoint of suppressing generation of voids in the first insulating film 110 and the second insulating film 111 formed in a later step, the curvature radius of the above-described curved state is 5 nm or more and the source electrode 108 of the transistor 150. And a distance between the source electrode 108 and the drain electrode 109 of the transistor 150, more preferably 20 nm or more and a distance between the source electrode 108 and the drain electrode 109 of the transistor 150.

For the source electrode 108 and the drain electrode 109, the first conductive film 108a to the third conductive film 108c are formed, and a mask is formed over the conductive film by a photolithography method, a printing method, an inkjet method, or the like. It can be formed by selectively removing part of the conductive film using a mask. Note that the removal process may be a known dry etching process or wet etching process.

For the formation of the recess 130 in the semiconductor layer 106, a mask used for forming the source electrode 108 and the drain electrode 109 is used. After forming the source electrode 108 and the drain electrode 109, a known dry etching process is performed on the semiconductor layer 106. A wet etching process may be performed.

FIG. 11 shows an enlarged view of the above-described recess.

As shown in FIG. 11A, the side surface of the recess 130 has a structure in which there is no step between the side surface of the source electrode 108 or the drain electrode 109. If there is a step in the portion (such as the region 1100 in FIG. 11A), when an insulating film is formed over the source electrode 108 and the drain electrode 109, voids may flow from the vicinity of the step portion toward the surface of the insulating film. It is easy to generate, and the void can be an entry route of impurities from the outside.

Note that an angle θ1 formed between the side surface of the source electrode 108 and the side surface of the drain electrode 109 with respect to the surface of the semiconductor layer 106 is set to an angle of 30 ° to 80 °, more preferably 30 ° to 60 °. Accordingly, when the first insulating film 110 and the second insulating film 111 are formed over the source electrode 108 and the drain electrode 109, the coverage of the insulating film on the side surface of the source electrode 108 and the side surface of the drain electrode 109 is reduced. Since it can suppress, a void | hole becomes difficult to enter into an insulating film further.

In the case where the source electrode 108 and the drain electrode 109 have a stacked structure of conductive films as in this embodiment mode, the side surface of the first layer of the conductive film (for example, the first conductive film 108a) and the conductive film It is desirable that there be no step between the side surface of the second layer (for example, the second conductive film 108b). The part having no step corresponds to, for example, the area 1102 or the area 1103 in FIG.

Note that in FIG. 11A, the side surfaces of the first conductive film 108a to the third conductive film 108c are all shown at the same angle with respect to the surface of the semiconductor layer 106, but as shown in FIG. Furthermore, the angle θ2 formed by the side surface of the first conductive film 108a with respect to the surface of the semiconductor layer 106, the angle θ3 formed by the side surface of the second conductive film 108b with respect to the surface of the semiconductor layer 106, and the angle θ3 formed with respect to the surface of the semiconductor layer 106. The angles θ4 formed by the side surfaces of the three conductive films 108c may be different angles.

In the above-described case, the first angle θ2, the second angle θ3, and the third angle θ4 are 30 ° or more and 80 ° or less, more preferably 30 ° or more and 60 ° or less, so that the source electrode 108 and the drain electrode When an insulating film is formed over 109, a decrease in the coverage of the insulating film on the side surface of the source electrode 108 and the side surface of the drain electrode 109 can be suppressed;

Note that a part of the structure may have a step as in the region 1104 in FIG. In addition, as in a region 1105 in FIG. 11C, the side surface of the conductive film is not necessarily flat. As long as there is no step between the side surface of the recess 130 and the side surface of the source electrode 108 or the drain electrode 109 as shown in FIG.

In addition, the source electrode 108 and the drain electrode 109 and the recess 130 are different from each other in different removal processes (for example, when the source electrode 108 and the drain electrode 109 are formed and when the recess 130 is formed, the gas type and applied power used in the dry etching process are changed. Etc.), but it is desirable to carry out the same removal treatment. In particular, when the thickness of the semiconductor layer 106 is thin (specifically, 100 nm or less), it is difficult to form the source electrode 108 and the drain electrode 109 and the recess 130 by different removal treatments. (For example, the concave portion 130 is formed in the central portion of the substrate, but the concave portion 130 is not formed in the vicinity of the end portion of the substrate). preferable.

The treatment speed (also referred to as an etching rate) in the removal process of the semiconductor layer 106 is desirably 1/10 or more and 1/3 or less of the film thickness of the semiconductor layer 106. For example, when the film thickness of the semiconductor layer 106 is 30 nm, the etching rate of the semiconductor layer 106 is 3 nm or more and 10 nm (for example, in the case of a dry etching process, used gas, applied power, processing chamber pressure, etc.) May be selected and removed.

The practitioner may appropriately select what conditions are used for the removal process from known techniques.

As described above, by performing the removal treatment under the condition that the thickness of the semiconductor layer 106 is 1/10 or more and 1/3 or less, the products generated during the removal treatment of the semiconductor layer 106 are removed. In this case, the electrodes are attached in order from the top (also expressed in order from the side closer to the source electrode 108 and the drain electrode 109). Since the portion to which the product is attached is less likely to be removed than the portion to which the product is not attached, the side portion of the semiconductor layer is processed into a curved shape due to the influence of the product.

Next, the first insulating film 110 including the first region 110 a and the second region 110 b and the second insulating film 111 are formed over the semiconductor layer 106, the source electrode 108, and the drain electrode 109. Thus, the transistor 150 is formed (see FIG. 3A).

The first insulating film 110 has a structure including at least a first region 110a and a second region 110b.

The first region 110a may be formed using an oxide film such as a silicon oxide film or a silicon oxynitride film or the like using a PVD method or a CVD method. As described above, the first region 110a serves as a layer for reducing damage to the semiconductor layer 106 due to the formation of the first insulating film 110. Therefore, the first region 110a is formed by a plasma CVD method, for example. In this case, it is desirable to form a film under low power conditions.

As a method for confirming damage to the semiconductor layer 106 and the first region 110a caused by the formation of the first region 110a, ESR measurement may be performed. In the ESR measurement of the surface of the semiconductor layer 106 after the formation of the first region 110a, a signal (specifically, a signal in the vicinity of g = 1.93) due to a bond defect between a metal and oxygen in the semiconductor layer 106 is 1 It is desirable that it is not more than × 10 ¹⁷ [spins / cm ³ ].

Further, in the ESR measurement of the first region 110a after the formation of the first region 110a, a signal (specifically, near g = 2.001) due to a bond defect between silicon and oxygen in the first region 110a. Signal) is 5 × 10 ¹⁶ [spins / cm ³ ] or less, preferably 3 × 10 ¹⁷ [spins / cm ³ ] or less.

Note that when the signal is within the above range, the film may not be formed under a low power condition.

Further, since the first region 110a is in direct contact with the semiconductor layer 106, it is preferable that the amount of released hydrogen molecules and the amount of released ammonia molecules be small as in the third gate insulating film 104c. For the specific content of the released amounts of hydrogen molecules and ammonia molecules, the description content of the third gate insulating film 104c can be referred to. However, in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above-described emission amount ranges of hydrogen molecules and ammonia molecules are not necessarily satisfied.

The method and material described in the first region 110a can be used for the second region 110b. Preferably, the first region 110a is formed using the same method and material. As a result, the first region 110a and the second region 110b can be collectively formed using the same apparatus and the same processing chamber, so that the first insulating film 110 is a high-quality layer free from particle contamination. And can. In addition, the manufacturing time of the transistor 150 can be shortened.

Note that in FIG. 3A, the first region 110a and the second region 110b are separated by a dotted line. This is because the first region 110a and the second region 110b are formed using the same material. This means that a clear boundary is not formed.

As described in <Structure example of semiconductor device>, the second region 110b plays a role of supplying oxygen to the semiconductor layer 106. Therefore, the second region 110b is preferably a film that releases oxygen by heat treatment. Specifically, in the TDS measurement, the amount of released oxygen molecules is 1.0 × 10 ¹⁸ [molecules / cm ³ ] or more, preferably 3.0 × 10 ¹⁹ [molecules / cm ³ ] or more, and more preferably 1. 0 × 10 ²⁰ [molecules / cm ³ ] or more.

In particular, it is preferable that the second region 110b (in the bulk) has an amount of oxygen that exceeds at least the stoichiometric ratio and releases oxygen by heat treatment. By using such a film as the second region 110b and performing heat treatment on the second region 110b, oxygen is supplied to the semiconductor layer 106, and defects generated in the semiconductor layer 106 (for example, oxygen defects) Thus, the electric characteristics of the transistor 150 including the semiconductor layer 106 can be improved. For example, normally-on of the transistor 150 can be suppressed.

For the introduction of oxygen into the second region 110b, heat treatment under an oxygen atmosphere, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment performed under an atmosphere containing oxygen, or the like can be used. . Note that in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above oxygen molecule emission amount range is not necessarily satisfied.

In addition, in order to reduce hysteresis in the electric characteristics of the transistor 150, a signal (specifically, a signal in the vicinity of g = 2.001) due to a bond defect between silicon and oxygen in the second region 110b is 1 × 10 ¹⁸ [spins / cm ³ ] or less, preferably 5 × 10 ¹⁷ [spins / cm ³ ] or less.

Since the first region 110a is already formed over the semiconductor layer 106, the second region 110b can be formed using higher applied power than the first region 110a. The practitioner may select an appropriate amount of applied power in consideration of a required film quality and a given film formation time.

Note that the first insulating film 110 described in this embodiment has a two-layer structure of the first region 110a and the second region 110b as described above; however, the first insulating film 110 is not necessarily required to have a two-layer structure. Absent.

For example, a structure may be employed in which a third region manufactured using the same method and material as the first region is further provided over the second region 110b.

As described above, the second region 110b functions as an oxygen supply film with respect to the semiconductor layer 106. Therefore, when the second insulating film 111 is formed with high applied power in contact with the second region 110b, the second region 110b There is a possibility that excess oxygen contained in the region 110b is desorbed and the oxygen supply capability is reduced.

Therefore, the second region 110b is formed by forming the second insulating film 111 by further providing a third region formed using the same method and material as the first region 110a over the second region 110b. A decrease in the oxygen supply capacity of the region 110b can be suppressed.

Alternatively, the first insulating film including the first region 110a and the second region 110b may be provided with n layers (n is a natural number), and the second insulating film 111 may be provided thereover. The effect of providing the first insulating film with n layers is briefly described below.

Since the first region 110a is formed under the low power condition as described above and is a film having a lower density than the second region 110b, the source electrode 108, the drain electrode 109, and the recess 130 are formed. The covering property with respect to the unevenness | corrugation formed by doing is high.

Therefore, the first region 110a is first formed on the unevenness formed by forming the source electrode 108, the drain electrode 109, and the recess 130, and the angle of the unevenness is made gentle (the corner of the unevenness is rounded). ).

Then, by forming the second region which is a denser film than the first region 110a on the first region 110a, the second region 110b has the effect of the first region 110a. The flatness of the concavo-convex portion due to the fact that it is high) makes it difficult for voids due to the concavo-convex to enter.

Although the first insulating film 110 having the above-described structure has the effect of suppressing voids even with a single layer, it is more difficult to generate voids by further stacking to have a structure of n layers (n is a natural number). .

The above is the effect of providing the first insulating film with n layers.

Alternatively, the above-described third region may be provided over the n-layer of the first insulating film 110.

As described in <Structure example of semiconductor device>, the second insulating film 111 is formed in order to prevent impurities from entering from the upper layer (for example, moisture from the partition 112). In particular, it is desirable that it has a high property of preventing intrusion of moisture (hereinafter also referred to as moisture blocking property).

The second insulating film 111 may be formed using a nitride film such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like by a PVD method or a CVD method. .

As a method for confirming the moisture blocking property of the second insulating film 111, a film used for the second region 110b and a film used as the second insulating film 111 are stacked over a substrate with few impurities such as a silicon substrate. A sample is prepared, TDS measurement is performed on the sample, and the desorbed water molecule (H ₂ O) may be measured.

Specifically, the amount of water molecules released by TDS measurement is 1.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 5.0 × 10 ²⁰ [molecules / cm ³ ] or less, more preferably 1. A film having a size of 0 × 10 ²⁰ [molecules / cm ³ ] or less is used as the second insulating film 111.

In addition, the second insulating film 111 has a characteristic of blocking the intrusion of oxygen molecules (hereinafter, referred to as “oxygen”) in order to help oxygen released from the second region functioning as an oxygen supply film to be efficiently supplied to the semiconductor layer 106. , Which is also described as oxygen blocking property).

As a method for confirming the oxygen blocking property of the second insulating film 111, a film used for the second region 110b and a film used as the second insulating film 111 are stacked over a substrate with few impurities such as a silicon substrate. A sample is prepared, TDS measurement is performed on the sample, and desorbed oxygen molecules (O ₂ ) may be measured.

Specifically, the amount of released oxygen molecules is 1.0 × 10 ¹⁹ [molecules / cm ³ ] or less, preferably 5.0 × 10 ¹⁸ [molecules / cm ³ ] or less, more preferably 1. A film having a size of 0 × 10 ¹⁸ [molecules / cm ³ ] or less is used as the second insulating film 111. Note that in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above oxygen molecule emission amount range is not necessarily satisfied.

Note that in the case where a nitride film or a nitrided oxide film is formed as the second insulating film 111 by a CVD method, a large amount of hydrogen is contained in the film, which may adversely affect the electrical characteristics of the transistor 150. Therefore, as described in the second gate insulating film 104b, a film containing silane gas (SiH ₄ ) and containing ammonia gas (NH ₃ ) as little as possible (or not containing) is formed, and the film is heated. When TDS measurement is performed, the peak of the amount of hydrogen molecules released from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 4.0 × 10 ²¹ [molecules / cm ³ ] or less, More preferably, a film having a size of 1.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

In the case where the semiconductor layer 106 is an oxide semiconductor, when ammonia enters the oxide semiconductor, part of nitrogen may serve as a donor and an electron serving as a carrier may be generated. Therefore, when TDS measurement is performed by heating the second insulating film 111, the peak of the amount of ammonia molecules released from the film is 5.0 × 10 ²¹ [molecules / cm ³ ] or less, preferably 1. A film having 0 × 10 ²¹ [molecules / cm ³ ] or less, more preferably 8.0 × 10 ²¹ [molecules / cm ³ ] or less is used.

However, in the case where an oxide semiconductor material is not used for the semiconductor layer 106, the above-described emission amount ranges of hydrogen molecules and ammonia molecules are not necessarily satisfied.

Next, a partition 112 and a wiring 114 are formed over the second insulating film 111 (see FIG. 3B).

For the partition wall 112, for example, an insulating material is applied using a spin coating method, a printing method, a dispensing method, an ink jet method, or the like, and a curing process (for example, a heat treatment or a light irradiation process) according to the applied material. Can be formed. Alternatively, after a layer having an insulating property is formed, a resist mask corresponding to a pattern shape to be processed is formed on the layer using a photolithography method, an inkjet method, or the like, and a dry etching method, a wet etching method, or the like is used. Then, it may be formed by selectively removing the layer.

Note that as the insulating material, for example, an organic resin such as an acrylic resin, a polyimide resin, a polyamide resin, a polyamideimide resin, and an epoxy resin, an inorganic material, and an organic-inorganic mixed material such as organic polysiloxane can be used.

The partition 112 only needs to have a thickness that can planarize unevenness formed on the surface of the substrate in the step of forming the second insulating film 111. However, if the partition 112 is too thick, the productivity of the transistor 150 is reduced. Hereinafter, it is preferably 500 nm or more and 3000 nm or less.

The wiring 114 may be formed using a method and a material similar to those of the gate electrode 102.

Through the above steps, the structure shown in FIG. 1 is completed.

When the transistor has the above structure, impurities that can cause variation in electrical characteristics can be prevented from entering a semiconductor layer included in the transistor, so that the electrical characteristics of the transistor can be improved. Further, a transistor having stable electrical characteristics with little deterioration due to a change in elapsed time can be obtained.

Note that although a bottom-gate / top-contact (BGTC) structure is described as the transistor 150 in this embodiment, for example, a top-gate / top-contact (TGTC) structure as illustrated in FIG. A transistor 170 may be formed.

In the case of forming a transistor with a TGTC structure, a base film 172 formed over the substrate 100 is formed using a PVD method or a CVD method by using a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like. An oxide film or an oxynitride film may be formed, and a film capable of supplying oxygen to the semiconductor layer 106 is preferably formed by heat treatment using a method and a material similar to those of the first region 110a. Is desirable.

In addition, since the gate electrode 102 exists over the semiconductor layer 106, the stacking order of the gate insulating layer 174 and the gate insulating layer 104 used in the transistor 150 is reversed.

Further, as shown in FIG. 4B, a dual gate (also referred to as a double gate) top contact transistor 180 including a back gate electrode 182 at a position facing the gate electrode 102 with the semiconductor layer 106 interposed therebetween is formed. May be.

With the structure having the back gate electrode 182, even if the transistor 180 is normally on (in this case, the transistor is on when no potential is applied by the power source) By appropriately applying voltage to the back gate electrode 182, the threshold value of the transistor 180 is shifted, so that the transistor is normally off (here, the transistor is off when no potential is applied by the power source). ) Can be kept.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a display device using the transistor described in the above embodiment will be described with reference to FIGS. FIGS. 6A, 6B, and 7 are cross-sectional views taken along dashed-dotted line MN in FIG. 5B.

FIG. 5A is an example of a plan view of a display device. A sealant 905 is provided so as to surround a pixel portion 902 provided over a first substrate 901 and is sealed by a second substrate 906. Yes. In FIG. 5A, a signal line formed of a single crystal semiconductor or a polycrystalline semiconductor over a separately prepared substrate in a region different from the region surrounded by the sealant 905 over the first substrate 901. A driver circuit 903 and a scanning line driver circuit 904 are mounted. In addition, a variety of signals and potentials are supplied to the signal line driver circuit 903, the scan line driver circuit 904, or the pixel portion 902 through an FPC (Flexible Printed Circuit) 918a and an FPC 918b.

FIG. 5B is an example of a plan view of the display device, in which a sealant 905 is provided so as to surround the pixel portion 902 and the scan line driver circuit 904 provided over the first substrate 901 and the second substrate. Sealed by 906. In FIG. 5B, a signal line driver circuit 903 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted in a region different from the region surrounded by the sealant 905 over the first substrate 901. Yes. In addition, a variety of signals and potentials are supplied to the signal line driver circuit 903, the scan line driver circuit 904, or the pixel portion 902 through the FPC 918a.

FIG. 5C is an example of a plan view of the display device, in which a sealant 905 is provided so as to surround the pixel portion 902 and the scan line driver circuit 904 provided over the first substrate 901 and the second substrate. Sealed by 906. In FIG. 5C, a signal line driver circuit 903 made of a single crystal semiconductor or a polycrystalline semiconductor is provided at a position overlapping with the FPC 918a. Therefore, a part of the FPC 918a (the signal line driver circuit 903 mounting portion) has an exposed wiring, and the FPC 918a and the signal line driver circuit 903 are electrically connected by installing the signal line driver circuit 903 at the location. Is done. In addition, a variety of signals and potentials are supplied to the signal line driver circuit 903, the scan line driver circuit 904, or the pixel portion 902 through the FPC 918a.

5B and 5C, an example in which the signal line driver circuit 903 formed of a single crystal semiconductor or a polycrystalline semiconductor is formed and mounted on the first substrate 901 or the FPC 918a. Although shown, it is not limited to this configuration. For example, the scan line driver circuit 904 formed of a single crystal semiconductor or a polycrystalline semiconductor may be formed and mounted on the first substrate 901 or the FPC 918a, or part of the signal line driver circuit 903 or the scan line driver circuit Only a part of 904 may be separately formed and mounted.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a known technique such as a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 5A illustrates an example in which the signal line driver circuit 903 and the scan line driver circuit 904 are mounted by a COG method, and FIG. 5B illustrates an example in which the signal line driver circuit 903 is mounted by a COG method. FIG. 5C illustrates an example in which the signal line driver circuit 903 is mounted by a TAB method.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). In addition, a connector, for example, a module to which an FPC or TCP is attached, a module in which a printed wiring board is provided at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method is all included in the display device. Shall be included.

In addition, the pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the transistors described in the above embodiments can be used.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

The display device illustrated in FIG. 6A includes a connection terminal electrode 915 and a connection terminal electrode 916. The connection terminal electrode 915 and the connection terminal electrode 916 are connected to a terminal included in the FPC 918a and an anisotropic conductive agent 919. Electrically connected.

The connection terminal electrode 915 is formed using the same conductive film as the first electrode 930, and the connection terminal electrode 916 is formed using the same conductive film as the pair of electrodes of the transistors 910 and 911. Note that the first electrode 930 may be formed using a method and a material similar to those of the wiring 114 described in Embodiment 1.

The display device illustrated in FIG. 6B includes connection terminal electrodes 915a and 915b and a connection terminal electrode 916. The connection terminal electrodes 915a and 915b and the connection terminal electrode 916 each include a terminal included in the FPC 918a and an anisotropic conductive agent. 919 is electrically connected.

The connection terminal electrode 915a is formed from the same conductive film as the first electrode 930, the connection terminal electrode 915b is formed from the same conductive film as the second electrode 941, and the connection terminal electrode 916 is a pair of transistors 910 and 911. The same conductive film as that of the electrode is formed.

The display device illustrated in FIG. 7 includes a connection terminal electrode 955, a connection terminal electrode 938, and a connection terminal electrode 916. The connection terminal electrode 955 and the connection terminal electrode 916 each include a terminal included in the FPC 918a and an anisotropic conductive agent 919. Are electrically connected.

The connection terminal electrode 955 is formed of the same conductive film as the second electrode 951, the connection terminal electrode 938 is formed of the same conductive film as the first electrode 930, and the connection terminal electrode 916 includes a pair of electrodes of the transistors 910 and 911. The same conductive film is formed.

In the display device illustrated in FIGS. 6 and 7, the pixel portion 902 and the scan line driver circuit 904 provided over the first substrate 901 include a plurality of transistors. In FIGS. A transistor 910 included in the pixel portion 902 and a transistor 911 included in the scan line driver circuit 904 are illustrated.

6A and 6B, the insulating film 924 corresponding to the first insulating film 110 and the second insulating film 111 described in Embodiment 1 is provided over the transistor 910 and the transistor 911. A planarization film 921 is further provided over the insulating film 924. The insulating film 924 can be formed using a method and a material similar to those of the partition 112. Note that the insulating film 923 is an insulating film functioning as a base film and can be formed using a method and a material similar to those of the first gate insulating film 104a.

The transistor 150 described in the above embodiment can be applied to the transistors 910 and 911 in this embodiment.

FIG. 7 illustrates an example in which a conductive film 917 is provided over the insulating film 924 so as to overlap with a channel formation region of the oxide semiconductor film of the transistor 911 for the driver circuit. In this embodiment, the conductive film 917 may be formed using a method and a material similar to those of the first electrode 930. Since the conductive film 917 functions as a back gate of the transistor 911, the threshold value of the transistor 911 can be controlled and the transistor 911 can be prevented from being normally on. In addition, the amount of change in the threshold voltage of the transistor 911 before and after the BT stress test can be further reduced.

Note that the potential of the conductive film 917 may be the same as that of the gate electrode of the transistor 911 or may be GND, 0 V, or a floating state.

The conductive film 917 also has a function of shielding an external electric field. That is, it also has a function (for example, an electrostatic shielding function against static electricity or a shielding function against X-rays) that prevents an external electric field from acting on the inside (a circuit portion including a transistor). The shielding function of the conductive film 917 can prevent a change in electrical characteristics of the transistor due to the influence of an external electric field such as static electricity. The conductive film 917 can be applied to any of the transistors described in the above embodiments.

A transistor 910 provided in the pixel portion 902 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as display can be performed, and various display elements can be used.

In the first electrode 930, the second electrode 931, and the second electrode 941 (also referred to as a pixel electrode, a common electrode, a counter electrode, or the like) that applies a voltage to the display element, a direction of light to be extracted, a place where the electrode is provided The light transmitting property and the reflecting property may be selected depending on the electrode pattern structure.

The first electrode 930, the second electrode 931, and the second electrode 941 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin containing titanium oxide. A light-transmitting conductive material such as an oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

In addition, the first electrode 930, the second electrode 931, and the second electrode 941 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb). Tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or other metals, or One or a plurality of these alloys or metal nitrides can be used.

The first electrode 930, the second electrode 931, and the second electrode 941 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

FIG. 6 shows an example of a liquid crystal display device using a liquid crystal element as a display element. FIG. 6A illustrates an example in which a vertical electric field method is employed.

In FIG. 6A, a liquid crystal element 913 which is a display element includes a first electrode 930, a second electrode 931, and a liquid crystal layer 908. Note that an insulating film 932 and an insulating film 933 which function as alignment films are provided so as to sandwich the liquid crystal layer 908. The second electrode 931 is provided on the second substrate 906 side, and the liquid crystal layer 908 is sandwiched between the first electrode 930 and the second electrode 931.

The spacer 935 is a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the first electrode 930 and the second electrode 931. A spherical spacer may be used.

FIG. 6B illustrates an example in which an FFS (Fringe Field Switching) mode is employed as an example of the horizontal electric field method.

6B, a liquid crystal element 943 which is a display element includes a first electrode 930, a second electrode 941, and a liquid crystal layer 908 which are formed over a planarization film 921. The second electrode 941 functions as a common electrode. An insulating film 944 is provided between the first electrode 930 and the second electrode 941. The insulating film 944 is formed using a silicon nitride film. Note that an insulating film 932 and an insulating film 933 which function as alignment films are provided so as to sandwich the liquid crystal layer 908.

Similarly to FIG. 6A, a spacer 935 for controlling the distance (cell gap) between the first electrode 930 and the second electrode 931 is provided.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependence is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved.

The first substrate 901 and the second substrate 906 are fixed by a sealant 905. As the sealant 905, an organic resin such as a thermosetting resin or a photocurable resin can be used.

Note that in the liquid crystal display device illustrated in FIG. 6A, the sealant 905 is in contact with the gate insulating film 922, and the planarization film 921 is provided inside the sealant 905. As described in Embodiment 1, the gate insulating film 922 is formed by stacking a silicon nitride film and a silicon oxynitride film. Note that when the insulating film 924 is selectively etched, the silicon oxynitride film over the gate insulating film 922 is preferably etched to expose the silicon nitride film. As a result, the sealant 905 and the silicon nitride film formed on the gate insulating film 922 are in contact with each other, so that water from the outside can be prevented from entering the sealant 905.

In the liquid crystal display device illustrated in FIG. 6B, the sealant 905 is in contact with the insulating film 924. Since the planarizing film 921 is provided inside the sealing material 905 and the silicon nitride film on the surface of the insulating film 924 is in contact with the sealing material 905, water from the outside is prevented from entering the sealing material 905. Is possible.

The size of the storage capacitor provided in the liquid crystal display device is set so that charges can be held for a predetermined period in consideration of a leakage current of a transistor arranged in the pixel portion. By using a transistor including a high-purity oxide semiconductor film, it is sufficient to provide a storage capacitor having a capacity of 1/3 or less, preferably 1/5 or less of the liquid crystal capacity of each pixel. Therefore, the aperture ratio in the pixel can be increased.

In the display device, a black matrix (light-shielding film), a polarizing member, a retardation member, an optical member (an optical substrate) such as an antireflection member, and the like are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, there is RGBW (W represents white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. The size of the display area may be different for each dot of the color element. However, the present invention is not limited to a display device for color display, and can also be applied to a display device for monochrome display.

FIG. 8 illustrates an example in which a common connection portion (pad portion) for electrically connecting to the second electrode 931 provided on the substrate 906 is formed over the substrate 901 in the display device illustrated in FIG. Indicates.

Here, since the area sizes are greatly different, the contact hole in the pixel portion and the opening portion of the common connection portion are referred to as appropriate. 5 and 8, the pixel portion 902 and the common connection portion are not shown in the same scale. For example, the length of the alternate long and short dash line I-J of the common connection portion is about 500 μm. The size of the transistor in the pixel portion 902 is less than 50 μm, and actually the area size is 10 times or more larger. However, for the sake of clarity, the scale of the pixel portion 902 and the common connection portion is changed in FIGS. It is shown.

The common connection portion is disposed at a position overlapping with a sealing material for bonding the substrate 901 and the substrate 906, and is electrically connected to the second electrode 931 through conductive particles included in the sealing material. Alternatively, a common connection portion is provided in a portion that does not overlap with the sealant (excluding the pixel portion), and a paste containing conductive particles is provided separately from the sealant so as to overlap the common connection portion, and the second electrode 931 You may connect electrically.

FIG. 8A is a cross-sectional view of the common connection portion, and corresponds to IJ in the top view shown in FIG. Note that since the components of the common connection portion are formed using the same material as the components of the transistor, the transistor is described next to the cross-sectional view of the common connection portion for the purpose of facilitating understanding of the structure. . Similarly, in FIG. 8C, a cross-sectional view of the transistor is shown next to the cross-sectional view of the common connection portion.

The common potential line 975 is provided over the gate insulating film 922 and is manufactured using the same material and through the same process as the source electrode 971 or the drain electrode 973 of the transistor 910 illustrated in FIGS.

The common potential line 975 is covered with an insulating film 924 and a planarization film 921, and the insulating film 924 and the planarization film 921 have a plurality of openings at positions overlapping the common potential line 975. This opening is formed in the same process as a contact hole connecting one of the source electrode 971 and the drain electrode 973 of the transistor 910 and the first electrode 930.

In addition, the common potential line 975 and the common electrode 977 are connected in the opening. The common electrode 977 is provided over the planarization film 921 and is manufactured using the same material and through the same process as the connection terminal electrode 915 and the first electrode 930 in the pixel portion.

In this manner, the common connection portion can be manufactured in common with the manufacturing process of the switching element of the pixel portion 902.

The common electrode 977 is an electrode that is in contact with conductive particles contained in the sealant, and is electrically connected to the second electrode 931 of the substrate 906.

As shown in FIG. 8C, the common potential line 985 may be formed using the same material and the same process as the gate electrode of the transistor 910.

In the common connection portion illustrated in FIG. 8C, the common potential line 985 is provided below the gate insulating film 922, the insulating film 924, and the planarization film 921, and the gate insulating film 922, the insulating film 924, and the planarization are provided. The film 921 has a plurality of openings at positions overlapping with the common potential line 985. The opening is formed by etching the insulating film 924 and the planarization film 921 in the same process as the contact hole connecting one of the source electrode 971 or the drain electrode 973 of the transistor 910 and the first electrode 930, and then the gate insulating film It is formed by selectively etching 922.

Further, the common potential line 985 and the common electrode 987 are connected in the opening. The common electrode 987 is provided over the planarization film 921 and is manufactured using the same material and through the same process as the connection terminal electrode 915 and the first electrode 930 in the pixel portion.

Note that in the FFS mode liquid crystal display device illustrated in FIG. 6B, the common electrodes 977 and 987 are each connected to the second electrode 941.

In the above description, a liquid crystal display device is described as a display device; however, a light-emitting element utilizing electroluminescence can be applied as a display element included in the display device. In the following, description is given of a display device including a light emitting element using electroluminescence.

A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes may be transparent. Then, a transistor and a light emitting element are formed on the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate, and a surface opposite to the substrate and the substrate are provided. There is a light-emitting element having a dual emission structure in which light emission is extracted from the light-emitting element, and any light-emitting element having an emission structure can be applied.

FIG. 7 illustrates an example of a light-emitting device using a light-emitting element as a display element. A light-emitting element 963 that is a display element is electrically connected to a transistor 910 provided in the pixel portion 902. Note that the structure of the light-emitting element 963 is a stacked structure of the first electrode 930, the light-emitting layer 961, and the second electrode 931; however, the structure is not limited to this structure. The structure of the light-emitting element 963 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 963, or the like.

A silicon nitride film 950 is provided between the planarization film 921 and the first electrode 930. The silicon nitride film 950 is in contact with the side surfaces of the planarization film 921 and the insulating film 924. A partition wall 960 is provided over the silicon nitride film 950 so as to cover an end portion of the first electrode 930. The partition wall 960 is formed using an organic insulating material or an inorganic insulating material. In particular, it is desirable to use a photosensitive resin material and form an opening on the first electrode 930 so that the side wall of the opening is an inclined surface formed with a continuous curvature.

The light emitting layer 961 may be formed of a single layer or may be formed of a plurality of layers stacked.

A protective layer may be formed over the second electrode 931 and the partition wall 960 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 963. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, a DLC film, or the like can be formed. In addition, a filler 964 is provided and sealed in a space sealed by the first substrate 901, the second substrate 906, and the sealant 936. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

As the sealant 936, an organic resin such as a thermosetting resin or a photocuring resin, a frit glass including a low melting glass, or the like can be used. Frit glass is desirable because it has a high barrier property against impurities such as water and oxygen. Further, when frit glass is used as the sealing material 936, as shown in FIG. 7, by providing the frit glass on the silicon nitride film 950, the adhesion between the silicon nitride film 950 and the frit glass is improved and the sealing material is externally provided. Intrusion of water into the interior of the 936 can be prevented.

A space surrounded by the first substrate 901, the second substrate 906, and the sealant 936 is filled with a filler 964. As the filler 964, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

Further, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the emission surface of the light emitting element. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, as a display device, electronic paper that drives electronic ink can be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the same readability as paper, low power consumption compared to other display devices, and the advantage that it can be made thin and light. ing.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a nonlinear element.

As described above, by using any of the transistors described in the above embodiments, a highly reliable semiconductor device having a display function can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). As electronic equipment, display devices such as televisions, monitors, lighting devices, desktop or notebook information terminals, word processors, image reproduction for reproducing still images or moving images stored in recording media such as DVDs (Digital Versatile Discs) Device, Portable CD player, Radio, Tape recorder, Headphone stereo, Stereo, Cordless phone cordless handset, Transceiver, Portable radio, Mobile phone, Car phone, Portable game machine, Calculator, Personal digital assistant, Electronic notebook, Electronic book, Electronic translators, audio input devices, video cameras, digital still cameras, high-frequency heating devices such as electric shavers, microwave ovens, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners, etc., dishwashers, dish drying Oven, clothes dryer, futon dryer, electric cooling Refrigerator, electric freezers, electric refrigerator, DNA storage freezers, smoke detectors, radiation counters, medical devices such as dialyzers, and the like. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, an engine using petroleum, a moving body driven by an electric motor using electric power from a non-aqueous secondary battery, and the like are also included in the category of electric equipment. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, and electric assist. Examples include motorbikes including bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and space ships. Specific examples of these electronic devices are shown in FIGS.

FIG. 9A illustrates a portable information terminal, which includes a housing 2101, a housing 2102, a first display portion 2103 a, a second display portion 2103 b, and the like. A plurality of transistors are incorporated in the housings 2101 and 2102 as one of electronic components. By applying the transistor described in any of the above embodiments as the transistor, the portable information terminal can have high electrical characteristics and high reliability with little deterioration due to a change in elapsed time. it can.

Note that at least one of the first display portion 2103a and the second display portion 2103b is a panel having a touch input function. For example, as shown in the left diagram of FIG. 9A, the first display portion 2103a A selection button 2104 displayed on the screen can be used to select “touch input” or “keyboard input”. Since the selection buttons can be displayed in various sizes, a wide range of people can feel ease of use. For example, when “keyboard input” is selected, a keyboard 2105 is displayed on the first display portion 2103a as shown in the right diagram of FIG. As a result, as in the conventional information terminal, quick character input by key input and the like are possible.

In addition, a portable information terminal illustrated in FIG. 9A includes a housing 2101 provided with a first display portion 2103a and a housing provided with a second display portion 2103b as shown in the right view of FIG. 9A. The body 2102 can be separated. Therefore, if necessary, only the housing 2101 or only the housing 2102 can be detached and used as a lighter portable information terminal.

The portable information terminal illustrated in FIG. 9A has a function of displaying various information (still images, moving images, text images, and the like), a function of displaying a calendar, a date, a time, or the like on the display unit, and a display on the display unit. It is possible to have a function of operating or editing the processed information, a function of controlling processing by various software (programs), and the like. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

Further, the portable information terminal illustrated in FIG. 9A may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Further, the housing 2101 or the housing 2102 illustrated in FIG. 9A may be provided with an antenna, a microphone function, or a wireless function and used as a mobile phone.

FIG. 9B illustrates an example of an electronic book 2120. For example, the electronic book 2120 includes two housings, a housing 2121 and a housing 2123. The housing 2121 and the housing 2123 are integrated with a shaft portion 2122, and can be opened / closed using the shaft portion 2122 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 2125 is incorporated in the housing 2121 and a display portion 2127 is incorporated in the housing 2123. The display unit 2125 and the display unit 2127 may be configured to display a continuation screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text is displayed on the right display unit (display unit 2125 in FIG. 9B) and an image is displayed on the left display unit (display unit 2127 in FIG. 9B). Can be displayed.

Inside the housing 2121 and the housing 2123, a plurality of transistors are incorporated as one of electronic components. By using the transistor described in the above embodiment as the transistor, the e-book reader 2120 can have high electric characteristics and high reliability with little deterioration due to a change in elapsed time.

FIG. 9B illustrates an example in which the housing 2121 is provided with an operation portion and the like. For example, the housing 2121 includes a power source 2126, operation keys 2128, a speaker 2129, and the like. Pages can be sent with the operation keys 2128. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing. Further, the e-book reader 2120 may have a configuration as an electronic dictionary.

Further, the e-book reader 2120 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

FIG. 9C illustrates a smartphone, which includes a housing 2130, a button 2131, a microphone 2132, a display portion 2133 provided with a touch panel, a speaker 2134, and a camera lens 2135, and is a mobile phone. As a function.

Inside the housing 2130, a plurality of transistors are incorporated as one of electronic components. By applying the transistor described in the above embodiment as the transistor, the smartphone can have high electrical characteristics and high reliability with little deterioration due to a change in elapsed time.

In the display portion 2133, the display direction can be appropriately changed depending on a usage pattern. In addition, since the camera lens 2135 is provided on the same surface as the display portion 2133, a videophone can be used. The speaker 2134 and the microphone 2132 can be used for videophone calls, recording and playing sound, and the like as well as voice calls.

The external connection terminal 2136 can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with an information terminal are possible. Further, a recording medium can be inserted into an external memory slot (not shown) to cope with storing and moving a larger amount of data.

In addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

FIG. 9D illustrates a digital video camera, which includes a housing 2141, a display portion 2142, operation switches 2143, a battery 2144, and the like.

Inside the housing 2141, a plurality of transistors are incorporated as one of electronic components. By using the transistor described in the above embodiment as the transistor, the digital video camera can have high electric characteristics and high reliability with little deterioration due to a change in elapsed time.

FIG. 9E illustrates an example of the television device 2150. In the television device 2150, a display portion 2153 is incorporated in a housing 2151. Images can be displayed on the display portion 2153. Here, a configuration in which the housing 2151 is supported by the stand 2155 is shown.

In the housing 2151, a plurality of transistors are incorporated as one of electronic components. By using the transistor described in the above embodiment as the transistor, the television device 2150 can have favorable electrical characteristics and high reliability with little deterioration due to a change in elapsed time.

The television device 2150 can be operated with an operation switch provided in the housing 2151 or a separate remote controller. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

Note that the television device 2150 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

This embodiment can be implemented in appropriate combination with any of the other embodiments.

In this example, the results of observing a cross section of a semiconductor device manufactured using the method described in Embodiment Mode 1 using a STEM will be described.

Hereinafter, a manufacturing method of a sample whose cross section is observed (hereinafter simply referred to as a sample) will be described.

First, alkali-free glass was used as the substrate.

Next, a gate electrode was formed on the substrate. For the gate electrode, after forming a 100 nm tungsten film using a sputtering apparatus, a resist mask is formed on the tungsten film using a photolithography method, and a part of the tungsten film is selectively removed using the resist mask. Formed.

Next, a gate insulating layer was formed over the gate electrode. For the gate insulating layer, a 300 nm silicon nitride film is used as the first gate insulating film excellent in dielectric breakdown resistance, and a 50 nm silicon nitride film is used as the second gate insulating film having a high hydrogen blocking property. A third gate electrode having a lowering effect was formed by stacking 50 nm of silicon oxynitride. In addition, a 50 nm silicon nitride film is formed between the gate electrode and the first gate insulating film as a film (described as a fourth gate insulating film) having an effect of preventing diffusion of a metal component contained in the gate electrode. did.

The silicon nitride film as the first gate insulating film has a monosilane gas (SiH ₄ ) of 200 [sccm], a nitrogen gas (N ₂ ) of 2000 [sccm], and an ammonia gas (NH ₃ ) of 2000 [sccm] in the deposition chamber. The substrate was heated at 350 [° C.] for 300 [sec] and then deposited with an applied power of 2000 [W].

The silicon nitride film as the second gate insulating film has a pressure of 100 [Pa] while introducing monosilane gas (SiH ₄ ) into the film formation chamber at a flow rate of 200 [sccm] and nitrogen gas (N ₂ ) at 5000 [sccm]. The substrate was heated at 350 [° C.] for 300 [sec], and then deposited with an applied power of 2000 [W].

The silicon oxynitride film, which is the third gate insulating film, has a pressure while introducing monosilane gas (SiH ₄ ) into the deposition chamber at a flow rate of 20 [sccm] and nitrous oxide gas (N ₂ O) at a flow rate of 3000 [sccm]. Was maintained at 40 [Pa], and the substrate was heated at 350 [° C.] for 300 [sec], and then deposited with an applied power of 100 [W].

The silicon nitride film as the fourth gate insulating film has a monosilane gas (SiH ₄ ) of 200 [sccm], a nitrogen gas (N ₂ ) of 2000 [sccm], and an ammonia gas (NH ₃ ) of 100 [sccm] in the deposition chamber. The substrate was heated at 350 [° C.] for 300 [sec] and then deposited with an applied power of 2000 [W].

Next, a semiconductor layer was formed over the gate insulating layer. After forming a 35 nm IGZO film using a sputtering apparatus, a semiconductor layer is formed using a photolithography method, a resist mask is formed on the IGZO film, and a part of the IGZO film is selectively removed using the resist mask. Formed.

Note that for the IGZO film, a target having a composition of In: Ga: Zn = 1: 1: 1 was used, the film formation chamber was kept at 50% oxygen atmosphere and 0.6 [Pa], and the substrate was 170 [° C.]. The film was formed with an applied power of 5 [kW] in a state where the film was heated.

Next, a source electrode and a drain electrode were formed on the semiconductor layer, and a recess was formed in the semiconductor layer on the gate electrode.

A source electrode and a drain electrode are formed by sequentially stacking a 50 nm titanium film, a 400 nm aluminum film, and a 100 nm titanium film using a sputtering apparatus, and then forming a resist mask on the titanium film using a photolithography method. A part of the laminated film including the above-described titanium film, aluminum film, and titanium film was selectively removed using a resist mask.

Further, in the above-described removal process, after removing the lower titanium film (50 nm titanium film), the IGZO film was further subjected to the removal process, thereby forming a recess in the IGZO film.

The above-described removal treatment uses a dry etching apparatus and introduces a pressure of 2.0 [Pa] while introducing chlorine gas (Cl ₂ ) at a flow rate of 150 [sccm] and boron trichloride (BCl ₃ ) at a flow rate of 750 [sccm]. The ICP (Inductively Coupled Plasma) process was performed with the upper electrode bias power set to 0 W and the lower electrode bias power set to 1500 W.

Note that the etching rate of the IGZO film by the above-described removal treatment was 10 [nm / min], which was 2/7 of the film thickness (35 nm) of the IGZO film.

Next, a first insulating film was formed over the semiconductor layer. As the first insulating film, a PECVD apparatus is used, and a 50 nm silicon oxynitride film is used as a first region for suppressing damage to the semiconductor layer, and a 400 nm silicon oxynitride film is used as a second region for supplying oxygen to the semiconductor layer. Were laminated.

The silicon oxynitride film as the first region has a pressure of 40 while introducing monosilane gas (SiH ₄ ) into the film formation chamber at a flow rate of 30 [sccm] and nitrous oxide gas (N ₂ O) at 4000 [sccm]. The film was formed with an applied power of 150 [W] while maintaining [Pa] and heating the substrate to 220 [° C.].

The silicon oxynitride film as the second region has a pressure of 200 while introducing monosilane gas (SiH ₄ ) into the deposition chamber at a flow rate of 160 [sccm] and nitrous oxide gas (N ₂ O) at 4000 [sccm]. The film was formed with an applied power of 1500 [W] while the substrate was maintained at [Pa] and heated to 220 [° C.].

In the above-described embodiment, the description has been given of forming the second insulating film, the partition wall, and the wiring on the first insulating film. However, in this embodiment, the side surface of the recess formed in the semiconductor layer is curved. In addition, for the purpose of confirming whether or not generation of voids in the first insulating film can be suppressed by adopting a structure in which there is no step between the side surface of the semiconductor layer recess and the side surface of the titanium film. Therefore, the second insulating film, the partition wall, and the wiring are not formed.

Finally, the completed substrate was baked for 1 hour in a 250 [° C.] oven in a nitrogen atmosphere.

A cross-sectional shape of the sample formed through the above steps is shown in FIG.

Note that in FIG. 12A, a structure below the third gate insulating film is not shown, but the structure is formed by the above-described manufacturing method.

In FIG. 12A, a white broken line is shown in the boundary portion for easy understanding of the boundary between the IGZO film which is a semiconductor layer and the titanium film.

From FIG. 12A, a curved shape is confirmed on the side surface of the concave portion of the IGZO film. Further, it is confirmed that there is no step between the side surface of the IGZO film and the side surface of the titanium film. Then, it is confirmed that no void due to the step of the IGZO film is generated in the insulating film formed in the upper layer because the concave side surface of the IGZO film is curved.

In addition, as a comparative sample in FIG. 12A, the etching rate of the IGZO film is very fast as 30 [nm / min] in the removal process of the manufacturing method described above, and it is difficult to form a curved shape on the side surface of the semiconductor layer recess. A cross-sectional photograph of the sample manufactured under the conditions is shown in FIG.

From FIG. 12B, generation of voids is confirmed from the vicinity of the side surface of the recess of the semiconductor layer.

From the above comparison results, it can be seen that when the side surface of the recess of the semiconductor layer has a curved shape, the insulating film formed over the semiconductor layer, the source electrode, and the drain electrode is less likely to enter.

100 substrate 102 gate electrode 104 gate insulating layer 104a first gate insulating film 104b second gate insulating film 104c third gate insulating film 106 semiconductor layer 108 source electrode 108a first conductive film 108b second conductive film 108c second 3 conductive film 109 drain electrode 110 first insulating film 110a first region 110b second region 111 second insulating film 112 partition 114 wiring 130 recess 150 transistor 170 transistor 172 base film 174 gate insulating layer 180 transistor 182 back Gate electrode 901 Substrate 902 Pixel portion 903 Signal line driver circuit 904 Scan line driver circuit 905 Seal material 906 Substrate 908 Liquid crystal layer 910 Transistor 911 Transistor 913 Liquid crystal element 915 Connection terminal electrode 915a Connection terminal electrode 915b Connection terminal Pole 916 connecting terminal electrodes 917 conductive film 918a FPC
918b FPC
919 Anisotropic conductive agent 921 Planarizing film 922 Gate insulating film 923 Insulating film 924 Insulating film 930 First electrode 931 Second electrode 932 Insulating film 933 Insulating film 935 Spacer 936 Sealing material 938 Connection terminal electrode 941 Second electrode 943 Liquid crystal element 944 Insulating film 950 Silicon nitride film 951 Second electrode 955 Connection terminal electrode 960 Partition wall 961 Light emitting layer 963 Light emitting element 964 Filler 971 Source electrode 973 Drain electrode 975 Common potential line 977 Common electrode 985 Common potential line 987 Common electrode 1000 Substrate 1002 Semiconductor layer 1003 Source electrode 1004 Drain electrode 1005 V 1006 Insulating film 1008 Region 1100 Region 1102 Region 1103 Region 1104 Region 1105 Region 2101 Case 2102 Case 2103a First display portion 2103b Second Display unit 2104 Selection button 2105 Keyboard 2120 Electronic book 2121 Housing 2122 Shaft 2123 Housing 2125 Display unit 2126 Power source 2127 Display unit 2128 Operation key 2129 Speaker 2130 Housing 2131 Button 2132 Microphone 2133 Display unit 2134 Speaker 2135 Camera lens 2136 External Connection terminal 2141 Case 2142 Display unit 2143 Operation switch 2144 Battery 2150 Television device 2151 Case 2153 Display unit 2155 Stand

Claims (10)

A gate electrode on an insulating surface;
A gate insulating layer in contact with the gate electrode;
A semiconductor layer in contact with the gate insulating layer;
A source electrode and a drain electrode in contact with the semiconductor layer;
An insulating film in contact with the semiconductor layer, the source electrode, and the drain electrode;
Have
The semiconductor layer has a recess where the thickness of the portion that does not overlap the source electrode or the drain electrode is smaller than the thickness of the portion that overlaps the source electrode or the drain electrode,
The rising portion from the bottom surface to the side surface of the concave portion has a curved shape,
A semiconductor device characterized in that there is no step between a side surface of the source or drain electrode and a side surface of the recess. The semiconductor device according to claim 1, wherein an angle formed by the side surface of the source electrode or the side surface of the drain electrode with respect to the surface of the semiconductor layer is 30 ° or more and 80 ° or less. The source electrode and the drain electrode have a stacked structure composed of a plurality of conductive films, and there is no step between the side surface of the first layer of the conductive film and the side surface of the second layer of the conductive film. The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 3, wherein an angle formed by a side surface of the conductive film with respect to the surface of the semiconductor layer is 30 ° or more and 80 ° or less. 5. The semiconductor device according to claim 1, wherein the semiconductor layer is a metal oxide film containing one or more elements selected from In, Ga, Sn, and Zn. The semiconductor device according to claim 1, wherein the insulating film includes a film capable of releasing oxygen of 1 × 10 ¹⁹ [atoms / cm ³ ] or more by heat treatment. Forming a gate electrode on the insulating surface;
Forming a gate insulating layer in contact with the gate electrode;
Forming a semiconductor layer in contact with the gate insulating layer;
Forming a conductive film on the semiconductor layer;
By selectively removing the conductive film and the semiconductor layer, a source electrode and a drain electrode are formed on the semiconductor layer, and a rising portion from the bottom surface to the side surface of the semiconductor layer is curved. Forming a recess having a shape;
Forming an insulating film covering the concave portion of the semiconductor layer and the source electrode and the drain electrode;
Have
A method for manufacturing a semiconductor device, characterized in that there is no step between a side surface of the source or drain electrode and a side surface of the recess. The method for manufacturing a semiconductor device according to claim 7, wherein a film thickness at which the semiconductor layer is removed per minute by the removal treatment is 1/10 or more and 1/3 or less of a film thickness of the semiconductor layer. 9. The method for manufacturing a semiconductor device according to claim 7, wherein a metal oxide film containing one or more elements selected from In, Ga, Sn, and Zn is formed as the semiconductor layer. 10. The method for manufacturing a semiconductor device according to claim 7, wherein a film capable of releasing oxygen of 1 × 10 ¹⁹ [atoms / cm ³ ] or more by heat treatment is used as the insulating film.