JP2016105444A - Manufacturing method of thin film transistor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a thin film transistor substrate which can secure the desired TFT performance.SOLUTION: A manufacturing method of a thin film transistor substrate 100 having a thin film transistor includes: a metal layer formation process for forming a gate electrode 120 with Cu as a main component on the upper side of a substrate 110; a first insulation layer formation process for forming a first SiN layer 131 at the deposition temperature equal to or lower than 360°C on the surface of the gate electrode 120; a second insulation layer formation process for forming a second SiN layer 132 at the deposition temperature higher than 360°C on the first SiN layer 131; and a channel layer formation process for forming an oxide semiconductor layer 140 being a channel layer of the thin film transistor on the upper side of the substrate 110.SELECTED DRAWING: Figure 6

Description

  The present disclosure relates to a method for manufacturing a thin film transistor substrate.

  An active matrix display device such as a liquid crystal display device using liquid crystal or an organic EL (OLED) display device using organic EL (Electro Luminescence) includes a thin film transistor (TFT) as a switching element or a driving element. : Thin Film Transistor).

  In recent years, as a TFT for a display device, an oxide semiconductor TFT using a transparent amorphous oxide semiconductor (TAOS) as a channel layer has been developed. For example, an oxide semiconductor TFT using TAOS made of a metal oxide (IGZO) of indium (In), gallium (Ga), and zinc (Zn) as a channel layer.

  In order to improve the characteristics of a channel layer in a TFT substrate in which thin film transistors using TAOS are formed in a matrix, an insulating layer formed around the channel layer, gate electrode, source electrode, drain electrode, and wiring is used. There is a need to reduce the hydrogen content.

In Patent Literature 1, the hydrogen content of the SiO ₂ layer in the lower region in contact with the source electrode or the drain electrode is in order to obtain good TFT characteristics while ensuring the adhesion between the electrode and wiring and the insulating layer. A semiconductor device is disclosed that is larger than the hydrogen content of the SiO ₂ layer in the upper region located above the lower region.

International Publication No. 2013/179837

  In TFT substrates used in display devices, it is necessary to reduce the hydrogen content of the insulating layer and improve the breakdown voltage of the insulating layer in order to ensure the desired TFT performance with respect to variations in TFT characteristics and lifetime, etc. There is a problem that it is difficult to secure a necessary breakdown voltage while reducing the hydrogen content.

  An object of this indication is to provide the manufacturing method of the thin-film transistor substrate which can ensure desired TFT performance.

  In order to achieve the above object, one aspect of a method of manufacturing a thin film transistor substrate is a method of manufacturing a thin film transistor substrate including a thin film transistor, wherein a metal layer forming step of forming a metal layer containing Cu as a main component above the substrate A first insulating layer forming step of forming a first insulating layer made of Si and N at a film forming temperature of 360 ° C. or less on the surface of the metal layer, and 360 ° C. on the first insulating layer. A second insulating layer forming step for forming a second insulating layer made of Si and N at a higher deposition temperature, and a channel layer for forming an oxide semiconductor layer to be a channel layer of the thin film transistor above the substrate And a forming step.

  According to the present disclosure, it is possible to realize a thin film transistor substrate in which desired TFT performance relating to variations in TFT characteristics, lifetime, and the like is ensured.

It is a partially cutaway perspective view of an organic EL display device according to an embodiment. It is a perspective view which shows an example of the pixel bank of the organic electroluminescence display which concerns on embodiment. It is an electric circuit diagram which shows the structure of the pixel circuit in the organic electroluminescence display which concerns on embodiment. It is sectional drawing of the thin-film transistor substrate which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on embodiment. It is a graph showing the relationship between the film-forming temperature of a SiN layer, hydrogen concentration, and the number of edge defects. It is a graph showing the bond energy waveform of Cu metal film when the film-forming temperature of Cu metal film is changed. It is a graph comparing the binding energy waveform of Cu ₂ O and CuO. It is a graph showing the absorption spectrum of a SiN film. It is a graph showing the threshold voltage variation of the thin-film transistor which has the 2nd SiN layer formed at the film-forming temperature of 360 degreeC. It is a graph showing the threshold voltage variation of the thin-film transistor which has the 2nd SiN layer formed at the film-forming temperature of 390 degreeC. It is a graph showing the relationship between the film thickness ratio of a 1st SiN layer, and threshold voltage dispersion | variation.

(Knowledge that became the basis of this disclosure)
The present inventor has found that the following problems occur with respect to the conventional semiconductor device (TFT substrate) described in the “Background Art” section.

  In the case of a TFT substrate for large-area and high-definition displays, an SiN (silicon nitride) layer made of Si and N is used as an insulating layer in close contact with the gate electrode because of its relationship with the TFT gate electrode, such as density and stress. Is used. In this case, in order to improve the characteristics of the oxide semiconductor forming the channel layer, it is necessary to minimize the amount of hydrogen remaining in the SiN layer. Moreover, it is necessary to improve the withstand voltage of the SiN layer. From the viewpoint of reducing the amount of hydrogen remaining in the SiN layer and improving the withstand voltage of the SiN layer, it is necessary to set the deposition temperature of the SiN layer as high as possible.

  On the other hand, a TFT substrate for a large area and high-definition display requires a reduction in resistance of electrodes and wiring, and therefore, a metal layer mainly composed of Cu is used for each electrode and wiring. At this time, when an SiN layer is formed on the Cu metal layer at a high temperature, an abnormal end of the Cu metal layer (reverse taper shape, chipping, etc.) occurs due to warpage of the substrate due to film stress and temperature distribution. It becomes easy. Due to the abnormal end, the SiN layer is cracked, and an interlayer short circuit and a decrease in dielectric strength are liable to occur, and the yield of the TFT is greatly deteriorated.

On the other hand, by adjusting the hydrogen content of the SiN layer by changing the SiH ₄ / N ₂ O flow rate ratio when forming the SiN layer by CVD, or by forming a diffusion prevention layer on the Cu metal layer A method for suppressing interlayer short-circuiting is conceivable. However, until now, sufficient insulation breakdown voltage of the SiN layer has not been secured by the above method, and the occurrence of abnormal end of the Cu metal layer has not been completely suppressed.

  Accordingly, a method of manufacturing a thin film transistor substrate according to the present disclosure is a method of manufacturing a thin film transistor substrate including a thin film transistor, wherein a metal layer forming step of forming a metal layer mainly composed of Cu above the substrate, and the metal layer A first insulating layer forming step of forming a first insulating layer made of Si and N at a film forming temperature of 360 ° C. or less on the surface of the film, and a film forming higher than 360 ° C. on the first insulating layer. A second insulating layer forming step of forming a second insulating layer made of Si and N at a temperature; and a channel layer forming step of forming an oxide semiconductor layer to be a channel layer of the thin film transistor above the substrate. .

  Thereby, by forming the first SiN layer on the surface of the metal layer, an abnormal end of the metal layer is suppressed, so that an interlayer short can be reduced, and the hydrogen content of the second SiN layer affecting the characteristics of the channel layer Can be reduced. Therefore, it is possible to realize a thin film transistor substrate having desired TFT performance with respect to variations in TFT characteristics and lifetime.

  Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Therefore, numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present disclosure. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

  Further, in this specification, the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute space recognition, but are based on the stacking order in the stacking configuration. Is used as a term defined by the relative positional relationship. Also, the terms “upper” and “lower” refer not only to the case where two components are spaced apart from each other and there is another component between the two components. The present invention is also applied when two components are in close contact with each other and are in contact with each other.

(Embodiment)
[1. Organic EL display device]
First, a configuration of an organic EL display device will be described as an example of a display device using a TFT substrate. FIG. 1 is a partially cutaway perspective view of an organic EL display device 10 according to the present embodiment. FIG. 2 is a perspective view showing an example of a pixel bank of the organic EL display device 10 according to the present embodiment.

[1-1. Constitution]
As shown in FIG. 1, an organic EL display device 10 includes a TFT substrate (TFT array substrate) 20 on which a plurality of thin film transistors are arranged, an anode 41 that is a lower electrode, and an EL layer 42 that is a light emitting layer made of an organic material. And it is comprised by the laminated structure with the organic EL element (light emission part) 40 which consists of the cathode 43 which is a transparent upper electrode.

  A plurality of pixels 30 are arranged in a matrix on the TFT substrate 20, and each pixel 30 is provided with a pixel circuit 31.

  The organic EL element 40 is formed corresponding to each of the plurality of pixels 30, and the light emission of each organic EL element 40 is controlled by the pixel circuit 31 provided in each pixel 30. The organic EL element 40 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.

  The organic EL element 40 has a configuration in which an EL layer 42 is disposed between an anode 41 and a cathode 43. A hole transport layer is further laminated between the anode 41 and the EL layer 42, and an electron transport layer is further laminated between the EL layer 42 and the cathode 43. Note that another organic functional layer may be provided between the anode 41 and the cathode 43.

  Each pixel 30 is driven and controlled by a respective pixel circuit 31. The TFT substrate 20 includes a plurality of gate wirings (scanning lines) 50 arranged along the row direction of the pixels 30 and a plurality of gate wirings 50 arranged along the column direction of the pixels 30 so as to intersect the gate wiring 50. Source wiring (signal wiring) 60 and a plurality of power supply wirings (not shown in FIG. 1) arranged in parallel with the source wiring 60 are formed. Each pixel 30 is partitioned by, for example, an orthogonal gate line 50 and a source line 60.

  The gate wiring 50 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each row. The source wiring 60 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a drive element included in each pixel circuit 31 for each column.

  As shown in FIG. 2, each pixel 30 of the organic EL display device 10 is composed of sub-pixels 30R, 30G, and 30B of three colors (red, green, and blue), and these sub-pixels 30R, 30G, and 30B. Are formed in a matrix on the display surface. The sub-pixels 30R, 30G, and 30B are separated from each other by the bank 21.

  The banks 21 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 50 and the ridges extending in parallel to the source wiring 60 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 21) and the sub-pixels 30R, 30G, and 30B have a one-to-one correspondence. In the present embodiment, the bank 21 is a pixel bank, but may be a line bank.

  The anode 41 is formed for each of the sub-pixels 30R, 30G, and 30B on the interlayer insulating film (flattening layer) on the TFT substrate 20 and in the opening of the bank 21. Similarly, the EL layer 42 is formed for each of the sub-pixels 30R, 30G, and 30B on the anode 41 and in the opening of the bank 21. The transparent cathode 43 is continuously formed on the plurality of banks 21 so as to cover all the EL layers 42 (all the sub-pixels 30R, 30G, and 30B).

  Furthermore, the pixel circuit 31 is provided for each of the sub-pixels 30R, 30G, and 30B, and each of the sub-pixels 30R, 30G, and 30B and the corresponding pixel circuit 31 are electrically connected by a contact hole and a relay electrode. Has been. The sub-pixels 30R, 30G, and 30B have the same configuration except that the emission color of the EL layer 42 is different.

[1-2. Pixel circuit]
Here, the circuit configuration of the pixel circuit 31 in the pixel 30 will be described with reference to FIG. FIG. 3 is an electric circuit diagram showing the configuration of the pixel circuit 31 in the organic EL display device 10 according to the present embodiment.

  As shown in FIG. 3, the pixel circuit 31 includes a thin film transistor 32 that operates as a driving element, a thin film transistor 33 that operates as a switching element, and a capacitor 34 that stores data to be displayed on the corresponding pixel 30. . In the present embodiment, the thin film transistor 32 is a drive transistor for driving the organic EL element 40, and the thin film transistor 33 is a switching transistor for selecting the pixel 30.

  The thin film transistor 32 includes a drain electrode 33d of the thin film transistor 33 and a gate electrode 32g connected to one end of the capacitor 34, a drain electrode 32d connected to the power supply wiring 70, the other end of the capacitor 34, and an anode 41 of the organic EL element 40. And a semiconductor film (not shown). The thin film transistor 32 supplies a current corresponding to the data voltage held by the capacitor 34 from the power supply wiring 70 to the anode 41 of the organic EL element 40 through the source electrode 32 s. Thereby, in the organic EL element 40, a drive current flows from the anode 41 to the cathode 43, and the EL layer 42 emits light.

  The thin film transistor 33 includes a gate electrode 33g connected to the gate wiring 50, a source electrode 33s connected to the source wiring 60, a drain electrode 33d connected to one end of the capacitor 34 and the gate electrode 32g of the thin film transistor 32, and a semiconductor film. (Not shown). In the thin film transistor 33, when a predetermined voltage is applied to the connected gate wiring 50 and source wiring 60, the voltage applied to the source wiring 60 is stored in the capacitor 34 as a data voltage.

  Note that the organic EL display device 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 30 located at the intersection of the gate line 50 and the source line 60. Thereby, the corresponding organic EL element 40 selectively emits light by the thin film transistors 32 and 33 of each pixel 30 (each sub-pixel 30R, 30G, 30B), and a desired image is displayed.

[2. Configuration of Thin Film Transistor Substrate]
Next, the structure of the thin film transistor substrate 100 according to this embodiment will be described with reference to FIG. FIG. 4 is a cross-sectional view of the thin film transistor substrate 100 according to the present embodiment.

  The thin film transistor substrate 100 includes a substrate 110, a gate electrode 120, a gate insulating layer 130, an oxide semiconductor layer 140, an insulating layer 150, a source electrode 160s and a drain electrode 160d, and a protective layer 170. The gate electrode 120, the gate insulating layer 130, the oxide semiconductor layer 140, the insulating layer 150, and the source electrode 160s and the drain electrode 160d form a thin film transistor. As shown in FIG. 4, the thin film transistor substrate 100 is provided with a channel protection type bottom gate type TFT, and a top contact structure is adopted.

  Hereinafter, each component of the thin film transistor substrate 100 according to the present embodiment will be described in detail.

  The substrate 110 is an insulating substrate made of an insulating material, for example, a glass substrate made of a glass material such as quartz glass, non-alkali glass, or high heat resistant glass.

  The substrate 110 is not limited to a glass substrate, and may be a resin substrate made of a resin material such as polyethylene, polypropylene, or polyimide. Further, the substrate 110 may be a flexible substrate having sheet-like or film-like flexibility, such as a flexible glass substrate or a flexible resin substrate, instead of a rigid substrate. As the flexible resin substrate, for example, a substrate composed of a single layer or a laminate of film materials such as polyimide, polyethylene terephthalate, and polyethylene naphthalate can be used. Note that an undercoat layer may be formed on the surface of the substrate 110.

  The gate electrode 120 is a metal layer mainly composed of Cu formed in a predetermined shape above the substrate 110. Specifically, the gate electrode 120 has a single layer structure or a multilayer structure of a conductive film made of Cu or Cu alloy. Have. The gate electrode 120 has, for example, a stacked structure of a first layer 121 made of Mo and a second layer 122 made of Cu. The film thickness of the gate electrode 120 is, for example, 20 nm to 500 nm. When the thin film transistor substrate 100 is applied to a TFT substrate for a large area and high definition display, it is important to reduce the resistance of each electrode and wiring. From this viewpoint, Cu, which is a low resistance material, is used as the material of the gate electrode 120.

  The gate insulating layer 130 is disposed between the gate electrode 120 and the oxide semiconductor layer 140. In this embodiment, the gate insulating layer 130 is disposed so as to be located above the gate electrode 120. For example, the gate insulating layer 130 is formed so as to cover the gate electrode 120 over the entire surface of the substrate 110 on which the gate electrode 120 is formed. The film thickness of the gate insulating layer 130 is, for example, 50 nm to 500 nm.

  The gate insulating layer 130 includes a first SiN layer 131, a second SiN layer 132, and a silicon oxide layer 133.

  The first SiN layer 131 is a first insulating layer formed on the surface of the gate electrode 120 and made of a silicon nitride material having electrical insulation and made of Si and N. The film thickness of the first SiN layer 131 is, for example, 20 nm.

  The second SiN layer 132 is a second insulating layer formed on the first SiN layer 131 and made of a silicon nitride material having electrical insulation and made of Si and N. The film thickness of the second SiN layer 132 is, for example, 320 nm.

  The silicon oxide layer 133 is a third insulating layer formed on the second SiN layer 132 and made of a silicon oxide material having electrical insulation. The film thickness of the silicon oxide layer 133 is, for example, 10 nm.

  The reason for using silicon nitride without forming the entire gate insulating layer from only silicon oxide is as follows.

  In general, the silicon oxide film can reduce the amount of hydrogen in the film (that is, the hydrogen content) more than the silicon nitride film. Accordingly, when a silicon oxide film is used as the gate insulating layer, the amount of hydrogen taken in by the oxide semiconductor layer 140 can be reduced, and reduction in resistance of the oxide semiconductor layer 140 can be suppressed. However, since it is difficult to control the stress of the silicon oxide film according to the film formation conditions, when forming a silicon oxide film dense enough to be adapted as a gate insulating layer of a thin film transistor, the compressive stress of the silicon oxide film is low. Inevitable to grow. Accordingly, when the entire gate insulating layer is formed only by the silicon oxide film, a gate insulating layer having a large compressive stress and a large film thickness is formed, and the substrate 110 is warped.

  From the above viewpoint, in the thin film transistor substrate 100 according to the present embodiment, a silicon nitride film having a finer film quality than a silicon oxide film and capable of controlling stress is used as a gate insulating layer. However, since the silicon oxide layer 133 formed of a silicon oxide film sufficiently thinner than the second SiN layer 132 is disposed in a region adjacent to the oxide semiconductor layer 140, the substrate 110 is not warped. The amount of hydrogen taken in by the oxide semiconductor layer 140 can be further reduced.

  Here, the hydrogen content of the second SiN layer 132 is lower than the hydrogen content of the first SiN layer 131. In order to realize this relationship, in the thin film transistor substrate 100 according to the present embodiment, the deposition temperature of the first SiN layer 131 is lower than the deposition temperature of the second SiN layer 132.

  As described above, in order to improve the characteristics of the oxide semiconductor layer 140, it is necessary to reduce the amount of hydrogen remaining in the gate insulating layer as much as possible. Moreover, it is necessary to improve the withstand voltage as an interlayer insulating film of the gate insulating layer. In a predetermined temperature region, the silicon nitride film has a lower hydrogen content and a higher withstand voltage as the deposition temperature is higher. From this viewpoint, it is preferable to set the deposition temperature of the silicon nitride film as high as possible.

  On the other hand, Cu is used as the material of the gate electrode 120. As the deposition temperature of the SiN layer on the gate electrode 120 made of Cu is higher, abnormalities (reverse tapered shape, defects, etc.) are more likely to occur at the ends of the electrode due to substrate warpage and temperature distribution due to film stress. Become. Due to this abnormal end portion, the SiN layer is cracked, and an interlayer short circuit of the gate insulating layer 130 and a decrease in the withstand voltage are likely to occur, and the yield of the TFT is deteriorated.

  From the above viewpoint, the first SiN layer 131 adjacent to the gate electrode 120 is formed at a temperature lower than the film formation temperature of the second SiN layer 132 in order to avoid an abnormal end of the electrode. On the other hand, the second SiN layer 132 is formed at a temperature higher than the film formation temperature of the first SiN layer 131 in order to reduce the hydrogen content and ensure the withstand voltage.

  Note that the thickness of the first SiN layer 131 is preferably 10% or less of the total thickness of the first SiN layer 131 and the second SiN layer. In order to ensure good TFT characteristics, it is desirable to suppress the diffusion of hydrogen into the oxide semiconductor layer 140 as much as possible. On the other hand, in order to suppress the end portion abnormality of the gate electrode 120, the outermost surface of the gate electrode 120 may be covered with the first SiN layer 131. Therefore, by increasing the film thickness ratio of the second SiN layer to the first SiN layer 131, diffusion of hydrogen into the oxide semiconductor layer 140 can be suppressed while an interlayer short in the gate insulating layer 130 is reduced. Therefore, it is possible to realize a thin film transistor substrate having desired TFT performance with respect to variations in TFT characteristics and lifetime.

  The oxide semiconductor layer 140 is formed over the substrate 110 so as to face the gate electrode 120. Specifically, the oxide semiconductor layer 140 is formed on the gate insulating layer 130 at a position facing the gate electrode 120. For example, the oxide semiconductor layer 140 is formed in an island shape over the gate insulating layer 130 above the gate electrode 120. The film thickness of the oxide semiconductor layer 140 is, for example, 30 nm to 150 nm.

  As a material of the oxide semiconductor layer 140, for example, an oxide semiconductor material containing at least one of indium (In), gallium (Ga), and zinc (Zn) is used. For example, the oxide semiconductor layer 140 is made of a transparent amorphous oxide semiconductor (TAOS) such as amorphous indium gallium zinc oxide (InGaZnO: IGZO).

  The ratio of In: Ga: Zn is, for example, about 1: 1: 1. The ratio of In: Ga: Zn may be in the range of 0.8 to 1.2: 0.8 to 1.2: 0.8 to 1.2, but is not limited to this range.

  The oxide semiconductor layer 140 is a channel layer of a thin film transistor included in the thin film transistor substrate 100. A thin film transistor in which a channel layer is formed using a transparent amorphous oxide semiconductor has high carrier mobility and is suitable for a large-screen and high-definition display device. In addition, since the transparent amorphous oxide semiconductor can be formed at a low temperature, it can be easily formed on a flexible substrate such as a plastic or a film.

  The insulating layer 150 is disposed over the oxide semiconductor layer 140. Specifically, the insulating layer 150 is formed over the gate insulating layer 130 so as to cover the oxide semiconductor layer 140. The film thickness of the insulating layer 150 is, for example, 50 nm to 500 nm.

  In this embodiment, the insulating layer 150 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 140. Specifically, the insulating layer 150 is an etch stopper that prevents the oxide semiconductor layer 140 from being etched when the source electrode 160s and the drain electrode 160d formed over the oxide semiconductor layer 140 are patterned by etching. Acts as a layer. Accordingly, process damage on the back channel side of the oxide semiconductor layer 140 can be reduced in the bottom-gate TFT.

  The insulating layer 150 is made of a material having electrical insulation, and as an example, is a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, or a laminated film thereof.

  The silicon oxide film generates less hydrogen during film formation than the silicon nitride film. Therefore, by using a silicon oxide film as the insulating layer 150, performance deterioration of the oxide semiconductor layer 140 due to hydrogen reduction can be suppressed. Further, by forming an aluminum oxide film as the insulating layer 150, hydrogen and oxygen generated in the upper layer can be blocked by the aluminum oxide film. For these reasons, as the insulating layer 150, for example, a laminated film having a three-layer structure of a silicon oxide film, an aluminum oxide film, and a silicon oxide film is preferably used.

  Note that the material of the insulating layer 150 is not limited to the inorganic material as described above, and a material mainly containing an organic material may be used.

  In addition, an opening (contact hole) is formed in the insulating layer 150 so as to penetrate a part of the insulating layer 150. Through the opening of the insulating layer 150, the oxide semiconductor layer 140 is connected to the source electrode 160s and the drain electrode 160d.

  The source electrode 160 s and the drain electrode 160 d are formed in a predetermined shape so as to be at least partially located above the insulating layer 150 and connected to the oxide semiconductor layer 140. Specifically, the source electrode 160 s and the drain electrode 160 d are disposed on the insulating layer 150 so as to be spaced apart from each other in a horizontal direction (substrate horizontal direction) with respect to the substrate 110, and on the insulating layer 150. The oxide semiconductor layer 140 is connected to the formed opening. The film thickness of the source electrode 160s and the drain electrode 160d on the insulating layer 150 is, for example, 100 nm to 500 nm.

  The source electrode 160s and the drain electrode 160d are electrodes having a single layer structure or a multilayer structure of a conductive film made of a conductive material or an alloy thereof. As a material of the source electrode 160s and the drain electrode 160d, for example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, chromium, or the like is used. As an example, the source electrode 160s and the drain electrode 160d are single layer electrodes formed of a molybdenum tungsten film (MoW film).

  The protective layer 170 is an insulating film disposed on the source electrode 160s and the drain electrode 160d. Specifically, the protective layer 170 is formed on the insulating layer 150 so as to cover the source electrode 160s and the drain electrode 160d. The film thickness of the protective layer 170 is, for example, 50 nm to 500 nm.

  The protective layer 170 is made of a material having electrical insulation, and is, for example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, or a laminated film thereof.

[3. Method for manufacturing thin film transistor substrate]
Next, a method for manufacturing the thin film transistor substrate 100 according to the present embodiment will be described with reference to FIGS. 5A and 5B. 5A and 5B are schematic cross-sectional views illustrating the manufacturing process of the thin film transistor substrate according to the present embodiment.

  First, as shown to (a) of FIG. 5A, the board | substrate 110 is prepared and the gate electrode 120 of a predetermined shape is formed above the board | substrate 110 (metal layer formation process). For example, a metal film is formed on the substrate 110 by sputtering, and the metal film is processed by photolithography and etching, whereby the gate electrode 120 having a predetermined shape is formed.

  Specifically, first, a glass substrate is prepared as the substrate 110, and a first layer 121 made of 20 nm of Mo and a second layer 122 made of 200 nm of Cu are sequentially formed on the substrate 110 by sputtering. Then, a resist pattern is formed by photolithography, and the first layer 121 and the second layer 122 are processed by wet etching at room temperature using a PAN (Phosphoric-Acetic-Nitric-acid) solution, whereby the gate electrode 120 is processed. Form. For removing the resist, a stripping solution containing an alkali additive may be used. The substrate 110 is, for example, a G8.5 glass substrate (thickness: 0.5 mm, X: 2500 mm × Y: 2200 mm). Note that an undercoat layer such as a silicon oxide film may be formed on the surface of the substrate 110 before the gate electrode 120 is formed.

Next, as shown in FIG. 5A (b), a first SiN layer 131 is formed on the surface of the gate electrode 120 at a film forming temperature of 360 ° C. or less (first insulating layer forming step). In the present embodiment, a first SiN layer 131 is formed over the entire surface of the substrate 110 so as to cover the gate electrode 120. In this case, for example, by the plasma CVD (Chemical Vapor Deposition) method, using the silane gas (SiH ₄ ), nitrogen (N ₂ ), and ammonia (NH ₃ ) as the introduction gas, the first SiN layer 131 at a processing temperature of 360 ° C. or less. Is deposited. As the conditions for the CVD film formation in this step, for example, the film formation temperature is 290 ° C., the processing pressure is 100-150 Pa, the N ₂ flow rate is 60000-70000 sccm, the NH ₃ flow rate is 20000-30000 sccm, and the SiH ₄ flow rate is 2000-3000 sccm. The input power was 6 kW and the film formation time was 15-17 seconds. Thereby, the first SiN layer 131 having a thickness of 20 nm is formed.

  When an undercoat layer is formed on the surface of the substrate 110, the first SiN layer 131 is formed on the undercoat layer.

Next, as shown in FIG. 5A (c), a second SiN layer 132 is formed on the first SiN layer 131 at a deposition temperature higher than 360 ° C. (second insulating layer forming step). In the present embodiment, the second SiN layer 132 is formed on the entire surface of the first SiN layer 131 so as to cover the first SiN layer 131. In this case, as in the first insulating layer forming step, silane gas (SiH ₄ ), nitrogen (N ₂ ), and ammonia (NH ₃ ) are used as the introduction gas by plasma CVD at a processing temperature higher than 360 ° C. A second SiN layer 132 is formed. As the conditions for the CVD film formation in this step, for example, the film formation temperature is 395 ° C., the processing pressure is 100-150 Pa, the N ₂ flow rate is 60000-70000 sccm, the NH ₃ flow rate is 20000-30000 sccm, and the SiH ₄ flow rate is 2000-3000 sccm. The input power was 6 kW and the film formation time was 270-280 seconds. Thereby, the second SiN layer 132 having a thickness of 320 nm is formed.

  Hereinafter, the characteristics of the first SiN layer 131 and the second SiN layer 132 formed in the above process will be described with reference to FIGS.

FIG. 6 is a graph showing the relationship between the deposition temperature of the SiN layer, the hydrogen concentration, and the number of edge defects. In this figure, the horizontal axis is the film formation temperature (° C.) when the SiN layer is formed by plasma CVD, the left side of the vertical axis is the hydrogen concentration (/ cm ³ ) of the SiN layer, and the right side of the vertical axis is This is the number of edge defects (pieces) representing the frequency of defects in the gate electrode 120 when the gate electrode 120 and the SiN layer are stacked. Note that the number of edge defects shown on the right side of the vertical axis indicates that the gate electrode is short-circuited with other electrodes due to an abnormal end of the gate electrode 120 in the TFTs for 100 pixels formed on the TFT substrate. This represents the number of TFTs.

  As shown in FIG. 6, the number of edge defects in the gate electrode 120 is abruptly generated when the film formation temperature is higher than 360.degree. This phenomenon will be described with reference to FIGS. 7A and 7B.

FIG. 7A is a graph showing a binding energy waveform of the Cu metal film when the processing temperature of the Cu metal film is changed. Specifically, the figure shows the XPS measurement waveform on the surface of the Cu metal film with the processing temperature changed. FIG. 7B is a diagram comparing the binding energy waveforms of Cu ₂ O and CuO.

As shown in FIG. 7B, significant differences are observed in the XPS measurement waveforms of Cu ₂ O and CuO within a predetermined binding energy range (945 eV-940 eV). That is, the surface oxidation state of the Cu metal film can be understood by comparing the waveforms in the predetermined binding energy range. Specifically, on the surface of the Cu metal film, it can be determined that the oxidation proceeds as CuO (Cu ²⁺ ) increases more than Cu ₂ O (Cu ⁺ ). From this point of view, when the binding energy waveforms in FIG. 7A are compared, the Cu metal film having a processing temperature of 360 ° C. or lower has a high Cu ₂ O (Cu ⁺ ) ratio, and the Cu metal film having a processing temperature of 395 ° C. has a CuO It can be seen that the ratio of (Cu ²⁺ ) increases rapidly.

  As described above, when the processing temperature exceeds 360 ° C., the oxidation on the surface of the Cu metal film proceeds. Therefore, even in the gate electrode 120 containing Cu as a main component, the film forming temperature of the upper first SiN layer 131 is 360. If the temperature exceeds ℃, it is presumed that Cu oxidation proceeds on the surface of the gate electrode 120. When Cu oxidation proceeds on the surface of the gate electrode 120, it is considered that the reconfiguration of the Cu film is promoted particularly at the end portion of the gate electrode 120, and a protrusion or a defect portion that becomes an edge defect is formed.

  From the above results based on FIGS. 6, 7A, and 7B, the deposition temperature T1 of the first SiN layer 131 needs to be 360 ° C. or lower.

  The film formation temperature T1 of the first SiN layer 131 is preferably 250 ° C. or higher. The stress applied to the gate electrode 120 and the substrate 110 by the film formation of the first SiN layer 131 is smaller as the film formation temperature T1 of the first SiN layer 131 is lower. On the other hand, the lower the deposition temperature T1 of the first SiN layer 131, the lower the binding energy between the gate electrode 120 and the first SiN layer 131. When the deposition temperature is lower than 250 ° C., the adhesion strength is significantly reduced. The 1SiN layer 131 is peeled off. Thereby, in the formation process of the 1st SiN layer 131, it is preferable to form a 1st SiN layer with the film-forming temperature T1 of 250 degreeC or more and 360 degrees C or less.

  On the other hand, as shown in FIG. 6, the hydrogen concentration of the SiN layer decreases as the film forming temperature increases. This phenomenon will be described with reference to FIGS.

FIG. 8 is a graph showing the absorption spectrum of the SiN film. Note that the hydrogen concentration of the SiN film shown in FIG. 6 is calculated from the absorbance spectrum of the SiN film obtained by FT-IR (Fourier transform infrared spectrophotometer) shown in FIG. Specifically, the hydrogen concentration of the SiN film can be calculated by obtaining the area of the peak waveform appearing in the absorption band (2200-2100 cm ⁻¹ ) derived from the stretching vibration of SiH molecules in the SiN film.

  In order to improve the characteristics of the oxide semiconductor layer 140, it is necessary to reduce the amount of hydrogen remaining in the gate insulating layer as much as possible. Moreover, it is necessary to improve the withstand voltage as an interlayer insulating film of the gate insulating layer. As shown in FIG. 6, the SiN layer has a lower hydrogen content and a higher withstand voltage in a predetermined temperature region as the film formation temperature is higher. From this viewpoint, it is preferable to set the deposition temperature of the SiN layer as high as possible.

  Here, the hydrogen content of the second SiN layer 132 can be made lower than the hydrogen content of the first SiN layer 131 by setting the film forming temperature T2 of the second SiN layer 132 to be higher than 360 ° C.

Furthermore, the film forming temperature T2 of the second SiN layer 132 is preferably 370 ° C. or higher. In a TFT substrate for a large area and high definition display, it is necessary to suppress variations in characteristics of thin film transistors. In particular, ΔVth, which is a variation range of the threshold voltage Vth of the thin film transistor, is required to be a predetermined value or less. In order to set this ΔVth to a predetermined value or less, the hydrogen concentration of the second SiN layer 132 is preferably 2.0 × 10 ²¹ / cm ³ or less. From the graph of FIG. 6, the film formation temperature T2 at which the hydrogen concentration becomes 2.0 × 10 ²¹ / cm ³ or less is required to be 370 ° C. or more.

  FIG. 9A is a graph showing threshold voltage variation of a thin film transistor having a second SiN layer formed at a film formation temperature of 360 ° C., and FIG. 9B shows a second SiN layer formed at a film formation temperature of 390 ° C. It is a graph showing the threshold voltage variation of the thin film transistor which has. Comparing FIG. 9A and FIG. 9B, it can be seen that the variation in threshold voltage value is smaller in the thin film transistor when the second SiN layer 132 is formed at a film formation temperature of 390 ° C.

  As described above, in the step of forming the second SiN layer 132, it is preferable to form the second SiN layer 132 at a film formation temperature of 370 ° C. or higher. Thereby, variation in threshold voltage of the thin film transistor is suppressed, and desired performance can be ensured.

  Note that the thickness of the first SiN layer 131 is preferably 10% or less of the total thickness of the first SiN layer 131 and the second SiN layer.

  FIG. 10 is a graph showing the relationship between the thickness ratio of the first SiN layer and the threshold voltage variation. The horizontal axis of FIG. 10 represents the film thickness ratio (%) of the first SiN layer 131 to the film thickness obtained by adding the film thickness of the first SiN layer 131 and the film thickness of the second SiN layer 132. The vertical axis represents ΔVth variation (V) indicating variation in threshold voltage of the thin film transistor after the positive bias temperature stress (PBTS) test.

  Note that, in the film thickness ratio of the first SiN layer 131 shown in FIG. 10, the total film thickness of the first SiN layer 131 and the second SiN layer 132 is fixed to 340 nm, and the film thickness of the silicon oxide layer 133 is fixed to 10 nm. The film thickness ratio between the first SiN layer 131 and the second SiN layer 132 is changed. The stress conditions of the PBTF test are a temperature of 90 degrees, a gate-source voltage of +20 V, a drain-source voltage of 0 V, and a time of 2000 seconds. The measurement conditions of the PBTS test are a drain-source voltage of 5V, a gate-source voltage range of -10V to + 10V, and a step of 0.1V. Note that the channel width and the channel length of the TFT substrate to be subjected to the PBTS test are both 12 μm. Further, when the coordinates (X, Y) of the lower left end of the substrate are represented by (0, 0), the measurement position has an X coordinate in the range of 1400 mm to 2400 mm and a Y coordinate of 960 mm.

  As shown in FIG. 10, when the film thickness ratio of the first SiN layer 131 is 10% or less, the ΔVth variation (V) is 0.5 V or less, but the film thickness ratio of the first SiN layer 131 is If it exceeds 10%, the ΔVth change amount (V) increases as the film thickness ratio increases.

  In order to ensure good TFT characteristics, it is desirable to suppress the diffusion of hydrogen into the oxide semiconductor layer 140 as much as possible. On the other hand, in order to suppress the end portion abnormality of the gate electrode 120, the outermost surface of the gate electrode 120 may be covered with the first SiN layer 131. Therefore, by increasing the film thickness ratio of the second SiN layer having a low hydrogen content with respect to the first SiN layer 131 having a high hydrogen content, the hydrogen content of the gate insulating layer 130 can be reduced. Therefore, diffusion of hydrogen into the oxide semiconductor layer 140 can be suppressed while reducing an interlayer short in the gate insulating layer 130. Therefore, it is possible to realize a thin film transistor substrate having desired TFT performance with respect to variations in TFT characteristics and lifetime.

  Returning to FIG. 5A, a method of manufacturing the thin film transistor substrate 100 according to the present embodiment will be described.

Next, as shown in FIG. 5A (d), a silicon oxide layer 133 is formed on the second SiN layer 132 (third insulating layer forming step). In this case, for example, the silicon oxide layer 133 is formed by plasma CVD (Chemical Vapor Deposition) using silane gas (SiH ₄ ), argon (Ar), and nitrogen (N ₂ ) as the introduction gas. As conditions for the CVD film formation in this step, for example, the Ar flow rate was 80000-90000 sccm, the N ₂ flow rate was 40000-50000 sccm, the SiH ₄ flow rate was 1000-2000 sccm, the input power was 6 kW, and the film formation time was 40 seconds. Thereby, a silicon oxide layer 133 having a thickness of 10 nm is formed.

  In addition, the 1st-3rd insulating layer formation process mentioned above is performed continuously. That is, after the first SiN layer 131 is formed using the plasma CVD apparatus, the second SiN layer 132 and the silicon oxide layer 133 are formed without breaking the vacuum in the chamber of the plasma CVD apparatus. Thereby, the possibility that impurities are mixed can be reduced.

  Next, as illustrated in FIG. 5A, an oxide semiconductor layer 140 having a predetermined shape is formed above the substrate 110 and at a position facing the gate electrode 120. For example, an oxide semiconductor film is formed over the gate insulating layer 130 by sputtering. Then, by processing the oxide semiconductor film by photolithography and etching, the oxide semiconductor layer 140 having a predetermined shape is formed.

Specifically, on the gate insulating layer 130 by sputtering in a mixed gas atmosphere of oxygen (O ₂ ) and argon (Ar) using a target material having a composition ratio of In: Ga: Zn = 1: 1: 1. Next, an amorphous InGaZnO film of 90 nm is formed. More specific film forming conditions are, for example, a power of 12 kW, an oxygen partial pressure of the film forming gas of 4.5%, and a film forming rate of 100 nm / min in the DC magnetron sputtering method.

Then, the oxide semiconductor layer 140 is formed by wet etching the amorphous InGaZnO formed over the gate insulating layer 130. InGaZnO wet etching can be performed using, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and a surfactant are mixed. For removing the resist, a stripping solution containing an alkali additive may be used.

  Next, as illustrated in FIG. 5A (f), the insulating layer 150 is formed over the oxide semiconductor layer 140. In this embodiment, the insulating layer 150 is formed over the entire surface of the gate insulating layer 130 so as to cover the oxide semiconductor layer 140.

The insulating layer 150 is, for example, a silicon oxide film. In this case, a silicon oxide film is formed by plasma CVD using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as the introduction gas.

  Next, as illustrated in FIG. 5B (a), a contact hole is formed in the insulating layer 150 so that a part of the region of the oxide semiconductor layer 140 is exposed. Specifically, a part of the insulating layer 150 is removed by etching by a photolithography method and an etching method, so that contact holes (openings) are formed over regions to be a source contact region and a drain contact region.

For example, when the insulating layer 150 is a silicon oxide film, a contact hole can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

  Next, as illustrated in FIGS. 5B and 5C, a source electrode 160s and a drain electrode 160d connected to the above region of the oxide semiconductor layer 140 are formed. For example, the source electrode 160s and the drain electrode 160d having a predetermined shape are formed on the insulating layer 150 so as to fill the contact holes formed in the insulating layer 150.

  In this embodiment, MoW film single-layer electrodes are formed as the source electrode 160s and the drain electrode 160d. In this case, first, as shown in FIG. 5B (b), a MoW film 160 is formed on the insulating layer 150 by sputtering so as to fill the contact hole of the insulating layer 150. Thereafter, as shown in FIG. 5B (c), the MoW film is patterned by photolithography and wet etching. Thereby, the source electrode 160s and the drain electrode 160d having a predetermined shape can be formed.

In addition, as the etching solution for the MoW film, for example, a chemical solution in which hydrogen peroxide solution (H ₂ O ₂ ) and an organic acid are mixed can be used.

  Finally, as shown in FIG. 5B (d), a protective layer 170 is formed on the source electrode 160s and the drain electrode 160d. In this embodiment, the protective layer 170 is formed over the entire surface of the insulating layer 150 so as to cover the source electrode 160s and the drain electrode 160d.

The protective layer 170 is, for example, a silicon oxide film. In this case, a silicon oxide film can be formed by plasma CVD using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases.

  As described above, the thin film transistor substrate 100 having the configuration shown in FIG. 4 can be manufactured.

[4. Summary]
As described above, the manufacturing method of the TFT substrate 100 according to the present embodiment includes the metal layer forming step of forming the gate electrode 120 mainly composed of Cu above the substrate 110 and the surface of the gate electrode 120. A first insulating layer forming step of forming a first SiN layer 131 made of Si and N at a film forming temperature T1 of 360 ° C. or less; and a film forming temperature T2 higher than 360 ° C. on the first SiN layer. And a second insulating layer forming step for forming a second SiN layer 132 made of N, and a channel layer forming step for forming an oxide semiconductor layer 140 to be a channel layer of the TFT above the substrate 110.

  In the thin film transistor substrate 100 according to the present embodiment, a silicon nitride film having a finer film quality than a silicon oxide film and capable of controlling stress is used as a gate insulating layer. In order to improve the characteristics of the oxide semiconductor layer 140, it is necessary to reduce the amount of hydrogen remaining in the gate insulating layer 130 as much as possible. In addition, it is necessary to improve the withstand voltage of the gate insulating layer 130 as an interlayer insulating film. In a predetermined temperature region, the silicon nitride film has a lower hydrogen content and a higher withstand voltage as the deposition temperature is higher. From this viewpoint, it is preferable to set the deposition temperature of the silicon nitride film as high as possible.

  On the other hand, Cu is used as the material of the gate electrode 120. As the deposition temperature of the SiN layer on the gate electrode 120 made of Cu is higher, abnormalities (reverse tapered shape, defects, etc.) are more likely to occur at the ends of the electrode due to substrate warpage and temperature distribution due to film stress. Become. Due to this abnormal end portion, the SiN layer is cracked, and an interlayer short circuit of the gate insulating layer 130 and a decrease in the withstand voltage are likely to occur, and the yield of the TFT is deteriorated.

  From the above viewpoint, the first SiN layer 131 adjacent to the gate electrode 120 is formed at a temperature lower than the film formation temperature of the second SiN layer 132 in order to avoid an abnormal end of the electrode. On the other hand, the second SiN layer 132 is formed at a temperature higher than the film formation temperature of the first SiN layer 131 in order to reduce the hydrogen content and to ensure the withstand voltage.

  Accordingly, the hydrogen content of the gate insulating layer 130 which affects the oxide semiconductor layer 140 can be reduced and the breakdown voltage of the gate insulating layer 130 can be improved, so that desired TFT performance with respect to variations in TFT characteristics and lifetime can be ensured. A thin film transistor substrate can be realized.

  Further, for example, in the second insulating layer forming step, the second SiN layer 132 may be formed at a film forming temperature T2 of 370 ° C. or higher.

In a TFT substrate for a large area and high definition display, it is necessary to suppress variations in characteristics of thin film transistors. In particular, it is required to reduce variations in threshold voltage Vth of thin film transistors. Therefore, the hydrogen concentration of the second SiN layer 132 is preferably 2.0 × 10 ²¹ / cm ³ or less, and the film formation temperature that satisfies this hydrogen concentration condition is required to be 370 ° C. or more. . Thereby, variation in threshold voltage of the thin film transistor is suppressed, and desired performance can be ensured.

  Further, for example, in the first insulating layer forming step, the first SiN layer 131 may be formed at a film forming temperature T1 of 250 ° C. or higher.

  The lower the deposition temperature of the first SiN layer 131, the lower the binding energy between the gate electrode 120 and the first SiN layer 131. On the other hand, according to the present configuration, the adhesion strength between the gate electrode 120 and the first SiN layer 131 is ensured, so that the film peeling of the first SiN layer 131 can be prevented.

  Further, for example, in the first insulating layer forming step, the thickness of the first SiN layer 131 is 10% or less of the total thickness of the thickness of the first SiN layer 131 and the thickness of the second SiN layer 132. The first SiN layer may be formed.

  In order to ensure good TFT characteristics, it is desirable to suppress the diffusion of hydrogen into the oxide semiconductor layer 140 as much as possible. On the other hand, in order to suppress the end portion abnormality of the gate electrode 120, the outermost surface of the gate electrode 120 may be covered with the first SiN layer 131. Therefore, by increasing the film thickness ratio of the second SiN layer to the first SiN layer 131, diffusion of hydrogen into the oxide semiconductor layer 140 can be suppressed while an interlayer short in the gate insulating layer 130 is reduced. Therefore, it is possible to realize a thin film transistor substrate having desired TFT performance with respect to variations in TFT characteristics and lifetime.

  For example, the hydrogen content of the second SiN layer is lower than the hydrogen content of the first SiN layer.

  Accordingly, it is possible to reduce the hydrogen content in a region adjacent to the oxide semiconductor layer 140 while suppressing an abnormal end on the surface of the gate electrode 120.

(Other embodiments)
As described above, the embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed.

  Thus, other embodiments will be exemplified below.

  For example, in the above embodiment, the metal layer mainly composed of Cu is the gate electrode 120. However, the present invention is not limited to this. The metal layer may be, for example, the source electrode 160s or the drain electrode 160d, and the protective layer 170 formed on the source electrode 160s and the drain electrode 160d includes a first insulating layer and a second layer made of Si and N. You may have the laminated structure of an insulating layer. The metal layer may be other wiring formed on the thin film transistor substrate. In these cases, it is possible to reduce the hydrogen content in a region adjacent to the oxide semiconductor layer 140 while suppressing end abnormalities on the surface of each electrode or wiring.

  In the above embodiment, an example in which the thin film transistor is a bottom gate type is shown, but a top gate type may be used. Even in the top-gate configuration, a metal layer containing Cu as a main component can be applied to at least one of a gate electrode, a source electrode, a drain electrode, and other wirings.

  In the above embodiment, the plasma CVD method is exemplified as the film formation method of the first SiN layer 131 and the second SiN layer 132, but is not limited thereto. As a film formation method of the first SiN layer 131 and the second SiN layer 132, for example, a sputtering method can also be applied. In the film formation process of the first SiN layer 131 and the second SiN layer 132, the parameter that most affects the hydrogen content is the film formation temperature, and the film formation temperature is a parameter derived from the silicon nitride material. That is, the film formation method of the first SiN layer 131 and the second SiN layer 132 is not limited to a specific film formation method.

In the above-described embodiment, the N ₂ O plasma process is described as an example of the oxidizing process, but the present invention is not limited to this. Oxygen plasma treatment using oxygen gas (O ₂ ) instead of N ₂ O may be used. Thus, for example, when silane gas and oxygen gas are used as the film formation gas for the silicon oxide film, the film formation and the plasma treatment are continuously performed in the same chamber by performing oxygen plasma treatment using oxygen gas. Can be implemented. Therefore, convenience in production such as simplification and cost reduction of the apparatus can be enhanced.

  Further, instead of the plasma treatment, a gas treatment using an oxidizing gas or a heating treatment (annealing treatment) in which heating is performed at a predetermined temperature may be performed as the oxidizing treatment. In addition, the relationship between the oxidation treatment parameter and the threshold value Vth of the thin film transistor may be a relationship other than a linear relationship.

  For example, in the above embodiment, the example in which the insulating layer 150 and the protective layer 170 are both formed of a silicon oxide film has been described, but the present invention is not limited thereto. For example, the insulating layer 150 and the protective layer 170 may be made of an oxide film such as an aluminum oxide film, for example.

  Further, for example, in the above embodiment, the example in which the insulating layer 150 has a single-layer structure is shown, but the present invention is not limited to this. The insulating layer 150 may include two or more oxide films.

  For example, in the above embodiment, the organic EL display device 10 has been described as a display device using the thin film transistor substrate 100. However, the thin film transistor substrate 100 in the above embodiment uses an active matrix substrate such as a liquid crystal display device. The present invention can also be applied to other display devices.

  In addition, the display device (display panel) such as the organic EL display device 10 described above can be used as a flat panel display, and is applied to all electronic devices having a display panel such as a television set, a personal computer, and a mobile phone. can do. In particular, it is suitable for a large-screen and high-definition display device.

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, among the components described in the accompanying drawings and the detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to illustrate the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, replacement, addition, omission, etc. can be performed in a claim or the equivalent range.

  The method for manufacturing a thin film transistor substrate according to the present disclosure can be used for a method for manufacturing a thin film transistor substrate using an oxide semiconductor and a method for manufacturing a display device such as an organic EL display device using the thin film transistor substrate.

10 Organic EL display device 20, 100 Thin film transistor substrate (TFT substrate)
21 banks 30 pixels 30B, 30G, 30R sub pixels 31 pixel circuits 32, 33 thin film transistors 32d, 33d, 160d drain electrodes 32g, 33g, 120 gate electrodes 32s, 33s, 160s source electrodes 34 capacitors 40 organic EL elements 41 anodes 42 EL layers 43 Cathode 50 Gate wiring 60 Source wiring 70 Power supply wiring 110 Substrate 121 First layer 122 Second layer 130 Gate insulating layer 131 First SiN layer 132 Second SiN layer 133 Silicon oxide layer 140 Oxide semiconductor layer 150 Insulating layer 160 MoW film 170 Protective layer

Claims (6)

A method of manufacturing a thin film transistor substrate including a thin film transistor,
A metal layer forming step of forming a metal layer mainly composed of Cu above the substrate;
A first insulating layer forming step of forming a first insulating layer made of Si and N at a film forming temperature of 360 ° C. or less on the surface of the metal layer;
A second insulating layer forming step of forming a second insulating layer made of Si and N on the first insulating layer at a film forming temperature higher than 360 ° C .;
And a channel layer forming step of forming an oxide semiconductor layer to be a channel layer of the thin film transistor above the substrate. The method for manufacturing a thin film transistor substrate according to claim 1, wherein in the second insulating layer forming step, the second insulating layer is formed at a film forming temperature of 370 ° C. or higher. 3. The method of manufacturing a thin film transistor substrate according to claim 1, wherein in the first insulating layer forming step, the first insulating layer is formed at a film forming temperature of 250 ° C. or higher. In the first insulating layer forming step, the thickness of the first insulating layer is 10% or less of the total thickness of the thickness of the first insulating layer and the thickness of the second insulating layer. The method for manufacturing a thin film transistor substrate according to claim 1, wherein the first insulating layer is formed. The method for manufacturing a thin film transistor substrate according to claim 1, wherein a hydrogen content of the second insulating layer is lower than a hydrogen content of the first insulating layer. The method for manufacturing a thin film transistor substrate according to claim 1, wherein the metal layer is a gate electrode of the thin film transistor.

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