WO2013018123A1

WO2013018123A1 - Thin film transistor and method for manufacturing same

Info

Publication number: WO2013018123A1
Application number: PCT/JP2011/004350
Authority: WO
Inventors: 林　宏; 孝啓川島; 玄士朗河内
Original assignee: パナソニック株式会社; パナソニック液晶ディスプレイ株式会社
Priority date: 2011-07-29
Filing date: 2011-07-29
Publication date: 2013-02-07

Abstract

The purpose of this thin film transistor is to provide a thin film transistor that can establish both superior ON characteristics and superior OFF characteristics and in which the electrical characteristics are symmetrical for interchanging the source electrode and drain electrode. The thin film transistor is provided with: a substrate (100); a gate electrode (110); a gate insulating layer (120); a crystalline silicon layer (131) formed on the gate insulating layer (120) and above the gate electrode (110); a noncrystalline silicon layer (130) formed on the gate insulating layer (120) and on both sides of the crystalline silicon layer (131); a channel protective layer (140) formed on the crystalline silicon layer (131); and a source electrode (171) and drain electrode (172). The thicknesses of the crystalline silicon layer (131) film and the noncrystalline silicon layer (130) film are the same.

Description

[Title of Invention Determined by ISA Based on Rule 37.2] Thin Film Transistor and Manufacturing Method

The present invention relates to a thin film transistor, a method for manufacturing the same, and a display device.

In recent years, organic EL displays using organic electroluminescence (EL) as one of the next generation flat panel displays that replace liquid crystal displays have attracted attention. Unlike a voltage-driven liquid crystal display, an organic EL display is a current-driven device, and development of a thin film transistor (thin film semiconductor device) having excellent on / off characteristics as a drive circuit for an active matrix display device is urgently required. Yes.

A thin film transistor in which a crystalline silicon layer is formed on a gate insulating layer and an amorphous silicon layer is formed on both sides of the crystalline silicon layer is disclosed as a thin film transistor that realizes excellent on and off characteristics (patent) Reference 1). In this disclosed technique, in order to crystallize amorphous silicon as a channel layer, laser light is irradiated to amorphous silicon from an opening between a source electrode and a drain electrode. Thereby, only the amorphous silicon in the central region of the channel layer exposed at the opening can be formed as crystalline silicon. The mobility of amorphous silicon is about 1 cm ² / Vs, whereas the mobility of crystalline silicon is as large as about 100 cm ² / Vs, so that the on-state current can be increased by forming crystalline silicon. In this disclosed technique, an amorphous silicon layer is formed on both sides of the crystalline silicon layer. Compared to crystalline silicon, amorphous silicon has a large band gap, and has a large energy barrier necessary for heat generation of electrons and holes and a potential barrier in which a tunnel effect occurs. Therefore, by forming an amorphous silicon layer on both sides of the crystalline silicon layer, generation of heat generation current and tunnel leakage current can be prevented, and off current can be reduced. As described above, by forming the crystalline silicon that increases the on-current and the amorphous silicon that decreases the off-current as the channel layer, excellent on-characteristics and off-characteristics can be realized.

JP 2005-322898 A

However, in the technique disclosed in Patent Document 1, the portion where the source electrode, the drain electrode, the channel protective layer, and the channel layer overlap is made of amorphous silicon. That is, the ratio of the amorphous silicon layer to the channel length of the thin film transistor defined by the width of the channel protective layer is large. The amorphous silicon layer acts as a resistance component and becomes a barrier for a current path parallel to the channel layer. As described above, since the resistance component due to the amorphous silicon exists in the horizontal direction in the channel layer, there is a limit in improving the on-characteristic.

Furthermore, manufacturing variations occur when forming the source electrode and the drain electrode. Therefore, it is difficult to form the source electrode and the drain electrode evenly with respect to the lower layer existing before the source electrode and the drain electrode are formed. is there. When the source electrode and the drain electrode are arranged unevenly with respect to the lower layer, the amorphous silicon layer is irradiated with laser from the opening of the source electrode and the drain electrode to crystallize the amorphous silicon layer. The distance from the crystalline silicon region formed by the crystallization of the amorphous silicon to the source electrode, and the distance from the crystalline silicon region formed by the crystallization of the amorphous silicon to the drain electrode And are not even. That is, the resistance component in the channel path by the amorphous silicon layer existing in the portion where the source electrode, the drain electrode, the channel protective layer, and the channel layer overlap is biased on either the source electrode side or the drain electrode side. Therefore, the characteristics of the thin film transistor between different substrates vary. In the case where a thin film transistor is formed over a large substrate, the positional deviation when forming the source electrode and the drain electrode is larger than that in the small substrate, which is a particular problem in forming the thin film transistor over the large substrate. Even in the same substrate, when the source electrode and the drain electrode are switched and operated, the electrical characteristics become asymmetric with respect to the switching of the source electrode and the drain electrode. When the electrical characteristics are asymmetric with respect to the replacement of the source electrode and the drain electrode, problems associated with the asymmetry of the electrical characteristics may occur in the operation of the driving circuit formed of the thin film transistors. For example, when a thin film transistor having an asymmetric electrical characteristic is used as a switching transistor of a liquid crystal display, flicker occurs and display characteristics as an image display device are impaired.

Therefore, the present invention has been made in view of the above problems, and can achieve both excellent on-characteristics and excellent off-characteristics, and the electric characteristics are symmetrical with respect to the replacement of the source electrode and the drain electrode. An object of the present invention is to provide a thin film transistor, a manufacturing method thereof, and a display device.

To achieve the above object, the thin film transistor of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, and the gate insulating layer. A crystalline silicon layer formed above the gate electrode, an amorphous silicon layer formed on both sides of the crystalline silicon layer on the gate insulating layer, and formed on the crystalline silicon layer A crystalline control layer, and an upper surface of an end portion of the crystalline control layer, a side surface of the crystalline control layer, and an upper surface of the non-crystalline silicon layer along the upper surface of the non-crystalline silicon layer. And the drain electrode formed above the other of the amorphous silicon layer, and the thickness of the crystalline silicon layer and the thickness of the amorphous silicon layer are the same. Special To.

According to the present invention, there are provided a thin film transistor, a manufacturing method thereof, and a display device, which can achieve both excellent on characteristics and excellent off characteristics, and whose electrical characteristics are symmetrical with respect to replacement of a source electrode and a drain electrode. be able to.

FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a change in current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed. FIG. 4A is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorptance of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing. FIG. 4B is a diagram for explaining a method of calculating the light absorption rate into the amorphous silicon layer. FIG. 5A is a contour diagram showing the calculation result of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5B is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5C is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5D is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5E is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5F is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 6A shows a value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by adding the refractive index of the gate insulating layer to the film thickness of the gate insulating layer in laser annealing, by dividing the wavelength of the laser beam by 0.330 (wavelength It is a figure which shows the change of the absorptivity of an amorphous silicon layer when it is set as a silicon oxide layer film thickness corresponding to 120 nm at 532 nm. FIG. 6B is a diagram showing an example of a value obtained by converting the value on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer. FIG. 6C is a diagram illustrating an example of a value obtained by converting the value on the vertical axis in FIGS. 5A to 5F into the film thickness of the silicon oxide layer or the silicon nitride layer. FIG. 7 is a contour line showing the calculation results of the absorptivity of the amorphous silicon layer below the channel protective layer when the thickness of the channel protective layer and the thickness of the gate insulating layer are changed in laser annealing. FIG. FIG. 8A is a diagram showing a change in the absorptance of the amorphous silicon layer below the channel protective layer when the thickness of the channel protective layer is changed. FIG. 8B is a diagram showing a change in the absorptance of the amorphous silicon layer below the channel protective layer when the thickness of the channel protective layer is changed. FIG. 8C is a diagram showing a change in the absorptance of the amorphous silicon layer below the channel protective layer when the thickness of the channel protective layer is changed. FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a modification of the first and second embodiments of the present invention. FIG. 12 is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorption rate of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing. FIG. 13A is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 13B is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 13C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 13D is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 14 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a comparative example of the first and second embodiments of the present invention. FIG. 15 is an external view of a display device according to the third embodiment of the present invention. FIG. 16 is a partially cutaway perspective view of an organic EL panel according to the third embodiment of the present invention. FIG. 17 is a diagram showing a circuit configuration of a pixel of an organic EL panel according to the third embodiment of the present invention. FIG. 18A is a top view showing a state of laser light irradiation according to the embodiment of the present invention. FIG. 18B is a cross-sectional view showing the rising of the amorphous silicon layer according to the embodiment of the present invention. FIG. 18C is a diagram showing a change in the amount of swelling of the amorphous silicon layer with respect to the input energy of the laser beam according to the embodiment of the present invention.

In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and the gate insulating layer. A crystalline silicon layer formed above the gate electrode; an amorphous silicon layer formed on both sides of the crystalline silicon layer on the gate insulating layer; and the crystalline silicon A crystallization control layer formed on the layer; and the amorphous silicon layer along an upper surface of an end portion of the crystallization control layer, a side surface of the crystallization control layer, and an upper surface of the amorphous silicon layer. A source electrode formed on one side of the first electrode and a drain electrode formed on the other side of the non-crystalline silicon layer, and the thickness of the crystalline silicon layer and the thickness of the non-crystalline silicon layer are Same And wherein the Rukoto.

Here, the average grain size of crystals contained in the crystalline silicon layer may be 10 nm or more and 1 μm or less.

Further, both ends of the crystalline silicon layer and both ends of the crystallization control layer may be arranged at the same position on the semiconductor substrate.

Further, the crystalline silicon layer and the source electrode may have an overlapping region, and the crystalline silicon layer and the drain electrode may have an overlapping region.

According to this aspect, the channel layer is formed from the crystalline silicon layer formed under the crystallization control layer and the amorphous silicon layers formed on both sides of the crystalline silicon layer. The crystalline silicon layer is formed under the crystallization control layer, and the crystalline silicon layer occupies all of the channel length defined by the width of the crystallization control layer. The direction resistance component decreases. In this way, all of the channel length defined by the width of the crystallization control layer is occupied by the crystalline silicon layer, and the horizontal resistance component of the channel layer due to the amorphous silicon layer is reduced, so that the on-characteristic Can be significantly improved.

In addition, according to this aspect, since the portions on both sides of the crystalline silicon layer of the channel layer are made of an amorphous silicon layer, the portion of the channel layer is made more than when the portions on both sides of the crystalline silicon layer of the channel are made of a crystalline silicon layer. The band gap on both sides of the crystalline silicon layer is increased. Therefore, the heat generation current and the tunnel current can be greatly suppressed, and the off characteristics can be greatly reduced.

These actions make it possible to achieve both excellent on and off characteristics.

Furthermore, in this embodiment, as described above, the crystalline silicon layer occupies all of the channel length defined by the width of the crystallization control layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the underlying crystallization control layer, the distance from the crystalline silicon layer to the source electrode in the channel path and the crystalline silicon layer in the channel path The distance to the drain electrode becomes uniform, and variations in characteristics of thin film transistors between different substrates can be suppressed. Further, even when the source electrode and the drain electrode are exchanged in the same substrate, the electrical characteristics are symmetric with respect to the exchange of the source electrode and the drain electrode. Occurrence of problems associated with asymmetry of electrical characteristics can be suppressed.

The thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and the gate insulating layer. A first crystalline silicon layer formed above the electrode; a second crystalline silicon layer formed on both sides of the first crystalline silicon layer on the gate insulating layer; and the first crystalline A crystallization control layer formed on the silicon layer; an upper surface of an end of the crystallization control layer; a side surface of the channel protective layer; and a second crystallinity along the upper surface of the second crystalline silicon layer. A source electrode formed on one side of the silicon layer and a drain electrode formed on the other side of the second crystalline silicon layer, wherein an average grain size of crystals contained in the first crystalline silicon layer is The second result Greater than the average grain size of crystals contained in sexual silicon layer, the thickness of the film thickness of the first crystalline silicon layer and the second crystalline silicon layer is characterized by the same.

Here, the average grain size of the crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less, and the average grain size of the crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm. Good.

Further, both end portions of the first crystalline silicon layer and both end portions of the crystallization control layer may be arranged at the same position on the semiconductor substrate.

Further, the first crystalline silicon layer and the source electrode may have an overlapping region, and the first crystalline silicon layer and the drain electrode may have an overlapping region.

According to this aspect, the first crystalline silicon layer having a low resistance formed under the crystallization control layer and the crystalline structure of the first crystalline silicon layer formed on both sides of the first crystalline silicon layer are compared with each other. A channel layer is formed from the second crystalline silicon layer having a small average grain size and high resistance. Therefore, the first crystalline silicon layer is formed under the crystallization control layer, and the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the crystallization control layer. The horizontal resistance component of the channel layer due to the crystalline silicon layer is reduced. In this way, all of the channel length defined by the width of the crystallization control layer is occupied by the low-resistance crystalline silicon layer, and the horizontal resistance component of the channel layer is reduced by the high-resistance crystalline silicon layer. Therefore, the on-characteristic can be remarkably improved.

In addition, according to this aspect, the portions on both sides of the first crystalline silicon layer of the channel layer are made of crystalline silicon layers having a small average crystal grain size, so the portions on both sides of the first crystalline silicon layer of the channel layer are There are more components of amorphous silicon having lower crystallinity and a larger band gap than in the case of a crystalline silicon layer having a large average crystal grain size. Therefore, the heat generation current and the tunnel current can be greatly suppressed, and the off characteristics can be greatly reduced.

Furthermore, in this embodiment, as described above, the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the crystallization control layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the lower crystallization control layer, the distance from the low resistance crystalline silicon layer to the source electrode in the channel path and the low resistance in the channel path. Thus, the distance from the crystalline silicon layer to the drain electrode becomes uniform, and variations in characteristics of the thin film transistor between different substrates can be suppressed. Further, even when the source electrode and the drain electrode are exchanged in the same substrate, the electrical characteristics are symmetric with respect to the exchange of the source electrode and the drain electrode. Occurrence of problems associated with asymmetry of electrical characteristics can be suppressed.

Still further, according to this aspect, there is a degree of freedom in forming the second crystalline silicon layer up to a crystalline silicon layer having a small average crystal grain size. Accordingly, the crystallinity of each of the first crystalline silicon layer of the channel layer and the second crystalline silicon layers on both sides of the channel layer is determined by placing importance on on-current or off-current. Can be made according to the design.

The thin film transistor manufacturing method according to one embodiment of the present invention includes a first step of preparing a substrate, a second step of forming a gate electrode over the substrate, and a gate insulating layer formed over the gate electrode. Three steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, a fifth step of forming a crystallization control layer on the amorphous silicon layer, and the crystallization control layer. A sixth step of patterning so as to leave a region above the gate electrode, a laser beam is continuously applied to the patterned crystallization control layer and the non-crystalline silicon layer on which the crystallization control layer is not formed. The amorphous silicon layer in which the crystallization control layer is formed is used as a crystalline silicon layer, and the non-crystalline silicon layer in which the crystallization control layer is not formed is used as an amorphous silicon layer. Ma A seventh step to leave, and the non-crystalline silicon layer along the upper surface of the end portion of the patterned crystallization control layer, the side surface of the patterned crystallization control layer, and the upper surface of the non-crystalline silicon layer. And an eighth step of forming a drain electrode above the other of the non-crystalline silicon layer.

Here, in the seventh step, the crystalline silicon layer containing crystals having an average particle diameter of 10 nm or more and 1 μm or less may be formed by irradiation with the laser beam.

In the seventh step, the absorptance of the amorphous silicon layer in which the crystallization control layer is formed with respect to the laser light is the same as that in the amorphous silicon layer in which the crystallization control layer is not formed. It may be larger than the absorptance with respect to laser light.

According to this aspect, the laser beam interference effect inside the crystallization control layer, the amorphous silicon layer and the gate insulating layer and the laser beam interference effect inside the amorphous silicon layer and the gate insulating layer are utilized. Thus, a crystalline silicon layer is formed. That is, the non-crystalline silicon layer under the crystallization control layer is configured to increase the laser light absorption rate, and the non-crystalline silicon layers existing on both sides of the non-crystalline silicon layer under the crystallization control layer are A crystalline silicon layer is formed by irradiating a laser beam after having a structure with low absorptance. Since the amorphous silicon layer under the crystallization control layer has a structure in which the absorptance of laser light is increased, the amorphous silicon layer is crystallized as a crystalline silicon layer when irradiated with laser light. On the other hand, the non-crystalline silicon layers existing on both sides of the non-crystalline silicon layer under the crystallization control layer have a structure in which the absorption rate of the laser light is low. It remains as a channel layer. Therefore, a channel layer composed of a crystalline silicon layer and an amorphous silicon layer formed on both sides of the crystalline silicon layer can be formed. As a result, both excellent on characteristics and off characteristics can be achieved.

Also, according to this aspect, the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the crystallization control layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the lower crystallization control layer, the distance from the low resistance crystalline silicon layer to the source electrode in the channel path and the low resistance in the channel path. The distance from the crystalline silicon layer to the drain electrode becomes uniform, and the electrical characteristics can be made symmetrical with respect to the replacement of the source electrode and the drain electrode.

Further, in the seventh step, the wavelength of the laser beam may be not less than 473 nm and not more than 561 nm.

According to this aspect, the laser beam interference effect can be easily generated in the crystallization control layer, the amorphous silicon layer, and the gate insulating layer, and the portion of the channel layer where the crystallization control layer is formed It is possible to easily cause a difference in the absorption rate of the laser light between the portions on both sides.

The thin film transistor manufacturing method according to one embodiment of the present invention includes a first step of preparing a substrate, a second step of forming a gate electrode over the substrate, and a gate insulating layer formed over the gate electrode. Three steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, a fifth step of forming a crystallization control layer on the amorphous silicon layer, and the crystallization control layer. A sixth step of patterning so as to leave a region above the gate electrode, a laser beam is continuously applied to the patterned crystallization control layer and the non-crystalline silicon layer on which the crystallization control layer is not formed. The non-crystalline silicon layer with the crystallization control layer formed as a first crystalline silicon layer and the non-crystalline silicon layer without the crystallization control layer with a second crystalline property silicon And the second crystal along the upper surface of the end portion of the patterned crystallization control layer, the side surface of the patterned crystallization control layer, and the upper surface of the second crystalline silicon layer. An eighth step of forming a source electrode above one of the crystalline silicon layers and forming a drain electrode above the other of the second crystalline silicon layers, and in the seventh step, the second crystalline silicon The first crystalline silicon layer including crystals having an average grain size larger than an average grain size of crystals contained in the layer is formed.

Here, the average grain size of the crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less, and the average grain size of the crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm. May be.

According to this aspect, not only the portion of the first crystalline silicon layer, that is, the amorphous silicon layer that forms the highly crystalline channel layer, in which the crystallization control layer is formed, but also the second crystalline silicon layer, that is, the crystalline property. A portion of the amorphous silicon layer that forms a low channel layer where the crystallization control layer is not formed is also irradiated with laser. Therefore, if the intensity of the laser beam and the film thickness are appropriately selected, there is a degree of freedom in forming a low crystalline channel layer up to a crystalline silicon layer having a small average crystal grain size. In the channel layer, since the second crystalline silicon layer has a smaller average crystal grain size and higher resistance than the first crystalline silicon layer, the entire region of the channel layer has the average grain size of the first crystalline silicon layer. Compared to the above, off characteristics can be reduced. In addition, since the first crystalline silicon layer has a larger average crystal grain size and lower resistance than the second crystalline silicon layer, the entire region of the channel layer has an average grain size of the second crystalline silicon layer. Thus, the transverse resistance can be lowered and the on-current can be increased. Therefore, a region having a large average particle size and a region having a small average particle size in the channel layer can be formed according to a desired thin film transistor design, such as emphasizing on-current or emphasizing off-current. As a result, both excellent on characteristics and off characteristics can be achieved.

In the seventh step, the laser light absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed, and the non-crystalline silicon layer in which the crystallization control layer is not formed The difference from the absorption rate with respect to the laser beam may be 7% or more.

According to this aspect, the portion of the channel layer where the crystallization control layer is formed can be a polycrystalline silicon layer, and the portion of the channel layer where the crystallization control layer is not formed can be a microcrystalline silicon layer.

In the seventh step, the laser light absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed, and the non-crystalline silicon layer in which the crystallization control layer is not formed The difference from the absorption rate with respect to the laser light may be 1% or more.

According to this aspect, the portion of the channel layer where the crystallization control layer is formed is a polycrystalline silicon layer, and the portion of the channel layer where the crystallization control layer is not formed is an amorphous silicon layer or a microcrystalline silicon layer. It can also be.

In the seventh step, l and m are integers starting from 0, and the refractive index of the amorphous silicon layer is set to a film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer. The value obtained by dividing the optical film thickness of the amorphous silicon layer, which is the integrated value, by the wavelength of the laser beam is X, and the value obtained by integrating the refractive index of the gate insulating layer to the film thickness of the gate insulating layer. A value obtained by dividing the optical film thickness of a certain gate insulating layer by the wavelength of the laser beam may be Y, and X and Y may satisfy the following (Expression 1) and (Expression 2).

(Formula 1) 0.50 m ≦ Y ≦ 0.40 + 0.50 m
(Formula 2) -3.75 (X-0.50 l) + 1.83 + 0.50 m ≦ Y ≦ −3.75 (X-0.50 l) + 0.35 + 0.50 m

According to this aspect, the absorption rate of the laser beam in the portion where the crystallization control layer of amorphous silicon is formed can include the maximum absorption rate, for example, 50% or more.

In the third step, the gate insulating layer composed of a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer may be formed. Specifically, the gate insulating layer includes a capacitance of a series capacitor formed by the silicon nitride layer and the silicon oxide layer, and a capacitance of a single silicon oxide layer having a thickness of 100 nm to 140 nm. May be formed in such a film thickness that becomes equal to each other.

According to this aspect, the gate insulating layer has a two-layer structure, and the absorptance of the laser beam in the portion where the amorphous silicon crystallization control layer is formed can be increased. Thereby, for example, the average grain size of the crystal in the portion where the crystallization control layer of the channel layer is formed can be increased, and the on-current can be increased.

In the seventh step, n is an integer starting from 0, and the refractive index of the amorphous silicon layer is added to the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer. The value obtained by dividing the optical film thickness of the amorphous silicon layer by the wavelength of the laser beam is X, and the gate insulating layer composed of the silicon nitride layer and the silicon oxide layer is used as the refractive index of the silicon oxide layer. The value obtained by dividing the optical film thickness converted by (1) by the value obtained by integrating the refractive index of the silicon oxide layer and the wavelength of the laser beam is defined as Y, where X and Y are the following (Expression 3) and (Expression 4). Or (Equation 5) and (Equation 6) may be satisfied.

(Formula 3) 0.226 ≦ Y ≦ 0.26
(Formula 4) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 5) 0.340 ≦ Y ≦ 0.543
(Formula 6) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28

According to this aspect, in the configuration in which the gate insulating layer has a two-layer structure, the absorption rate of the laser beam in the portion where the crystallization control layer of amorphous silicon is formed includes the maximum absorption rate, for example, 50 % Or more.

In the fifth step, the optical thickness of the crystallization control layer, which is a value obtained by integrating the refractive index of the crystallization control layer to the thickness of the crystallization control layer, is divided by the wavelength of the laser beam. The value may be Z, k may be an integer starting from 0, and the Z may satisfy (Equation 7) below.

(Expression 7) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7)

According to this aspect, the crystallization control layer functions as an antireflection film for laser light, and can increase the laser light absorption rate of amorphous silicon. The degree of increase in the absorptance periodically varies with the film thickness of the crystallization control layer, but the range in which the absorptance particularly increases is expressed by (Equation 7) using the optical film thickness of the crystallization control layer. . Therefore, by forming the crystallization control layer that satisfies (Equation 7), the absorption efficiency of the laser light below the channel layer can be increased.

In the fourth step, the amorphous silicon layer may be formed so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 100 nm or less.

When the amorphous silicon layer is extremely thick, the laser light passes through the amorphous silicon layer in the thickness direction and attenuates until reaching the position directly above the gate insulating layer serving as a current path. However, by setting the film thickness of the amorphous silicon layer to 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer and crystallizes to the amorphous silicon layer directly above the gate insulating layer serving as a current path. be able to. Thereby, the subthreshold swing characteristic of the thin film transistor can be improved.

In the fourth step, the amorphous silicon layer may be formed so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 10 nm or more.

When the amorphous silicon layer is extremely thin, the absorption rate of the laser beam by the amorphous silicon layer is low. Therefore, most of the energy of the laser beam transmitted through the amorphous silicon layer is input to the gate electrode, and the gate The electrode will be damaged. However, by setting the thickness of the amorphous silicon layer to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented.

In the first step, the substrate having an undercoat layer formed on the surface may be prepared, and in the second step, the gate electrode may be formed on the undercoat layer.

According to this aspect, the intrusion of impurities contained in the substrate into the channel layer can be suppressed.

In the second step, a metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal may be formed as the gate electrode.

In the third step, a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the gate insulating layer.

According to this aspect, the light absorption of the laser light by the gate insulating layer can be suppressed, and the absorption rate of the amorphous silicon laser light can be increased.

In the third step, a silicon oxide layer may be formed as the gate insulating layer.

In the third step, a silicon nitride layer may be formed as the gate insulating layer.

In the fifth step, a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the crystallization control layer.

According to this aspect, it is possible to suppress the light absorption of the laser light by the crystallization control layer and increase the absorption rate of the laser light in the portion where the crystallization control layer of amorphous silicon is formed.

In the fifth step, a silicon oxide layer may be formed as a crystallization control layer.

In the fifth step, a silicon nitride layer may be formed as a crystallization control layer.

Further, in the seventh step, the laser light may be light in a continuous oscillation mode or a pseudo continuous oscillation mode.

In the seventh step, the laser light may be light emitted from a solid-state laser device.

In the seventh step, the laser light may be light emitted from a laser device using a semiconductor laser element.

In the seventh step, the fluctuation of the irradiation energy density of the laser light on the amorphous silicon layer may be less than 5%.

According to this aspect, it is possible to suppress variations in channel layer characteristics caused by laser light.

In the seventh step, the non-crystalline silicon layer on which the crystallization control layer is formed and the non-crystalline silicon layer on which the crystallization control layer is not formed at a constant scan speed with laser light May be continuously irradiated.

A display device according to one embodiment of the present invention is a display device including a liquid crystal panel or an organic EL panel, and includes the thin film transistor. The thin film transistor includes the liquid crystal panel when the display device includes the liquid crystal panel. The organic EL panel is driven when the display device includes the organic EL panel.

According to this aspect, it is possible to achieve both excellent on-characteristics and excellent off-characteristics and to make the electrical characteristics symmetrical with respect to the replacement of the source electrode and the drain electrode.

Hereinafter, a thin film transistor, a manufacturing method thereof, and a display device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
First, the thin film transistor according to the first embodiment of the present invention will be described below.

FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the present embodiment.

This thin film transistor is a channel protection type bottom gate thin film transistor for a display device, and includes a substrate 100, a gate electrode 110 formed on the substrate 100, a gate insulating layer 120 formed on the gate electrode 110, A crystalline silicon layer 131 formed on the gate insulating layer 120 and above the gate electrode 110; and an amorphous silicon layer formed on both sides of the crystalline silicon layer 131 on the gate insulating layer 120. Layer (amorphous silicon) 130, channel protective layer 140 formed on crystalline silicon layer 131, the upper surface of the end of channel protective layer 140, the side surface of channel protective layer 140, and the upper surface of amorphous silicon layer 130 A source electrode 171 formed on one side of the amorphous silicon layer 130 and the amorphous silicon layer And a drain electrode 172 formed on the other of the upper con layer 130 is identical to the thickness of each of the crystalline silicon layer 131 and the amorphous silicon layer 130. Furthermore, a contact layer 162 formed between the amorphous silicon layer 130 and the source electrode 171 and a contact layer 161 formed between the amorphous silicon layer 130 and the drain electrode 172 are provided.

Here, both ends of the crystalline silicon layer 131 and both ends of the channel protective layer 140 are disposed at the same position on the substrate 100. The crystalline silicon layer 131 and the source electrode 171 have an overlapping region, and the crystalline silicon layer 131 and the drain electrode 172 have an overlapping region.

Next, the thin film transistor of FIG. 1 will be described in detail.

The substrate 100 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistance glass. Note that in order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the crystalline silicon layer 131 and the amorphous silicon layer 130, silicon nitride (SiNx), silicon oxide (SiOy) is formed on the surface. Or a substrate on which an undercoat layer made of silicon oxynitride film (SiOyNx) or the like is formed. In addition, the undercoat layer may play a role of reducing the influence of heat on the substrate 100 in a high-temperature heat treatment process such as laser annealing. The thickness of the undercoat layer is, for example, about 100 nm to 2000 nm.

The gate electrode 110 has a single layer structure or a multilayer structure such as a conductive material that can withstand the melting point temperature of silicon or an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W) , Ta (tantalum), Nb (niobium), Ni (nickel), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW), etc. are formed on the substrate 100 and patterned into a predetermined shape. It is formed. The thickness of the gate electrode 110 is preferably 30 nm to 300 nm, more preferably 50 nm to 100 nm. This is because if the thickness of the gate electrode 110 is small, the transmittance of the gate electrode 110 increases, and the reflection of the laser beam is likely to decrease. On the other hand, when the thickness of the gate electrode 110 is large, the coverage of the gate insulating layer 120 is lowered, and in particular, the characteristics of the thin film transistor are deteriorated such that the gate insulating layer 120 is disconnected at the end of the gate electrode 110. This is because it becomes easier.

The crystalline silicon layer 131 and the amorphous silicon layer 130 are semiconductor layers formed on the gate insulating layer 120 and constitute a channel layer whose carrier movement is controlled by the voltage of the gate electrode 110. The crystalline silicon layer 131 is formed of a crystalline silicon layer such as a polycrystalline silicon layer, and is made polycrystalline by irradiating a part of amorphous silicon of the amorphous silicon layer 130 with a laser. Formed). Note that the crystalline silicon layer 131 can be a silicon layer having a mixed crystal structure of amorphous silicon and a crystalline silicon layer.

Note that the average particle diameter of crystals contained in the crystalline silicon layer 131 is 10 nm or more and 1 μm or less.

In the channel layer, the bottom surface of the crystalline silicon layer 131 of the channel layer and the bottom surface of the amorphous silicon layer 130 are flush and form the same plane, and the top surface of the crystalline silicon layer 131 and the top surface of the amorphous silicon layer 130 are also formed. Similarly, the same plane is formed on the same plane. Further, the crystalline silicon layer 131 is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110. That is, the gate length (channel length) of the gate electrode 110 is longer than the length of the channel layer in the gate length direction. Thus, both sides of the crystalline silicon layer 131 of the channel layer, that is, the amorphous silicon layer 130 of the channel layer serve as a charge transfer path.

The gate insulating layer 120 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride film, aluminum oxide (AlOz), tantalum oxide (TaOw), or a laminated film thereof, and covers the gate electrode 110 on the substrate 100 so as to cover it. It is formed on the substrate 100 and the gate electrode 110.

Note that since crystalline silicon is used for the channel layer, the gate insulating layer 120 is preferably formed of silicon oxide. This is because it is preferable to make the interface state between the channel layer and the gate insulating layer 120 good in order to maintain good threshold voltage characteristics in the TFT.

The channel protective layer 140 is a light-transmitting crystallization control layer that controls the degree of crystallization from amorphous silicon in the formation of the crystalline silicon layer 131, and is a protective film that protects the channel layer, It is formed on the upper surface of the crystalline silicon layer 131 of the channel layer. The side surface of the channel protective layer 140 and the side surface of the crystalline silicon layer 131 are flush with each other. The channel protective layer 140 functions as a channel etching stopper (CES) layer for preventing the channel layer from being etched during the etching process when forming the pair of

contact layers

161 and 162. However, the upper portion of the channel protective layer 140 is etched by etching when patterning the contact layers 161 and 162 (not shown).

The channel protective layer 140 is an inorganic material layer mainly composed of an inorganic material such as silicon oxide or silicon nitride. Note that the channel protective layer 140 has an insulating property, and the pair of

contact layers

161 and 162 are not electrically connected to each other.

The pair of

contact layers

161 and 162 is made of an amorphous semiconductor layer containing impurities at a high concentration or a polycrystalline semiconductor layer containing impurities at a high concentration, and a part of the contact layers 161 and 162 is located above the channel layer with a channel protection layer 140 interposed therebetween. The other part is formed on and in contact with the channel layer. Further, the pair of

contact layers

161 and 162 are arranged to face each other with a predetermined interval on the channel protective layer 140.

Each of the pair of

contact layers

161 and 162 is formed so as to extend from the upper surface of the channel protective layer 140 to the amorphous silicon layer 130 of the channel layer. It is formed so as to cover the side surface of the crystalline silicon layer 131 and the upper surface of the amorphous silicon layer 130. More specifically, the two

contact layers

161 and 162 are separately provided on both sides of the crystalline silicon layer 131 of the channel layer, and are formed on the upper surface and side surface of the end portion of the channel protective layer 140 and on the side surface of the channel protective layer 140. It is formed on the upper surface of the amorphous silicon layer 130 of the sparse channel layer.

The pair of

contact layers

161 and 162 is, for example, an n-type semiconductor layer in which amorphous silicon is doped with phosphorus (P) as an impurity, and a high-concentration impurity of 1 × 10 ¹⁹ [atm / cm ³ ] or more is formed. Including n ⁺ layer. Each of the contact layers 161 and 162 can have a film thickness of, for example, 5 nm to 100 nm.

The pair of source electrode 171 and drain electrode 172 are formed along the upper surface and side surface of the end portion of the channel protective layer 140 and the upper surface of the non-crystalline silicon layer 130 of the channel layer connected to the side surface of the channel protective layer 140. In addition, the pair of source electrode 171 and drain electrode 172 are provided to be separated from each other.

The pair of source electrode 171 and drain electrode 172 is formed above the channel layer, and is formed on the

corresponding contact layer

161 or 162, respectively. That is, the source electrode 171 is formed on the pair of contact layers 162, and the drain electrode 172 is formed on the contact layer 161.

The source electrode 171 and the drain electrode 172 can each have a single layer structure or a multilayer structure made of a conductive material or an alloy thereof, for example, aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), silver (Ag), copper (Cu), titanium (Ti), or chromium (Cr). Further, the source electrode 171 and the drain electrode 172 can have a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 171 and the drain electrode 172 is, for example, about 100 nm to 500 nm.

Hereinafter, a method of manufacturing the thin film transistor according to the present embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the present embodiment.

The thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate A fourth step of forming the amorphous silicon layer 130 on the insulating layer 120, a fifth step of forming the channel protective layer 140 on the amorphous silicon layer 130, and the channel protective layer 140 over the gate electrode 110; Patterning was performed by continuously irradiating the patterned channel protective layer 140 and the amorphous silicon layer 130 where the channel protective layer 140 is not formed with a sixth step of patterning so as to leave a region. The amorphous silicon layer 130 on which the channel protective layer 140 is formed is referred to as a crystalline silicon layer 131, and the channel protective layer 14 A seventh step of leaving the amorphous silicon layer 130 on which the layer is not formed as the amorphous silicon layer 130, the upper surface of the end portion of the channel protective layer 140, the side surface of the channel protective layer 140, and the amorphous silicon layer 130 And an eighth step of forming a source electrode 171 above one of the amorphous silicon layers 130 and a drain electrode 172 above the other of the amorphous silicon layers 130.

Here, in the seventh step, the absorption rate of the amorphous silicon layer 130 in which the channel protective layer 140 is formed with respect to the laser light is the absorption rate of the amorphous silicon layer 130 in which the channel protective layer 140 is not formed with respect to the laser light. Greater than rate.

Next, a method for manufacturing the thin film transistor of FIG. 2 will be described in detail.

First, a glass substrate is prepared as a substrate 100 as shown in FIG. Before forming the gate electrode 110, an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the surface of the substrate 100 by plasma CVD (Chemical Vapor Deposition) or the like. . The undercoat layer is preferably a silicon oxide film (SiOy) of 1.5 <y <2.0, and has a thickness of 300 nm to 1500 nm. A more preferable thickness range of the undercoat layer is 500 nm or more and 1000 nm or less. This is because if the thickness of the undercoat layer is increased, the thermal load on the substrate 100 can be reduced, but if it is too thick, film peeling or cracking occurs.

Next, as shown in FIG. 2B, a gate electrode 110 having a predetermined shape is formed on the substrate 100. For example, a gate metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal is formed on the substrate 100 by sputtering as the gate electrode 110, and the gate metal film is formed using a photolithography method and a wet etching method. The gate electrode 110 having a predetermined shape can be formed by patterning. MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and water are mixed in a predetermined composition. In the case where an undercoat layer is formed on the surface of the substrate 100, the gate electrode 110 is formed on the undercoat layer.

Next, as shown in FIG. 2C, a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110. For example, a silicon oxide layer or a silicon nitride layer is formed as the gate insulating layer 120 over the gate electrode 110 by a plasma CVD method.

Next, as shown in FIG. 2D, an amorphous silicon layer 130 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do.

Next, as shown in FIG. 2E, a channel protective layer 140 made of silicon oxide is formed on the amorphous silicon layer 130 by plasma CVD or the like.

Next, as shown in FIG. 2F, a part of the channel protective layer 140 is removed by etching.

Next, as shown in FIG. 2G, the amorphous silicon layer 130 is made into a crystalline silicon layer 131 by laser annealing. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 130 is crystallized using the laser beam to generate the crystalline silicon layer 131. More specifically, first, the formed amorphous silicon layer 130 is subjected to dehydrogenation treatment (dehydrogenation annealing treatment at a temperature of 400 ° C. or higher, which is a temperature at which hydrogen escapes from the amorphous silicon layer 130). carry out. After that, the amorphous silicon layer 130 is made polycrystalline (including microcrystals) by laser annealing to form a crystalline silicon layer 131.

At this time, the laser light is emitted from the portion of the amorphous silicon layer 130 where the channel protective layer 140 is not formed, the portion of the amorphous silicon layer 130 where the channel protective layer 140 is formed, and the channel of the amorphous silicon layer 130. The amorphous silicon layer 130 is scanned in the order of the portion where the protective layer 140 is not formed, but the absorption rate of the laser light in the portion where the channel protective layer 140 is not formed is low. Therefore, in the amorphous silicon layer 130, the portion where the channel protective layer 140 is formed is crystallized to form the crystalline silicon layer 131, but the portion where the channel protective layer 140 is not formed is not crystallized. The amorphous silicon layer 130 remains. As a result, only the portion of the amorphous silicon layer 130 where the channel protective layer 140 is formed is selectively crystallized, and only the portion of the amorphous silicon layer 130 where the channel protective layer 140 is formed is selectively crystalline. A silicon layer 131 can be formed.

Further, the laser light source of the laser light is a laser having a wavelength in the visible light region. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a green laser having a wavelength of 473 nm to 561 nm. The laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 130 is irradiated with the laser light discontinuously. This is because the amorphous silicon layer 130 cannot always be kept in a molten state. The reason why the quasi-continuous oscillation mode is also included is that the amorphous silicon layer 130 can be maintained in its molten state by applying a pulse and reheating it before it is cooled to below its melting point. Therefore, a preferred mode of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 130 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained. Further, the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element. In any case, it is preferable because laser light can be controlled with high accuracy. Further, the laser light having a wavelength in the visible light region is irradiated on the non-crystalline silicon layer 130 with the laser light when irradiated on the non-crystalline silicon layer 130 in order to form the crystalline silicon layer 131 without crystal unevenness. It is preferable if the fluctuation of the energy density is less than 5%. By forming the crystalline silicon layer 131 having no crystal unevenness, the initial design characteristics of the thin film transistor can be achieved, and the characteristics can be made uniform.

In addition, when the amorphous silicon layer 130 is extremely thick, the laser light is transmitted through the amorphous silicon layer 130 in the thickness direction and attenuated until it reaches directly above the gate insulating layer 120 serving as a current path. However, by setting the film thickness of the amorphous silicon layer 130 to 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer 130 and the amorphous silicon layer 130 immediately above the gate insulating layer 120 serving as a current path. Can be crystallized. Therefore, in the process of FIG. 2D, the amorphous silicon layer 130 is formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the amorphous silicon layer 130 is 100 nm or less. Is preferred.

In addition, when the amorphous silicon layer 130 is extremely thin, the absorption rate of the laser light by the amorphous silicon layer 130 is lowered. Therefore, most of the energy of the laser light transmitted through the amorphous silicon layer 130 is input to the gate electrode 110, and the gate electrode 110 is damaged. However, by setting the thickness of the amorphous silicon layer 130 to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented. Therefore, in the process of FIG. 2D, the amorphous silicon layer 130 is formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the amorphous silicon layer 130 is 10 nm or more. Is preferred.

Further, in order to suppress the laser light from being absorbed by the gate insulating layer 120 and increase the absorption rate of the laser light of the amorphous silicon layer 130, the process of FIG. A film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light is preferably formed as the gate insulating layer 120.

Further, in order to prevent the laser light from being absorbed by the channel protective layer 140 and increase the absorptance of the laser light of the amorphous silicon layer 130, in the step of FIG. 2E, the step of FIG. A film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light is preferably formed as the channel protective layer 140.

The amorphous silicon layer 130 is irradiated with linearly focused laser light. There are, for example, two irradiation methods, one of which is a fixed irradiation position of the linearly focused laser light. There is a method of moving the stage on which the substrate 100 on which the amorphous silicon layer 130 is formed is moved, and the other is a method in which the stage is fixed and the irradiation position of the laser beam is moved. In any method, the laser beam is irradiated while moving relative to the amorphous silicon layer 130. As described above, the amorphous silicon layer 130 irradiated with the laser light absorbs the energy of the laser light and rises in temperature to be crystallized to become the crystalline silicon layer 131.

Next, as shown in FIG. 2 (h), a contact layer 160 to be the contact layers 161 and 162 is formed so as to extend from the upper surface of the channel protective layer 140 to the amorphous silicon layer 130. Specifically, the noncrystalline property doped with an impurity of a pentavalent element such as phosphorus by plasma CVD so as to cover the upper surface and side surfaces of the channel protective layer 140 and the upper surface of the amorphous silicon layer 130. A contact layer 160 made of silicon is formed.

Next, as shown in FIG. 2I, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160. For example, the source / drain metal film 170 having a three-layer structure of MoW / Al / MoW is formed by sputtering.

Next, although not shown, in order to form the source electrode 171 and the drain electrode 172 having a predetermined shape, a resist material is applied onto the source / drain metal film 170, exposed and developed, and then patterned into a predetermined shape. Form. Thereafter, as shown in FIG. 2J, etching is performed using this resist as a mask to pattern the source / drain metal film 170, thereby forming a source electrode 171 and a drain electrode 172 having predetermined shapes. At this time, the contact layer 160 functions as an etching stopper. Thereafter, the resist on the source electrode 171 and the drain electrode 172 is removed, and dry etching is performed using the source electrode 171 and the drain electrode 172 as a mask, thereby patterning the contact layer 160 and patterning the channel layer in an island shape. Thereby, a pair of

contact layers

161 and 162 having a predetermined shape and an island-shaped channel layer can be formed.

Hereinafter, characteristics of the thin film transistor according to the present embodiment will be described with reference to FIGS. 3 to 8C.

FIG. 3 is a diagram showing changes in the current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed. FIG. 3 shows the characteristics when a voltage of 12 V is applied between the source and drain, the horizontal axis shows the gate-source voltage, and the vertical axis shows the source-drain current.

In the thin film transistor of FIG. 1, the channel layer is composed of the amorphous silicon layer 130 and the crystalline silicon layer 131. However, the channel layer is composed of only the amorphous silicon layer 130 and only the crystalline silicon layer 131. The channel layer exhibits different characteristics when the channel layer is configured. That is, as shown in FIG. 3, when the channel layer is formed of only the amorphous silicon layer 130, the off characteristics are good, but the on characteristics are bad. On the other hand, when the channel layer is composed of only the crystalline silicon layer 131, the off characteristics are poor, but the on characteristics are good.

The thin film transistor shown in FIG. 1 achieves both good off-characteristics and on-characteristics by utilizing the change in characteristics due to the difference in crystallinity shown in FIG. In other words, the portion below the channel protective layer 140 in the channel layer is all made of the crystalline silicon layer 131 to increase the on-current, and the portions on both sides thereof are made to be the amorphous silicon layer 130 to reduce the off-current (leakage current). is there.

FIG. 4A shows the crystallinity of the crystalline silicon layer 131 when the laser light absorptivity of the amorphous silicon layer 130 and the scan speed of the laser light are changed in the laser annealing in the step of FIG. It is a figure which shows the change of.

Note that changing the absorptance of the amorphous silicon layer 130 is realized by changing the thickness of the amorphous silicon layer 130, that is, the thickness of the channel layer.

4A, a sample is used in which the laser output is 60 kW / cm ² , the gate electrode 110 is 50 nm thick MoW, and the gate insulating layer 120 is 120 nm thick silicon oxide.

In FIG. 4A, “a-Si” indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon, and “SPC” indicates the average grain size of the crystalline silicon layer 131. “Ex & .SPC” indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm, and “p-Si” indicates the crystalline silicon layer. The average particle size of 131 is about 60 nm or more and 1 μm or less, and “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.

As shown in FIG. 4A, different crystalline silicon layers can be formed by changing the scanning speed of laser annealing and the absorption rate of the amorphous silicon layer 130. Even in the case where the scanning speed is constant, in the step of FIG. 2F, the absorptance with respect to the laser light of the portion below the channel protective layer 140 of the amorphous silicon layer 130 in which the channel protective layer 140 is formed, The difference between the absorption ratio to the laser light of the portions on both sides (the portion of the amorphous silicon layer 130 where the channel protective layer 140 is not formed) is set to 1% or more, so that the amorphous silicon layer and the crystalline The silicon layer can be formed simultaneously by one laser scan, and the crystalline silicon layer 131 of the channel layer and the amorphous silicon layers 130 on both sides thereof can be formed.

Note that the absorptance of the amorphous silicon layer 130 depends on the configuration, thickness and optical constant of the channel protective layer 140, the thickness and optical constant of the amorphous silicon layer 130, the configuration, thickness and optical constant of the gate insulating layer 120. It is derived by optical calculation taking into account multiple interference of laser light, using the constant and the optical constant of the metal material forming the underlying gate electrode 110 as parameters. Hereinafter, examples of optical calculation will be described in detail.

FIG. 4B is a diagram for explaining a method for calculating the light absorption rate of the amorphous silicon layer 130.

FIG. 4B shows a model structure of a multilayer structure in which the structure of the thin film transistor shown in FIG. 1 is modeled. In the model structure shown in FIG. 4B, a layer 401 of the complex refractive index _{N 1,} and 402 of the complex refractive index _{N 2,} a layer 403 of the complex refractive index _{N 3,} a layer 404 of the complex refractive index _{N 4,} the complex index of refraction N ₅ substrate 405. In this model structure, a layer 404, a layer 403, a layer 402, and a layer 401 are stacked on the substrate 405 in this order. Further, the region of the complex refractive index N ₀ shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. This region is, for example, air. In this case, the refractive index is 1 and the extinction coefficient is 0.

The substrate 405 is an insulating substrate made of, for example, transparent glass or quartz, and has a refractive index of 1.46, for example, and corresponds to the substrate 100 shown in FIG. The layer 404 is made of, for example, 50 nm MoW having a refractive index of 3.47 and an extinction coefficient of 3.78, and corresponds to the gate electrode 110 shown in FIG. The layer 403 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the gate insulating layer 120 shown in FIG. The layer 402 corresponds to the amorphous silicon layer 130 having a refractive index of 5.074 and an extinction coefficient of 0.621, for example. The layer 401 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the channel protective layer 140 shown in FIG.

As shown in FIG. 4B, the amplitude reflection coefficient for light incident on the layer 401 from the outside is r ₀₁ , the amplitude reflection coefficient for light incident on the layer 402 from the layer 401 is r ₁₂ , and the amplitude reflection coefficient is incident on the layer 403 from the layer 402. R ₂₃ is the amplitude reflection coefficient with respect to the incident light, and r ₃₄ is the amplitude reflection coefficient with respect to the light incident on the layer 404 from the layer 403. Further, the amplitude transmission coefficient of light incident on the layer 401 from the outside is t ₀₁ , the amplitude transmission coefficient of light incident on the layer 402 from the layer 401 is t ₁₂ , and the amplitude transmission of light incident on the layer 402 from the layer 402 The coefficient is t ₂₃ , and the amplitude transmission coefficient of light incident on the layer 404 from the layer 403 is t ₃₄ .

Further, the amplitude reflection coefficients of the entire layers above the region where the layer 404 corresponding to the gate electrode 110 is formed are r ₀₁₂₃₄ (R1), r ₁₂₃₄ (R2), and r ₂₃₄ (R3), respectively. Specifically, the amplitude reflection coefficient when the

layers

404 and 403 are regarded as one layer is r ₂₃₄ (R3). Similarly, the amplitude reflection coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer is r ₁₂₃₄ (R2), and the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer. The reflection coefficient is r ₀₁₂₃₄ (R1). In addition, the amplitude transmission coefficients of the entire layers in the first region are t ₀₁₂₃₄ (T1), t ₁₂₃₄ (T2), and t ₂₃₄ (T3), respectively. Specifically, the amplitude transmission coefficient when the

layers

404 and 403 are regarded as one layer is t ₂₃₄ (T3). Similarly, t ₁₂₃₄ (T2) is an amplitude transmission coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer, and the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer. The transmission coefficient is t ₀₁₂₃₄ (T1).

The amplitude reflection coefficient and amplitude transmission coefficient of each layer in the first region can be expressed by the following (Expression 12) to (Expression 17).

Also, the amplitude reflection coefficient and amplitude transmission coefficient of each layer in the second region can be expressed by the following (Equation 18) to (Equation 23).

here,

Where d is the film thickness of each layer, θ is the incident angle / transmission angle in each layer, and λ is the wavelength of the laser beam.

In addition, θ can be calculated as shown below from Snell's law of the following equation.

The amplitude reflection coefficients r ₀₁ , r ₁₂ , r ₂₃ , r ₃₄ , r ₃₅ and the amplitude transmission coefficients t ₀₁ , t ₁₂ , t ₁₂ , t ₃₄ , t _{35 of each layer} are expressed by the following (formula 24) to (formula). 33).

Here, the light is monochromatic laser light, and the polarization is assumed to be P-polarized light.

Next, using the above equations, the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer in the first region are calculated as follows. That is, first, r ₂₃₄ is calculated by substituting (Equation 26) and (Equation 27) into (Equation 14). Next, r ₁₂₃₄ is calculated by substituting (Equation 25) and r ₂₃₄ into (Equation 13). Next, r ₀₁₂₃₄ is calculated by substituting (Equation 24) and r ₁₂₃₄ into (Equation 12). Next, t ₂₃₄ is calculated by substituting (Equation 26), (Equation 27), (Equation 31), and (Equation 32) into (Equation 17). Next, t ₁₂₃₄ is calculated by substituting (Equation 25), (Equation 30), r ₂₃₄ and t ₂₃₄ into (Equation 16). Next, t ₀₁₂₃₄ is calculated by substituting (Equation 24), (Equation 29), r ₁₂₃₄ and t ₁₂₃₄ into (Equation 15).

Next, the reflectances R1, R2 and R3 and the transmittances T1, T2 and T3 in each layer are calculated by (Expression 34) to (Expression 39).

Finally, the light absorption rate A _Si for the amorphous silicon layer can be calculated by (Equation 40).

Next, using the calculation method described above, perpendicular to the model structure shown in FIG. 4B, ie theta ₀ = 0 or sin [theta ₀ = 0 is longer than the wavelength 473nm at an incident angle theta ₀ range holds an approximation, 561 nm When the following green laser light was incident, the absorptance of the laser light of the amorphous silicon layer 130 was calculated. In this case, the calculation result is the same even if the polarization of the laser beam is S polarization.

In this example, an example of a model structure including the gate electrode 110 made of MoW, the gate insulating layer 120 made of silicon oxide, the amorphous silicon 130, and the channel protective layer 140 made of silicon oxide is shown. Modification cases such as a case where the film 120 has a laminated structure of silicon oxide and silicon nitride or a case where the channel protective layer 140 is not present can be similarly calculated by appropriately modifying the model structure of FIG. 4B. When the material of the gate electrode 110 is changed (for example, the material of the gate electrode 110 is Cu (refractive index 1.04, extinction coefficient 2.59), Al (refractive index 0.867, extinction coefficient 6.42), Mo. (When the refractive index is 3.61, extinction coefficient is 3.79), W (refractive index is 3.48, extinction coefficient is 2.72), and the material of the gate insulating layer 120 and the channel protective layer 140 is changed. (When the material of the gate insulating layer 120 and the channel protective layer 140 is, for example, silicon nitride (refractive index 1.947, extinction coefficient 0)) can be calculated in the same manner by appropriately changing the physical property values. 5F shows the absorption of the amorphous silicon layer 130 when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG. Show rate calculation results, etc. It is a diagrammatic view. 6A is a diagram showing a change in the absorptance of the amorphous silicon layer 130 when the thickness of the gate insulating layer 120 made of silicon oxide is 120 nm in FIGS. 5D and 5F.

5A to 5F, the lower horizontal axis represents the optical film thickness of the amorphous silicon layer 130, that is, the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the amorphous silicon layer 130. Is divided by the wavelength of the laser beam. The left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam. For reference, the film thickness of the amorphous silicon layer 130 when the wavelength of the laser light is 532 nm without being normalized by the wavelength of the laser light is shown on the horizontal axis, and the film thickness of the gate insulating layer 120 is shown on the right side. It is shown on the vertical axis. In FIG. 6A, the value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam is shown on the horizontal axis, and the absorptance of the amorphous silicon layer 130 is shown on the vertical axis.

5A uses a model in which the gate electrode 110 is made of Cu, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm (the channel protective layer 140 is not formed). . The calculation in FIG. 5B uses a model in which the gate electrode 110 is made of Al, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. The calculation in FIG. 5C uses a model in which the gate electrode 110 is made of Mo, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5D uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5E uses a model in which the gate electrode 110 is made of W, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5F uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is made of 275 nm silicon oxide.

By the way, for example, when the refractive index of the amorphous silicon layer 130 at a wavelength of 532 nm is used, the values on the horizontal axis in FIGS. 5A to 5F can be converted into the film thickness of the amorphous silicon layer 130. FIG. 6B is a diagram illustrating an example of a value obtained by converting the value on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130. FIG. 6B shows values obtained by converting the values on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130 at the wavelength of 532 nm, the wavelength of 473 nm, and the wavelength of 569 nm. .

Similarly, for example, when the refractive index of the gate insulating layer 120 at a wavelength of 532 nm is used, the value on the vertical axis in FIGS. 5A to 5F can be converted into the film thickness of the gate insulating layer 120. FIG. 6C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIGS. 5A to 5F into the thickness of the gate insulating layer 120 made of silicon oxide or the gate insulating layer 120 made of silicon nitride. FIG. 6C shows values obtained by converting the values on the vertical axis in FIGS. 5A to 5F into the film thickness of the gate insulating layer 120 when the wavelength is 532 nm, the wavelength is 473 nm, and the wavelength is 569 nm. 6C shows an example of values obtained by converting the values on the horizontal axis and the vertical axis into the film thickness of the channel protective layer 140 made of silicon oxide or silicon nitride or the film thickness of the gate insulating layer 120 in FIG. 7 described later. It can also be applied as a diagram shown.

5A to 5F, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, in the step of FIG. 2F, l and m are integers starting from 0, and the amorphous silicon layer 130 A value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam, which is a value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness from the bottom surface to the upper surface of the amorphous silicon layer 130. Is X, Y is a value obtained by dividing the optical film thickness of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and the refractive index of the gate insulating layer 120 by the wavelength of the laser beam, and X and Y If the following (Equation 1) and (Equation 2) are satisfied, the absorption rate of the laser light of the amorphous silicon layer 130 includes the maximum absorption rate, for example, 50% or more. 5A to 5F indicate ranges where X and Y satisfy the following (formula 1) and (formula 2), respectively.

FIG. 7 shows channel protection of the amorphous silicon layer 130 when the thickness of the channel protective layer 140 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG. FIG. 6 is a contour diagram showing the calculation result of the absorptance of the portion below the layer 140. 8A to 8C are diagrams showing changes in the absorptance of the portion of the amorphous silicon layer 130 below the channel protective layer 140 when the film thickness of the channel protective layer 140 is changed.

In FIG. 7, the lower horizontal axis represents the optical film thickness of the channel protective layer 140, that is, the value obtained by adding the refractive index of the channel protective layer 140 to the film thickness of the channel protective layer 140 divided by the wavelength of the laser beam. The value is shown. The left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam. For reference, the film thickness of the channel protective layer 140 when the wavelength of the laser light is 532 nm without being normalized by the wavelength of the laser light is shown on the horizontal axis, and the film thickness of the gate insulating layer 120 is shown on the right vertical axis. It shows. 8A to 8C, the horizontal axis represents the value obtained by dividing the optical film thickness of the channel protective layer 140 by the wavelength of the laser beam, and the absorptance of the portion below the channel protective layer 140 of the amorphous silicon layer 130 is represented vertically. Shown on the axis.

Further, in the calculation of FIG. 7, the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the optical film thickness of the amorphous silicon layer 130, that is, the film thickness of the amorphous silicon layer 130 is amorphous. The value obtained by integrating the refractive index of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (corresponding to a wavelength of 532 nm and an amorphous silicon layer thickness of 50 nm), and the channel protective layer 140 is oxidized. A model consisting of silicon is used.

8A, the gate electrode 110 is made of MoW, and the optical film thickness of the gate insulating layer 120, that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, A model obtained by dividing the wavelength by 0.331 (corresponding to a wavelength of 532 nm and a silicon oxide layer thickness of 120 nm) is used, and the channel protective layer 140 is made of silicon oxide. 8A, the broken line, the alternate long and two short dashes line, and the solid line represent values obtained by adding the refractive index of the amorphous silicon layer 130 to the optical thickness of the amorphous silicon layer 130, that is, the thickness of the amorphous silicon layer 130, respectively. Is divided by the wavelength of the laser beam to be 0.286 (corresponding to a non-crystalline silicon layer thickness of 30 nm at a wavelength of 532 nm), 0.763 (corresponding to a non-crystalline silicon layer thickness of 80 nm at a wavelength of 532 nm) And 0.954 (wavelength of 532 nm and the amorphous silicon layer thickness corresponds to 100 nm).

Further, in the calculation of FIG. 8B, the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the amorphous film has an optical film thickness of the amorphous silicon layer 130, that is, the film thickness of the amorphous silicon layer 130. The value obtained by integrating the refractive index of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (corresponding to a wavelength of 532 nm and an amorphous silicon layer thickness of 50 nm), and the channel protective layer 140 is oxidized. A model consisting of silicon is used. 8B represents the optical film thickness of the gate insulating layer 120, that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, respectively. The value divided by 0.276 (corresponding to a silicon oxide layer thickness of 100 nm at a wavelength of 532 nm), 0.552 (corresponding to a silicon oxide layer thickness of 200 nm at a wavelength of 532 nm) and 1.103 (silicon oxide at a wavelength of 532 nm). The calculation results when the layer thickness corresponds to 400 nm are shown.

In the calculation of FIG. 8C, the gate insulating layer 120 is made of silicon oxide, and the refractive index of the amorphous silicon layer 130 is set to the optical film thickness of the amorphous silicon layer 130, that is, the film thickness of the amorphous silicon layer 130. A value obtained by dividing the integrated value by the wavelength of the laser beam is 0.477 (corresponding to a wavelength of 532 nm and an amorphous silicon layer thickness of 50 nm), and a model is used in which the channel protective layer 140 is made of silicon oxide. ing. And the broken line of FIG. 8C, the dashed-two dotted line, and the continuous line have shown the calculation result in case the gate electrode 110 is Cu, Al, and MoW, respectively.

From FIG. 7 to FIG. 8C, in the process of FIG. 2 (f), the value obtained by dividing the optical film thickness of the channel protective layer 140 by the wavelength of the laser beam is Z, and k is an integer starting from 0. If Expression 3) is satisfied, the absorption efficiency of the laser light in the portion below the channel protective layer 140 of the amorphous silicon layer 130 can be increased. In addition, A of FIG. 7 has shown the range where Z satisfy | fills the following (Formula 3). 8A to 8C, k = 0, 1, and 2 indicate the range of Z when k = 0, 1, and 2 in (Equation 3), respectively.

(Formula 3) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7)

As described above, according to the thin film transistor of the present embodiment, the portion of the channel layer below the channel protective layer 140 is formed of the crystalline silicon layer 131 and both sides thereof are formed of the amorphous silicon layer 130. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.

Even when the source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the underlying channel protective layer 140, the distance from the crystalline silicon layer 131 to the source electrode 171 in the channel path and the crystal in the channel path The distance from the conductive silicon layer 131 to the drain electrode 172 is uniform. Therefore, the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

(Second Embodiment)
Next, a thin film transistor according to a second embodiment of the present invention will be described below.

FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this embodiment.

In the thin film transistor according to the present embodiment, the first crystalline silicon layer 130 is replaced with the second crystalline silicon layer 230, and the crystalline silicon layer 131 is replaced with the first crystalline silicon layer 231. Different from the thin film transistor of the embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

The thin film transistor is formed on the substrate 100, the gate electrode 110 formed on the substrate 100, the gate insulating layer 120 formed on the gate electrode 110, and the gate insulating layer 120 above the gate electrode 110. On the first crystalline silicon layer 231 and the gate insulating layer 120, the second crystalline silicon layer 230 formed on both sides of the first crystalline silicon layer 231 and the first crystalline silicon layer 231 The channel protective layer 140 formed on the upper surface of the channel protective layer 140, the side surface of the channel protective layer 140, and the upper surface of the second crystalline silicon layer 230. A source electrode 171 formed above the second crystalline silicon layer 230 and a drain electrode 172 formed above the other of the second crystalline silicon layer 230, and a first crystal The average grain size of crystals contained in the silicon layer 231 is larger than the average grain size of crystals contained in the second crystalline silicon layer 230, and the film thickness of the first crystalline silicon layer 231 and the film of the second crystalline silicon layer Thickness is the same. Further, a contact layer 162 formed between the second crystalline silicon layer 230 and the source electrode 171 and a contact layer 161 formed between the second crystalline silicon layer 230 and the drain electrode 172 are provided.

Here, both ends of the crystalline silicon layer 131 and both ends of the channel protective layer 140 are disposed at the same position on the substrate 100. The first crystalline silicon layer 231 and the source electrode 171 have an overlapping region, and the first crystalline silicon layer 231 and the drain electrode 172 have an overlapping region.

Next, the thin film transistor of FIG. 9 will be described in detail.

The first crystalline silicon layer 231 and the second crystalline silicon layer 230 are semiconductor layers formed on the gate insulating layer 120 and constitute a channel layer whose carrier movement is controlled by the voltage of the gate electrode 110. . The first crystalline silicon layer 231 and the second crystalline silicon layer 230 are made of a crystalline silicon layer, and are made polycrystalline by irradiating the amorphous silicon of the amorphous silicon layer with laser. Formed). Note that the first crystalline silicon layer 231 and the second crystalline silicon layer 230 may be silicon layers having a mixed crystal structure of amorphous silicon and crystalline silicon layers.

The average grain size of crystals contained in the first crystalline silicon layer 231 is not less than 40 nm and not more than 1 μm, and the average grain size of crystals contained in the second crystalline silicon layer 230 is not less than 10 nm and less than 40 nm.

In the channel layer, the bottom surface of the first crystalline silicon layer 231 and the bottom surface of the second crystalline silicon layer 230 in the channel layer are flush and form the same plane, and the top surface of the first crystalline silicon layer 231 and the second crystalline silicon layer 231 are formed. Similarly, the upper surface of the silicon layer 230 is flush and forms the same plane. Further, the first crystalline silicon layer 231 is located above the gate electrode 110 and both ends thereof are located inside the both ends of the gate electrode 110.

The side surface of the channel protective layer 140 and the side surface of the first crystalline silicon layer 231 are flush with each other.

Hereinafter, a method of manufacturing the thin film transistor according to the present embodiment will be described with reference to FIG. FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to this embodiment.

The thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate A fourth step of forming the amorphous silicon layer 330 on the insulating layer 120, a fifth step of forming the channel protective layer 140 on the amorphous silicon layer 330, and the channel protective layer 140 above the gate electrode 110. A sixth step of patterning so as to leave the region, and irradiating the patterned channel protective layer 140 and the non-crystalline silicon layer 330 on which the channel protective layer 140 is not formed with a laser beam continuously The amorphous silicon layer 330 on which the layer 140 is formed is used as the first crystalline silicon layer 231, and the channel protective layer 140 is formed. A seventh step in which the non-crystalline silicon layer 330 is the second crystalline silicon layer 230, the upper surface of the end portion of the patterned channel protective layer 140, the side surface of the patterned channel protective layer 140, and the second crystalline property An eighth step of forming a source electrode 171 above one of the second crystalline silicon layers 230 and forming a drain electrode 172 above the other of the second crystalline silicon layers 230 along the upper surface of the silicon layer 230; In the seventh step, the first crystalline silicon layer 231 containing crystals having an average grain size larger than the average grain size of crystals contained in the second crystalline silicon layer 230 is formed.

Here, in the seventh step, the absorption rate of the amorphous silicon layer 330 in which the channel protective layer 140 is formed with respect to the laser beam is the absorption rate of the amorphous silicon layer 330 in which the channel protective layer 140 is not formed with respect to the laser beam. Greater than rate.

Next, a method for manufacturing the thin film transistor of FIG. 10 will be described in detail.

First, a glass substrate is prepared as the substrate 100 as shown in FIG.

Next, as shown in FIG. 10B, a gate electrode 110 having a predetermined shape is formed on the substrate 100.

Next, as shown in FIG. 10C, a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.

Next, as shown in FIG. 10D, an amorphous silicon layer 330 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do. Note that the amorphous silicon layer 330 is made of the same material as the amorphous silicon layer 130.

Next, as shown in FIG. 10E, a channel protective layer 140 is formed on the amorphous silicon layer 330.

Next, as shown in FIG. 10F, a part of the channel protective layer 140 is removed by etching.

Next, as shown in FIG. 10G, the non-crystalline silicon layer 330 is formed into a first crystalline silicon layer 231 and a second crystalline silicon layer 230 by laser annealing. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 330 is crystallized using the laser beam, so that the first crystalline silicon layer 231 and the second crystalline silicon layer 231 A crystalline silicon layer 230 is generated. More specifically, first, a dehydrogenation process is performed on the formed amorphous silicon layer 330. Thereafter, the first crystalline silicon layer 231 and the second crystalline silicon layer 230 are formed by making the amorphous silicon layer 330 polycrystalline (including microcrystals) by laser annealing.

At this time, the laser beam is emitted from the portion of the amorphous silicon layer 330 where the channel protective layer 140 is not formed, the portion of the amorphous silicon layer 330 where the channel protective layer 140 is formed, and the channel of the amorphous silicon layer 330. The amorphous silicon layer 330 is scanned in the order of the portion where the protective layer 140 is not formed, but the absorption rate of the laser light in the portion where the channel protective layer 140 is not formed is low. Accordingly, in the amorphous silicon layer 330, the first crystalline silicon layer 231 having a large average crystal grain size is formed in the portion where the channel protective layer 140 is formed, but the channel protective layer 140 is not formed. A second crystalline silicon layer 230 having a small average crystal grain size is formed in the portion.

Further, the laser light source of the laser light is a laser having a wavelength in the visible light region. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a green laser having a wavelength of 473 nm to 561 nm. The laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 330 is irradiated with the laser light discontinuously. This is because the amorphous silicon layer 330 cannot always be kept in a molten state. The reason why the pseudo continuous oscillation mode is also included is that the amorphous silicon layer 330 can be maintained in its molten state by being reheated by applying a pulse before it is cooled to below its melting point. Therefore, a preferred embodiment of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 330 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained. Further, the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element. In any case, it is preferable because laser light can be controlled with high accuracy. Furthermore, the irradiation energy of the laser light on the amorphous silicon layer 330 when the laser light having a wavelength in the visible light region is irradiated on the amorphous silicon layer 330 in order to form a crystalline silicon layer without crystal unevenness. A density variation of less than 5% is preferred. By forming the first crystalline silicon layer 231 and the second crystalline silicon layer 230 having no crystal unevenness, initial design characteristics of the thin film transistor can be achieved, and uniform characteristics can be realized.

Further, in the process of FIG. 10D, from the bottom surface of the non-crystalline silicon layer 330 to the top surface of the non-crystalline silicon layer 330 so that the laser beam does not attenuate until it reaches directly above the gate insulating layer 120. The amorphous silicon layer 330 is preferably formed so that the thickness of the amorphous silicon layer 330 is 100 nm or less.

Further, in order to suppress the laser light from being transmitted through the amorphous silicon layer 330 and damaging the gate electrode 110, in the process of FIG. 10D, the amorphous silicon layer 330 starts from the bottom surface of the amorphous silicon layer 330. It is preferable that the amorphous silicon layer 330 is formed so that the film thickness up to the upper surface is 10 nm or more.

In addition, in order to prevent the laser light from being absorbed by the gate insulating layer 120, in the process of FIG. 10C, the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG. A film such as silicon oxide or silicon nitride is preferably formed as the gate insulating layer 120.

Further, in order to prevent the laser light from being absorbed by the channel protective layer 140, in the process of FIG. 10E, the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG. A film of silicon oxide or silicon nitride is preferably formed as the channel protective layer 140.

Note that the amorphous silicon layer 330 is irradiated with the laser beam condensed linearly, and there are, for example, two irradiation methods as described above.

Next, as shown in FIG. 10 (h), a contact layer 160 to be the contact layers 161 and 162 is formed so as to straddle the upper surface of the channel protective layer 140 to the second crystalline silicon layer 230. Specifically, the contact layer 160 is formed so as to cover the upper surface and side surfaces of the channel protective layer 140 and the upper surface of the second crystalline silicon layer 230.

Next, as shown in FIG. 10I, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.

Next, as shown in FIG. 10J, a source electrode 171 and a drain electrode 172 and

contact layers

161 and 162 corresponding to the source electrode 171 and the drain electrode 172 are formed by using a photolithography method and an etching method.

Here, from FIG. 4A, even when the scan speed is constant in the process of FIG. 10G, the absorption rate of the amorphous silicon layer 330 on which the channel protective layer 140 is formed with respect to the laser beam, and the channel protective layer By making the difference between the absorptivity with respect to the laser light of the amorphous silicon layer 330 in which 140 is not formed 7% or more, silicon layers having different average grain sizes of crystals can be simultaneously formed by one laser scan, The first crystalline silicon layer 231 of the channel layer and the second crystalline silicon layers 230 on both sides thereof can be formed.

As described above, according to the thin film transistor of the present embodiment, the channel protective layer 140 below the channel layer is formed of the first crystalline silicon layer 231 having a large average crystal grain size, and both sides have a small average crystal grain size. A second crystalline silicon layer 230 is formed. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.

Even when the source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the underlying channel protective layer 140, the distance from the first crystalline silicon layer 231 to the source electrode 171 in the channel path, and the channel path The distance from the first crystalline silicon layer 231 to the drain electrode 172 in FIG. Therefore, the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

(Modification)
Next, modifications of the thin film transistor according to the first and second embodiments of the present invention will be described below. In the following, a modification of the thin film transistor according to the first embodiment will be described, but it is needless to say that the modification can be applied to the thin film transistor according to the second embodiment.

FIG. 11 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this modification.

In this thin film transistor, the first and second embodiments are that the gate insulating layer 120 has a two-layer structure and includes a silicon nitride layer 121 and a silicon oxide layer 122 formed on the silicon nitride layer 121. Different from form. The following description will focus on differences from the first and second embodiments.

This thin film transistor includes a substrate 100, a gate electrode 110, a gate insulating layer 120, a crystalline silicon layer 131, an amorphous silicon layer 130, a channel protective layer 140, a source electrode 171 and a drain electrode 172, and contacts.

Layers

162 and 161.

In the gate insulating layer 120, the capacitance of the series capacitor formed by the silicon nitride layer 121 and the silicon oxide layer 122 is equal to the capacitance of the single-layer silicon oxide layer 122 having a thickness of 100 nm to 140 nm. It has such a film thickness.

The manufacturing method of the thin film transistor of this modification is the same as the manufacturing method shown in FIG. 2, but in the step of FIG. 2C, the silicon nitride layer 121 and the silicon oxide layer formed on the silicon nitride layer 121 are used. 2 is different from the manufacturing method of FIG. 2 in that a gate insulating layer 120 composed of 122 is formed. Since the gate insulating layer 120 has a two-layer structure, the laser light of the laser annealing in FIG. 2G is easily reflected by the gate insulating layer 120, so that the laser light absorption rate of the amorphous silicon layer 130 is increased. be able to.

Hereinafter, characteristics of the thin film transistor according to this modification will be described with reference to FIGS. 12 to 13D.

FIG. 12 shows the crystal of the crystalline silicon layer 131 when the absorption rate of the laser beam of the amorphous silicon layer 130 and the scan speed of the laser beam are changed in the step of FIG. It is a figure which shows the change of sex.

In the measurement of FIG. 12, the laser output is 40 kW / cm ² , the gate electrode 110 is 50 nm thick MoW, the gate insulating layer 120 is 65 nm thick silicon nitride layer 121, and the 85 nm thick silicon oxide layer 122 is A sample consisting of

Further, “a-Si” in FIG. 12 indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon, and “SPC” indicates the average grain size of the crystalline silicon layer 131. “Ex & .SPC” indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm, and “p-Si” indicates the crystalline silicon layer. The average particle size of 131 is about 60 nm or more and 1 μm or less, and “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.

As shown in FIG. 12, an amorphous silicon layer and a crystalline silicon layer can be formed by changing the scanning speed of laser annealing and the absorptance of the amorphous silicon layer 130. Even when the scan speed is constant, the absorption rate of the amorphous silicon layer 130 in which the channel protective layer 140 is formed and the absorption rate of the amorphous silicon layer 130 in which the channel protective layer 140 is not formed are obtained. By making a difference of 1% or more, the amorphous silicon layer 130 and the crystalline silicon layer 131 of the channel layer can be formed. When this modification is applied to the thin film transistor according to the second embodiment, the absorptance of the amorphous silicon layer 330 on which the channel protective layer 140 is formed and the amorphous on which the channel protective layer 140 is not formed. By making a difference of 7% or more to the absorptivity of the crystalline silicon layer 330, the first crystalline silicon layer 231 of the channel layer and the second crystalline silicon layers 230 on both sides thereof can be formed.

FIG. 13A shows an amorphous silicon layer 130 when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the step of FIG. It is a contour map which shows the calculation result of the absorptivity.

In FIG. 13A, the lower horizontal axis indicates the optical thickness of the amorphous silicon layer 130, that is, the value obtained by integrating the refractive index of the amorphous silicon layer 130 with the thickness of the amorphous silicon layer 130. The value divided by the wavelength of light is shown. The left vertical axis shows the optical thickness obtained by converting the gate insulating layer 120 composed of the silicon nitride layer 121 and the silicon oxide layer 122 by the refractive index of the silicon oxide layer 122, that is, the silicon nitride layer 121 has a thickness of silicon nitride. The sum of the value obtained by integrating the refractive index of the layer 121 and the value obtained by integrating the refractive index of the silicon oxide layer 122 with the thickness of the silicon oxide layer 122 is integrated with the refractive index of the silicon oxide layer 122 and the wavelength of the laser beam. The value divided by the value is shown. For reference, the film thickness (film thickness) of the gate insulating layer 120 is plotted with the film thickness of the amorphous silicon layer 130 when the laser beam wavelength is set to 532 nm without being normalized by the laser beam wavelength. The thickness of the 120 nm single-layer silicon oxide layer 122 is shown on the right vertical axis. Further, on the right vertical axis, the film thickness ratio of the silicon oxide layer 122 and the silicon nitride layer 121 is also indicated by “film thickness of the silicon oxide layer 122 / film thickness of the silicon nitride layer 121”.

In the calculation of FIG. 13A, a model is used in which the gate electrode 110 is made of MoW and the channel protective layer 140 is 0 nm.

By the way, for example, when the wavelength is 532 nm, by using the respective refractive indexes of the silicon oxide layer 122 and the silicon nitride layer 121, the silicon oxide layer 122 and the nitride that constitute the gate insulating layer 120 from the values on the vertical axis in FIG. Each film thickness of the silicon layer 121 can be calculated. 13B to 13D are diagrams showing examples of values obtained by converting the values on the vertical axis in FIG. 13A into the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 included in the gate insulating layer 120. FIG. FIG. 13B shows values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at a wavelength of 532 nm. Similarly, FIGS. 13C and 13D show values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at wavelengths of 561 nm and 473 nm, respectively. Here, the relative dielectric constants of the silicon oxide layer 122 and the silicon nitride layer 121 are calculated as 4.1 and 7.9, respectively. Note that C in the figure indicates the film thickness of a single silicon oxide layer corresponding to the total capacitance of the laminated film composed of the silicon oxide layer and the silicon nitride layer, and the gate insulating layer 120 is oxidized with the film thickness C. It shows that the total capacitance of the laminated film is fixed to the capacitance value in the case of a single silicon layer. For example, if C = 140 nm, it indicates that the total capacitance value of the gate insulating layer 120 is the capacitance value of a single silicon oxide layer of 140 nm. Similarly, for example, when C = 120 nm or C = 100 nm, the value of the total capacitance of the gate insulating layer 120 is the value of the capacitance of a single silicon oxide layer of 120 nm or 100 nm.

From FIG. 12 to FIG. 13D, regardless of the material of the gate electrode 110 and the thickness of the channel protective layer 140, in the process of FIG. The value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam, which is a value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of 130, is X, and the silicon nitride layer 121 is oxidized. An optical film thickness obtained by converting the gate insulating layer 120 composed of the silicon layer 122 by the refractive index of the silicon oxide layer 122, that is, a value obtained by adding the refractive index of the silicon nitride layer 121 to the film thickness of the silicon nitride layer 121 and silicon oxide A value obtained by dividing the sum of the film thickness of the layer 122 and the value obtained by integrating the refractive index of the silicon oxide layer 122 by the value obtained by integrating the refractive index of the silicon oxide layer 122 and the wavelength of the laser beam is Y. , X and Y satisfy the following (Expression 4) and (Expression 5), or (Expression 6) and (Expression 7), the absorption rate of the laser light of the amorphous silicon layer 130 includes the maximum absorption rate. For example, it can be 50% or more. 12A shows a range where X and Y satisfy the following (formula 4) and (formula 5), and B in FIG. 12 shows that X and Y satisfy the following (formula 6) and (formula 7). The range is shown.

(Formula 4) 0.226 ≦ Y ≦ 0.26
(Formula 5) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 6) 0.340 ≦ Y ≦ 0.543
(Formula 7) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28

As described above, according to the thin film transistor of the present modification, both excellent on characteristics and excellent off characteristics can be achieved for the same reason as in the first embodiment. Further, the electrical characteristics can be made symmetrical with respect to the replacement of the source electrode and the drain electrode.

Further, according to the thin film transistor of this modification, since the gate insulating layer 120 has a two-layer structure, it is possible to increase the absorptance of the laser light in the portion below the channel protective layer 140 of the amorphous silicon layer 130. Therefore, for example, the average grain size of the crystal in the portion of the channel layer below the channel protective layer 140 can be increased to increase the on-current.

(Comparative example)
Next, comparative examples of the thin film transistors according to the first and second embodiments of the present invention will be described below.

FIG. 14 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this comparative example.

This thin film transistor is the same as the first and second embodiments in that the crystalline silicon layer 131 is formed by irradiating the amorphous silicon layer 130 with laser light using the source electrode 171 and the drain electrode 172 as a mask. Different.

Layers

162 and 161.

The crystalline silicon layer 131 is not formed in the entire region below the channel protective layer 140, but is formed only in a part of the region. Therefore, a part of the channel length defined by the width of the channel protective layer 140 (C and D in FIG. 14) is occupied by the high-resistance amorphous silicon layer 130. Compared to the first and second embodiments, The horizontal resistance component of the channel layer increases.

The source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the lower channel protective layer 140. Accordingly, the distance from the crystalline silicon layer 131 to the source electrode 171 in the channel path (B in FIG. 14) and the distance from the crystalline silicon layer 131 to the drain electrode 172 in the channel path are unequal. As a result, when the source electrode 171 and the drain electrode 172 are switched to operate, the electrical characteristics are asymmetric with respect to the replacement of the source electrode 171 and the drain electrode 172.

As described above, the thin film transistor according to the first and second embodiments can realize excellent on characteristics and excellent off characteristics as compared with the thin film transistor according to this comparative example, and the electrical characteristics can be switched between the source electrode and the drain electrode. It can be symmetric.

(Third embodiment)
FIG. 15 is an external view of a display device according to the third embodiment of the present invention. FIG. 16 is a partially cutaway perspective view of the organic EL panel according to the present embodiment.

The display device 340 is a display device including an organic EL panel, and includes the thin film transistor of the first or second embodiment, and the thin film transistor drives the organic EL panel. The display device 340 includes an organic EL panel 320 using the thin film transistor of the first or second embodiment as a switching transistor or a driving transistor of an active matrix substrate.

The organic EL panel 320 includes an active matrix substrate 321, a plurality of pixels 322 arranged in a matrix on the active matrix substrate 321, and a pixel circuit connected to the pixels 322 and arranged in an array on the active matrix substrate 321. 323, an anode 324, an organic EL layer 325, and a cathode 326 (transparent electrode) sequentially stacked on the pixel 322 and the pixel circuit 323, and a plurality of pixels that connect each pixel circuit 323 and a control circuit (not shown). A source line 327 and a gate line 328 are provided. The organic EL layer 325 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.

FIG. 17 is a diagram showing a circuit configuration of the pixel 322 of the organic EL panel 320 of FIG.

As shown in FIG. 17, the pixel 322 includes a driving transistor 331, a switching transistor 332, an organic EL element 333, and a capacitor 334. The drive transistor 331 is a transistor that drives the organic EL element 333, and the switching transistor 332 is a transistor for selecting the pixel 322.

The source electrode 332S of the switching transistor 332 is connected to the source line 327, the gate electrode 332G is connected to the gate line 328, and the drain electrode 332D is connected to the capacitor 334 and the gate electrode 331G of the driving transistor 331.

Also, the drain electrode 331D of the drive transistor 331 is connected to the power supply line 335, and the source electrode 331S is connected to the anode of the organic EL element 333.

In this configuration, when a gate signal is input to the gate line 328 and the switching transistor 332 is turned on, the signal voltage supplied through the source line 327 is written to the capacitor 334. Then, the holding voltage written in the capacitor 334 is held throughout one frame period. With this holding voltage, the conductance of the drive transistor 331 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 333. Thereby, the organic EL element 333 emits light and is displayed as an image.

In the present embodiment, the organic EL display device using the organic EL panel has been described. However, the thin film transistor of the first or second embodiment can also be applied to a transistor that drives the liquid crystal panel of the liquid crystal display device. In this case, the display device includes a liquid crystal panel, and includes the thin film transistor according to the first or second embodiment, and the thin film transistor drives the liquid crystal panel.

As mentioned above, although the thin-film transistor, its manufacturing method, and the display apparatus of this invention were demonstrated based on embodiment, this invention is not limited of these embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

For example, the display device of the above-described embodiment can be used as a flat panel display, and can be applied to an electronic apparatus having any display unit such as a television set, a personal computer, and a mobile phone.

In the thin film transistor of the above embodiment, the thickness of the crystalline silicon layer 131 and the thickness of the amorphous silicon layer 130 are the same, or the thickness of the first crystalline silicon layer 231 and the thickness of the second crystalline silicon layer are the same. Although the film thickness is the same, the “same” at this time includes a state in which there is a step formed by laser light irradiation. For example, as shown in the top view of FIG. 18A (upper view of the step of FIG. 2G), the amorphous silicon layer 130 is irradiated with laser light in forming the crystalline silicon layer 131. A bulge is formed on the surface of the amorphous silicon layer 130 by a volume change according to the irradiation energy of the laser light. Since the absorption rate of the laser beam in the portion below the channel protective layer 140 of the amorphous silicon layer 130 is particularly large, as shown in the cross-sectional view of FIG. 18B (the cross-sectional view of the step of FIG. 2G), the crystalline property A step is formed between the surface of the silicon layer 131 and the surface of the amorphous silicon layer 130. Therefore, the state where there is such a step is also included in the “same” in the present invention. Note that the change in the bulge amount with respect to the input energy of the laser light to the amorphous silicon layer 130 is as shown in FIG. 18C.

In addition, according to the present invention, it goes without saying that the semiconductor layer such as the channel layer may be an n-type semiconductor or a p-type semiconductor.

The present invention can be used for a thin film transistor, a method for manufacturing the same, and a display device, and in particular, can be used for a display device such as a television set, a personal computer and a mobile phone, or various electric devices having a thin film transistor.

100, 405 Substrate 110, 331G, 332G Gate electrode 120 Gate insulating layer 121 Silicon nitride layer 122

Silicon oxide layer

130, 330 Amorphous silicon layer 131 Crystalline silicon layer 140 Channel

protective layer

160, 161, 162 Contact layer 170 Source drain Metal film 171, 331S, 332S Source electrode 172, 331D, 332D Drain electrode 230 Second crystalline silicon layer 231 First crystalline silicon layer 320 Organic EL panel 321 Active matrix substrate 322 Pixel 323 Pixel circuit 324 Anode 325 Organic EL layer 326 Cathode 327 Source line 328 Gate line 331 Drive transistor 332 Switching transistor 333 Organic EL element 334 Capacitor 335 Power line 340

Display device

401, 402, 403, 404 layers

Claims

A substrate,
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A crystalline silicon layer formed on the gate insulating layer and above the gate electrode;
An amorphous silicon layer formed on both sides of the crystalline silicon layer on the gate insulating layer;
A crystallization control layer formed on the crystalline silicon layer;
A source electrode formed above one of the non-crystalline silicon layers along an upper surface of an end portion of the crystallization control layer, a side surface of the crystallization control layer, and an upper surface of the non-crystalline silicon layer; A drain electrode formed on the other side of the amorphous silicon layer,
The film thickness of the crystalline silicon layer and the film thickness of the amorphous silicon layer are the same.
Thin film transistor.
Both ends of the crystalline silicon layer and both ends of the crystallization control layer are disposed at the same position on the semiconductor substrate.
The thin film transistor according to claim 1.
The crystalline silicon layer and the source electrode have overlapping regions,
The crystalline silicon layer and the drain electrode have overlapping regions;
The thin film transistor according to claim 1 or 2.
The average particle size of crystals contained in the crystalline silicon layer is 10 nm or more and 1 μm or less.
The thin film transistor according to any one of claims 1 to 3.
A substrate,
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A first crystalline silicon layer formed on the gate insulating layer and above the gate electrode;
A second crystalline silicon layer formed on both sides of the first crystalline silicon layer on the gate insulating layer;
A crystallization control layer formed on the first crystalline silicon layer;
A source electrode formed above one of the second crystalline silicon layers along the upper surface of the end portion of the crystallization control layer, the side surface of the crystallization control layer, and the upper surface of the second crystalline silicon layer And a drain electrode formed on the other side of the second crystalline silicon layer,
An average grain size of crystals contained in the first crystalline silicon layer is larger than an average grain size of crystals contained in the second crystalline silicon layer;
The film thickness of the first crystalline silicon layer and the film thickness of the second crystalline silicon layer are the same.
Thin film transistor.
Both ends of the first crystalline silicon layer and both ends of the crystallization control layer are disposed at the same position on the semiconductor substrate.
The thin film transistor according to claim 5.
The first crystalline silicon layer and the source electrode have overlapping regions;
The first crystalline silicon layer and the drain electrode have overlapping regions;
The thin film transistor according to claim 5 or 6.
The average grain size of crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less,
The average grain size of crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm,
The thin film transistor according to any one of claims 5 to 7.
A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating layer on the gate electrode;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
A fifth step of forming a crystallization control layer on the non-crystalline silicon layer;
A sixth step of patterning the crystallization control layer so as to leave a region above the gate electrode;
The non-crystalline property in which the crystallization control layer is formed by continuously irradiating the patterned crystallization control layer and the non-crystalline silicon layer in which the crystallization control layer is not formed. A seventh step in which the silicon layer is a crystalline silicon layer, and the non-crystalline silicon layer in which the crystallization control layer is not formed is left as an amorphous silicon layer;
A source above one of the non-crystalline silicon layers along the upper surface of the edge of the patterned crystallization control layer, the side surface of the patterned crystallization control layer, and the upper surface of the non-crystalline silicon layer Forming an electrode and forming a drain electrode over the other of the non-crystalline silicon layer,
A method for manufacturing a thin film transistor.
In the seventh step,
The absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed is greater than the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is not formed.
A method for manufacturing the thin film transistor according to claim 9.
In the seventh step,
The crystalline silicon layer containing crystals having an average particle diameter of 10 nm or more and 1 μm or less is formed by the laser light irradiation.
The manufacturing method of the thin-film transistor of Claim 9 or 10.
In the seventh step,
The wavelength of the laser light is 473 nm or more and 561 nm or less,
The method for producing a thin film transistor according to any one of claims 9 to 11.
A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating layer on the gate electrode;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
A fifth step of forming a crystallization control layer on the non-crystalline silicon layer;
A sixth step of patterning the crystallization control layer so as to leave a region above the gate electrode;
The non-crystalline property in which the crystallization control layer is formed by continuously irradiating the patterned crystallization control layer and the non-crystalline silicon layer in which the crystallization control layer is not formed. A seventh step in which the silicon layer is a first crystalline silicon layer, and the non-crystalline silicon layer in which the crystallization control layer is not formed is a second crystalline silicon layer;
An upper surface of an end portion of the patterned crystallization control layer, a side surface of the patterned crystallization control layer, and an upper surface of one of the second crystalline silicon layers along the upper surface of the second crystalline silicon layer Forming a source electrode, and forming a drain electrode above the other of the second crystalline silicon layers,
In the seventh step,
Forming the first crystalline silicon layer including crystals having an average grain size larger than an average grain size of crystals contained in the second crystalline silicon layer;
A method for manufacturing a thin film transistor.
In the seventh step,
The absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed is greater than the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is not formed.
A method for manufacturing the thin film transistor according to claim 13.
The average grain size of crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less,
The average grain size of crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm.
15. A method for manufacturing a thin film transistor according to claim 13 or 14.
In the seventh step,
The wavelength of the laser light is 473 nm or more and 561 nm or less,
The method for producing a thin film transistor according to any one of claims 13 to 15.
In the seventh step,
The difference between the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed with respect to the laser beam and the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is not formed with respect to the laser beam Is 7% or more,
The method for producing a thin film transistor according to any one of claims 13 to 16.
In the seventh step,
The difference between the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed with respect to the laser beam and the absorption rate of the non-crystalline silicon layer in which the crystallization control layer is not formed with respect to the laser beam Is 1% or more,
The method for producing a thin film transistor according to any one of claims 9 to 17.
In the seventh step,
Let l and m be integers starting from 0,
The optical film thickness of the amorphous silicon layer, which is a value obtained by integrating the refractive index of the amorphous silicon layer to the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer, Let X be the value divided by the wavelength of the laser beam,
A value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by integrating the refractive index of the gate insulating layer with the film thickness of the gate insulating layer, is divided by the wavelength of the laser beam, and Y.
X and Y satisfy the following (formula 1) and (formula 2).
The method for producing a thin film transistor according to any one of claims 9 to 18.
(Formula 1) 0.50 m ≦ Y ≦ 0.40 + 0.50 m
(Formula 2) -3.75 (X-0.50 l) + 1.83 + 0.50 m ≦ Y ≦ −3.75 (X-0.50 l) + 0.35 + 0.50 m
In the third step,
Forming the gate insulating layer composed of a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer;
The method for producing a thin film transistor according to any one of claims 9 to 18.
In the gate insulating layer, the capacitance of the series capacitor formed by the silicon nitride layer and the silicon oxide layer is equal to the capacitance of a single silicon oxide layer having a thickness of 100 nm to 140 nm. Formed with different film thickness,
The manufacturing method of the thin-film transistor of Claim 20.
In the seventh step,
Let n be an integer starting from 0,
The optical film thickness of the amorphous silicon layer, which is a value obtained by integrating the refractive index of the amorphous silicon layer to the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer, Let X be the value divided by the wavelength of the laser beam,
A value obtained by dividing the optical film thickness obtained by converting the gate insulating layer composed of the silicon nitride layer and the silicon oxide layer by the refractive index of the silicon oxide layer by the sum of the refractive index of the silicon oxide layer and the wavelength of the laser beam. Is Y,
X and Y satisfy the following (formula 3) and (formula 4), or (formula 5) and (formula 6).
The manufacturing method of the thin-film transistor of Claim 20 or 21.
(Formula 3) 0.226 ≦ Y ≦ 0.26
(Formula 4) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 5) 0.340 ≦ Y ≦ 0.543
(Formula 6) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28
In the fifth step,
A value obtained by dividing the optical film thickness of the crystallization control layer by the film thickness of the crystallization control layer and the refractive index of the crystallization control layer divided by the wavelength of the laser light is Z, and k is 0. An integer starting from
Said Z satisfies the following (formula 7):
The method for producing a thin film transistor according to any one of claims 9 to 22.
(Expression 7) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7)
In the fourth step,
Forming the amorphous silicon layer such that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 100 nm or less;
The method for producing a thin film transistor according to any one of claims 9 to 23.
In the fourth step,
Forming the amorphous silicon layer so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 10 nm or more;
The method for producing a thin film transistor according to any one of claims 9 to 24.
In the first step,
Preparing the substrate having an undercoat layer formed on the surface;
In the second step,
Forming the gate electrode on the undercoat layer;
The method for producing a thin film transistor according to any one of claims 9 to 25.
In the second step,
Forming a metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal as the gate electrode;
The method for producing a thin film transistor according to any one of claims 9 to 26.
In the third step,
A film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam is formed as the gate insulating layer.
The method for producing a thin film transistor according to any one of claims 9 to 27.
In the third step,
Forming a silicon oxide layer as the gate insulating layer;
The method for producing a thin film transistor according to any one of claims 9 to 28.
In the third step,
Forming a silicon nitride layer as the gate insulating layer;
The method for producing a thin film transistor according to any one of claims 9 to 28.
In the fifth step,
Forming a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light as the crystallization control layer;
The method for producing a thin film transistor according to any one of claims 9 to 30.
In the fifth step,
Forming a silicon oxide layer as a crystallization control layer;
32. A method of manufacturing a thin film transistor according to claim 31.
In the fifth step,
Forming a silicon nitride layer as a crystallization control layer;
32. A method of manufacturing a thin film transistor according to claim 31.
In the seventh step,
The method of manufacturing a thin film transistor according to any one of claims 9 to 33, wherein the laser light is light in a continuous oscillation mode or a pseudo continuous oscillation mode.
In the seventh step,
The method of manufacturing a thin film transistor according to any one of claims 9 to 33, wherein the laser light is light emitted from a solid-state laser device.
In the seventh step,
The method of manufacturing a thin film transistor according to any one of claims 9 to 33, wherein the laser light is light emitted from a laser device using a semiconductor laser element.
In the seventh step,
The method of manufacturing a thin film transistor according to any one of claims 9 to 36, wherein a variation in irradiation energy density of the laser light on the amorphous silicon layer is less than 5%.
In the seventh step,
The laser light is continuously irradiated at a constant scanning speed to the amorphous silicon layer in which the crystallization control layer is formed and the amorphous silicon layer in which the crystallization control layer is not formed. The method for producing a thin film transistor according to any one of 9 to 37.
A display device comprising a liquid crystal panel or an organic EL panel,
A thin film transistor according to any one of claims 1 to 8,
The thin film transistor drives the liquid crystal panel when the display device includes the liquid crystal panel, and drives the organic EL panel when the display device includes the organic EL panel.