KR20110075518A - Method of fabricating an array substrate - Google Patents

Abstract

PURPOSE: A method for manufacturing an array substrate is provided to comprise a thin film transistor with simple structure and high mobility and reliability, by crystallizing an amorphous silicon using a stable laser apparatus. CONSTITUTION: A gate wiring is formed on a substrate where a pixel region is defined. A gate electrode(108) is connected to the gate wiring. A gate insulation film and a pure amorphous silicon layer are formed on the front of the substrate on the gate wiring and the gate electrode. A barrier film of SiO2 is formed on the pure amorphous silicon layer through O2 plasma process. The pure amorphous silicon layer is micro-crystallized into a polysilicon layer. A polysilicon active layer is formed on the gate insulation film by patterning the polysilicon layer. A source electrode and a drain electrode are separated from a data line and an ohmic contact layer. A protection layer reveals the drain electrode on the source and drain electrode and the data line. A pixel electrode is formed through the drain contact hole on the protection layer. The pixel electrode contacts with the drain electrode.

Description

Method of fabricating an array substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to a method of manufacturing an array substrate including a thin film transistor having excellent mobility characteristics and using polysilicon as an active layer.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling voltage on and off, is realized in each pixel. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided in order to control each pixel area on / off.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

The cross-sectional structure of the thin film transistor which serves as such a switching element will be described with reference to FIG. 1.

1 is a cross-sectional view of one pixel area including a portion in which a thin film transistor is formed in the above-described conventional array substrate.

The gate electrode 3 is formed on the transparent insulating substrate 1 to correspond to the element region TrA in the pixel region P, and the gate insulating layer 6 is formed on the entire surface of the gate electrode 3. have. In addition, an ohmic contact layer 10b formed of an active layer 10a made of pure amorphous silicon on the gate insulating film 6 and corresponding to the gate electrode 3, and amorphous silicon containing impurities in a form spaced apart from each other. The semiconductor layer 10 which consists of these is formed.

In addition, the ohmic contact layer 10b formed to expose the active layer 10a below and spaced apart from each other is in contact with the ohmic contact layer 10b and spaced apart from each other to correspond to the gate electrode 10. The source electrode 13 and the drain electrode 16 are formed while exposing the layer 10a.

The gate electrode 3, the gate insulating layer 6, and the source and drain electrodes 13 and 16 spaced apart from each other and sequentially stacked on the substrate 1 form a thin film transistor Tr.

A passivation layer 20 having a drain contact hole 23 exposing a part of the drain electrode 16 is formed on the front surface of the thin film transistor Tr having the above structure, and each passivation layer 20 is formed on the passivation layer 20. A pixel electrode 26 is formed in each pixel region P to contact the drain electrode 16 through the drain contact hole 23. In addition, a gate wiring (not shown) connected to the gate electrode 3 on the same layer on which the gate electrode 3 is formed, and the source electrode 13 on the same layer on which the source and drain electrodes 13 and 16 are formed. ) And a data line (not shown) connected to each other is formed to form the array substrate 1.

However, it can be seen that the active layer 10a uses pure amorphous silicon in the case of a thin film transistor that is generally configured in a conventional array substrate. When the active layer 10a is formed using the pure amorphous silicon, the pure amorphous silicon is changed into a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered. The carrier mobility within the channel is low, 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as an element for a driving circuit.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of pure amorphous silicon into a semiconductor layer of polysilicon by a crystallization process through an Eximer Laser Annealing (ELA). .

However, in the fabrication of an array substrate including a thin film transistor using polysilicon as a semiconductor layer through the crystallization process of ELA, FIG. 2 (in the array substrate having a thin film transistor using a conventional polysilicon semiconductor layer, the thin film transistor is used. Referring to a cross-sectional view of one pixel region including the same), it is necessary to form an n + region 35b or a p + region (not shown) containing a high concentration of impurities, so that these n + regions 35b or p + regions ( A doping process for forming is required, and an ion implantation equipment is additionally required to proceed with the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured for manufacturing the array substrate 30 by adding new equipment.

In addition, the laser device used in the crystallization process through ELA is an excimer laser device to generate a laser beam having a 308 nm wavelength by a gas medium. However, the use of gas as the source medium for generating the laser beam produces a laser beam having an optimal power for melting the amorphous silicon, and the generated laser beam has a very large error range of its energy density. As the energy density of the laser beam irradiated for each position is increased when the layer is irradiated, streaks are generated due to the difference in characteristics of the thin film transistor itself, which causes a problem of deteriorating display quality.

In addition, the array substrate used in the organic light emitting diode is driven by a current flowing through the thin film transistor, in particular, the driving thin film transistor, unlike the voltage driving of the liquid crystal display device. Therefore, in the case of a driving thin film transistor, which is a device for driving an organic light emitting device, stability is required, and in order to satisfy this, a thin film transistor is manufactured using polysilicon as a semiconductor layer, or fabrication including ELA crystallization. When manufactured in the method, many errors occur in the uniformity of the thin film transistor.

Therefore, a thin film transistor using amorphous silicon as an active layer, which has a simple manufacturing process and excellent uniformity in manufacturing, although the mobility and device stability are slowed down, and a polysilicon having high manufacturing stability and mobility characteristics but high manufacturing cost and high manufacturing cost. There is a need for an array substrate including a new type of thin film transistor having the advantages of a thin film transistor having silicon as a semiconductor layer.

In order to solve the above problems, the present invention crystallizes amorphous silicon using a relatively stable laser device having a small energy density error range of the laser beam without introducing additional ion implantation equipment, thereby having excellent device characteristics, high mobility, and reliability. It is an object of the present invention to provide a method of manufacturing an array substrate having a thin film transistor having a simple structure.

By eliminating the ion doping step as compared to the conventional method of manufacturing an array substrate having a thin film transistor using polysilicon as a semiconductor layer, the production process is simplified and the productivity is improved, and no additional ion implant equipment for ion doping is introduced. Another aim is to reduce manufacturing costs.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a gate wiring extending in one direction on a substrate on which a pixel region is defined, and forming a gate electrode connected to the gate wiring; Sequentially forming a gate insulating film and a pure amorphous silicon layer on the entire surface of the substrate over the gate wiring and the gate electrode; Performing an oxygen (O ₂ ) plasma process to form a barrier film of silicon oxide (SiO ₂ ) on the surface of the pure amorphous silicon layer; Forming a photothermal conversion layer of a metal material on the barrier film of silicon oxide (SiO ₂ ); Microcrystalline crystallizing the pure amorphous silicon layer into a polysilicon layer by irradiating a laser beam to the photothermal conversion layer; Removing the photothermal conversion layer; Performing a first cleaning using a buffered oxide etchant (BOE) to remove the barrier layer of silicon oxide (SiO ₂ ); Patterning the polysilicon layer to form an active layer of polysilicon on the gate insulating film corresponding to the gate electrode; Forming a data line over the gate insulating layer to define the pixel region crossing the gate line, and a source and drain electrode spaced apart from each other over an active layer of polysilicon and an ohmic contact layer of impurity amorphous silicon; Forming a protective layer exposing the drain electrode over the source and drain electrodes and the data line; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

In this case, the gate insulating film is characterized in that it has a single layer structure or a double layer structure made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx), wherein the gate insulating film is plasma enhanced chemical vapor depdsition (PECVD) It is characterized in that it is formed to have a thickness of 2000 ℃ to 4500 ℃ in a temperature atmosphere of 320 ℃ to 450 ℃ using the device.

In addition, the silicon oxide (SiO ₂ ) barrier film is preferably formed to have a thickness of about 100 ~ 500Å.

The method further includes forming a data line defining the pixel region on the gate insulating layer and crossing the gate line, and a source and drain electrode spaced apart from the ohmic contact layer of impurity amorphous silicon spaced apart from each other on an active layer of polysilicon. Forming an impurity amorphous silicon layer and a metal layer on the entire surface of the substrate sequentially over the active layer of polysilicon; Forming the data line and the source and drain electrodes spaced apart from each other in the device region on the impurity amorphous silicon layer by patterning the metal layer; Removing the pure amorphous silicon layer exposed to the outside of the data line and the source and drain electrodes to form an ohmic contact layer of impurity amorphous silicon spaced apart from each other under the source and drain electrodes, wherein the polysilicon And performing a secondary cleaning using a buffered oxide etchant (BOE) on the substrate on which the active layer of polysilicon is formed before forming the impurity amorphous silicon layer over the active layer of the film.

In addition, the laser beam is characterized in that the laser beam generated by a DPOD (Diode Pumped Solid State) laser apparatus using a solid medium.

In addition, the photo-thermal conversion layer is formed to have a thickness of 800 Å to 1200 하여 by depositing any one of chromium (Cr), chromium alloy, titanium (Ti), titanium alloy, which is a metal material having excellent ability to convert light into thermal energy. to be.

In the array substrate for a liquid crystal display device according to the present invention, the amorphous silicon layer is crystallized into a polysilicon layer by a solid laser crystallization process through a heat conversion layer, and a thin film transistor is used as the semiconductor layer to form a semiconductor of the amorphous silicon layer. Compared to the thin film transistor having a layer, the mobility property is improved by several tens to several hundred times.

In addition, by having a stable thin film transistor characteristics without the doping process through the ion implant equipment has the effect of reducing the manufacturing cost through the suppression of new equipment investment.

In addition, compared to a general thin film transistor using polysilicon, the laminated structure thereof is simple like a thin film transistor using an amorphous silicon layer, and is manufactured through a relatively simple manufacturing process, thereby improving productivity.

In addition, while the crystallization process is performed by using a laser through the heat conversion layer, the metal silicide is completely removed to correspond to the portion where the channel is formed, thereby improving device characteristics of the thin film transistor and suppressing device defects. .

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

3A to 3N are cross-sectional views illustrating manufacturing steps of one pixel area of an array substrate including a thin film transistor having an active layer of polysilicon according to an exemplary embodiment of the present invention. In this case, for convenience of description, an area in which the thin film transistor Tr is formed in each pixel area is defined as an element area TrA.

First, as shown in FIG. 3A, a selected one of a first metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, and chromium (Cr) on the transparent substrate 101 is shown. To deposit a material to form a first metal layer (not shown). Subsequently, the first metal layer (not shown) is patterned by performing a mask process including a series of unit processes such as application of photoresist, exposure using a mask, development of photoresist, etching, and stripping of photoresist. A gate line (not shown) extending in one direction is formed, and at the same time, a gate electrode 108 connected to the gate line (not shown) is formed in each device region TrA.

 At this time, the first metal layer (not shown) by continuously depositing two or more different metal materials among the above-described first metal material to form a double layer or more, the gate wiring (not shown) and the gate of the double-filled or multilayer structure An electrode (not shown) may be formed. In the drawings, a gate wiring (not shown) and a gate electrode 108 having a single layer structure are shown for convenience.

Next, as shown in FIG. 3B, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 on which the gate wiring (not shown) and the gate electrode 108 are formed. ) Is formed using a plasma enhanced chemical vapor deposition (PECVD) device (not shown) to form the gate insulating film 112.

In this case, the gate insulating layer 112 may be formed to have a double layer structure by using both inorganic insulating materials. In this case, the gate insulating film 112 is preferably formed to have a thickness of about 2000 kPa to about 4000 kPa in a temperature atmosphere of 320 ℃ to 450 ℃. When the gate insulating layer 112 is formed to have a thickness lower than the 2000 kPa at a temperature lower than 320 ° C., a micro void is formed on the surface of the gate insulating layer 112 after a crystallization process through laser beam irradiation. Experiments show that the semiconductor layer (131 in FIG. 3N) of the transistor (Tr in FIG. 3N) adversely affects channel formation and degrades the device characteristics of the thin film transistor (Tr in FIG. 3N).

Accordingly, in order to prevent the formation of such micro voids, the gate insulating layer 112 may maintain a temperature atmosphere of about 320 ° C. to 450 ° C. in the chamber 193 during deposition using a PECVD apparatus (not shown). It is preferable to form so as to have a thickness of about 2000 kPa to 4000 kPa in one state.

Thereafter, the pure amorphous silicon layer 116 is formed by depositing pure amorphous silicon on the gate insulating layer 112. In this case, the pure amorphous silicon layer 116 is preferably formed to have a thickness of about 300 kPa to 1000 kPa, and has a thickness thicker than that of the barrier film (125 in FIG. 3C) of silicon oxide (SiO ₂ ) to be formed thereafter. to be.

Next, as shown in FIG. 3C, a PECVD apparatus (not shown) in which the pure amorphous silicon layer 116 is formed on the substrate 101 on which the pure amorphous silicon layer 116 is formed is the most characteristic configuration of the present invention. After changing the atmosphere in the chamber 193 to the oxygen (O ₂ ) atmosphere, a plasma process is performed to react the surface of the pure amorphous silicon layer 116 with the oxygen (O ₂ ) plasma. The barrier layer 125 of silicon oxide (SiO ₂ ) is formed.

As described above, the oxygen (O ₂ ) plasma treatment may be continuously performed in the chamber 193 of the PECVD apparatus (not shown) in which the pure amorphous silicon layer 116 is formed, or the dry etching equipment (not shown). After moving into a chamber (not shown) of the city may be made in the chamber (not shown) of the dry etching equipment (not shown).

Meanwhile, the oxygen (O ₂ ) plasma process is performed on the pure amorphous silicon layer 116 to form a barrier film 125 of silicon oxide (SiO ₂ ) at the top of the thin film transistor (see FIG. 3N). This is to prevent the deterioration of the device characteristics and the driving failure of Tr).

After the direct contact between the photothermal conversion layer (190 of FIG. 3d) and the pure amorphous silicon layer 116 to be formed through the process later, the pure amorphous silicon layer 116 and the photothermal conversion layer (FIG. 3d) 2) reacts, and more precisely, a metal silicide is formed by diffusing a metal material constituting the photothermal conversion layer (190 in FIG. 3D) into the pure amorphous silicon layer 116, and the metal silicide is formed in the light heat. It still remains during the etching process to remove the conversion layer (190 in FIG. 3D).

When the metal silicide (not shown) is finally left over the semiconductor layer (131 in FIG. 3n) to form a thin film transistor (Tr in FIG. 3n), the thin film transistor (Tr in FIG. 3n) adversely affects the channel portion. Even when a voltage smaller than the threshold voltage is applied to the gate electrode, the thin film transistor (Tr of FIG. 3n) is in an on state. Such a thin film transistor (Tr of FIG. 3n) does not perform a proper role as a switching device. As a result, the driving failure of the array substrate 101 having the same may be caused.

Therefore, in the embodiment of the present invention, silicon oxide (SiO ₂ ) through oxygen (O ₂ ) plasma treatment on the surface of the pure amorphous silicon layer 116, as described above, in order to prevent the metal silicide formation by the process proceeds later. Barrier film 125 is formed. In this case, a time (for example, 30 seconds to 120 seconds) for exposing the pure amorphous silicon layer 116 to the oxygen (O ₂ ) plasma and an amount of oxygen (O ₂ ) introduced into a chamber of the PECVD apparatus (not shown) (For example, 200 sccm to 400 sccm) and the magnetic field strength (for example, 150 mT to 250 mT) of the oxygen (O ₂ ) plasma, etc., by appropriately adjusting the amorphous silicon layer 116 by the oxygen plasma (SiO). It is preferable that the barrier film 125 of ₂ ) has a thickness of about 100 mW to 500 mW.

If the barrier film 125, the silicon oxide (SiO ₂₎ is to have a thickness less than 100Å may be a metal silicide is formed by diffusion crystallization, in the case to have a thickness greater than 500Å, since the silicon oxide (SiO ₂ Removal of the barrier layer 131 takes a relatively long time, so productivity per unit time is reduced. Therefore, the barrier layer 131 of the silicon oxide (SiO ₂ ) may be formed to have a thickness of about 100 GPa to 500 GPa.

Next, as illustrated in FIG. 3D, a metal material having excellent characteristics of absorbing a laser beam onto the barrier layer 131 of the silicon oxide (SiO ₂ ) formed by the oxygen (O ₂ ) plasma treatment and converting it into thermal energy is illustrated. For example, by depositing any one of chromium (Cr), chromium alloy, titanium (Ti), titanium alloy using a sputter device by the sputter device (photothermal conversion layer for even heat transfer to the pure amorphous silicon layer 116 during the crystallization process proceeds. Form 190.

In this case, the light-to-heat conversion layer 190 is preferably formed to have a thickness of about 800 ~ 1200Å. When the light-to-heat conversion layer 190 has a thickness smaller than 800Å, the light-to-heat conversion ability is lowered when the laser beam is irradiated using the laser device (195 of FIG. 3E). This is because the capacity is degraded and the cost is increased because a laser beam having a larger energy density per unit area must be irradiated.

 3E, the pure amorphous silicon layer 116 of FIG. 3D is irradiated with the laser beam LB using the laser device 195 to the substrate 101 on which the photothermal conversion layer 190 is formed. ) Is crystallized to form a fine crystallized polysilicon layer 118.

In this case, the laser device 195 is preferably a DPOD (Diode Pumped Solid State) laser device, characterized in that a solid material is used as a medium source for generating the laser beam LB.

Thus, in the embodiment of the present invention, using the DPSS laser device 195 using a solid as a medium source, the DPSS laser device 195 using a solid as a medium source is the energy density per unit area of the laser beam (LB) generated This is because the error of is much smaller than the laser beam LB generated through the excimer laser apparatus using gas as a medium source, and thus the energy density difference of each position of the irradiated laser beam LB hardly occurs during the crystallization process. In this case, the laser beam LB generated by using the solid medium has a wavelength of 700 nm to 1300 nm, and is irradiated to the photothermal conversion layer 190 so that the silicon oxide (SiO ₂ ) positioned below the photothermal conversion layer 190. The thermal energy is uniformly transferred to the pure amorphous silicon layer (116 of FIG. 3D) by the barrier film 125 of FIG. 3) to finely crystallize the pure amorphous silicon layer (116 of FIG. 3D) and finally to the polysilicon layer 118. ) Is achieved.

Next, as shown in FIG. 3F, the substrate 101 on which the polysilicon layer 118 is formed is etched by a laser beam (LB in FIG. 3E) to etch the photothermal conversion layer (190 in FIG. 3E). The barrier layer 125 of silicon oxide (SiO ₂ ) is exposed by removing the oxide.

Next, as shown in FIG. 3G, the barrier layer (125 of FIG. 3F) of the silicon oxide (SiO ₂ ) exposed by removing the photothermal conversion layer (190 of FIG. 3E) is removed using BOE (Buffered Oxide Etchant). It removes by carrying out a primary washing process. In this case, the polysilicon layer 118 is not affected by the first cleaning using the BOE, and the polysilicon layer 118 is clean by removing the contaminants and the like by the first cleaning using the BOE. It has a surface state.

Next, as shown in FIG. 3H, a mask is applied to the polysilicon layer (118 in FIG. 3G) exposed by removing the barrier film (125 in FIG. 3F) of silicon oxide (SiO ₂ ) by the BOE primary cleaning. By performing the process and patterning, an active layer 120 of island-type polysilicon overlapping with the gate electrode 108 is formed corresponding to the central portion of the gate electrode 108 of the device region TrA.

In the meantime, the gate insulating layer 112 is exposed to the outside of the active layer 120 of the polysilicon.

Next, as shown in FIG. 3I, the impurity amorphous silicon layer 128 is formed by depositing the impurity amorphous silicon on the entire surface of the substrate 101 over the active layer 120 of the polysilicon.

Meanwhile, before the impurity amorphous silicon layer 128 is formed on the active layer 120 of polysilicon, secondary cleaning using BOE may be further performed. The reason for performing the secondary cleaning using BOE is that the polysilicon active layer 120 is formed during the process of forming the polysilicon layer 118 of FIG. 3G to form the active layer 120 of the polysilicon. A natural oxide film (not shown) may be formed on a surface of the active layer 120 of polysilicon by exposure to air, and the natural oxide film (not shown) is an ohmic provided on the active layer 120 of polysilicon and an upper portion thereof. The contact layer (130 of FIG. 3n) acts as a factor to decrease the ohmic characteristics, and may also act as a factor to reduce the characteristics of the thin film transistor (Tr of FIG. 3n), and thus to remove it.

Next, as illustrated in FIG. 3J, the second metal material molybdenum (Mo), molybdenum (MoTi), aluminum (Al), and aluminum alloy (AlNd) are disposed on the entire surface of the substrate 101 on the impurity amorphous silicon layer 128. ), The second metal layer 132 is formed by depositing any one of copper (Cu) and copper alloy.

Next, as shown in FIG. 3K, a photoresist layer (not shown) is formed on the second metal layer (132 of FIG. 3J), and the photoresist layer is exposed and developed to correspond to the device region TrA. The first photoresist pattern 181 having a shape spaced apart from each other on the upper part of the layer 120 is formed, and at the same time, the boundary of the pixel area P is more precisely corresponding to the portion where the data line 134 should be formed. The second photoresist pattern 182 is formed.

Subsequently, the gate wiring (not shown) is formed on the impurity amorphous silicon layer 128 by removing the second metal layer 132 of FIG. 3J exposed to the outside of the first and second photoresist patterns 181 and 182. And a data electrode 134 defining the pixel region P to cross each other, and at the same time, a source electrode connected to the data line 134 on the impurity amorphous silicon layer 128 in the device region TrA. 136 and a drain electrode 138 spaced apart from each other are formed.

Next, as shown in FIG. 3L, the impurity amorphous silicon layer (128 of FIG. 3K) exposed to the outside of the data line 134 and the source and drain electrodes 136 and 138 is removed by dry etching. An ohmic contact layer 129 of impurity amorphous silicon is formed under the source and drain electrodes 136 and 138 spaced apart from each other. In this case, in the device region TrA, the active layer 120 of the polysilicon is exposed between the source and drain electrodes 136 and 138.

On the other hand, a dummy pattern 130 made of the impurity amorphous silicon material is formed under the data line 134 due to the manufacturing process characteristic as described above. In this case, the active layer 120 of the polysilicon and the ohmic contact layer 129 spaced apart from each other form a semiconductor layer 131, the gate electrode 108 sequentially stacked on the device region TrA, and a gate. The semiconductor layer 131 including the insulating layer 112, the ohmic contact layer 129 spaced apart from the active layer 120 of polysilicon, and the source and drain electrodes 136 and 138 spaced apart from each other are thin films that are switching elements. A transistor Tr is formed.

Next, as shown in FIG. 3M, the first and second photoresist patterns (181 and 182 of FIG. 3K) remaining on the source and drain electrodes 136 and 138 and the data line 134 are stripped. (strip) to remove.

Next, an organic insulating material, such as benzocyclobutene, is disposed on the source and drain electrodes 136 and 138 and the data line 134 exposed by removing the first and second photoresist patterns 181 and 182 of FIG. 3K. The protective layer 140 is formed by coating (BCB) or photo acryl or depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). In the drawing, the protective layer 140 is formed using an inorganic insulating material as an example.

Thereafter, the protective layer 140 is patterned by a mask process to form a drain contact hole 142 exposing the drain electrode 138.

Next, as shown in FIG. 3N, a transparent conductive material such as a metal material indium tin oxide (ITO) or indium zinc oxide (IZO) is disposed on the protective layer 140 having the drain contact hole 142. Is deposited on the entire surface to form a transparent conductive material layer (not shown), and patterned by a mask process to contact the drain electrode 138 through the drain contact hole 142 for each pixel region P. By forming the pixel electrode 150, the array substrate 101 according to the exemplary embodiment of the present invention is completed.

As described above, the completed array substrate 101 includes a bottom gate type thin film transistor having a semiconductor layer 131 including an active layer 120 made of polysilicon and an ohmic contact layer 129 made of impurity amorphous silicon. Tr) is characterized by not requiring a doping process. Therefore, the mask process is simplified compared to a method of manufacturing an array substrate having a thin film transistor using polysilicon as a semiconductor layer.

In addition, the polysilicon as the active layer 120 has the advantage that the mobility characteristics are significantly improved compared to the conventional array substrate having the amorphous silicon as the active layer.

In addition, the metal silicide formed by the diffusion of the metal material into the amorphous silicon layer during the crystallization process is prevented, thereby reducing the driving failure of the thin film transistor (Tr).

1 is a cross-sectional view of one pixel area including a portion where a thin film transistor is formed in a conventional array substrate.

FIG. 2 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer.

3A to 3N are cross-sectional views of manufacturing steps of one pixel region of an array substrate including a thin film transistor having an active layer of polysilicon according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 108 gate electrode

110: gate insulating film 119: pure amorphous silicon layer

190: barrier film of silicon oxide (SiO ₂ )

193: chamber of PECVD apparatus

P: pixel area TrA: device area

Claims (8)

Forming a gate wiring extending in one direction on the substrate on which the pixel region is defined, and a gate electrode connected to the gate wiring; Sequentially forming a gate insulating film and a pure amorphous silicon layer on the entire surface of the substrate over the gate wiring and the gate electrode; Performing an oxygen (O ₂ ) plasma process to form a barrier film of silicon oxide (SiO ₂ ) on the surface of the pure amorphous silicon layer; Forming a photothermal conversion layer of a metal material on the barrier film of silicon oxide (SiO ₂ ); Microcrystalline crystallizing the pure amorphous silicon layer into a polysilicon layer by irradiating a laser beam to the photothermal conversion layer; Removing the photothermal conversion layer; Performing a first cleaning using a buffered oxide etchant (BOE) to remove the barrier layer of silicon oxide (SiO ₂ ); Patterning the polysilicon layer to form an active layer of polysilicon on the gate insulating film corresponding to the gate electrode; Forming a data line over the gate insulating layer to define the pixel region crossing the gate line, and a source and drain electrode spaced apart from each other over an active layer of polysilicon and an ohmic contact layer of impurity amorphous silicon; Forming a protective layer exposing the drain electrode over the source and drain electrodes and the data line; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer; Method of manufacturing an array substrate comprising a. The method of claim 1, And the gate insulating film has a single layer structure made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) or a double layer structure. The method of claim 2, The gate insulating film is formed using a plasma enhanced chemical vapor depdsition (PECVD) apparatus to form a thickness of 2000 ℃ to 4500 ℃ in a temperature atmosphere of 320 ℃ to 450 ℃. The method of claim 1, The silicon oxide (SiO ₂ ) barrier film manufacturing method of the array substrate, characterized in that formed to have a thickness of about 100 ~ 500Å. The method of claim 1, Forming a data line over the gate insulating layer to define the pixel region crossing the gate line, and a source and drain electrode spaced apart from each other over an active layer of polysilicon; and an ohmic contact layer of impurity amorphous silicon. Sequentially forming an impurity amorphous silicon layer and a metal layer on the entire surface of the substrate over the active layer of polysilicon; Forming the data line and the source and drain electrodes spaced apart from each other in the device region on the impurity amorphous silicon layer by patterning the metal layer;  Forming an ohmic contact layer of impurity amorphous silicon spaced apart from each other under the source and drain electrodes by removing the pure amorphous silicon layer exposed outside the data line and the source and drain electrodes. Method of manufacturing an array substrate comprising a. The method of claim 5, Before forming the impurity amorphous silicon layer over the active layer of polysilicon, performing a second cleaning using a buffered oxide etchant (BOE) on the substrate on which the active layer of polysilicon is formed. .  The method of claim 1, The laser beam is a method of manufacturing an array substrate, characterized in that the laser beam generated by a DPSS (Diode Pumped Solid State) laser device using a solid medium.  The method of claim 1, The photo-thermal conversion layer is an array characterized in that it is formed to have a thickness of 800 하여 to 1200 중 by depositing any one of chromium (Cr), chromium alloy, titanium (Ti), titanium alloy, which is a metal material having excellent ability to convert light into thermal energy Method of manufacturing a substrate.

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