KR101588448B1 - Array substrate including thin film transistor of polycrystalline silicon and method of fabricating the same - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate wiring extending in one direction on a substrate; and a gate electrode connected to the gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern sequentially on the gate insulating film in correspondence with the gate electrode; A data line crossing over the gate insulating film and defining a pixel region over the gate insulating film; and forming source and drain electrodes spaced apart from each other on the impurity amorphous silicon pattern; Forming an ohmic contact layer spaced apart from each other by removing the impurity amorphous silicon pattern exposed between the source and drain electrodes; A pure amorphous silicon pattern of a portion exposed between the source and drain electrodes is irradiated with a laser beam using a laser device having a solid medium, A portion of the source and drain electrodes overlapping the source and drain electrodes and the portion corresponding to each of the first widths are made of polysilicon by crystallizing the amorphous silicon pattern, Forming an active layer of amorphous silicon; Forming a protective layer having source and drain electrodes and a contact hole exposing the drain electrode over a data line; And forming a pixel electrode in the pixel region in contact with the drain electrode through the contact hole over the protective layer.

Array substrate, polysilicon, active layer, DPSS laser, mobility, splitter

Description

[0001] The present invention relates to an array substrate including a thin film transistor using polysilicon and a method of fabricating the same,

The present invention relates to an array substrate, and more particularly, to an array substrate including a thin film transistor having excellent mobility characteristics and having polysilicon as a part of an active layer and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix type liquid crystal display device including an array substrate having thin film transistors, which are switching elements capable of controlling the on and off voltages of respective pixels, It has the most attention because it has excellent implementation ability.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In the liquid crystal display device and the organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is provided in order to commonly control ON / OFF of each pixel region.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

A sectional structure of a thin film transistor serving as such a switching element will be described with reference to FIG.

1 is a cross-sectional view of one pixel region including a portion where a thin film transistor is formed in the above-described conventional array substrate.

A gate electrode 10 is formed on a transparent insulating substrate 9 in correspondence with a switching region TrA in the pixel region P. A gate insulating film 18 is formed on the entire surface of the gate electrode 10 . An active layer 20a made of pure amorphous silicon and an ohmic contact layer 20b made of amorphous silicon containing impurities are formed on the gate insulating film 18 so as to correspond to the gate electrode 10, The semiconductor layer 20 is formed.

The ohmic contact layer 20b which is spaced from the active layer 20a and exposes the lower active layer 20a is in contact with the ohmic contact layer 20b to be spaced apart from each other, The source electrode 26 and the drain electrode 28 are formed to expose the layer 20a.

The source and drain electrodes 26 and 28 spaced apart from the gate electrode 10, the gate insulating film 18 and the semiconductor layer 20 sequentially stacked on the substrate 9 constitute a thin film transistor Tr.

A protective layer 36 having a drain contact hole 30 exposing a part of the drain electrode 28 is formed on the entire surface of the thin film transistor Tr having such a structure. A pixel electrode 38 is formed for each pixel region P to be in contact with the drain electrode 28 through the drain contact hole 30. A gate wiring (not shown) connected to the gate electrode 10 is formed on the same layer on which the gate electrode 10 is formed and the source electrode 26 (not shown) is formed in the same layer in which the source and drain electrodes 26 and 28 are formed. (Not shown) is further formed, thereby forming the array substrate 9. [0158] As shown in FIG.

However, in the case of the thin film transistor generally constituted in the conventional array substrate, it can be seen that the active layer 20a uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, and stability becomes a problem when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s and it is difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process through ELA (Eximer Laser Annealing) has been proposed.

[0004] However, in the fabrication of an array substrate including a thin film transistor using polysilicon as a semiconductor layer through the crystallization process of ELA, a method of manufacturing the array substrate including the thin film transistor in the array substrate having the thin film transistor, , It is necessary to form an n + region 55b or a p + region (not shown) containing a high concentration of impurities, and these n + regions 55b or p + regions Doping process is required, and ion implantation equipment is additionally needed for such a doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment.

The array substrate 51 having the polysilicon as the semiconductor layer 55 has a structure in which the thin film transistor Tr formed thereon is composed of the pure polysilicon region 55a and the semiconductor layer 55 composed of the n + region 55b or the p + An interlayer insulating film 61 having first contact holes 63 and 64 exposing the n + region 55b or the p + region, a gate insulating film 58, a gate electrode 59, Source and drain electrodes 70 and 72 contacting and spaced apart from the n + region 55b or the p + region (not shown) through the first contact holes 63 and 64, A protective layer 75 having a drain contact hole 78 and a pixel electrode 82 in contact with the drain electrode 72. Therefore, since the lamination structure of the transistor (the transistor Tr in FIG. 1) in which amorphous silicon is used as the active layer (20a in FIG. 1) is complicated, complicated manufacturing steps are required to be performed, have.

Further, the laser device used in the crystallization process through ELA is an excimer laser device, which generates a laser beam having a wavelength of 308 nm by a gas medium. However, by using a gas as a source medium for generating a laser beam, a laser beam having an optimal power for melting amorphous silicon is generated. The substantially generated laser beam has a very large error range of its energy density, A large difference in energy density of the laser beam irradiated to each layer during the irradiation of the layer causes a problem of streaking unevenness due to the difference in the characteristics of the thin film transistor itself, thereby deteriorating the display quality.

Furthermore, in the case of an array substrate used in an organic electroluminescent device, unlike the voltage driving of a liquid crystal display device, it is driven by a current flowing in a thin film transistor, in particular, a driving thin film transistor. Therefore, in particular, a driving thin film transistor, which is an element for driving an organic electroluminescent device, is required to have stability. To satisfy this requirement, a thin film transistor is manufactured using polysilicon as a semiconductor layer, A large error occurs in the uniformity of the thin film transistor.

Therefore, it is an object of the present invention to provide a thin film transistor in which amorphous silicon is used as an active layer, which is simple in manufacturing process and excellent in uniformity at the time of manufacture, though its mobility and device stability are dominant. An array substrate including a new type of thin film transistor having the advantages of a thin film transistor having a semiconductor layer of polysilicon is required.

In order to solve the above problems, in the present invention, amorphous silicon is crystallized using a stable laser device because the energy density error range of the laser beam is small, without introducing additional ion implantation equipment, And an object of the present invention is to provide a method of manufacturing an array substrate having a simple thin film transistor.

Another object of the present invention is to simplify the manufacturing process by omitting the ion doping step in comparison with a conventional method of manufacturing an array substrate having a thin film transistor made of polysilicon as a semiconductor layer.

It is another object to reduce the manufacturing cost by not introducing additional ion implant equipment for ion doping.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, including: forming a gate wiring extending in one direction on a substrate; and a gate electrode connected to the gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern sequentially on the gate insulating film in correspondence with the gate electrode; A data line crossing over the gate insulating film and defining a pixel region over the gate insulating film; and forming source and drain electrodes spaced apart from each other on the impurity amorphous silicon pattern; Forming an ohmic contact layer spaced apart from each other by removing the impurity amorphous silicon pattern exposed between the source and drain electrodes; A pure amorphous silicon pattern of a portion exposed between the source and drain electrodes is irradiated with a laser beam using a laser device having a solid medium, A portion of the source and drain electrodes overlapping the source and drain electrodes and the portion corresponding to each of the first widths are made of polysilicon by crystallizing the amorphous silicon pattern, Forming an active layer of amorphous silicon; Forming a protective layer having source and drain electrodes and a contact hole exposing the drain electrode over a data line; And forming pixel electrodes in the pixel region that are in contact with the drain electrode through the contact hole over the protective layer.

The laser device having the solid medium includes a diode for supplying light energy in the form of infrared rays, a YAG rod for generating a laser beam by collecting light energy emitted from the diode, a laser beam A second-harmonic generation (SHG) optical system in which the wavelength of a part of the laser beam is different from the wavelength of the laser beam, (Dielectric Pumped Solid State) laser device including a WSM (Wavelength Separation Mirror). In this case, the laser beam is generated by applying a power of 15.4 W to 16.2 W to the DPSS laser device Feature.

Further, the irradiation of the laser beam using the laser device having the solid medium is carried out through the splitter, so that the splitter separates the laser beam into the first laser beam and the second laser beam, The beam is irradiated to the pure amorphous silicon pattern corresponding to the respective first widths shielded by the source and drain electrodes by being irradiated with symmetrical first and second angles corresponding to a normal line perpendicular to the substrate surface .

In this case, the splitter has a triangular or quadrangular cross-sectional shape. When the cross-sectional shape of the splitter is triangular, the laser beam incident on the splitter is in a direction parallel to the normal line, Is characterized in that the laser beam has the first angle or the second angle.

The first and second angles can change the size of the splitter by swinging the splitter clockwise or counterclockwise.

In addition, the laser beam using the laser device having the solid medium may be irradiated on the substrate surface so as to have a first angle with a normal line perpendicular to the substrate surface to proceed with the first scan, And the second scan is performed in a state in which the laser beam is irradiated so as to have a second angle that is an angle of 1 to the normal line.

It is preferable to form the active layer partially made of polysilicon and anneal the substrate for 30 minutes to 120 minutes at a temperature of 280 ° C to 350 ° C before forming the protective layer, After the annealing, the substrate is placed in a vacuum chamber having an internal pressure of 10 mTorr to 100 mTorr, hydrogen is supplied at a flow rate of 1000 sccm to 2000 sccm, and hydrogen plasma treatment is performed.

At this time, the hydrogen plasma treatment preferably proceeds for 2 minutes to 4 minutes 30 seconds.

In addition, the step of forming the impurity and the pure amorphous silicon pattern, and the step of forming the data line and the source and drain electrodes are simultaneously performed through one mask process.

An array substrate according to the present invention includes: a substrate; A gate wiring extending in one direction on the substrate; a gate electrode connected to the gate wiring; A gate insulating film formed to cover the gate wiring and the gate electrode; A data line formed on the gate insulating film and defining a pixel region intersecting the gate line; An active layer corresponding to the gate electrode over the gate insulating film in the pixel region and consisting of a first region of polysilicon and a second region of pure amorphous silicon on both sides of the first region; The second region being located on both sides of the first region and the first region corresponding to the first width of the first region in contact with the second region, An ohmic contact layer of silicon; Source and drain electrodes formed to expose the first region over the ohmic contact layer; A protective layer formed on the source and drain electrodes and the data line, the protective layer having a contact hole exposing the drain electrode; And a pixel electrode formed in the pixel region in contact with the drain electrode through the contact hole over the protective layer.

At this time, the first width is 1 탆 to 2 탆.

The array substrate for a liquid crystal display according to the present invention is crystallized into a polysilicon layer by a DPSS (Diode Pumped Solid State) solid-state laser crystallization process of the amorphous silicon layer and constitutes a thin film transistor as a semiconductor layer, There is an effect of improving the mobility characteristics by tens to hundreds of times.

In addition, stable thin film transistor characteristics can be achieved without doping through ion implantation equipment, thereby reducing manufacturing costs through inhibiting investment in new equipment.

By using the DPSS solid state laser device in the crystallization process, the error range of the energy density by the irradiation position of the laser beam is much smaller than the ELA crystallization process using the excimer laser device using the gas as a source thereof, There is an effect of preventing occurrence of scan unevenness, and it is advantageous that uniform thin film transistor characteristics can be ensured by relatively uniform crystallization.

In addition, when a crystallization process using a DPSS solid state laser device is performed, a laser beam is irradiated by using a splitter or at a predetermined angle to form not only an active layer exposed between the source and drain electrodes but also an active layer below the ohmic contact layer The active layer corresponding to the entire region where the channel is formed is made of polysilicon by causing the crystallization to proceed to a part of the active layer positioned thereon, thereby further improving the mobility characteristics.

In addition, compared with a general thin film transistor using polysilicon, the stacked structure of the thin film transistor can be manufactured through a simple and simple manufacturing process like a thin film transistor using an amorphous silicon layer, thereby improving productivity.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3A to 3I are cross-sectional views illustrating a pixel region including a thin film transistor having an active layer including a first region of polysilicon and a second region of amorphous silicon in an array substrate according to an embodiment of the present invention. Here, for convenience of description, a region where the thin film transistor is formed is defined as a switching region, and FIG. 3E showing the most characteristic step in the present invention is an enlarged view of the switching region.

3A, a first metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy and chromium (Cr) is coated on a transparent substrate 101 To form a first metal layer (not shown). Thereafter, the first metal layer (not shown) is patterned by performing a mask process including a series of unit processes such as application of a photoresist, exposure using a mask, development of a photoresist, etching, and stripping of a photoresist A gate wiring (not shown) extending in one direction is formed and a gate electrode 105 connected to the gate wiring (not shown) is formed in the switching region TrA.

At this time, the first metal layer (not shown) is formed by continuously depositing two or more different metal materials among the first metal materials to form a double layer or more. Thus, a gate wiring (not shown) An electrode (not shown) may be formed. For convenience, gate wiring (not shown) and gate electrode 105 having a single layer structure are shown.

Next, as shown in Figure 3b, the gate wiring (not shown) and a gate electrode 105 is formed, the substrate 101 over the entire surface of the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx of Is deposited on the gate insulating film 108 to form the gate insulating film 108. Subsequently, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed by successively depositing pure amorphous silicon and impurity amorphous silicon on the gate insulating layer 108, A pure amorphous silicon pattern 120 and an impurity amorphous silicon pattern 123 are formed on the pure amorphous silicon pattern 120 so as to overlap with the gate electrode 105 in the switching region TrA.

Next, as shown in FIG. 3C, a second metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, chromium (Cr), or the like is formed on the impurity- Is deposited to form a second metal layer (not shown). Thereafter, a masking process is performed on the second metal layer (not shown) and patterned to form a data line 130 which intersects the gate line (not shown) and defines the pixel region P. At the same time, source and drain electrodes 133 and 136 are formed in the switching region TrA at predetermined intervals on the impurity amorphous silicon pattern 123. At this time, the source electrode 133 is connected to the data line 130.

Although it is shown in the embodiment of the present invention that the formation of the pure and impurity amorphous silicon patterns 120 and 123 and the source and drain electrodes 133 and 136 is formed through two masking processes in total, For example, through a single mask process.

FIGS. 4A to 4D are cross-sectional views illustrating steps of fabricating an array substrate according to a modification of the present invention. FIGS. 4A to 4D are cross-sectional views illustrating steps of forming a pure and impurity amorphous silicon pattern and a source and drain electrode through a single mask process. At this time, the same components as those shown in FIGS. 3A to 3C are denoted by reference numerals by adding 100 to them.

First, as shown in FIG. 4A, pure water and impurity amorphous silicon are continuously deposited on the gate insulating film 208 formed over the gate electrode (not shown) and the gate electrode 205 to form a pure water and impurity amorphous silicon layer A second metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, and chromium (Cr) is formed on the impurity amorphous silicon layer 219, A second metal layer 228 is formed. Thereafter, a photoresist is applied on the second metal layer 228 to form a photoresist layer (not shown).

Next, a photoresist layer (not shown) is formed in a light transmission region, a blocking region, and a slit shape, or may further include a plurality of coating layers to control the amount of light passing therethrough, Exposure is performed using an exposure mask (not shown) composed of a transflective region larger than the blocking region. Thereafter, by developing the exposed photoresist layer (not shown), a first photoresist pattern having a first thickness corresponding to a portion where a data line is to be formed on the second metal layer 228 and a portion where the source and drain electrodes are to be formed, A second photoresist pattern 291b having a second thickness smaller than the first thickness is formed corresponding to a portion to be a spacing region between the source and drain electrodes. At this time, the photoresist layer (not shown) is removed to expose the second metal layer 228 corresponding to the other regions.

Next, as shown in FIG. 4B, the second metal layer (228 in FIG. 4A) exposed to the outside of the first and second photoresist patterns 291a and 291b is etched and removed to form a data line 230 And a source / drain pattern 229 connected to the data line 230 is formed in the switching region TrA. Thereafter, the impurity amorphous silicon layer (219 in FIG. 4A) and the pure amorphous silicon layer (217 in FIG. 4A) located below the second metal layer (228 in FIG. 4A) Pure and impurity amorphous silicon patterns 220 and 223 which are sequentially stacked under the source and drain patterns 229 are formed. At this time, unlike the above-described embodiment, a semiconductor pattern with a double-layer structure made of a first pattern 221 of pure impurity amorphous silicon and a second pattern 222 of impurity amorphous silicon is formed under the data line 230, (225) is formed.

Next, as shown in FIG. 4C, ashing is performed on the substrate 201 on which the source drain pattern 229 and the data line 230 are formed to form a second photoresist pattern having the second thickness (291b in FIG. 4B) is removed to expose the central portion of the source / drain pattern 229 in the switching region TrA. At this time, ashing progresses, the first photoresist pattern 291a is reduced in thickness but remains on the substrate 101. [

Next, as shown in FIG. 4D, the source and drain electrodes 233 and 236 spaced apart from each other are formed by removing the source drain pattern (229 in FIG. 4C) exposed between the first photoresist patterns 291a It is possible.

In this case, the difference between the pure water and the impurity amorphous silicon pattern and the array substrate on which the source and drain electrodes are formed through two mask processes is that the semiconductor pattern 225 of the double layer structure is formed under the data line 230, And the ends of the pure and impurity amorphous silicon patterns 220 and 223 located at one end and the lower part of the drain electrodes 233 and 236 coincide with each other. The semiconductor pattern is not formed under the data line 130 and the ends of the source and drain electrodes 133 and 136 are not formed in the lower part of the data line 130 in the embodiment where the pure and impurity amorphous silicon patterns and the source and drain electrodes are formed through two mask processes The amorphous silicon pattern 120 and the impurity amorphous silicon pattern 120 are located outside the ends of the pure and impurity amorphous silicon patterns 120 and 123 located at the lower portion thereof.

The subsequent steps in the fabrication of the array substrate according to the modified example proceed in the same manner as the embodiment, so that the embodiments will be mainly described.

The source and drain electrodes 133 and 136 are formed by removing the impurity amorphous silicon pattern (123 in FIG. 3C) exposed through the source and drain electrodes 133 and 136 by dry etching, The ohmic contact layer 126 of the impurity amorphous silicon is formed in such a manner that the pure amorphous silicon patterns 120 (120a, 120b, and 120c) are exposed downward and separated from each other.

3E, the substrate 101 on which the ohmic contact layer 126 of the impurity amorphous silicon layer is formed under the source and drain electrodes 133 and 136 is subjected to a diode pumped solid state (DPSS) laser device (120a in FIG. 3D) exposed between the source and drain electrodes 133 and 136 and the source and drain electrodes 133 and 136 (FIG. 3D) facing each other by irradiating the laser beam LB using the laser beam LB A pure amorphous silicon pattern 120b corresponding to a predetermined width w1 at the end of the first amorphous silicon layer 120b is crystallized so that a first region 127a partially crystallized into polysilicon is formed.

In this case, the DPSS laser device 180 uses a solid state material as a medium source for generating the laser beam LB. In a laser device using such a solid as a source, an error in the energy density per unit area of the generated laser beam LB is far smaller than the laser beam generated through the excimer laser device using the gas as a medium source, LB) is hardly generated due to the difference in energy density of the respective regions.

The configuration of the DPSS laser device used for manufacturing the array substrate according to the embodiment of the present invention will be briefly described.

5 is a schematic configuration diagram of a DPSS laser device used in the present invention.

As shown, the DPSS laser device 180 includes a diode 182 for supplying light energy in the form of infrared rays, and a YAG (Yttrium Aluminum Oxide Semiconductor) device for collecting light energy from the diode 182 to generate a substantial laser beam LB An aluminum garnet rod 184, a second-harmonic generation (SHG) optical system 186 and a WSM (Wavelength Separation Mirror) 188.

At this time, the diode 182 serves to supply light energy to the YAG rod 184 in the form of infrared rays, and the YAG rod 184 is connected to the YAG rod 184 through the light energy incident therein. Atoms are in a high energy state and then return to their original state to generate a laser beam (LB). The second harmonic generation optical system 186 doubles the wavelength of the laser beam LB emitted from the YAG rod 184 and is incident on the YAG rod 184 from the diode 182 The laser beam LB emerging therefrom still has a wavelength of 1064 nm but another part of the laser beam LB having a wavelength of 1064 nm still passes through the second harmonic generation optical system 186 by its action, A laser beam LB having a reduced wavelength of 532 nm is produced.

The laser beam LB having two wavelength bands passing through the second harmonic generation optical system 186 passes through a wavelength separation mirror 188 to form a laser beam LB having a wavelength of 532 nm and an infrared ray (IR) having a wavelength of 1064 nm. . At this time, in the present invention, the laser beam LB having a wavelength of 532 nm separated through the wavelength separation mirror 188 is used for crystallization.

In the case of the DPSS laser apparatus 180 having the above-described configuration, the diode 182 used as an energy source and the YAG rod 184 used as a medium for generating the laser beam LB usually have a lifetime of 15-18 hours , Which is about two to three times longer than a laser device (not shown) using a gas or a liquid as a medium for generating a laser beam.

The DPSS laser device 180 is characterized in that a diode 182 is used as an energy source and a YAG rod 184 which is solid as a laser beam (LB) generating medium is used. The DPSS laser device 180 includes a gas or a liquid as a laser beam generating medium The density of the laser beam finally irradiated onto the substrate is uniform as compared with the laser device (not shown) used, and the uniformity of the crystallization is improved.

Hereinafter, a method of manufacturing an array substrate according to the present invention including crystallization of a pure amorphous silicon pattern using the DPSS laser device 180 having the above-described configuration will be described.

Referring again to FIG. 3E, the laser beam LB is irradiated to the front surface of the substrate 101 on which the source and drain electrodes 133 and 136 are formed through the DPSS laser device 180 having the above-described configuration, do. At this time, the power of the DPSS laser device 180 is preferably in the range of 15.4W to 16.2W. The crystallization of the pure amorphous silicon pattern (120a and 120b in FIG. 3d) is greatly influenced by the energy density of the laser beam LB, and when a power larger than the above-mentioned range is applied, The energy density is too high and the hydrogen in the pure amorphous silicon pattern (120 in FIG. 3D) suddenly escapes, and a large number of recessed parts appearing on the surface thereof are formed, so that the surface is not formed smoothly.

Therefore, in this case, the characteristics of the thin film transistor are deteriorated due to the deterioration of the interface characteristics with the protective layer to be formed later, and the characteristics of the thin film transistor are different for each pixel region.

6A to 6D are photographs showing the surface state of the crystallized portion when the laser beam is irradiated to the pure amorphous silicon pattern on the array substrate by the power of the DPSS laser device for the same time, respectively.

6A, 6B, and 6D show the crystallized surface photographs when the laser beam is irradiated with the powers of 15.4W and 16.2W, respectively, with the powers of 15.4W, 16.2W, When the beam is irradiated, it can be seen that the surface state is smoothly formed after crystallization.

However, when the laser beam is irradiated with a power of more than 16.2 W, for example, 18.4 W or 19.5 W, the surface of the laser beam is not smooth and appears to have a large amount of stains. I was able to find a partially recessed lumbar.

3E, when the laser beam LB is irradiated by the DPSS laser device 180 as the power of the above-described range, the laser beam LB is irradiated with the pure amorphous silicon pattern directly irradiated with the laser beam LB 120a and 120b are melted and gradually solidified to be crystallized, thereby being converted into a polysilicon layer.

In this embodiment of the present invention, irradiation of the laser beam LB through the DPSS laser 180 is performed by irradiating the laser beam LB through a splitter 181 The angle is changed so that the amorphous silicon pattern (120a in FIG. 3D) exposed between the source and drain electrodes 133 and 136 as well as the source and drain electrodes 133 and 136 (120b in FIG. 3D) corresponding to the predetermined width w1 of the first region 127a of the polysilicon layer to form the first region 127a of the polysilicon.

The splitter 181 is made of quartz or the like and serves to divide the incident laser beam LB into two laser beams LB1 and LB2 with a predetermined angle. The first and second laser beams LB1 and LB2 divided by the first and second laser beams LB1 and LB2 are symmetrical with respect to the normal line L with respect to the normal line L perpendicular to the surface of the substrate 101, And is irradiated onto the surface of the substrate 101.

In this case, although the splitter 181 is shown as a triangular prism (see FIG. 3E) having a triangular cross section in the drawing, the splitter 181 may be variously arranged in a cubic shape It can be deformed.

That is, in the drawing, the laser beam LB through the DPSS laser device 180 is perpendicularly incident on the surface of the substrate 101, so that the first and second laser beams LB1 and LB2 are incident on the amorphous silicon pattern (120b in FIG. 3D) corresponding to a predetermined width w1 of one of the source and drain electrodes 133 and 136 facing each other, 181 are triangular in cross section and their bottom faces the DPSS laser device 180 and their both sides face the source and drain electrodes 133, 136.

In this case, when the laser beam LB irradiated through the DPSS laser device 180 is not perpendicular to the surface of the substrate 101 but is incident at a predetermined angle with respect to the normal line, the splitter 181 The beam is reflected by the first laser beam LB1 passing through the splitter 181 without being reflected in the splitter 181 and the reflected laser beam LB1 The second laser beam LB2 having an angle of 90 degrees with respect to the second laser beam LB2.

In this way, the laser beam LB is irradiated in two directions with a predetermined angle with respect to the surface of the substrate 101 by using the splitter 181. That is, the source and drain electrodes 133 and 136, The first and second laser beams LB1 and LB2 are simultaneously incident on the amorphous silicon pattern (120b in FIG. 3D) of a predetermined width w1 located at the bottom.

As the two first and second laser beams LB1 and LB2 are scanned in one direction in a state where the two laser beams LB1 and LB2 are symmetrically incident on the substrate 101 at a predetermined angle through the splitter 180, An area on the substrate 101 that is pre-shrunk to the width of the first and second laser beams LB1 and LB2 by moving the laser device 180 or by moving the substrate 101 is scanned once with a laser beam LB scan The amorphous silicon pattern (120a in FIG. 3D) exposed to the space between the source and drain electrodes 133 and 136 by the irradiation differs from the amorphous silicon pattern corresponding to the predetermined width of one end of the source and drain electrodes 133 and 136 To be crystallized up to 120b in FIG. 3d to form the first region 127a of polysilicon.

At this time, the splitter 180 itself can rotate at a predetermined interval. By performing a swing operation to rotate the splitter 180 itself clockwise and counterclockwise at a predetermined interval, the splitter 180 The irradiation angle of the first and second laser beams LB1 and LB2 separated by the first and second laser beams LB1 and LB2 can be changed.

8A and 8B (a method of manufacturing an array substrate according to a modification of the present invention is shown as a modification, in which the active layer is crystallized by laser beam irradiation at a predetermined angle with respect to the substrate surface) The DPSS laser device 180 is irradiated with the laser beam LB so as to have the first angle? 1 with respect to the normal L of the surface of the substrate 101 without using the splitter, The DPSS laser device 180 is positioned so as to have a second angle -θ1 symmetrical to the first angle θ1 with respect to the normal line L, The crystallization process may be performed in a manner that the second scan is performed on the scanned area.

In this case, as in the case where the first and second laser beams LB1 and LB2 are irradiated through the splitter 181 as in the above embodiment, the exposed amorphous silicon (120a in FIG. 3D) corresponding to a predetermined width w1 of one end of the source and drain electrodes 133 and 136 facing the pattern (120a in FIG. 3D) 127a.

3E, the first and second laser beams LB are irradiated through the splitter 181 in the state where the source and drain electrodes 133 and 136 are formed. Therefore, in the embodiment of the present invention, An amorphous silicon pattern (not shown) located at a portion shielded by the source and drain electrodes 133 and 136 except for a portion corresponding to a predetermined width w1 of one end of each electrode among the portions where the source and drain electrodes 133 and 136 are formed, 3d is not exposed to the first and second laser beams, and thus is not crystallized but remains in a pure amorphous silicon state to form a second region 127b of pure amorphous silicon.

Therefore, in the case of the array substrate 101 according to the embodiment and the modification of the present invention, the semiconductor layer 128 is composed of the lower active layer 127 and the upper ohmic contact layer 126, The active layer 127 is formed to have a thickness of about 1 탆 to about 2 탆 at the center thereof, that is, a portion exposed between the source and drain electrodes 133 and 136 and one end of the source and drain electrodes 133 and 136 facing each other And a first region 127a made of polysilicon is formed by crystallization for a predetermined width. The source and drain electrodes 127a and 127b are formed on both sides of the first region 127a, except for the predetermined width w1 of about 1 mu m to 2 mu m, 133, and 136 are formed as a second region 127b made of pure amorphous silicon.

At this time, since the active layer 127 can be formed in the first region 127a made of polysilicon, the entire region of the active layer 127, which serves as a channel of holes or electrons, may be formed of only pure amorphous silicon, (20a in Fig. 1).

The channel forming region in the active layer 127 is formed by a portion corresponding to the spacing region of the source and drain electrodes 133 and 136 and a portion corresponding to the ohmic contact layer 126 below the source electrode 133, The ohmic contact layer 126 under the drain electrode 136 and the active layer 127 corresponding to the ohmic contact layer 126. In the case of the array substrate 101 according to the embodiment and the modification of the present invention, The first region 127a made of polysilicon is formed in correspondence with the first region 127a, so that the channel region can be formed in the first region made of polysilicon.

On the other hand, the gate electrode 105, the gate insulating film 108, and the active layer 127 having the first and second regions 127a and 127b are formed in each switching region TrA by the process steps up to the above- The semiconductor layer 128 composed of the ohmic contact layer 126 and the source and drain electrodes 133 and 136 is formed.

Next, as shown in FIG. 3F, an active layer (first region 127a) having a first region 127a partially crystallized by irradiating a laser beam (LB in FIG. 3E) using a DPSS laser apparatus 127 is annealed by heat treatment for a predetermined time. At this time, the annealing of the substrate 101 is preferably performed through an oven or a firing apparatus 195 at a temperature of 280 ° C to 350 ° C for 30 minutes to 120 minutes.

The reason why the annealing process is performed is that since the active layer 127 does not have a stable molecular state in the first region 127a crystallized into polysilicon by the progress of the crystallization process, And further to improve the degree of crystallization.

3G, the annealed substrate 101 is placed in a vacuum chamber 197 and hydrogen (H ₂ ) plasma is applied to the surface of the substrate 101 for a suitable time H ₂ ) plasma treatment is performed. At this time, hydrogen (H ₂ ) is supplied to the vacuum chamber 197 at a flow rate of about 1000 sccm to 2000 sccm, and the pressure in the chamber 197 is preferably 10 mTorr to 100 mTorr. In addition, it is preferable that the above-mentioned hydrogen (H ₂ ) plasma treatment is performed for 2 minutes to 4 minutes 30 seconds.

On the other hand, the reason why hydrogen (H ₂ ) plasma treatment is performed in the above-mentioned environment is that hydrogen contained in the pure amorphous silicon pattern escapes during the crystallization process by laser beam irradiation to compensate for the hydrogen . The pure amorphous silicon layer is formed by plasma enhanced chemical vapor deposition (PECVD) in a mixed gas atmosphere of SiH ₄ / H ₂ , and a silicon atom is formed in a random network form. Silicon (Si) and silicon (Si) bond is not formed, and this portion forms a dangling bond. This dangling bond is inevitably generated when a pure amorphous silicon layer is formed through the above-described chemical vapor deposition. When hydrogen is bonded instead of silicon in a portion where silicon (Si) and silicon (Si) are not bonded Dangling bonds can be compensated.

However, in the course of the crystallization process, the dehydrogenation of the pure amorphous silicon layer progresses inevitably, and the number of hydrogen atoms therein is drastically reduced, so that the number of hydrogen atoms to be combined with silicon becomes insufficient, and many dangling bonds are generated. The hydrogen plasma process is carried out in order to suppress the increase of the dangling bonds due to the dehydrogenation caused by the dehydrogenation.

By injecting hydrogen into the first region 127a of the polysilicon through the hydrogenation plasma process to reduce the dangling bonds, the mobility characteristics and the uniformity of the thin film transistor Tr can be improved.

Next, as shown in FIG. 3H, an inorganic insulating material such as SiO 2 (SiO 2) is deposited on the source and drain electrodes 133 and 136 and the data line 130 of the substrate 101 subjected to the hydrogen plasma process, ₂ ) or silicon nitride (SiNx), or by applying an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

Thereafter, the mask layer is removed by removing the protective layer 140 corresponding to a part of the drain electrode 136, thereby forming the drain contact hole 145 exposing the drain electrode 136.

Next, as shown in FIG. 3I, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the passivation layer 140 having the drain contact hole 145 (Not shown) is formed on the entire surface of the substrate 110. The masking process is then performed to pattern the pixel electrode 150 through the drain contact hole 145 to form the pixel electrode 150, which contacts the drain electrode 136, The array substrate 101 according to the embodiment of the present invention can be completed.

1 is a cross-sectional view of one pixel region including a portion where a thin film transistor is formed in a conventional array substrate;

FIG. 2 is a sectional view of one pixel region including the thin film transistor in an array substrate including a conventional thin film transistor having a semiconductor layer of polysilicon. FIG.

FIGS. 3A through 3I are cross-sectional process views of a pixel region including a thin film transistor having an active layer made of a first region of polysilicon and a second region of amorphous silicon in an array substrate according to an embodiment of the present invention.

FIGS. 4A to 4D are cross-sectional views showing steps of manufacturing an array substrate according to a modification of the present invention, and showing cross-sectional views illustrating steps of forming a pure and impurity amorphous silicon pattern and a source and drain electrodes through a single mask process.

5 is a schematic configuration diagram of a DPSS laser device used in the present invention.

6A to 6D are photographs showing the surface states of the crystallized portions when the laser beam is irradiated to the pure amorphous silicon pattern on the array substrate by the power of the DPSS laser device for the same time, respectively.

FIG. 7 illustrates a method of manufacturing an array substrate according to a modification of the present invention, in which an active layer is crystallized by laser beam irradiation using a square-shaped splitter. FIG.

FIGS. 8A and 8B illustrate a method of manufacturing an array substrate according to a modification of the present invention, in which the active layer is crystallized by laser beam irradiation at a predetermined angle with respect to a substrate surface. FIG.

Description of the Related Art

101: substrate 105: gate electrode

108: gate insulating film 126: ohmic contact layer

127: active layer 127a: first region (of polysilicon)

127b: a second region (of pure amorphous silicon)

128: semiconductor layer 130: data wiring

133: source electrode 136: drain electrode

180: DPSS laser device 181: Splitter

LB: laser beam LB1, LB2: first and second laser beams

P: pixel region Tr: thin film transistor

TrA: switching area

Claims (14)

A gate wiring extending in one direction on a substrate; and a gate electrode connected to the gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern sequentially on the gate insulating film in correspondence with the gate electrode; A data line crossing over the gate insulating film and defining a pixel region over the gate insulating film; and forming source and drain electrodes spaced apart from each other on the impurity amorphous silicon pattern; Forming an ohmic contact layer spaced apart from each other by removing the impurity amorphous silicon pattern exposed between the source and drain electrodes; A pure amorphous silicon pattern of a portion exposed between the source and drain electrodes is irradiated with a laser beam using a laser device having a solid medium, A portion of the source and drain electrodes overlapping the source and drain electrodes and the portion corresponding to each of the first widths are made of polysilicon by crystallizing the amorphous silicon pattern, Forming an active layer of amorphous silicon; Forming a protective layer having source and drain electrodes and a contact hole exposing the drain electrode over a data line; Forming a pixel electrode in the pixel region that contacts the drain electrode through the contact hole over the protective layer; Wherein the substrate is a substrate. The method according to claim 1, The laser device having the solid medium includes a diode for supplying light energy in the form of infrared rays, a YAG rod for generating a laser beam by collecting light energy emitted from the diode, and a part of a laser beam A second-harmonic generation (SHG) optical system for making the wavelength of the laser beam a half of the wavelength of the laser beam, and a wavelength-division mirror for separating the laser beams having different wavelength values from each other, (DPM) laser device including a WSM (Wavelength Separation Mirror).  3. The method of claim 2, Wherein the laser beam is generated by applying a power of 15.4 W to 16.2 W to the DPSS laser device.  The method according to claim 1, The irradiation of the laser beam using the laser device having the solid medium is carried out through the splitter so that the splitter separates the laser beam into a first laser beam and a second laser beam, And is irradiated to the pure amorphous silicon pattern corresponding to each of the first widths shielded by the source and drain electrodes by being irradiated with symmetrical first and second angles corresponding to a normal line perpendicular to the substrate surface Wherein the method comprises the steps of:  5. The method of claim 4, Wherein the splitter has a triangular or quadrangular cross-sectional shape.  5. The method of claim 4, Wherein when the cross-sectional shape of the splitter is triangular, the laser beam incident on the splitter is in a direction parallel to the normal line, And the laser beam incident on the splitter has the first angle or the second angle when the laser beam is rectangular.  5. The method of claim 4, Wherein the first and second angles are capable of changing the size of the splitter by swinging the splitter clockwise or counterclockwise.  The method according to claim 1, The laser beam using the laser device having the solid medium is irradiated on the substrate surface so as to have a first angle with a normal line perpendicular to the substrate surface to advance the first scan, And the second scan is performed in a state in which the laser beam is irradiated so as to have a second angle that is symmetrical to the normal line.  The method according to claim 1, Forming an active layer made of said partially polysilicon and annealing said substrate at a temperature of from 280 DEG C to 350 DEG C for 30 minutes to 120 minutes before forming said protective layer; Way.  10. The method of claim 9, Wherein after the annealing, the substrate is placed in a vacuum chamber having an internal pressure of 10 mTorr to 100 mTorr, hydrogen is supplied at a flow rate of about 1000 sccm to 2000 sccm, and hydrogen plasma treatment is performed. Way.  11. The method of claim 10, Wherein the hydrogen plasma treatment is performed for 2 minutes to 4 minutes and 30 seconds.  The method according to claim 1, Wherein the step of forming the impurity and the pure amorphous silicon pattern and the step of forming the data line and the source and drain electrodes proceed simultaneously through a single mask process. Claims [1] A gate wiring extending in one direction on the substrate; a gate electrode connected to the gate wiring; A gate insulating film formed to cover the gate wiring and the gate electrode; A data line formed on the gate insulating film and defining a pixel region intersecting the gate line; An active layer corresponding to the gate electrode over the gate insulating film in the pixel region and consisting of a first region of polysilicon and a second region of pure amorphous silicon on both sides of the first region; The second region being located on both sides of the first region and the first region corresponding to the first width of the first region in contact with the second region, An ohmic contact layer of silicon; Source and drain electrodes formed to expose the first region over the ohmic contact layer; A protective layer formed on the source and drain electrodes and the data line, the protective layer having a contact hole exposing the drain electrode; And a pixel electrode formed in the pixel region, the pixel electrode being in contact with the drain electrode through the contact hole, ≪ / RTI > 14. The method of claim 13, Wherein the first width is 1 占 퐉 to 2 占 퐉.

Images