KR101528506B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate wiring and a gate electrode extending in one direction on a substrate; Depositing a gate insulating layer, a pure amorphous silicon layer, and an inorganic insulating layer all over the gate wiring and the gate electrode over the entire surface; Patterning the inorganic insulating layer and the pure amorphous silicon layer to form a pure amorphous silicon pattern on the gate insulating film in correspondence with the gate electrode and an etch stopper corresponding to a central portion of the pure amorphous silicon pattern on the pure amorphous silicon pattern; The impurity amorphous silicon layer and the metal layer are sequentially deposited on the entire surface of the pure amorphous silicon pattern exposed on both sides of the etch stopper and the etch stopper, and then patterned to form a data wire crossing the gate wiring over the gate insulating film, An ohmic contact layer made of impurity amorphous silicon and in contact with the pure amorphous silicon pattern spaced apart from the upper portion of the etch stopper and exposed to the outside of the etch stopper; Forming source and drain electrodes spaced apart from each other at an upper portion thereof; A first region which becomes polysilicon by crystallizing the pure amorphous silicon pattern corresponding to a spacing region between the source and drain electrodes by irradiating a laser beam through a Diode Pumped Solid State (DPSS) laser device, Forming an active layer consisting of a second region that is not crystallized and maintains a pure amorphous silicon state; Forming a protective layer having drain contact holes exposing the drain electrodes over the source and drain electrodes; Forming a pixel electrode on the protective layer, the pixel electrode being in contact with the drain electrode through the drain contact hole in the pixel region; and a method of manufacturing an array substrate manufactured by such a manufacturing method do.

       Laser crystallization, thin film transistor, etch stopper, DPSS, array substrate

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

The present invention relates to an array substrate, and more particularly, to a thin film transistor array substrate having an active layer which originally suppresses occurrence of surface damage of an active layer by dry etching and has excellent mobility characteristics, and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

An array substrate having a thin film transistor, which is essentially a switching element, is provided in order to commonly turn on and off each pixel region in the liquid crystal display device and the organic electroluminescent device.

FIG. 1 is a cross-sectional view of a conventional array substrate constituting the above-described liquid crystal display device or organic electroluminescent device including one pixel region including a thin film transistor.

A gate electrode 15 is formed in a switching region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a data wiring 33 are defined in the array substrate 11, And a gate insulating film 18 is formed on the entire surface of the gate electrode 15. An active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon A semiconductor layer 28 is formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method and the characteristic difference of the thin film transistor Tr occurs due to the difference in thickness (t1? T2) of the active layer 22 have.

2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate. In the figure, the gate electrode and the gate insulating film are omitted for convenience of explanation.

2A, a pure amorphous silicon layer 20 is formed on a substrate 11, and an impurity amorphous silicon layer 24 and a metal layer 30 are sequentially formed thereon. Thereafter, a photoresist layer is formed on the metal layer 30 to form a photoresist layer (not shown), exposing the photoresist layer using an exposure mask, and successively developing the photoresist layer, thereby forming a third And a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed corresponding to the spacing region between the source and drain electrodes .

Next, as shown in FIG. 2B, the metal layer (30 in FIG. 2A) exposed at the outside of the first and second photoresist patterns 91 and 92 and the impurities and the pure amorphous silicon layer 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top and an impurity amorphous silicon pattern 25 and an active layer 22 as a bottom portion.

Next, as shown in FIG. 2C, the second photoresist pattern (92 in FIG. 2B) of the fourth thickness is removed by performing ashing. In this case, the first photoresist pattern (91 of FIG. 2B) having the third thickness becomes a third photoresist pattern 93 in a reduced thickness and remains on the source drain pattern 31.

Next, as shown in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching away the source drain pattern (31 in FIG. 2C) exposed to the outside of the third photoresist pattern 93, . At this time, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, dry etching is performed on the impurity amorphous silicon pattern (25 in FIG. 2D) exposed in the spacing region between the source and drain electrodes 36 and 38, The ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38.

At this time, the dry etching is performed for a sufficiently long time to completely eliminate the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38. In this process, the impurity amorphous silicon pattern A portion of the impurity amorphous silicon pattern (25 in FIG. 2D) is etched to a predetermined thickness even to the active layer 22 located at the lower portion of the impurity-amorphous silicon pattern 25 (FIG. 2D). Therefore, in the active layer 22, there is a difference in thickness (t1? T2) between the portion where the ohmic contact layer 26 is formed on the active layer 22 and the portion where the ohmic contact layer 26 is formed. If the dry etching is not performed for a sufficiently long time, the impurity amorphous silicon pattern (25 in FIG. 2D) to be removed in the spacing region between the source and drain electrodes 36 and 38 remains on the active layer 22 This is to prevent this.

Therefore, in the above-described conventional method of manufacturing the array substrate 11, inevitably, the thickness of the active layer 22 is different, and the characteristics of the thin film transistor (Tr in FIG. 1) deteriorates.

2A) which is thick enough to form the active layer 22 in consideration of the thickness at which the active layer 22 is etched away during the dry etching for forming the ohmic contact layer 26, The deposition must be sufficiently thick that the deposition time is increased and the productivity is lowered.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

However, in the case of a thin film transistor generally constituted in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, and stability becomes a problem when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s and it is difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process using a laser device has been proposed.

3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate including a thin film transistor having a conventional polysilicon as a semiconductor layer, polysilicon is formed on the semiconductor layer Region 55b containing a high-concentration impurity or a p + region (not shown) containing a high concentration of impurities is formed in the semiconductor layer 55 made of polysilicon, in order to manufacture the array substrate 51 including the thin- Lt; / RTI > Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the progress of the doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment.

It is an object of the present invention to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching and the surface of the active layer is not damaged so that the characteristics of the thin film transistor are improved .

It is another object of the present invention to provide a method of manufacturing an array substrate including a thin film transistor which does not require a doping process and which can improve mobility characteristics even when the semiconductor layer is formed of polysilicon.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including forming gate lines and gate electrodes extending in one direction on a substrate; Depositing a gate insulating layer, a pure amorphous silicon layer, and an inorganic insulating layer all over the gate wiring and the gate electrode over the entire surface; Patterning the inorganic insulating layer and the pure amorphous silicon layer to form a pure amorphous silicon pattern on the gate insulating film in correspondence with the gate electrode and an etch stopper corresponding to a central portion of the pure amorphous silicon pattern on the pure amorphous silicon pattern; The impurity amorphous silicon layer and the metal layer are sequentially deposited on the entire surface of the pure amorphous silicon pattern exposed on both sides of the etch stopper and the etch stopper, and then patterned to form a data wire crossing the gate wiring over the gate insulating film, An ohmic contact layer made of impurity amorphous silicon and in contact with the pure amorphous silicon pattern spaced apart from the upper portion of the etch stopper and exposed to the outside of the etch stopper; Forming source and drain electrodes spaced apart from each other at an upper portion thereof; A first region which becomes polysilicon by crystallizing the pure amorphous silicon pattern corresponding to a spacing region between the source and drain electrodes by irradiating a laser beam through a Diode Pumped Solid State (DPSS) laser device, Forming an active layer consisting of a second region that is not crystallized and maintains a pure amorphous silicon state; Forming a protective layer having drain contact holes exposing the drain electrodes over the source and drain electrodes; And forming the pixel electrode in the pixel region on the protective layer, the pixel electrode being in contact with the drain electrode through the drain contact hole.

The inorganic insulating layer may be formed to have a single layer structure by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or may be formed to have a bilayer structure of a lower layer of silicon oxide (SiO ₂ ) and an upper layer of silicon nitride .

The step of forming the etch stopper corresponding to the center portion of the pure amorphous silicon pattern and the upper portion of the pure amorphous silicon pattern includes forming a photoresist layer on the inorganic insulating layer; The photoresist layer is subjected to halftone exposure or diffraction exposure to form a first photoresist pattern having a first thickness corresponding to a portion where the etch stopper is to be formed by performing a developing process, Forming a second photoresist pattern having a second thickness thinner than the first thickness, corresponding to a pure amorphous silicon pattern to be formed; Forming an inorganic insulating layer on the pure amorphous silicon pattern and an upper portion of the pure amorphous silicon pattern by removing the inorganic insulating layer and the pure amorphous silicon below the inorganic insulating layer in a portion exposed outside the first and second photoresist patterns; Exposing both sides of the inorganic insulating pattern outside the first photoresist pattern by ashing and removing the second photoresist pattern of the second thickness; Removing the inorganic insulating pattern exposed outside the first photoresist pattern; And removing the first photoresist pattern.

The step of forming the data line, the source and drain electrodes, and the ohmic contact layer may include patterning the metal layer to form the data line and the source and drain electrodes spaced apart from each other above the impurity amorphous silicon layer corresponding to the etch stopper, ; ≪ / RTI > The impurity amorphous silicon layer exposed to the outside of the data line and the source and drain electrodes is removed by dry etching to form the ohmic contact layer under the source and drain electrodes and an impurity amorphous silicon pattern is formed under the data line .

The laser beam is generated by applying a power of 15.4 W to 16.2 W to the DPSS (Diode Pumped Solid State) laser device.

The thickness of the active layer is preferably 400 to 600 angstroms.

The gate insulating layer, the pure amorphous silicon layer, and the inorganic insulating layer are continuously deposited by changing only the reaction gas in the chamber of the chemical vapor deposition apparatus.

An array substrate according to an embodiment of the present invention includes a substrate; A gate wiring extending in one direction on the substrate; a gate electrode connected to the gate wiring; A gate insulating film formed to cover the gate wiring and the gate electrode; A data line formed on the gate insulating film and defining a pixel region intersecting the gate line; An active layer corresponding to the gate electrode over the gate insulating film in the pixel region, the active layer comprising a first region of polysilicon and a second region of pure amorphous silicon on both sides of the first region; An etch stopper formed to completely cover the first region over the active layer; An ohmic contact layer of impurity amorphous silicon spaced apart from the upper portion of the etch stopper and corresponding to a second region of the active layer; Source and drain electrodes formed on the ohmic contact layer and spaced apart from each other to expose an etch stopper corresponding to the first region; A protective layer formed on the source and drain electrodes and the data line, the protective layer having a contact hole exposing the drain electrode; And a pixel electrode formed in the pixel region in contact with the drain electrode through the contact hole over the protective layer.

As described above, according to the method of manufacturing an array substrate according to the present invention, since the active layer is not exposed to dry etching, its surface damage does not occur, and the thin film transistor characteristics are prevented from being degraded by having a constant thickness throughout the switching region It is effective.

Since the active layer is not affected by the dry etching, it is not necessary to consider the thickness of the active layer to be etched away. Thus, the thickness of the active layer is reduced to shorten the deposition time and improve the productivity.

The array substrate manufactured by the manufacturing method according to the present invention includes a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process using a DPSS laser device, The mobility characteristics of the array substrate having the thin film transistor are improved by several tens to several hundreds.

Since the active layer of polysilicon is used as a semiconductor layer of a thin film transistor, doping of impurities is not required, and thus it is not necessary to invest new equipment to proceed the doping process, which is advantageous in reducing initial investment cost

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

4A to 4K are cross-sectional views illustrating a pixel region including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention. Here, for convenience of description, a portion where a thin film transistor connected to the gate and data lines in each pixel region P is to be formed is defined as a switching region TrA.

4A, a low resistance metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, and chromium (Cr) is formed on a transparent substrate 101 (Not shown) to form a first metal layer (not shown), and a mask process including a photoresist application, exposure using an exposure mask, development of exposed photoresist, and a unit process such as etching and stripping is performed (Not shown) extending in one direction by patterning the first metal layer (not shown), and a gate electrode 105 connected to the gate wiring (not shown) is formed in the switching region TrA at the same time, .

Next, as shown in Fig. 4b, the gate wiring (not shown) and a gate electrode 105 over the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) gate insulating film (108 by deposition to ). Subsequently, pure amorphous silicon is deposited on the gate insulating layer 108 to form a pure amorphous silicon layer 110. Although the pure amorphous silicon layer 110 is formed to have a thickness of about 800 Å to 1000 Å in consideration of being etched in the conventional case, the active amorphous silicon layer 110, which is implemented using the pure amorphous silicon layer 110, 4k < / RTI > 121) are not exposed to dry etching and thus are preferably formed to have a relatively thin thickness of about 400 to 600 Angstroms.

Next, the inorganic insulating layer 113 is formed on the pure amorphous silicon layer 110 by depositing an inorganic insulating material on the entire surface. At this time, the inorganic insulating layer 113 is preferably formed to have a bilayer structure. That is, the lower layer 113a contacting the polysilicon pattern 110 is formed of silicon oxide (SiO ₂ ) to have a thickness of about 50 Å to 500 Å, and the upper layer 113b located on the lower layer 113a is nitrided It is preferable to form silicon (SiNx) to have a thickness of about 50 to 500 ANGSTROM. The reason why the inorganic insulating layer 113 is formed as a double layer using different inorganic insulating materials is that the bonding property between silicon oxide (SiO ₂ ) and pure amorphous silicon and the characteristic at the interface formed on the bonding surface between the heteroatom (SiNx) and superior to the junction characteristics and interfacial characteristics between the pure amorphous silicon, and further such a bonding property of the photoresist used during patterning of the inorganic insulating layer 113 is a silicon nitride (SiNx), silicon oxide (SiO ₂₎ Is better.

However, the inorganic insulating layer 113 is not necessarily formed to have a bilayer structure, and may be formed to have a single layer structure of any one of silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

Since the gate insulating film 108, the pure amorphous silicon layer 110 and the inorganic insulating layer 113 are formed through chemical vapor deposition (CVD) equipment (not shown) (Not shown) by changing only the reaction gas injected into a chamber (not shown) of a CVD (chemical vapor deposition) apparatus (not shown). Therefore, after forming the gate insulating film 108, the pure amorphous silicon layer 110 is continuously formed without being exposed to the air, so that the gate insulating film 108 is not contaminated and the gate insulating film 108 and the pure amorphous silicon layer 110) is improved, and further, there is no need to clean the surface of the contaminated gate insulating film, which is advantageous in simplifying the process by omitting the process. The inorganic insulating layer 113 formed on the pure amorphous silicon layer 110 is formed in the same chamber (not shown) of a chemical vapor deposition (CVD) apparatus (not shown) after the pure amorphous silicon layer 110 is formed. As shown in Fig. Accordingly, since the surface of the pure amorphous silicon layer 110 is not contaminated by exposure to air, the active layer (121 of FIG. 4k) is formed by using the pure amorphous silicon layer 110, Thereby improving the characteristics of the thin film transistor including the thin film transistor.

Next, as shown in FIG. 4C, a photoresist layer (not shown) is formed by applying a photoresist on the inorganic insulating layer 113, and a light transmission region (not shown) is formed on the photoresist layer (Not shown) having a light transmittance lower than that of the transmissive area and larger than that of the blocking area by adjusting the amount of light passing therethrough, To perform exposure.

Thereafter, the exposed photoresist layer (not shown) is developed to form a first photoresist pattern 191a having a first thickness corresponding to the gate electrode 105 on the inorganic insulating layer 113 And a second photoresist pattern 191b having a second thickness thinner than the first thickness is formed corresponding to a predetermined width of both sides of the gate electrode 105 with reference to the center of the gate electrode 105. [ At this time, the photoresist layer (not shown) is removed to expose the inorganic insulating layer 113 corresponding to the other regions.

Next, as shown in FIG. 4D, the inorganic insulating layer (113 in FIG. 4C) exposed to the outside of the first and second photoresist patterns 191a and 191b and the pure amorphous silicon layer 4c are removed by etching to form an island-shaped pure amorphous silicon pattern 120 and an inorganic insulating pattern 125 on the island-shaped pure amorphous silicon pattern 120 in the switching region TrA. Since the inorganic insulating layer 125 has a double layer structure as an inorganic insulating layer 113 in the previous step, the lower layer 125a of silicon oxide (SiO ₂ ) and the upper layer 125b of silicon nitride (SiNx) ) Layer structure.

As shown in FIG. 4E, ashing is performed on the substrate 101 on which the pure amorphous silicon pattern 120 and the inorganic insulating pattern 125 are formed to form a second photoresist having the second thickness, (191b in Fig. 4D) is removed to expose both side portions of the inorganic insulating pattern 125 in the switching region TrA. At this time, the first photoresist pattern 191a is also reduced in thickness by the ashing process, but remains on the central portion of the inorganic insulating pattern 125.

 Next, as shown in FIG. 4F, the inorganic insulating pattern (125 in FIG. 4E) exposed to the outside of the first photoresist pattern 191a is etched and removed to expose both sides of the pure amorphous silicon pattern 120 . At this time, the inorganic insulating pattern which is not etched by the first photoresist pattern 191a but remains in correspondence with the central portion of the pure amorphous silicon pattern 120 forms the etch stopper 126.

Next, as shown in FIG. 4G, the strip is moved to remove the first photoresist pattern (191a in FIG. 4F) remaining on the etch stopper 126. Thereafter, the impurity amorphous silicon layer 130 is formed by depositing impurity amorphous silicon on the etch stopper 126 and the pure amorphous silicon patterns 120 exposed on both sides of the etch stopper 126, and the impurity amorphous silicon layer 130 is formed continuously, The second metal layer 135 is formed by depositing a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chrome (Cr), or molybdenum (Mo) do.

Then, as shown in FIG. 4H, the impurity amorphous silicon layer (130 in FIG. 4G) located at the lower portion of the second metal layer (135 in FIG. 4G) And the data lines 140 defining the pixel regions P are formed in the switching region TrA so as to be spaced apart from each other above the etch stoppers 126. The exposed pure amorphous silicon patterns 120 The source and drain electrodes 143 and 146 are formed. At this time, the data line 140 and the source electrode 143 formed in the switching region TrA are formed to be connected to each other. On the other hand, the impurity amorphous silicon layer 130 (FIG. 4G) is patterned in the lower part of the source and drain electrodes 143 and 146 to form the pure amorphous silicon pattern The ohmic contact layer 132 of the impurity amorphous silicon is formed.

Meanwhile, the impurity amorphous silicon layer 130 (FIG. 4G) is continuously patterned together with the second metal layer 135 (FIG. 4G) located thereon, so that the impurity amorphous silicon layer 133 remains under the data line 140, . That is, the data line 140 and the source and drain electrodes 143 and 146 are formed by patterning the second metal layer 135 (FIG. 4G), and then the data line 140 and the source and drain electrodes 143 and 143 are patterned, The patterning of the impurity amorphous silicon layer (130 in FIG. 4G) exposed to the outside of the gate insulating layer 146 is performed by dry etching. In the dry etching, the pure amorphous silicon pattern 120 is etched using an etch stopper 126 are formed, so that they are not exposed to the dry etching at all. Therefore, unlike the conventional array substrate fabrication, the impurity amorphous silicon layer (130 of FIG. 4G) is patterned to prevent surface damage of the pure amorphous silicon pattern 120 by dry etching when the ohmic contact layer 132 is formed, And the thickness thereof is not reduced so that the switching region TrA has a constant thickness throughout the switching region TrA.

Next, as shown in FIG. 4I, by using a DPSS (Diode Pumped Solid State) laser device 180 corresponding to the substrate 101 on which the source and drain electrodes 143 and 146 and the data line 140 are formed The center portion of the pure amorphous silicon pattern (120 in FIG. 4H) located below the etch stopper 126 corresponding to the region between the source and drain electrodes 143 and 146 is crystallized by irradiating the laser beam LB So that a first region 121a made of polysilicon is partially formed.

In this case, the DPSS laser device 180 uses a solid state material as a medium source for generating the laser beam LB. In a laser device using such a solid as a source, an error in the energy density per unit area of the generated laser beam LB is far smaller than the laser beam generated through the excimer laser device using the gas as a medium source, LB) is hardly generated due to the difference in energy density of the respective regions.

The configuration of the DPSS laser device 180 used for manufacturing the array substrate 101 according to the present invention will be briefly described. The DPSS laser device 180 includes a diode for supplying light energy in an infrared form and a Yttrium Aluminum Garnet (YAG) rod for generating a substantial laser beam LB by collecting light energy from the diode, And a second-harmonic generation (SHG) optical system and a wavelength separation mirror (WSM). At this time, the diode serves to supply light energy to the YAG rod in the form of infrared rays, and the atoms of the YAG rod become high energy state through the light energy introduced into the YAG rod, Thereby generating a laser beam LB. The second harmonic generation optical system doubles the wavelength of the laser beam LB emitted from the YAG rod. The laser beam LB emitted from the diode through the YAG rod enters the YAG rod, But the laser beam LB having a wavelength of 532 nm, which partly still has a wavelength of 1064 nm and another part, whose length is reduced by half, is produced by the action of the second harmonic generation optical system do. The laser beam LB passing through the second harmonic generation optical system and having two wavelength bands is separated into a laser beam LB having a wavelength of 532 nm and an infrared ray having a wavelength of 1064 nm through a wavelength separation mirror. At this time, in the present invention, the laser beam LB having a wavelength of 532 nm separated through the wavelength separation mirror is used for crystallization. The DPSS laser device 180 using a diode as an energy source and using a solid YAG rod as a laser beam (LB) generating medium is a laser device (not shown) using gas or liquid as a laser beam generating medium The density of the laser beam finally irradiated onto the substrate is uniform, and the uniformity of the crystallization is improved.

On the other hand, with respect to the substrate 101 on which the source and drain electrodes 143 and 146 are formed, the laser is selectively scanned with respect to the front surface through the DPSS laser device 180 having the above- And irradiates the beam LB. At this time, the power of the DPSS laser device 180 is preferably in the range of 15.4W to 16.2W. When the laser beam is irradiated to the substrate with such a power, the laser beam is adjusted to be positioned below the etch stopper 126 in consideration of the thickness of the etch stopper 126, and then the laser beam LB is combined with the pure amorphous silicon Energy is concentrated only on the pattern (120 in FIG. 4H), and only the pure amorphous silicon pattern (120 in FIG. 4H) is melted to be crystallized. The laser beam LB incident on the portion where the source and drain electrodes 143 and 146 are formed is reflected so that the laser beam LB is incident on the pure amorphous silicon pattern 121b The ohmic contact layer 132 and the pure amorphous silicon pattern 121b located under the source and drain electrodes 143 and 146 maintain the amorphous silicon state of the pure water and the impurity as they are.

The crystallization of the pure amorphous silicon pattern (120 in FIG. 4H) having the above structure is greatly influenced by the focusing and the energy density of the laser beam LB. In the case of focusing, it is not a problem if the thickness of the etch stopper 126 located at the upper portion is known. However, the power of the laser beam (LB) becomes a very sensitive factor. When a power greater than the above-described range is applied to the DPSS laser device 180, the energy density per unit area of the laser beam LB itself is too large and the pure amorphous silicon pattern 120 (FIG. 4H) Hydrogen in the pure amorphous silicon pattern 120 (FIG. 4H) suddenly escapes at a time. Therefore, the hydrogen diffused at once from the pure amorphous silicon pattern (120 in FIG. 4H) pushes the etch stopper 126 located at the upper portion thereof, thereby causing the etch stopper 126 to lift, break or crack Or a large number of depressions such as dents are formed on the surface of the first region 121a crystallized by the polysilicon because the hydrogen is emitted at the same time, so that the surface of the first region 121a is not smooth. Therefore, in this case, the characteristics of the thin film transistor are deteriorated due to the deterioration of the interface characteristics with the etch stopper 126 located at the upper portion thereof, and the characteristics of the thin film transistor are different for each pixel region P.

However, when the power in the above-described range is applied to the DPSS laser device 180, it can be seen that the defect described above does not occur.

On the other hand, as the crystallization process using the DPSS laser device 180 described above proceeds, the pure amorphous silicon pattern 120 (FIG. 4H) has a first region 121a having a central portion crystallized into polysilicon and a first region 121a And a second region 121b contacting the ohmic contact layer 132 on both sides and maintaining a pure amorphous silicon state. The active layer 121 formed of the first and second regions 121a and 121b and the ohmic contact layer 132 formed on the upper portion of the active layer 121 form a semiconductor layer 134. Since most of the active layer 121 is made of polysilicon, the active layer 121 is formed of only pure amorphous silicon, and thus the active layer 121 is much superior to the active layer 20a of FIG. 1 And it has a characteristic of having a high degree of freedom.

The gate electrode 105, the gate insulating film 108, the semiconductor layer 134, the etch stopper 126, the source and drain electrodes 143 , And 146 are formed on the substrate.

Although not shown in the drawing, in the case where the array substrate 101 is used as an array substrate for an organic electroluminescent device, in the step of forming the source and drain electrodes 143 and 146 and the data line 140, And a power supply line (not shown) may be further formed to be spaced apart from each other in parallel to the data line 140. The pixel region P may have the same structure as the thin film transistor Tr connected to the data line 140 A plurality of driving thin film transistors (not shown) may be further formed.

Next, as shown in FIG. 4J, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiO ₂ ) is deposited on the entire surface of the substrate 101 on which crystallization is performed over the source and drain electrodes 143 and 146 A protective layer 150 is formed on the entire surface by depositing an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

Then, the protective layer 150 is patterned to form a drain contact hole 153 for exposing the drain electrode 146 in the switching region TrA.

Next, as shown in FIG. 4K, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the protective layer 150 having the drain contact hole 153 Thereby forming a transparent conductive material layer (not shown). Then, the pixel electrode 160, which is in contact with the drain electrode 146 through the drain contact hole 153, is formed in each pixel region P by patterning the transparent conductive material layer (not shown) Thereby completing the array substrate 101 according to the embodiment of the present invention.

When a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr formed in the switching region TrA does not contact the pixel electrode 160, A drain electrode (not shown) of a driving thin film transistor (not shown) is formed to be connected to the pixel electrode 160 as shown in the figure, and the thin film transistor Tr of the switching region TrA, (Not shown) are electrically connected to each other. In the case of an array substrate in which driving thin film transistors (not shown) are formed in the pixel region P and the thin film transistor Tr connected to the gate and data lines (not shown) 140 in the switching region TrA, Thereby forming an array substrate.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device, including one pixel region including a thin film transistor. Fig.

FIGS. 2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate; FIGS.

3 is a cross-sectional view of a pixel region including the thin film transistor in an array substrate having a thin film transistor having a conventional polysilicon semiconductor layer.

4A to 4K are cross-sectional views illustrating a pixel region including a thin film transistor of an array substrate according to an embodiment of the present invention.

Description of the Related Art

101: substrate 105: gate electrode

108: gate insulating film 121: active layer

121a: first region (of active layer) 121b: second region (of active layer)

126: etch stopper 126a: lower layer (of silicon oxide)

126b: upper layer (of silicon nitride) 132: ohmic contact layer

133: impurity amorphous pattern 134: semiconductor layer

140: data wiring 143: source electrode

146: drain electrode

P: pixel region TrA: switching region

Claims (8)

Forming a gate wiring and a gate electrode extending in one direction on a substrate; Depositing a gate insulating layer, a pure amorphous silicon layer, and an inorganic insulating layer all over the gate wiring and the gate electrode over the entire surface; Patterning the inorganic insulating layer and the pure amorphous silicon layer to form a pure amorphous silicon pattern on the gate insulating film in correspondence with the gate electrode and an etch stopper corresponding to a central portion of the pure amorphous silicon pattern on the pure amorphous silicon pattern; The impurity amorphous silicon layer and the metal layer are sequentially deposited on the entire surface of the pure amorphous silicon pattern exposed on both sides of the etch stopper and the etch stopper, and then patterned to form a data wire crossing the gate wiring over the gate insulating film, An ohmic contact layer made of impurity amorphous silicon and in contact with the pure amorphous silicon pattern spaced apart from the upper portion of the etch stopper and exposed to the outside of the etch stopper; Forming source and drain electrodes spaced apart from each other at an upper portion thereof; A first region which becomes polysilicon by crystallizing the pure amorphous silicon pattern corresponding to a spacing region between the source and drain electrodes by irradiating a laser beam through a Diode Pumped Solid State (DPSS) laser device, Forming an active layer consisting of a second region that is not crystallized and maintains a pure amorphous silicon state;   Forming a protective layer having drain contact holes exposing the drain electrodes over the source and drain electrodes; Forming a pixel electrode in the pixel region on the protective layer, the pixel electrode being in contact with the drain electrode through the drain contact hole; Wherein the substrate is a substrate. The method according to claim 1, The inorganic insulating layer may be formed to have a single layer structure by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or may be formed to have a bilayer structure of a lower layer of silicon oxide (SiO ₂ ) and an upper layer of silicon nitride Wherein the substrate is a substrate. The method according to claim 1, Forming an etch stopper on the pure amorphous silicon pattern and a central portion of the pure amorphous silicon pattern on the pure amorphous silicon pattern, Forming a photoresist layer on the inorganic insulating layer; The photoresist layer is subjected to halftone exposure or diffraction exposure to form a first photoresist pattern having a first thickness corresponding to a portion where the etch stopper is to be formed by performing a developing process, Forming a second photoresist pattern having a second thickness thinner than the first thickness, corresponding to a pure amorphous silicon pattern to be formed; Forming an inorganic insulating layer on the pure amorphous silicon pattern and an upper portion of the pure amorphous silicon pattern by removing the inorganic insulating layer and the pure amorphous silicon below the inorganic insulating layer in a portion exposed outside the first and second photoresist patterns; Exposing both sides of the inorganic insulating pattern outside the first photoresist pattern by ashing and removing the second photoresist pattern of the second thickness; Removing the inorganic insulating pattern exposed outside the first photoresist pattern; Removing the first photoresist pattern Wherein the substrate is a substrate. The method according to claim 1, Forming the data line, the source and drain electrodes, and the ohmic contact layer, Forming the data line and the source and drain electrodes spaced apart from each other on the impurity amorphous silicon layer corresponding to the etch stopper by patterning the metal layer; The impurity amorphous silicon layer exposed to the outside of the data line and the source and drain electrodes is removed by dry etching to form the ohmic contact layer under the source and drain electrodes and an impurity amorphous silicon pattern is formed under the data line Forming step Wherein the substrate is a substrate.  The method according to claim 1, Wherein the laser beam is generated by applying a power of 15.4 W to 16.2 W to the DPSS (Diode Pumped Solid State) laser device. The method according to claim 1, Wherein the active layer has a thickness of 400 ANGSTROM to 600 ANGSTROM. The method according to claim 1, Wherein the gate insulating layer, the pure amorphous silicon layer, and the inorganic insulating layer are continuously deposited by changing the reaction gas only in the chamber of the chemical vapor deposition apparatus. Claims [1] A gate wiring extending in one direction on the substrate; a gate electrode connected to the gate wiring; A gate insulating film formed to cover the gate wiring and the gate electrode; A data line formed on the gate insulating film and defining a pixel region intersecting the gate line; An active layer corresponding to the gate electrode over the gate insulating film in the pixel region, the active layer comprising a first region of polysilicon and a second region of pure amorphous silicon on both sides of the first region; An etch stopper formed to completely cover the first region over the active layer; An ohmic contact layer of impurity amorphous silicon spaced apart from the upper portion of the etch stopper and corresponding to a second region of the active layer; Source and drain electrodes formed on the ohmic contact layer and spaced apart from each other to expose an etch stopper corresponding to the first region; A protective layer formed on the source and drain electrodes and the data line, the protective layer having a contact hole exposing the drain electrode; And a pixel electrode formed in the pixel region, the pixel electrode being in contact with the drain electrode through the contact hole, ≪ / RTI >

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