JPWO2013005250A1 - THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Google Patents

Abstract

  The thin film transistor of the present invention aims to provide a thin film transistor that can achieve both excellent on-characteristics and excellent off-characteristics, and whose electric characteristics are symmetric with respect to replacement of the source electrode and the drain electrode. A crystalline silicon layer (131) formed on the substrate (100), the gate electrode (110), the gate insulating layer (120), and the gate insulating layer (120) above the gate electrode (110). An amorphous silicon layer (130) formed on both sides of the crystalline silicon layer (131) on the gate insulating layer (120) and having a thickness smaller than that of the crystalline silicon layer (131); A channel protective layer (140) formed on the crystalline silicon layer (131), a source electrode (171), and a drain electrode (172) are provided.

Description

  The present invention relates to a thin film transistor, a method for manufacturing the same, and a display device.

  In recent years, an organic EL display using EL (ElectroLuminescence) of an organic material as one of the next generation flat panel displays replacing a liquid crystal display attracts attention. Unlike a voltage-driven liquid crystal display, an organic EL display is a current-driven device, and development of a thin film transistor (thin film semiconductor device) having excellent on / off characteristics as a drive circuit for an active matrix display device is urgently required. Yes.

As a thin film transistor that realizes excellent on characteristics, a thin film transistor in which a single semiconductor layer is formed on a gate insulating layer and this is used as a convex channel layer is disclosed (Patent Document 1). In this disclosed technique, the film thickness from the convex bottom surface to the convex upper surfaces on both sides is made thinner than the film thickness from the convex bottom surface to the central top surface of the convex shape. That is, when current flows between the source electrode and the drain electrode via the lower portions on both sides of the convex shape of the channel layer at the lower portion of the convex shape of the channel layer serving as a current path, Since the lower part is thinner than the convex upper part of the channel layer, the resistance component in the vertical direction of the channel layer can be reduced. Therefore, the transverse resistance at the lower part of the convex shape of the channel layer can be kept low, and the on-current of the thin film transistor can be increased. Note that the mobility of amorphous silicon is about 1 cm ² / Vs, whereas the mobility of crystalline silicon is as large as about 100 cm ² / Vs. Therefore, in order to realize a thin film transistor having excellent on characteristics, the semiconductor layer is preferably formed of crystalline silicon.

  A thin film transistor in which a crystalline silicon layer is formed on a gate insulating layer and an amorphous silicon layer is formed on both sides of the crystalline silicon layer is disclosed as a thin film transistor that realizes excellent on characteristics and off characteristics. (Patent Document 2). In this disclosed technique, in order to crystallize amorphous silicon as a channel layer, laser light is irradiated to amorphous silicon from an opening between a source electrode and a drain electrode. Thereby, the amorphous silicon in the central region of the channel layer is formed as crystalline silicon, and the crystalline silicon is formed as a current path in the channel layer, thereby increasing the on-current of the thin film transistor. In general, when a thin film transistor performs an off operation, a depletion layer formed with a channel layer and a drain being reverse-biased serves as a carrier barrier to realize the off operation. However, electrons and holes are thermally generated in the depletion layer, which deteriorates off characteristics as a heat generation current. Further, when a large gate voltage is applied to the off side, a depletion layer is formed in the channel layer facing the gate electrode. Here, since a large electric field is intensively applied to the depletion layer, the band of the channel layer is bent greatly, a tunnel current is generated, and the off-characteristic is deteriorated as a leakage current. In this disclosed technique, an amorphous silicon layer is formed on both sides of a crystalline silicon layer. Compared to crystalline silicon, the band gap of amorphous silicon is large, and the energy necessary for heat generation of electrons and holes and the potential barrier for tunnel effect are large. By forming the silicon layer, generation of heat generation current and tunnel leakage current is prevented, and off-current is reduced. As described above, by forming the crystalline silicon that increases the on-current and the amorphous silicon that decreases the off-current as the channel layer, excellent on-characteristics and off-characteristics can be realized.

US Pat. No. 6,794,682 JP 2005-322898 A

  However, in the disclosed technique of Patent Document 1, since the film quality is the same in the thick region at the center and the thin region at both end portions, there is a limit in reducing the off-current. That is, in the region where the film thickness is thin at both end portions, the volume of the depletion layer decreases in conjunction with the decrease in the film thickness, and the leakage current tends to decrease. However, as in Patent Document 2, it is difficult to reduce the off-current more than when an amorphous silicon layer is provided on both sides of a crystalline silicon layer. For this reason, in the disclosed technique of Patent Document 1, in the thin film transistor in which the channel layer is made of crystalline silicon, the heat generation current and the tunnel current significantly deteriorate the off characteristics and become a serious problem in realizing the excellent off characteristics. .

  In the technique disclosed in Patent Document 2, the portion where the source electrode, the drain electrode, the channel protective layer, and the channel layer overlap is made of amorphous silicon. That is, the ratio of the amorphous silicon layer to the channel length of the thin film transistor defined by the width of the channel protective layer is large. The amorphous silicon layer acts as a resistance component and becomes a barrier for a current path parallel to the channel layer. The film thickness of the crystalline silicon layer and the film thickness of the amorphous silicon layer are the same, and the upper surface of the crystalline silicon layer and the upper surface of the amorphous silicon layer are flat and continuous surfaces. Therefore, when current flows between the source electrode and the drain electrode through both sides of the channel layer, the amorphous silicon layer on both sides of the channel layer has a thickness, so that the amorphous silicon layer acts as a resistance component, and the channel It becomes a barrier for the current path perpendicular to the layer. Thus, the resistance component due to the amorphous silicon exists in the channel layer in both the horizontal direction and the vertical direction, so there is a limit to improving the on-characteristic.

  Furthermore, manufacturing variations occur when forming the source electrode and the drain electrode. Therefore, it is difficult to form the source electrode and the drain electrode evenly with respect to the lower layer existing before the source electrode and the drain electrode are formed. is there. When the source electrode and the drain electrode are arranged unevenly with respect to the lower layer, the amorphous silicon layer is irradiated with laser from the opening of the source electrode and the drain electrode to crystallize the amorphous silicon layer. Is formed, the distance from the crystalline silicon layer to the source electrode in the channel path is not equal to the distance from the crystalline silicon region to the drain electrode. That is, the resistance component in the channel path by the amorphous silicon layer existing in the portion where the source electrode, the drain electrode, the channel protective layer, and the channel layer overlap is biased on either the source electrode side or the drain electrode side. Therefore, the characteristics of the thin film transistor between different substrates vary. In the case where a thin film transistor is formed over a large substrate, the positional deviation when forming the source electrode and the drain electrode is larger than that in the small substrate, which is a particular problem in forming the thin film transistor over the large substrate. Even in the same substrate, when the source electrode and the drain electrode are switched and operated, the electrical characteristics become asymmetric with respect to the switching of the source electrode and the drain electrode. When the electrical characteristics are asymmetric with respect to the replacement of the source electrode and the drain electrode, problems associated with the asymmetry of the electrical characteristics may occur in the operation of the driving circuit formed of the thin film transistors. For example, when a thin film transistor having an asymmetric electrical characteristic is used as a switching transistor of a liquid crystal display, flicker occurs and display characteristics as an image display device are impaired.

  Therefore, the present invention has been made in view of the above problems, and can achieve both excellent on-characteristics and excellent off-characteristics, and the electric characteristics are symmetrical with respect to the replacement of the source electrode and the drain electrode. An object of the present invention is to provide a thin film transistor, a manufacturing method thereof, and a display device.

  In order to achieve the above object, a thin film transistor of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, and the gate insulation above the gate electrode. A crystalline silicon layer formed on the layer; an amorphous silicon layer formed on both sides of the crystalline silicon layer on the gate insulating layer and having a thickness smaller than that of the crystalline silicon layer; A channel protective layer formed on the crystalline silicon layer; an upper surface of an end of the channel protective layer; a side surface of the channel protective layer and the crystalline silicon layer; and an upper surface of the amorphous silicon layer. A source electrode formed above one of the non-crystalline silicon layers and a drain electrode formed above the other non-crystalline silicon layer.

  According to the present invention, there are provided a thin film transistor, a manufacturing method thereof, and a display device, which can achieve both excellent on characteristics and excellent off characteristics, and whose electrical characteristics are symmetrical with respect to replacement of a source electrode and a drain electrode. be able to.

FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a change in current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed. FIG. 4A is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorptance of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing. FIG. 4B is a diagram for explaining a method of calculating the light absorption rate into the amorphous silicon layer. FIG. 5A is a contour diagram showing the calculation result of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5B is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5C is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5D is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5E is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 5F is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 6A shows a value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by adding the refractive index of the gate insulating layer to the film thickness of the gate insulating layer in laser annealing, by dividing the wavelength of the laser beam by 0.330 (wavelength It is a figure which shows the change of the absorptivity of an amorphous silicon layer when it is set as a silicon oxide layer film thickness corresponding to 120 nm at 532 nm. FIG. 6B is a diagram illustrating an example of values obtained by converting the values on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer. FIG. 6C is a diagram illustrating an example of a value obtained by converting the value on the vertical axis of FIGS. 5A to 5F into the film thickness of the silicon oxide layer or the silicon nitride layer. FIG. 7 is a contour diagram showing the calculation results of the absorptance of the protrusions of the amorphous silicon layer when the thickness of the channel protective layer and the thickness of the gate insulating layer are changed in laser annealing. is there. FIG. 8A is a diagram showing the change in the absorptance of the convex portions of the amorphous silicon layer when the thickness of the channel protective layer is changed. FIG. 8B is a diagram showing a change in the absorptance of the convex portion of the amorphous silicon layer when the thickness of the channel protective layer is changed. FIG. 8C is a diagram showing the change in the absorptance of the convex portions of the amorphous silicon layer when the thickness of the channel protective layer is changed. FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a modification of the first and second embodiments of the present invention. FIG. 12 is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorption rate of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing. FIG. 13A is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. . FIG. 13B is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 13C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 13D is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120. FIG. 14 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a comparative example of the first and second embodiments of the present invention. FIG. 15 is an external view of a display device according to the third embodiment of the present invention. FIG. 16 is a partially cutaway perspective view of an organic EL panel according to the third embodiment of the present invention. FIG. 17 is a diagram showing a circuit configuration of a pixel of an organic EL panel according to the third embodiment of the present invention.

  In order to achieve the above object, a thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and an upper portion of the gate electrode. A crystalline silicon layer formed on the gate insulating layer, and an amorphous film formed on both sides of the crystalline silicon layer on the gate insulating layer and having a thickness smaller than that of the crystalline silicon layer A crystalline silicon layer, a channel protective layer formed on the crystalline silicon layer, an upper surface of an end of the channel protective layer, side surfaces of the channel protective layer and the crystalline silicon layer, and the amorphous silicon layer A source electrode formed on one side of the amorphous silicon layer and a drain electrode formed on the other side of the amorphous silicon layer. And features.

  Here, the average grain size of crystals contained in the crystalline silicon layer may be not less than 10 nm and not more than 1 μm.

  The side surface of the crystalline silicon layer and the side surface of the channel protective layer may be flush with each other.

  According to this aspect, a convex channel layer is formed which includes a crystalline silicon layer formed under the channel protective layer and an amorphous silicon layer formed on both sides of the crystalline silicon layer. The film thickness from the bottom surface of the channel layer to the upper surface of both sides of the convex portion of the channel layer is made thinner than the film thickness from the bottom surface to the upper surface of the convex portion of the channel layer. The crystalline silicon layer is formed under the channel protective layer, and since the crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer, the horizontal direction of the channel layer by the amorphous silicon layer is The resistance component decreases. Furthermore, the film thickness from the bottom surface of the channel layer to the top surface of both sides of the convex portion of the channel layer is smaller than the film thickness from the bottom surface of the channel layer to the top surface of the convex portion. Compared to the case where the film thickness from the bottom surface of the channel layer to the top surface of the portions on both sides of the convex portion is equal, the resistance component in the vertical direction of the channel layer due to the amorphous silicon layer is reduced. . In this way, all of the channel length defined by the width of the channel protective layer is occupied by the crystalline silicon layer, and the horizontal resistance component and the vertical resistance component of the channel layer by the amorphous silicon layer are Therefore, the ON characteristic can be remarkably improved.

  In addition, according to this aspect, since the portions on both sides of the convex portion of the channel layer are made of an amorphous silicon layer, both sides of the convex portion of the channel layer are formed compared to the case where the portions on both sides of the convex portion of the channel are made of a crystalline silicon layer. The band gap of this part becomes large. Therefore, the heat generation current and the tunnel current can be greatly suppressed, and the off characteristics can be greatly reduced. In addition, since the film thickness from the bottom surface of the channel layer to the top surface of both sides of the convex portion is smaller than the film thickness from the bottom surface of the channel layer to the top surface of the convex portion, The volume of the depletion layer can be reduced, the off current can be reduced, and the off characteristics can be remarkably improved.

  With these actions, both excellent on-characteristics and off-characteristics can be achieved.

  Furthermore, in this aspect, as described above, the crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the underlying channel protective layer, the distance from the crystalline silicon layer to the source electrode in the channel path and the drain from the crystalline silicon layer in the channel path The distance to the electrode is uniform, and variations in characteristics of the thin film transistor between different substrates can be suppressed. Further, even when the source electrode and the drain electrode are exchanged in the same substrate, the electrical characteristics are symmetric with respect to the exchange of the source electrode and the drain electrode. Occurrence of problems associated with asymmetry of electrical characteristics can be suppressed.

  The thin film transistor according to one embodiment of the present invention includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and the gate insulating layer over the gate electrode. A first crystalline silicon layer formed on the gate insulating layer and on both sides of the first crystalline silicon layer, the second crystalline silicon layer being thinner than the first crystalline silicon layer. A crystalline silicon layer; a channel protective layer formed on the first crystalline silicon layer; an upper surface of an end of the channel protective layer; a side surface of the channel protective layer and the first crystalline silicon layer; A source electrode formed on one side of the second crystalline silicon layer and a drain electrode formed on the other side of the second crystalline silicon layer are provided along the upper surface of the second crystalline silicon layer. , An average particle diameter of crystals contained in the first crystalline silicon layer is characterized by greater than an average grain size of crystals contained in the second crystalline silicon layer.

  Here, the average grain size of the crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less, and the average grain size of the crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm. Good.

  Further, the side surface of the first crystalline silicon layer may be flush with the side surface of the channel protective layer.

  According to this aspect, the first crystal silicon layer having a low resistance formed under the channel protective layer and the average of crystals compared to the first crystal silicon layer formed on both sides of the first crystal silicon layer A convex channel layer composed of a second crystalline silicon layer having a small particle size and high resistance is formed, and from the bottom surface of the channel layer to the upper surface of the convex portion of the channel layer, the channel layer is formed from the bottom surface of the channel layer. The film thickness up to the upper surface of the both sides of the convex portion is made thinner. Therefore, the first crystalline silicon layer is formed under the channel protective layer, and the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer. The horizontal resistance component of the channel layer due to the silicon layer decreases. Furthermore, the film thickness from the bottom surface of the channel layer to the top surface of both sides of the convex portion of the channel layer is smaller than the film thickness from the bottom surface of the channel layer to the top surface of the convex portion. Compared with the case where the film thickness from the bottom surface of the channel layer to the top surface of the portions on both sides of the convex portion is equal, the resistance component in the vertical direction of the channel layer by the high resistance crystalline silicon layer is Decrease. In this way, all of the channel length defined by the width of the channel protective layer is occupied by the low-resistance crystalline silicon layer, and the horizontal resistance component of the channel layer by the high-resistance crystalline silicon layer and the vertical Therefore, the on-state characteristics can be remarkably improved.

  In addition, according to this aspect, since the portions on both sides of the convex portion of the channel layer are made of a crystalline silicon layer having a small average grain size of the crystal, the portions on both sides of the convex portion of the channel layer are crystals having a large average grain size of the crystal. As compared with the case of the crystalline silicon layer, there are more amorphous silicon components having lower crystallinity and a large band gap. Therefore, the heat generation current and the tunnel current can be greatly suppressed, and the off characteristics can be greatly reduced. In addition, since the film thickness from the bottom surface of the channel layer to the top surface of both sides of the convex portion is smaller than the film thickness from the bottom surface of the channel layer to the top surface of the convex portion, The volume of the depletion layer can be reduced, the off current can be reduced, and the off characteristics can be remarkably improved.

  With these actions, both excellent on-characteristics and off-characteristics can be achieved.

  Furthermore, in this aspect, as described above, the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the underlying channel protection layer, the distance from the low resistance crystalline silicon layer to the source electrode in the channel path and the low resistance in the channel path The distance from the crystalline silicon layer to the drain electrode becomes uniform, and variations in characteristics of thin film transistors between different substrates can be suppressed. Further, even when the source electrode and the drain electrode are exchanged in the same substrate, the electrical characteristics are symmetric with respect to the exchange of the source electrode and the drain electrode. Occurrence of problems associated with asymmetry of electrical characteristics can be suppressed.

  Furthermore, according to this aspect, there is a degree of freedom in separately forming the second crystalline silicon layer up to a crystalline silicon layer having a small average crystal grain size. Therefore, the on-state current or the off-state current is important for the crystallinity of the convex part of the channel layer and the crystalline silicon layer below it and the crystalline silicon layer on both sides of the convex part of the channel layer. For example, it can be made according to the design of a desired thin film transistor.

  The thin film transistor manufacturing method according to one embodiment of the present invention includes a first step of preparing a substrate, a second step of forming a gate electrode over the substrate, and a gate insulating layer formed over the gate electrode. 3 steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, a fifth step of forming a channel protective layer on the amorphous silicon layer, the amorphous silicon layer, and the By processing the channel protective layer, a sixth step of forming a convex portion in which the upper layer is a channel protective layer and the lower layer is an amorphous silicon layer; and a laser beam is emitted from the convex portion of the amorphous silicon layer, Irradiating the lower part of the convex part and the parts on both sides of the convex part, the convex part of the amorphous silicon layer and the lower part of the convex part are made into a crystalline silicon layer, and the amorphous silicon Said convex part of the layer A seventh step of leaving the portions on both sides as an amorphous silicon layer; an upper surface of an end portion of the channel protective layer; a side surface of the channel protective layer and the crystalline silicon layer; and an upper surface of the amorphous silicon layer. And forming a source electrode above one of the non-crystalline silicon layers and forming a drain electrode above the other non-crystalline silicon layer, and in the seventh step, The absorptivity of the amorphous silicon layer with respect to the laser light is such that the absorptance of the convex part of the amorphous silicon layer and the part below the convex part corresponds to the lower part of the channel protective layer. The absorptance is larger than the absorptance of both sides of the convex portion of the conductive silicon layer.

  Here, in the seventh step, the crystalline silicon layer including crystals having an average particle diameter of 10 nm or more and 1 μm or less may be formed by irradiation with the laser beam.

  According to this aspect, the interference effect of laser light inside the channel protective layer, the amorphous silicon layer and the gate insulating layer and the interference effect of laser light inside the amorphous silicon layer and the gate insulating layer are utilized. To form a crystalline silicon layer. That is, the film thickness of the channel protective layer and the amorphous silicon layer in the convex portion of the channel layer and the thickness of the gate insulating layer, and the film of the amorphous silicon layer and the gate insulating layer on both sides of the convex portion of the channel layer The crystalline silicon layer is formed by controlling the absorption rate of the laser light of the amorphous silicon layer with respect to a desired laser wavelength by utilizing the thickness structure. Specifically, the amorphous silicon layer under the channel protective layer is configured to have a film thickness that increases the absorption rate of the laser beam, and the amorphous silicon layer that exists on both sides of the amorphous silicon layer under the channel protective layer by convex processing. A crystalline silicon layer is formed by irradiating laser light after making the crystalline silicon layer have a film thickness structure that reduces the absorption rate of laser light. Since the amorphous silicon layer under the channel protective layer has a film thickness structure that increases the absorption rate of laser light, the amorphous silicon layer is crystallized as a crystalline silicon layer when irradiated with laser light. On the other hand, the non-crystalline silicon layers existing on both sides of the non-crystalline silicon layer under the channel protective layer have a structure in which the absorption rate of laser light is low, so that the non-crystalline silicon layer is irradiated even when irradiated with laser light. It remains as a channel layer. Accordingly, a convex channel layer composed of a crystalline silicon layer and an amorphous silicon layer formed on both sides of the crystalline silicon layer is formed, and a film extending from the bottom surface of the channel layer to the upper surface of the convex portion of the channel layer. It is possible to realize a channel layer in which the film thickness from the bottom surface of the channel layer to the upper surface of the both sides of the convex portion of the channel layer is made thinner than the thickness. As a result, both excellent on characteristics and off characteristics can be achieved.

  According to this aspect, the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the underlying channel protection layer, the distance from the low resistance crystalline silicon layer to the source electrode in the channel path and the low resistance in the channel path The distance from the crystalline silicon layer to the drain electrode is uniform, and the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

  In the seventh step, the wavelength of the laser beam may be not less than 473 nm and not more than 561 nm.

  According to this aspect, the channel protective layer, the non-crystalline silicon layer, and the gate insulating layer can easily cause an interference effect of laser light inside, and the laser on the convex portion of the channel layer and the portions on both sides thereof Differences in light absorption can be easily generated.

  The thin film transistor manufacturing method according to one embodiment of the present invention includes a first step of preparing a substrate, a second step of forming a gate electrode over the substrate, and a gate insulating layer formed over the gate electrode. 3 steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, a fifth step of forming a channel protective layer on the amorphous silicon layer, the amorphous silicon layer and the channel By processing the protective layer, a sixth step of forming a convex portion in which the upper layer is a channel protective layer and the lower layer is an amorphous silicon layer; and a laser beam is emitted from the convex portion of the amorphous silicon layer, Irradiating the lower part of the convex part and the parts on both sides of the convex part, the convex part of the non-crystalline silicon layer and the lower part of the convex part serve as a first crystalline silicon layer, and the non-crystalline property The convex part of the silicon layer A seventh step of forming a second crystalline silicon layer on both sides; an upper surface of an end of the channel protective layer; a side surface of the channel protective layer and the first crystalline silicon layer; and the second crystalline silicon layer Forming a source electrode over one of the second crystalline silicon layers and forming a drain electrode over the other of the second crystalline silicon layer along the upper surface of the second crystalline silicon layer, In step 7, the absorptivity of the amorphous silicon layer with respect to the laser light is an absorptance of the convex portion of the amorphous silicon layer and a portion below the convex portion corresponding to the lower portion of the channel protective layer. Wherein the first crystal includes a crystal having an average grain size larger than an absorptance of both sides of the convex portion of the amorphous silicon layer and larger than an average grain size of crystals contained in the second crystalline silicon layer. Sex Siri And forming a down layer.

  Here, the average grain size of the crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less, and the average grain size of the crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm. May be.

  According to this aspect, not only the convex portion of the first crystalline silicon, that is, the noncrystalline silicon layer that forms the highly crystalline channel layer, but also the second crystalline silicon layer, that is, the non-crystalline layer that forms the low crystalline channel layer. The laser is also irradiated to both sides of the convex portion of the crystalline silicon layer. Therefore, if the intensity of the laser beam and the film thickness are appropriately selected, there is a degree of freedom in forming a low crystalline channel layer up to a crystalline silicon layer having a small average crystal grain size. In the convex channel layer, the second crystalline silicon layer on both sides of the convex portion has a smaller average crystal grain size and higher resistance than the first crystalline silicon layer of the convex portion. Compared with the case where the first crystalline silicon layer has an average grain size, the off-characteristic can be reduced. In addition, since the first crystalline silicon layer has a larger average crystal grain size and lower resistance than the second crystalline silicon layer, the entire region of the channel layer has an average grain size of the second crystalline silicon layer. Thus, the transverse resistance can be lowered and the on-current can be increased. Therefore, a region having a large average particle size and a region having a small average particle size in the channel layer can be formed according to a desired thin film transistor design, such as emphasizing on-current or emphasizing off-current. As a result, both excellent on characteristics and off characteristics can be achieved.

  According to this aspect, the low resistance crystalline silicon layer occupies all of the channel length defined by the width of the channel protective layer. Therefore, even when the source electrode and the drain electrode are non-uniformly arranged with respect to the underlying channel protection layer, the distance from the low resistance crystalline silicon layer to the source electrode in the channel path and the low resistance in the channel path The distance from the crystalline silicon layer to the drain electrode is uniform, and the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

  In the seventh step, the wavelength of the laser beam may be not less than 473 nm and not more than 561 nm.

  According to this aspect, the channel protective layer, the non-crystalline silicon layer, and the gate insulating layer can easily cause an interference effect of laser light inside, and the convex portion of the channel layer and the lower portion thereof and the both sides thereof It is possible to easily cause a difference in the absorption rate of the laser light between the portions.

  Alternatively, in the seventh step, the wavelength of the laser light is 473 nm, and in the sixth step, from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer. The convex portion may be formed so that the film thickness is 13 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the convex portion of the amorphous silicon layer.

  Alternatively, in the seventh step, the wavelength of the laser beam is 532 nm, and in the sixth step, from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer. The convex portion may be formed so that the film thickness is 15 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of the convex portion of the amorphous silicon layer.

  Alternatively, in the seventh step, the wavelength of the laser beam is 561 nm, and in the sixth step, from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer. The protrusion may be formed so that the film thickness is 16 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the protrusion of the amorphous silicon layer.

  According to this aspect, the convex portion of the channel layer can be a polycrystalline silicon layer, and the portions on both sides of the convex portion of the channel layer can be an amorphous silicon layer or a microcrystalline silicon layer.

  In the seventh step, the laser light absorptance of the convex portion of the amorphous silicon layer and a portion below the convex portion, and the laser light of the portions on both sides of the convex portion of the amorphous silicon layer The difference from the absorption rate may be 3% or more.

  According to this aspect, the convex portion of the channel layer can be a polycrystalline silicon layer, and the portions on both sides of the convex portion of the channel layer can be an amorphous silicon layer or a microcrystalline silicon layer.

  In the seventh step, the wavelength of the laser beam is 473 nm, and in the sixth step, from the bottom surface of the amorphous silicon layer to the upper surfaces of both sides of the convex portion of the amorphous silicon layer. The convex portion may be formed so that the film thickness is 4 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of the convex portion of the amorphous silicon layer. Specifically, in the sixth step, the film thickness from the bottom surface of the amorphous silicon layer to the top surfaces of both sides of the convex portion of the amorphous silicon layer is 27 nm or less and greater than 0 nm, The convex portion may be formed so that the film thickness from the bottom surface of the crystalline silicon layer to the upper surface of the convex portion of the amorphous silicon layer is 35 nm or more.

  Alternatively, in the seventh step, the wavelength of the laser beam is 532 nm, and in the sixth step, from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer. The convex portion may be formed so that the film thickness is 5 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of the convex portion of the amorphous silicon layer. Specifically, in the sixth step, the film thickness from the bottom surface of the amorphous silicon layer to the top surfaces of both sides of the convex portion of the amorphous silicon layer is 30 nm or less and greater than 0 nm, The convex portion may be formed so that the film thickness from the bottom surface of the crystalline silicon layer to the upper surface of the convex portion of the amorphous silicon layer is 40 nm or more.

  Alternatively, in the seventh step, the wavelength of the laser beam is 561 nm, and in the sixth step, from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer. The convex portion may be formed so that the film thickness is 5 nm or more thinner than the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of the convex portion of the amorphous silicon layer. Specifically, in the sixth step, a film thickness from the bottom surface of the non-crystalline silicon layer to the top surfaces of both sides of the convex portion of the non-crystalline silicon layer is 32 nm or less and greater than 0 nm, The convex portion may be formed so that the film thickness from the bottom surface of the crystalline silicon layer to the upper surface of the convex portion of the amorphous silicon layer is 42 nm or more.

  According to this aspect, the convex portion of the channel layer and the portion below it can be a polycrystalline silicon layer, and the portions on both sides of the convex portion of the channel layer can be an amorphous silicon layer or a microcrystalline silicon layer.

  In the seventh step, the laser light absorptance of the convex portion of the amorphous silicon layer and the portion below the convex portion is 30% or more, and the both sides of the convex portion of the amorphous silicon layer are The absorption rate of the laser light in the portion may be 20% or less.

  According to this aspect, the convex portion of the channel layer can be a polycrystalline silicon layer, and the portions on both sides of the convex portion of the channel layer can be an amorphous silicon layer or a microcrystalline silicon layer.

  Further, in the seventh step, the refractive index of the amorphous silicon layer is integrated to the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of both sides of the convex portion of the amorphous silicon layer. The value obtained by dividing the optical film thickness of the amorphous silicon layer by the wavelength of the laser beam is 0.286 or less, and the value of the amorphous silicon layer from the bottom surface of the amorphous silicon layer is 0.286 or less. The value obtained by dividing the optical film thickness of the amorphous silicon layer, which is a value obtained by integrating the refractive index of the amorphous silicon layer with the film thickness up to the top surface of the convex portion, is 0.381. It may be the above.

  According to this aspect, the absorptivity of the laser light of the convex part of the amorphous silicon is set to 30% or more, and the absorptivity of the laser light at both sides of the convex part of the amorphous silicon layer is set to 20% or less. Can do.

  In the seventh step, l and m are integers starting from 0, and the amorphous silicon layer has a thickness from the bottom surface of the amorphous silicon layer to the top surface of the convex portion of the amorphous silicon layer. A value obtained by dividing the optical film thickness of the amorphous silicon layer, which is a value obtained by integrating the refractive index of the above, is X, and a value obtained by dividing the optical film thickness of the amorphous silicon layer by the wavelength of the laser beam is X. The value obtained by dividing the optical film thickness of the gate insulating layer, which is an integrated value, by the wavelength of the laser beam is Y, and X and Y satisfy the following (Equation 1) and (Equation 2). Good.

(Formula 1) 0.50 m ≦ Y ≦ 0.40 + 0.50 m
(Formula 2) -4.00 (X-0.50 l) + 1.92 + 0.50 m≤Y≤-4.00 (X-0.50 l) + 2.68 + 0.50 m

  According to this aspect, the absorption rate of the laser beam of the convex portion of the amorphous silicon can be set to 50% or more, for example, including the maximum absorption rate.

  In the third step, the gate insulating layer including a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer may be formed. Specifically, the gate insulating layer includes a capacitance of a series capacitor formed by the silicon nitride layer and the silicon oxide layer, and a capacitance of a single silicon oxide layer having a thickness of 100 nm to 140 nm. May be formed in such a film thickness that becomes equal to each other.

  According to this aspect, the gate insulating layer has a two-layer structure, and the absorptivity of the laser light at the convex portion of the amorphous silicon and the portion below it can be increased. As a result, for example, the average grain size of the crystal in the convex portion of the channel layer and the portion below the channel layer can be increased to increase the on-current.

  Further, in the seventh step, n is an integer starting from 0, and the refraction of the non-crystalline silicon layer is from the bottom surface of the non-crystalline silicon layer to the top surface of the convex portion of the non-crystalline silicon layer. A value obtained by dividing the optical film thickness of the non-crystalline silicon layer, which is a value obtained by dividing the rate by the wavelength of the laser beam, is X, and a gate insulating layer composed of a silicon nitride layer and a silicon oxide layer is formed of silicon oxide. A value obtained by dividing the optical film thickness converted by the refractive index of the layer by a value obtained by integrating the refractive index of the silicon oxide layer and the wavelength of the laser beam is defined as Y, where X and Y are the following (Equation 3) and (Equation 4) or (Equation 5) and (Equation 6) may be satisfied.

(Formula 3) 0.226 ≦ Y ≦ 0.26
(Formula 4) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 5) 0.340 ≦ Y ≦ 0.543
(Expression 6) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28

  According to this aspect, in the configuration in which the gate insulating layer has a two-layer structure, the absorption rate of the laser light including the maximum absorption rate and the convex portion of the amorphous silicon and the lower portion thereof is set to, for example, 50% or more. be able to.

  In the sixth step, a value obtained by dividing the optical film thickness of the channel protective layer, which is a value obtained by adding the refractive index of the channel protective layer to the film thickness of the channel protective layer, by the wavelength of the laser beam is Z And k is an integer starting from 0, and Z may satisfy the following (formula 7).

  (Expression 7) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7)

  According to this aspect, the channel protective layer functions as an antireflection film for laser light, and can increase the laser light absorption rate of amorphous silicon. The degree of increase in the absorptance varies periodically with respect to the film thickness of the channel protective layer, but the range in which the absorptance increases in particular is expressed by (Equation 7) using the optical film thickness of the channel protective layer. Therefore, by forming a channel protective layer that satisfies (Equation 7), it is possible to increase the absorption efficiency of the convex portion of the channel layer and the laser light below it.

  In the sixth step, the convex portion may be formed so that a film thickness from the bottom surface of the amorphous silicon layer to the top surface of the convex portion of the amorphous silicon layer is 100 nm or less.

  When the amorphous silicon layer at the convex portion is extremely thick, the laser light is transmitted through the amorphous silicon layer in the thickness direction and attenuated until it reaches directly above the gate insulating layer serving as a current path. However, by setting the film thickness of the amorphous silicon layer to 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer and crystallizes to the amorphous silicon layer directly above the gate insulating layer serving as a current path. be able to. Thereby, the subthreshold swing characteristic of the thin film transistor can be improved.

  Further, in the sixth step, the convex portion is formed so that a film thickness from the bottom surface of the amorphous silicon layer to the upper surface of both sides of the convex portion of the amorphous silicon layer is 10 nm or more. May be.

  When the amorphous silicon layer on both sides of the convex part is extremely thin, the absorption rate of the laser light by the amorphous silicon layer is low, so most of the energy of the laser light transmitted through the amorphous silicon layer is It is thrown into the gate electrode and the gate electrode is damaged. However, by setting the thickness of the amorphous silicon layer to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented.

  Further, in the sixth step, the convex portion in which the side surface of the lower amorphous silicon layer and the side surface of the upper channel protective layer are flush with each other may be formed.

  Moreover, the said board | substrate with which the undercoat layer was formed in the said 1st process may be prepared, and the said gate electrode may be formed on the said undercoat layer in the said 2nd process.

  According to this aspect, the intrusion of impurities contained in the substrate into the channel layer can be suppressed.

  In the second step, a metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal may be formed as the gate electrode.

  In the third step, a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the gate insulating layer.

  According to this aspect, the light absorption of the laser light by the gate insulating layer can be suppressed, and the absorption rate of the laser light at the convex part of the amorphous silicon and the part below the amorphous silicon can be increased.

  In the third step, a silicon oxide layer may be formed as the gate insulating layer.

  In the third step, a silicon nitride layer may be formed as the gate insulating layer.

  In the fifth step, a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the channel protective layer.

  According to this aspect, the absorption of laser light by the channel protective layer can be suppressed, and the absorption rate of the laser light at the convex part of the amorphous silicon and the part below it can be increased.

  In the fifth step, a silicon oxide layer may be formed as a channel protective layer.

  In the fifth step, a silicon nitride layer may be formed as a channel protective layer.

  In the seventh step, the laser light may be light in a continuous oscillation mode or a pseudo continuous oscillation mode.

  In the seventh step, the laser light may be light emitted from a solid-state laser device.

  In the seventh step, the laser light may be light emitted from a laser apparatus using a semiconductor laser element.

  In the seventh step, the fluctuation of the irradiation energy density of the laser beam on the amorphous silicon layer may be less than 5%.

  According to this aspect, it is possible to suppress variations in channel layer characteristics caused by laser light.

  Further, in the seventh step, laser light may be irradiated to the convex portion of the amorphous silicon layer, a portion below the convex portion, and portions on both sides of the convex portion at a constant scanning speed.

  A display device according to one embodiment of the present invention is a display device including a liquid crystal panel or an organic EL panel, and includes the thin film transistor. The thin film transistor includes the liquid crystal panel when the display device includes the liquid crystal panel. The organic EL panel is driven when the display device includes the organic EL panel.

  According to this aspect, it is possible to achieve both excellent on-characteristics and excellent off-characteristics, and to make the electrical characteristics symmetrical with respect to the replacement of the source electrode and the drain electrode.

  Hereinafter, a thin film transistor, a manufacturing method thereof, and a display device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
First, the thin film transistor according to the first embodiment of the present invention will be described below.

  FIG. 1 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this embodiment.

  This thin film transistor is a channel protection type bottom gate thin film transistor for a display device, and includes a substrate 100, a gate electrode 110 formed on the substrate 100, a gate insulating layer 120 formed on the gate electrode 110, The crystalline silicon layer 131 formed on the gate insulating layer 120 above the gate electrode 110 and the crystalline silicon layer 131 formed on both sides of the crystalline silicon layer 131 on the gate insulating layer 120. A thinner amorphous silicon layer (amorphous silicon) 130, a channel protective layer 140 formed on the crystalline silicon layer 131, the upper surface of the end of the channel protective layer 140, the channel protective layer 140, and the crystallinity Along the side surface of the silicon layer 131 and the top surface of the amorphous silicon layer 130, the amorphous silicon layer 13 Comprising one of a drain electrode 172 formed above the other of the source electrode 171 and the amorphous silicon layer 130 formed over the. Furthermore, a contact layer 162 formed between the amorphous silicon layer 130 and the source electrode 171 and a contact layer 161 formed between the amorphous silicon layer 130 and the drain electrode 172 are provided.

  Next, the thin film transistor of FIG. 1 will be described in detail.

  The substrate 100 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass. Note that in order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the crystalline silicon layer 131 and the amorphous silicon layer 130, silicon nitride (SiNx), silicon oxide (SiOy) is formed on the surface. Or a substrate on which an undercoat layer made of silicon oxynitride film (SiOyNx) or the like is formed. In addition, the undercoat layer may play a role of reducing the influence of heat on the substrate 100 in a high-temperature heat treatment process such as laser annealing. The film thickness of the undercoat layer is, for example, about 100 nm to 2000 nm.

  The gate electrode 110 has a single layer structure or a multilayer structure such as a conductive material that can withstand the melting point temperature of silicon or an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W) , Ta (tantalum), Nb (niobium), Ni (nickel), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW), etc. are formed on the substrate 100 and patterned into a predetermined shape. It is formed. The thickness of the gate electrode 110 is preferably 30 nm to 300 nm, more preferably 50 nm to 100 nm. This is because if the thickness of the gate electrode 110 is small, the transmittance of the gate electrode 110 increases, and the reflection of the laser beam is likely to decrease. On the other hand, when the thickness of the gate electrode 110 is large, the coverage of the gate insulating layer 120 is lowered, and in particular, the characteristics of the thin film transistor are deteriorated such that the gate insulating layer 120 is disconnected at the end of the gate electrode 110. This is because it becomes easier.

  The crystalline silicon layer 131 and the amorphous silicon layer 130 are semiconductor layers formed over the gate insulating layer 120 and constitute a channel layer in which carrier movement is controlled by the voltage of the gate electrode 110. The crystalline silicon layer 131 is formed of a crystalline silicon layer such as a polycrystalline silicon layer, and is made polycrystalline by irradiating a part of amorphous silicon of the amorphous silicon layer 130 with a laser. Formed). Note that the crystalline silicon layer 131 can be a silicon layer having a mixed crystal structure of amorphous silicon and a crystalline silicon layer.

  Note that the average particle diameter of crystals contained in the crystalline silicon layer 131 is 10 nm or more and 1 μm or less.

  The channel layer has a convex part and a flat part on the surface. In the channel layer, the film thickness (film thickness of the flat portion) from the bottom surface of the channel layer (the bottom surfaces of the crystalline silicon layer 131 and the amorphous silicon layer 130) to the surface of the flat portion (the upper surface of the amorphous silicon layer 130). Is thinner than the film thickness (film thickness of the convex portion) from the bottom surface of the channel layer to the upper surface of the convex portion (the upper surface of the crystalline silicon layer 131). Further, the convex portion of the channel layer is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110. That is, the gate length (channel length) of the gate electrode 110 is longer than the length of the channel layer in the gate length direction. Thus, both sides of the convex portion of the channel layer, that is, the flat portion of the channel layer serve as a charge transfer path.

  The gate insulating layer 120 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride film, aluminum oxide (AlOz), tantalum oxide (TaOw), or a laminated film thereof, and covers the gate electrode 110 on the substrate 100 so as to cover it. It is formed on the substrate 100 and the gate electrode 110.

  Note that since crystalline silicon is used for the channel layer, the gate insulating layer 120 is preferably formed using silicon oxide. This is because it is preferable to make the interface state between the channel layer and the gate insulating layer 120 good in order to maintain good threshold voltage characteristics in the TFT.

  The channel protective layer 140 is a protective film that protects the channel layer, and is formed on the upper surface of the convex portion of the channel layer. The side surface of the channel protective layer 140 is flush with the side surface of the crystalline silicon layer 131 (the side surface of the convex portion of the channel layer). The channel protective layer 140 functions as a channel etching stopper (CES) layer for preventing the channel layer from being etched during the etching process when forming the pair of contact layers 161 and 162. However, the upper portion of the channel protective layer 140 is etched by etching when patterning the contact layers 161 and 162 (not shown).

  The channel protective layer 140 is an inorganic material layer mainly composed of an inorganic material such as silicon oxide or silicon nitride. Note that the channel protective layer 140 has an insulating property, and the pair of contact layers 161 and 162 are not electrically connected to each other.

  The pair of contact layers 161 and 162 is made of an amorphous semiconductor layer containing impurities at a high concentration or a polycrystalline semiconductor layer containing impurities at a high concentration, and a part of the contact layers 161 and 162 is located above the channel layer with a channel protection layer 140 interposed therebetween. The other part is formed on and in contact with the channel layer. Further, the pair of contact layers 161 and 162 are arranged to face each other with a predetermined interval on the channel protective layer 140.

  Each of the pair of contact layers 161 and 162 is formed so as to extend from the upper surface of the channel protective layer 140 to the flat portion of the channel layer, and the upper surface and side surfaces of the channel protective layer 140 and the convex portion of the channel layer. Are formed so as to cover the side surfaces and the upper surface of the flat portion. More specifically, the two contact layers 161 and 162 are separately provided on both sides of the convex portion of the channel layer, and are formed on the upper surface and the side surface of the end portion of the channel protective layer 140 and the channel layer formed on the side surface of the channel protective layer 140. And the upper surface of the flat portion of the channel layer extending from the side surface of the convex portion of the channel layer.

The pair of contact layers 161 and 162 is, for example, an n-type semiconductor layer in which amorphous silicon is doped with phosphorus (P) as an impurity, and a high-concentration impurity of 1 × 10 ¹⁹ [atm / cm ³ ] or more is formed. Including n ⁺ layer. Each of the contact layers 161 and 162 can have a film thickness of, for example, 5 nm to 100 nm.

  The pair of the source electrode 171 and the drain electrode 172 includes an upper surface and a side surface of the end portion of the channel protective layer 140, a side surface of the convex portion of the channel layer that extends from the side surface of the channel protective layer 140, and a channel It is formed along the upper surface of the flat portion of the layer. In addition, the pair of source electrode 171 and drain electrode 172 are provided to be separated from each other.

  The pair of source electrode 171 and drain electrode 172 is formed above the channel layer, and is formed on the corresponding contact layer 161 or 162, respectively. That is, the source electrode 171 is formed on the pair of contact layers 162, and the drain electrode 172 is formed on the contact layer 161.

  The source electrode 171 and the drain electrode 172 can each have a single layer structure or a multilayer structure made of a conductive material or an alloy thereof, for example, aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), silver (Ag), copper (Cu), titanium (Ti), or chromium (Cr). Further, the source electrode 171 and the drain electrode 172 can have a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 171 and the drain electrode 172 is, for example, about 100 nm to 500 nm.

  Hereinafter, the manufacturing method of the thin film transistor according to the present embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the present embodiment.

  The thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate A fourth step of forming the amorphous silicon layer 130 on the insulating layer 120, a fifth step of forming the channel protective layer 140 on the amorphous silicon layer 130, and the amorphous silicon layer 130 and the channel protective layer 140 , A sixth step of forming a convex portion in which the upper layer is the channel protective layer 140 and the lower layer is the amorphous silicon layer 130, and the laser light is projected to the convex portion and convex portion of the amorphous silicon layer 130. The portions below the projections and the portions on both sides of the projections are irradiated to form the crystalline silicon layer 131 at the projections and the portions below the projections of the amorphous silicon layer 130. A seventh step in which portions on both sides of the convex portion of the con layer 130 remain as the amorphous silicon layer 130, an upper surface of the end portion of the channel protective layer 140, side surfaces of the channel protective layer 140 and the crystalline silicon layer 131, and non- An eighth step of forming a source electrode 171 on one side of the amorphous silicon layer 130 and a drain electrode 172 on the other side of the amorphous silicon layer 130 along the upper surface of the crystalline silicon layer 130; In the seventh step, the absorption rate of the amorphous silicon layer 130 with respect to the laser light is the absorption of the convex portion of the amorphous silicon layer 130 and the portion below the convex portion corresponding to the lower portion of the channel protective layer 140. The rate is larger than the absorption rate of the portions on both sides of the convex portion of the amorphous silicon layer 130.

  Next, a method for manufacturing the thin film transistor of FIG. 2 will be described in detail.

  First, as shown in FIG. 2A, a glass substrate is prepared as the substrate 100. Before forming the gate electrode 110, an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the surface of the substrate 100 by plasma CVD (Chemical Vapor Deposition) or the like. . The undercoat layer is preferably a silicon oxide film (SiOy) of 1.5 <y <2.0, and has a thickness of 300 nm to 1500 nm. A more preferable thickness range of the undercoat layer is 500 nm or more and 1000 nm or less. This is because if the thickness of the undercoat layer is increased, the thermal load on the substrate 100 can be reduced, but if it is too thick, film peeling or cracking occurs.

Next, as shown in FIG. 2B, a gate electrode 110 having a predetermined shape is formed on the substrate 100. For example, a gate metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal is formed on the substrate 100 by sputtering as the gate electrode 110, and the gate metal film is formed using a photolithography method and a wet etching method. The gate electrode 110 having a predetermined shape can be formed by patterning. MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and water are mixed in a predetermined composition. In the case where an undercoat layer is formed on the surface of the substrate 100, the gate electrode 110 is formed on the undercoat layer.

  Next, as illustrated in FIG. 2C, a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110. For example, a silicon oxide layer or a silicon nitride layer is formed as the gate insulating layer 120 over the gate electrode 110 by a plasma CVD method.

  Next, as shown in FIG. 2D, an amorphous silicon layer 130 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do.

  Next, as shown in FIG. 2E, a channel protective layer 140 made of silicon oxide is formed on the amorphous silicon layer 130 by plasma CVD or the like.

  Next, as shown in FIG. 2F, the amorphous silicon layer 130 and a part of the channel protective layer 140 are continuously removed by etching. This removal is performed even after the channel protective layer 140 is removed and the amorphous silicon layer 130 is exposed on the surface. Therefore, a convex part and a flat part are formed in the amorphous silicon layer 130, and the channel protective layer 140 remains on the convex part. Since the etching of the amorphous silicon layer 130 and the channel protective layer 140 is continuously performed, that is, a convex portion is formed by self-alignment, the side surface of the lower amorphous silicon layer 130 and the upper channel protective layer 140 are formed. A convex portion is formed which is flush with the side surface.

  Next, as shown in FIG. 2G, the amorphous silicon layer 130 is formed into a crystalline silicon layer 131 by laser annealing. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 130 is crystallized using the laser beam to generate the crystalline silicon layer 131. More specifically, first, the formed amorphous silicon layer 130 is subjected to dehydrogenation treatment (dehydrogenation annealing treatment at a temperature of 400 ° C. or higher, which is a temperature at which hydrogen escapes from the amorphous silicon layer 130). carry out. After that, the amorphous silicon layer 130 is made polycrystalline (including microcrystals) by laser annealing to form a crystalline silicon layer 131.

  At this time, the laser beam scans the amorphous silicon layer 130 in the order of one flat portion, the convex portion, and the other flat portion of the amorphous silicon layer 130, and the film thickness of the flat portion is the film thickness of the convex portion. Since it is thinner, the absorption rate of the laser beam in the flat portion is low. Therefore, in the non-crystalline silicon layer 130, the convex portion and the lower portion thereof are crystallized to form the crystalline silicon layer 131, but the flat portions on both sides of the convex portion are not crystallized, and the amorphous silicon layer 131 is not crystallized. Layer 130 remains. As a result, only the convex portion of the amorphous silicon layer 130 and the lower portion thereof are selectively crystallized, and the crystalline silicon layer 131 is selectively formed only on the convex portion of the amorphous silicon layer 130 and the lower portion thereof. Can be formed.

  The laser light source of the laser light is a laser having a wavelength in the visible light region. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and is preferably a green laser having a wavelength of 473 nm to 561 nm. The laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 130 is irradiated with the laser light discontinuously. This is because the amorphous silicon layer 130 cannot always be kept in a molten state. The reason why the quasi-continuous oscillation mode is also included is that the amorphous silicon layer 130 can be maintained in its molten state by applying a pulse and reheating it before it is cooled to below its melting point. Therefore, a preferred mode of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 130 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained. Further, the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element. In any case, it is preferable because laser light can be controlled with high accuracy. Further, the laser light having a wavelength in the visible light region is irradiated on the non-crystalline silicon layer 130 with the laser light when irradiated on the non-crystalline silicon layer 130 in order to form the crystalline silicon layer 131 without crystal unevenness. It is preferable if the fluctuation of the energy density is less than 5%. By forming the crystalline silicon layer 131 having no crystal unevenness, the initial design characteristics of the thin film transistor can be achieved, and the characteristics can be made uniform.

  In addition, when the non-crystalline silicon layer 130 is extremely thick, the laser light is transmitted through the non-crystalline silicon layer 130 in the thickness direction and attenuated until it reaches the top of the gate insulating layer 120 serving as a current path. End up. However, by setting the film thickness of the amorphous silicon layer 130 to 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer 130 and the amorphous silicon layer 130 immediately above the gate insulating layer 120 serving as a current path. Can be crystallized. Accordingly, in the step of FIG. 2F, the convex portion is formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 is 100 nm or less. preferable.

  In addition, when the amorphous silicon layer 130 on both sides of the convex portion of the amorphous silicon layer 130 is extremely thin, the absorption rate of the laser light by the amorphous silicon layer 130 is lowered. Therefore, most of the energy of the laser light transmitted through the amorphous silicon layer 130 is input to the gate electrode 110, and the gate electrode 110 is damaged. However, by setting the thickness of the amorphous silicon layer 130 to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented. Therefore, in the process of FIG. 2F, the protrusions are formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the upper surfaces of both sides of the protrusions of the amorphous silicon layer 130 is 10 nm or more. It is preferred that

  Further, in order to suppress the laser light from being absorbed by the gate insulating layer 120 and increase the absorption rate of the laser light of the amorphous silicon layer 130, the process of FIG. A film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light is preferably formed as the gate insulating layer 120.

  Further, in order to prevent the laser light from being absorbed by the channel protective layer 140 and increase the absorptance of the laser light of the amorphous silicon layer 130, in the step of FIG. 2E, the step of FIG. A film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light is preferably formed as the channel protective layer 140.

  The amorphous silicon layer 130 is irradiated with linearly focused laser light. There are, for example, two irradiation methods, one of which is a fixed irradiation position of the linearly focused laser light. There is a method of moving the stage on which the substrate 100 on which the amorphous silicon layer 130 is formed is moved, and the other is a method in which the stage is fixed and the irradiation position of the laser beam is moved. In any method, the laser beam is irradiated while moving relative to the amorphous silicon layer 130. As described above, the amorphous silicon layer 130 irradiated with the laser light absorbs the energy of the laser light and rises in temperature to be crystallized to become the crystalline silicon layer 131.

  Next, as illustrated in FIG. 2H, a contact layer 160 to be the contact layers 161 and 162 is formed so as to extend from the upper surface of the channel protective layer 140 to the flat portion of the amorphous silicon layer 130. Specifically, for example, by plasma CVD so as to cover the upper surface and side surface of the channel protective layer 140 and the side surface of the convex portion of the crystalline silicon layer 131 and the upper surface of the flat portion of the amorphous silicon layer 130. A contact layer 160 made of amorphous silicon doped with an impurity of a pentavalent element such as phosphorus is formed.

  Next, as illustrated in FIG. 2I, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160. For example, the source / drain metal film 170 having a three-layer structure of MoW / Al / MoW is formed by sputtering.

  Next, although not shown, in order to form the source electrode 171 and the drain electrode 172 having a predetermined shape, a resist material is applied onto the source / drain metal film 170, exposed and developed, and then patterned into a predetermined shape. Form. Thereafter, as shown in FIG. 2J, etching is performed using this resist as a mask to pattern the source / drain metal film 170, thereby forming a source electrode 171 and a drain electrode 172 having predetermined shapes. At this time, the contact layer 160 functions as an etching stopper. Thereafter, the resist on the source electrode 171 and the drain electrode 172 is removed, and dry etching is performed using the source electrode 171 and the drain electrode 172 as a mask, thereby patterning the contact layer 160 and patterning the channel layer in an island shape. Thereby, a pair of contact layers 161 and 162 having a predetermined shape and an island-shaped channel layer can be formed.

  Hereinafter, the characteristics of the thin film transistor according to the present embodiment will be described with reference to FIGS.

  FIG. 3 is a diagram illustrating a change in current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed. FIG. 3 shows the characteristics when a voltage of 12 V is applied between the source and drain, the horizontal axis shows the gate-source voltage, and the vertical axis shows the source-drain current.

  In the thin film transistor of FIG. 1, the channel layer is composed of the amorphous silicon layer 130 and the crystalline silicon layer 131. However, the channel layer is composed of only the amorphous silicon layer 130 and only the crystalline silicon layer 131. The channel layer exhibits different characteristics when the channel layer is configured. That is, as shown in FIG. 3, when the channel layer is formed of only the amorphous silicon layer 130, the off characteristics are good, but the on characteristics are bad. On the other hand, when the channel layer is composed of only the crystalline silicon layer 131, the off characteristics are poor, but the on characteristics are good.

  The thin film transistor of FIG. 1 uses the change in characteristics due to the difference in crystallinity in FIG. 3 to achieve both good off characteristics and on characteristics. That is, the convex portion of the channel layer below the channel protective layer 140 and the portion below the channel protective layer 140 are all made of the crystalline silicon layer 131 to increase the on-current, and the portions on both sides of the convex portion of the channel layer are made of the amorphous silicon layer 130. This is to reduce off current (leakage current).

  FIG. 4A shows the crystallinity of the crystalline silicon layer 131 when the laser light absorptivity of the amorphous silicon layer 130 and the scan speed of the laser light are changed in the laser annealing in the step of FIG. It is a figure which shows the change of.

  Note that changing the absorptance of the amorphous silicon layer 130 is realized by changing the thickness of the amorphous silicon layer 130, that is, the thickness of the channel layer.

4A, a sample is used in which the laser output is 60 kW / cm ² , the gate electrode 110 is 50 nm thick MoW, and the gate insulating layer 120 is 120 nm thick silicon oxide.

  In FIG. 4A, “a-Si” indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon, and “SPC” indicates the average grain size of the crystalline silicon layer 131. “Ex & .SPC” indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm, and “p-Si” indicates the crystalline silicon layer. The average particle size of 131 is about 60 nm or more and 1 μm or less, and “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.

  As shown in FIG. 4A, different crystalline silicon layers can be formed by changing the scanning speed of laser annealing and the absorption rate of the amorphous silicon layer 130. Even in the case where the scanning speed is constant, in the step of FIG. 2 (f), in the step of FIG. By making the difference between the absorption ratios of the laser light on both sides of the part 1% or more, an amorphous silicon layer and a crystalline silicon layer can be formed simultaneously by one laser scan, and the channel layer The projecting crystalline silicon layer 131 and the amorphous silicon layers 130 on both sides of the projecting section can be formed.

  Note that the absorptance of the amorphous silicon layer 130 depends on the configuration, thickness and optical constant of the channel protective layer 140, the thickness and optical constant of the amorphous silicon layer 130, the configuration, thickness and optical constant of the gate insulating layer 120. It is derived by optical calculation taking into account multiple interference of laser light, using the constant and the optical constant of the metal material forming the underlying gate electrode 110 as parameters. Hereinafter, examples of optical calculation will be described in detail.

  FIG. 4B is a diagram for explaining a method for calculating the light absorption rate of the amorphous silicon layer 130.

FIG. 4B shows a model structure of a multilayer structure in which the structure of the thin film transistor shown in FIG. 1 is modeled. In the model structure shown in FIG. 4B, a layer 401 of the complex refractive index _{N 1,} and 402 of the complex refractive index _{N 2,} a layer 403 of the complex refractive index _{N 3,} a layer 404 of the complex refractive index _{N 4,} the complex index of refraction N ₅ substrate 405. In this model structure, a layer 404, a layer 403, a layer 402, and a layer 401 are stacked on the substrate 405 in this order. Further, the region of the complex refractive index N ₀ shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. This region is, for example, air. In this case, the refractive index is 1 and the extinction coefficient is 0.

  The substrate 405 is an insulating substrate made of, for example, transparent glass or quartz, and has a refractive index of 1.46, for example, and corresponds to the substrate 100 shown in FIG. The layer 404 is made of, for example, 50 nm MoW having a refractive index of 3.47 and an extinction coefficient of 3.78, and corresponds to the gate electrode 110 shown in FIG. The layer 403 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the gate insulating layer 120 shown in FIG. The layer 402 corresponds to the amorphous silicon layer 130 having a refractive index of 5.074 and an extinction coefficient of 0.621, for example. The layer 401 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the channel protective layer 140 shown in FIG.

As shown in FIG. 4B, the amplitude reflection coefficient for light incident on the layer 401 from the outside is r ₀₁ , the amplitude reflection coefficient for light incident on the layer 401 from the layer 401 is r ₁₂ , and the amplitude reflection coefficient is incident on the layer 401 from the layer 402. R ₂₃ is the amplitude reflection coefficient with respect to the incident light, and r ₃₄ is the amplitude reflection coefficient with respect to the light incident on the layer 404 from the layer 403. Further, the amplitude transmission coefficient of light incident on the layer 401 from the outside is t ₀₁ , the amplitude transmission coefficient of light incident on the layer 402 from the layer 401 is t ₁₂ , and the amplitude transmission of light incident on the layer 402 from the layer 402 The coefficient is t ₂₃ , and the amplitude transmission coefficient of light incident on the layer 404 from the layer 403 is t ₃₄ .

Further, the amplitude reflection coefficients of the entire layers above the region where the layer 404 corresponding to the gate electrode 110 is formed are r ₀₁₂₃₄ (R1), r ₁₂₃₄ (R2), and r ₂₃₄ (R3), respectively. Specifically, the amplitude reflection coefficient when the layers 404 and 403 are regarded as one layer is r ₂₃₄ (R3). Similarly, the amplitude reflection coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer is r ₁₂₃₄ (R2), and the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer. The reflection coefficient is r ₀₁₂₃₄ (R1). In addition, the amplitude transmission coefficients of the entire layers in the first region are t ₀₁₂₃₄ (T1), t ₁₂₃₄ (T2), and t ₂₃₄ (T3), respectively. Specifically, the amplitude transmission coefficient when the layers 404 and 403 are regarded as one layer is t ₂₃₄ (T3). Similarly, t ₁₂₃₄ (T2) is an amplitude transmission coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer, and the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer. The transmission coefficient is t ₀₁₂₃₄ (T1).

  Then, the amplitude reflection coefficient and amplitude transmission coefficient of each layer in the first region can be expressed by the following (Expression 12) to (Expression 17).

  In addition, the amplitude reflection coefficient and amplitude transmission coefficient of each layer in the second region can be expressed by the following (Expression 18) to (Expression 23).

  here,

であり、ｄは各層の膜厚、θは各層での入射角・透過角、λはレーザー光の波長である。

Where d is the film thickness of each layer, θ is the incident angle / transmission angle in each layer, and λ is the wavelength of the laser beam.

  Further, θ can be calculated as shown below from Snell's law of the following equation.

The amplitude reflection coefficients r ₀₁ , r ₁₂ , r ₂₃ , r ₃₄ , r ₃₅ and the amplitude transmission coefficients t ₀₁ , t ₁₂ , t ₁₂ , t ₃₄ , t _{35 of each layer} are expressed by the following (formula 24) to (formula). 33).

  Here, the light is monochromatic laser light, and its polarization is assumed to be P-polarized light.

Next, using the above equations, the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer in the first region are calculated as follows. That is, first, r ₂₃₄ is calculated by substituting (Equation 26) and (Equation 27) into (Equation 14). Next, r ₁₂₃₄ is calculated by substituting (Equation 25) and r ₂₃₄ into (Equation 13). Next, r ₀₁₂₃₄ is calculated by substituting (Equation 24) and r ₁₂₃₄ into (Equation 12). Next, t ₂₃₄ is calculated by substituting (Equation 26), (Equation 27), (Equation 31), and (Equation 32) into (Equation 17). Next, t ₁₂₃₄ is calculated by substituting (Equation 25), (Equation 30), r ₂₃₄ and t ₂₃₄ into (Equation 16). Next, t ₀₁₂₃₄ is calculated by substituting (Equation 24), (Equation 29), r ₁₂₃₄ and t ₁₂₃₄ into (Equation 15).

  Next, the reflectances R1, R2 and R3 and the transmittances T1, T2 and T3 in each layer are calculated by (Expression 34) to (Expression 39).

Finally, the light absorption rate A _Si for the amorphous silicon layer can be calculated by (Equation 40).

Next, using the calculation method described above, perpendicular to the model structure shown in FIG. 4B, ie theta ₀ = 0 or sin [theta ₀ = 0 is longer than the wavelength 473nm at an incident angle theta ₀ range holds an approximation, 561 nm When the following green laser light was incident, the absorptance of the laser light of the amorphous silicon layer 130 was calculated. In this case, the calculation result is the same even if the polarization of the laser beam is S polarization.

  In this example, an example of a model structure including the gate electrode 110 made of MoW, the gate insulating layer 120 made of silicon oxide, the amorphous silicon 130, and the channel protective layer 140 made of silicon oxide is shown. Modification cases such as a case where the film 120 has a laminated structure of silicon oxide and silicon nitride or a case where the channel protective layer 140 is not present can be similarly calculated by appropriately modifying the model structure of FIG. 4B. When the material of the gate electrode 110 is changed (for example, the material of the gate electrode 110 is Cu (refractive index 1.04, extinction coefficient 2.59), Al (refractive index 0.867, extinction coefficient 6.42), Mo. (When the refractive index is 3.61, extinction coefficient is 3.79), W (refractive index is 3.48, extinction coefficient is 2.72), and the material of the gate insulating layer 120 and the channel protective layer 140 is changed. (For example, when the material of the gate insulating layer 120 and the channel protective layer 140 is silicon nitride (refractive index: 1.947, extinction coefficient: 0)), it can be calculated in the same manner by appropriately changing the physical property values.

  5A to 5F show amorphous silicon when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG. FIG. 6 is a contour diagram showing the calculation result of the absorptance of the layer 130. 6A is a diagram showing a change in the absorptance of the amorphous silicon layer 130 when the thickness of the gate insulating layer 120 made of silicon oxide is 120 nm in FIGS. 5D and 5F.

  5A to 5F, the lower horizontal axis represents the optical film thickness of the amorphous silicon layer 130, that is, the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the amorphous silicon layer 130. Is divided by the wavelength of the laser beam. The left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam. For reference, the film thickness of the amorphous silicon layer 130 when the wavelength of the laser light is 532 nm without being normalized by the wavelength of the laser light is shown on the horizontal axis, and the film thickness of the gate insulating layer 120 is shown on the right side. It is shown on the vertical axis. In FIG. 6A, the value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam is shown on the horizontal axis, and the absorptance of the amorphous silicon layer 130 is shown on the vertical axis.

  5A uses a model in which the gate electrode 110 is made of Cu, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm (the channel protective layer 140 is not formed). . The calculation in FIG. 5B uses a model in which the gate electrode 110 is made of Al, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. The calculation in FIG. 5C uses a model in which the gate electrode 110 is made of Mo, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5D uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5E uses a model in which the gate electrode 110 is made of W, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is 0 nm. 5F uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the channel protective layer 140 is made of 275 nm silicon oxide.

  By the way, for example, when the refractive index of the amorphous silicon layer 130 at a wavelength of 532 nm is used, the value on the horizontal axis in FIGS. 5A to 5F can be converted into the film thickness of the amorphous silicon layer 130. FIG. 6B is a diagram illustrating an example of a value obtained by converting the value on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130. FIG. 6B shows values obtained by converting the values on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130 when the wavelength is 532 nm, when the wavelength is 473 nm, and when the wavelength is 569 nm. .

  Similarly, for example, when the refractive index of the gate insulating layer 120 at a wavelength of 532 nm is used, the value on the vertical axis in FIGS. 5A to 5F can be converted into the thickness of the gate insulating layer 120. FIG. 6C is a diagram illustrating an example of a value obtained by converting the value on the vertical axis of FIGS. 5A to 5F into the film thickness of the gate insulating layer 120 made of silicon oxide or the gate insulating layer 120 made of silicon nitride. FIG. 6C shows values obtained by converting the values on the vertical axis of FIGS. 5A to 5F into the film thickness of the gate insulating layer 120 when the wavelength is 532 nm, the wavelength is 473 nm, and the wavelength is 569 nm. 6C shows an example of values obtained by converting the values on the horizontal axis and the vertical axis into the film thickness of the channel protective layer 140 made of silicon oxide or silicon nitride or the film thickness of the gate insulating layer 120 in FIG. 7 described later. It can also be applied as a diagram shown.

  4C, the wavelength of the laser beam is 473 nm in the process of FIG. 2G regardless of the material of the gate electrode 110 and the thickness of the channel protective layer 140, and in the process of FIG. The film thickness from the bottom surface of the amorphous silicon layer 130 to the top surfaces of both sides of the convex portion of the amorphous silicon layer 130 is such that the thickness of the convex portion of the amorphous silicon layer 130 is from the bottom surface of the amorphous silicon layer 130. By forming the convex portion so as to be 4 nm or more thinner than the film thickness up to the upper surface, the crystalline silicon layer 131 of the convex portion of the channel layer and the amorphous silicon layer 130 on both sides of the convex portion can be formed. Specifically, in the process of FIG. 2F, the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surfaces of both sides of the convex portion of the amorphous silicon layer 130 is 27 nm or less and more than 0 nm, By forming the convex portion so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 is 35 nm or more, the crystalline silicon layer 131 of the convex portion of the channel layer is formed. And the amorphous silicon layer 130 on both sides of the convex portion can be formed.

  In other words, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, the wavelength of the laser beam is 532 nm in the step of FIG. 2G, and the non-crystallinity in the step of FIG. The film thickness from the bottom surface of the silicon layer 130 to the upper surface of both sides of the convex portion of the amorphous silicon layer 130 is a film from the bottom surface of the amorphous silicon layer 130 to the upper surface of the convex portion of the amorphous silicon layer 130. By forming the convex portion so as to be 5 nm or more thinner than the thickness, the crystalline silicon layer 131 on the convex portion of the channel layer and the amorphous silicon layer 130 on both sides of the convex portion can be formed. Specifically, in the step of FIG. 2F, the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surfaces of both sides of the convex portion of the amorphous silicon layer 130 is 30 nm or less and more than 0 nm, By forming the convex portion so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 is 40 nm or more, the crystalline silicon layer 131 of the convex portion of the channel layer is formed. And the amorphous silicon layer 130 on both sides of the convex portion can be formed.

  In other words, the laser light wavelength is 561 nm in the step of FIG. 2G regardless of the material of the gate electrode 110 and the thickness of the channel protective layer 140, and the non-crystalline property in the step of FIG. The film thickness from the bottom surface of the silicon layer 130 to the upper surface of both sides of the convex portion of the amorphous silicon layer 130 is a film from the bottom surface of the amorphous silicon layer 130 to the upper surface of the convex portion of the amorphous silicon layer 130. By forming the convex portion so as to be 5 nm or more thinner than the thickness, the crystalline silicon layer 131 on the convex portion of the channel layer and the amorphous silicon layer 130 on both sides of the convex portion can be formed. Specifically, in the step of FIG. 2F, the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surfaces of both sides of the convex portion of the amorphous silicon layer 130 is 32 nm or less and more than 0 nm, By forming the convex portion so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 is 42 nm or more, the crystalline silicon layer 131 of the convex portion of the channel layer is formed. And the amorphous silicon layer 130 on both sides of the convex portion can be formed.

  5A to 6C, the amorphous silicon layer 130 is formed from the bottom surface of the amorphous silicon layer 130 in the step of FIG. 2F regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140. The value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam, which is a value obtained by integrating the refractive index of the amorphous silicon layer 130 with the film thickness up to the upper surface of both sides of the convex portion of Non-crystalline property which is 0.286 or less and is a value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130. If the value obtained by dividing the optical film thickness of the silicon layer 130 by the wavelength of the laser beam is 0.381 or more, the absorptivity of the laser beam at the convex portion and the portion below the amorphous silicon layer 130 and the non-crystalline property Silicon layer 1 The difference between the laser beam absorption rate of the both side portions of the convex portions of 0 to can be 10% or more. For example, the absorptivity of the laser beam at the convex portion of the amorphous silicon layer 130 and the portion under the convex portion is 30% or more, and the absorptivity of the laser beam at the portions on both sides of the convex portion of the amorphous silicon layer 130 is 20%. It can be as follows. Therefore, the crystalline silicon layer 131 on the convex portion of the channel layer and the amorphous silicon layer 130 on both sides of the convex portion can be formed.

  5A to 5F, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, in the step of FIG. 2F, l and m are integers starting from 0, and the amorphous silicon layer The optical film thickness of the amorphous silicon layer 130, which is a value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130, A value obtained by dividing the optical film thickness of the gate insulating layer 120, which is a value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120 by the wavelength of the laser light, is X. If X and Y satisfy (Equation 1) and (Equation 2) below, the maximum absorptance is included, and the absorptivity of the laser light at the convex portion of the amorphous silicon layer 130 and the portion below the amorphous silicon layer 130 is, for example, 50% or more Can. 5A to 5F indicate ranges in which X and Y satisfy the following (formula 1) and (formula 2), respectively.

(Formula 1) 0.50 m ≦ Y ≦ 0.40 + 0.50 m
(Formula 2) -4.00 (X-0.50 l) + 1.92 + 0.50 m≤Y≤-4.00 (X-0.50 l) + 2.68 + 0.50 m

  FIG. 7 shows a protrusion of the amorphous silicon layer 130 when the thickness of the channel protective layer 140 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG. It is a contour map which shows the calculation result of the absorptivity. 8A to 8C are diagrams showing changes in the absorptance of the convex portions of the amorphous silicon layer 130 when the thickness of the channel protective layer 140 is changed.

  In FIG. 7, the lower horizontal axis represents the optical film thickness of the channel protective layer 140, that is, the value obtained by adding the refractive index of the channel protective layer 140 to the film thickness of the channel protective layer 140 divided by the wavelength of the laser beam. The value is shown. The left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam. For reference, the film thickness of the channel protective layer 140 when the wavelength of the laser light is 532 nm without being normalized by the wavelength of the laser light is shown on the horizontal axis, and the film thickness of the gate insulating layer 120 is shown on the right vertical axis. It shows. 8A to 8C, the horizontal axis represents the value obtained by dividing the optical film thickness of the channel protective layer 140 by the wavelength of the laser beam, and the vertical axis represents the absorptance of the convex portions of the amorphous silicon layer 130. .

  In the calculation of FIG. 7, the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the optical film thickness of the amorphous silicon layer 130 at the convex portion of the amorphous silicon layer 130, i.e., amorphous. The value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the convex portion of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (the thickness of the amorphous silicon layer at the wavelength of 532 nm is And a model in which the channel protective layer 140 is made of silicon oxide.

  8A, the gate electrode 110 is made of MoW, and the optical film thickness of the gate insulating layer 120, that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, A model obtained by dividing the wavelength by 0.331 (corresponding to a wavelength of 532 nm and a silicon oxide layer thickness of 120 nm) is used, and the channel protective layer 140 is made of silicon oxide.

  8A, the broken line, the two-dot chain line, and the solid line respectively indicate the refractive index of the amorphous silicon layer 130 to the optical film thickness of the amorphous silicon layer 130, that is, the film thickness of the convex portion of the amorphous silicon layer 130. The value obtained by dividing the integrated value by the wavelength of the laser beam is 0.286 (corresponding to a non-crystalline silicon layer thickness of 30 nm at a wavelength of 532 nm), 0.763 (non-crystalline silicon layer thickness of 80 nm at a wavelength of 532 nm). ) And 0.954 (corresponding to a film thickness of the amorphous silicon layer of 100 nm at a wavelength of 532 nm).

  Further, in the calculation of FIG. 8B, the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the optical film thickness of the amorphous silicon layer 130 at the convex portion of the amorphous silicon layer 130, that is, amorphous. The value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the convex portion of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (the thickness of the amorphous silicon layer at the wavelength of 532 nm is And a model in which the channel protective layer 140 is made of silicon oxide.

  8B represents the optical film thickness of the gate insulating layer 120, that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, respectively. The value divided by 0.276 (corresponding to a silicon oxide layer thickness of 100 nm at a wavelength of 532 nm), 0.552 (corresponding to a silicon oxide layer thickness of 200 nm at a wavelength of 532 nm) and 1.103 (silicon oxide at a wavelength of 532 nm). The calculation results when the layer thickness corresponds to 400 nm are shown.

  Further, in the calculation of FIG. 8C, the gate insulating layer 120 is made of silicon oxide, and the optical film thickness of the amorphous silicon layer 130 on the projection of the amorphous silicon layer 130, that is, the projection of the projection on the amorphous silicon layer 130. The value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness divided by the wavelength of the laser beam is 0.477 (corresponding to the film thickness of the amorphous silicon layer at a wavelength of 532 nm and 50 nm). A model composed of the protective layer 140 made of silicon oxide is used. And the broken line of FIG. 8C, the dashed-two dotted line, and the continuous line have shown the calculation result in case the gate electrode 110 is Cu, Al, and MoW, respectively.

  From FIG. 7 to FIG. 8C, in the process of FIG. 2 (f), the value obtained by dividing the optical film thickness of the channel protective layer 140 by the wavelength of the laser beam is Z, and k is an integer starting from 0. If Expression 3) is satisfied, the absorption efficiency of the laser light at the convex portion of the amorphous silicon layer 130 and the portion below the convex portion can be increased. In addition, A of FIG. 7 has shown the range where Z satisfy | fills the following (Formula 3). Further, k = 0, 1, and 2 in FIGS. 8A to 8C indicate the range of Z when k = 0, 1, and 2 in (Equation 3), respectively.

  (Formula 3) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7)

  As described above, according to the thin film transistor of this embodiment, the convex portion of the channel layer is formed of the crystalline silicon layer 131, and both sides of the convex portion are formed of the amorphous silicon layer 130. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.

  Even when the source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the underlying channel protective layer 140, the distance from the crystalline silicon layer 131 to the source electrode 171 in the channel path and the crystal in the channel path The distance from the conductive silicon layer 131 to the drain electrode 172 is uniform. Therefore, the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

(Second Embodiment)
Next, a thin film transistor according to a second embodiment of the present invention will be described below.

  FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this embodiment.

  The thin film transistor according to the present embodiment is different from the present embodiment in that the amorphous silicon layer 130 is replaced with the second crystalline silicon layer 230 and the crystalline silicon layer 131 is replaced with the first crystalline silicon layer 231. This is different from the thin film transistor. Hereinafter, a description will be given focusing on differences from the first embodiment.

  The thin film transistor includes a substrate 100, a gate electrode 110 formed on the substrate 100, a gate insulating layer 120 formed on the gate electrode 110, and a first insulating layer 120 formed on the gate insulating layer 120 above the gate electrode 110. One crystalline silicon layer 231 and a second crystalline silicon layer formed on both sides of the first crystalline silicon layer 231 on the gate insulating layer 120 and having a thickness smaller than that of the first crystalline silicon layer 231 230, the channel protective layer 140 formed on the first crystalline silicon layer 231, the upper surface of the end of the channel protective layer 140, the side surfaces of the channel protective layer 140 and the second crystalline silicon layer 230, and the second crystal The source electrode 171 and the second crystalline silicon layer formed on one side of the second crystalline silicon layer 230 along the upper surface of the crystalline silicon layer 230 30 and the drain electrode 172 formed above the other of the first crystalline silicon layer 231 has an average grain size larger than that of the second crystalline silicon layer 230. . Further, a contact layer 162 formed between the second crystalline silicon layer 230 and the source electrode 171 and a contact layer 161 formed between the second crystalline silicon layer 230 and the drain electrode 172 are provided.

  Next, the thin film transistor of FIG. 9 will be described in detail.

  The first crystalline silicon layer 231 and the second crystalline silicon layer 230 are semiconductor layers formed on the gate insulating layer 120 and constitute a channel layer whose carrier movement is controlled by the voltage of the gate electrode 110. . The first crystalline silicon layer 231 and the second crystalline silicon layer 230 are made of a crystalline silicon layer, and are made polycrystalline by irradiating the amorphous silicon of the amorphous silicon layer with laser. Formed). Note that the first crystalline silicon layer 231 and the second crystalline silicon layer 230 may be silicon layers having a mixed crystal structure of amorphous silicon and crystalline silicon layers.

  The average grain size of crystals contained in the first crystalline silicon layer 231 is 40 nm or more and 1 μm or less, and the average grain size of crystals contained in the second crystalline silicon layer 230 is 10 nm or more and less than 40 nm.

  The channel layer has a convex part and a flat part on the surface. In the channel layer, the film thickness (flat portion) from the bottom surface of the channel layer (bottom surfaces of the first crystalline silicon layer 231 and the second crystalline silicon layer 230) to the surface of the flat portion (upper surface of the second crystalline silicon layer 230). Is thinner than the thickness from the bottom surface of the channel layer to the top surface of the convex portion (the top surface of the first crystalline silicon layer 231) (thickness of the convex portion). Further, the convex portion of the channel layer is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110.

  The side surface of the channel protective layer 140 is flush with the side surface of the first crystalline silicon layer 231 (the side surface of the convex portion of the channel layer).

  Hereinafter, the manufacturing method of the thin film transistor according to the present embodiment will be described with reference to FIGS. FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to this embodiment.

  The thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate A fourth step of forming the amorphous silicon layer 330 on the insulating layer 120, a fifth step of forming the channel protective layer 140 on the amorphous silicon layer 330, and the amorphous silicon layer 330 and the channel protective layer 140 , A sixth step of forming a convex portion in which the upper layer is the channel protective layer 140 and the lower layer is the amorphous silicon layer 330, and the convex portion and the convex portion of the amorphous silicon layer 330 are irradiated with laser light. Is irradiated to both the lower part and the parts on both sides of the convex part, and the convex part of the amorphous silicon layer 330 and the part below the convex part are used as the first crystalline silicon layer 231, thereby A seventh step of forming the second crystalline silicon layer 230 on both sides of the convex portion of the silicon layer 330; an upper surface of the end portion of the channel protective layer 140; a side surface of the channel protective layer 140 and the first crystalline silicon layer 231; In addition, along the upper surface of the second crystalline silicon layer 230, a source electrode 171 is formed above one of the second crystalline silicon layers 230, and a drain electrode 172 is formed above the other crystalline second silicon layer 230. In the seventh step, the absorptivity of the amorphous silicon layer 330 with respect to the laser light is such that the convexity and convexity of the amorphous silicon layer 330 corresponding to the lower part of the channel protective layer 140 are The absorption rate of the lower portion is larger than the absorption rate of the portions on both sides of the convex portion of the amorphous silicon layer 330, and the average grain size of crystals contained in the second crystalline silicon layer 230 Forming a first crystalline silicon layer 231 containing heard average grain size of the crystal.

  Next, a method for manufacturing the thin film transistor of FIG. 10 will be described in detail.

  First, as shown in FIG. 10A, a glass substrate is prepared as the substrate 100.

  Next, as shown in FIG. 10B, a gate electrode 110 having a predetermined shape is formed on the substrate 100.

  Next, as illustrated in FIG. 10C, a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.

  Next, as shown in FIG. 10D, an amorphous silicon layer 330 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do. Note that the amorphous silicon layer 330 is made of the same material as the amorphous silicon layer 130.

  Next, as shown in FIG. 10E, a channel protective layer 140 is formed on the amorphous silicon layer 330.

  Next, as shown in FIG. 10F, the amorphous silicon layer 330 and a part of the channel protective layer 140 are continuously removed by etching. As a result, a convex portion of the amorphous silicon layer 330 is formed by self-alignment, and the side surface of the lower amorphous silicon layer 330 and the side surface of the upper channel protective layer 140 are flush with each other. 330 convex portions are formed.

  Next, as shown in FIG. 10G, the amorphous silicon layer 330 is formed into a first crystalline silicon layer 231 and a second crystalline silicon layer 230 by laser annealing. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 330 is crystallized using the laser beam, so that the first crystalline silicon layer 231 and the second crystalline silicon layer 231 A crystalline silicon layer 230 is generated. More specifically, first, a dehydrogenation process is performed on the formed amorphous silicon layer 330. Thereafter, the first crystalline silicon layer 231 and the second crystalline silicon layer 230 are formed by making the amorphous silicon layer 330 polycrystalline (including microcrystals) by laser annealing.

  At this time, the laser beam scans the amorphous silicon layer 330 in the order of one flat portion, the convex portion, and the other flat portion of the amorphous silicon layer 330, and the film thickness of the flat portion is the film thickness of the convex portion. Since it is thinner, the absorption rate of the laser beam in the flat portion is low. Accordingly, in the amorphous silicon layer 330, the first crystalline silicon layer 231 having a large average grain size of crystals is formed on the convex portion and the portion below the convex portion, but the crystalline portion is formed on the flat portions on both sides of the convex portion. A second crystalline silicon layer 230 having a small average grain size is formed.

  The laser light source of the laser light is a laser having a wavelength in the visible light region. The laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and is preferably a green laser having a wavelength of 473 nm to 561 nm. The laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 330 is irradiated with the laser light discontinuously. This is because the amorphous silicon layer 330 cannot always be kept in a molten state. The reason why the pseudo continuous oscillation mode is also included is that the amorphous silicon layer 330 can be maintained in its molten state by being reheated by applying a pulse before it is cooled to below its melting point. Therefore, a preferred embodiment of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 330 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained. Further, the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element. In any case, it is preferable because laser light can be controlled with high accuracy. Furthermore, the irradiation energy of the laser light on the amorphous silicon layer 330 when the laser light having a wavelength in the visible light region is irradiated on the amorphous silicon layer 330 in order to form a crystalline silicon layer without crystal unevenness. A density variation of less than 5% is preferred. By forming the first crystalline silicon layer 231 and the second crystalline silicon layer 230 having no crystal unevenness, initial design characteristics of the thin film transistor can be achieved, and uniform characteristics can be realized.

  Further, in the process of FIG. 10F, the convex portion of the amorphous silicon layer 330 is formed from the bottom surface of the amorphous silicon layer 330 so that the laser beam does not attenuate until it reaches directly above the gate insulating layer 120. It is preferable that the convex part is formed so that the film thickness up to the upper surface of the film is 100 nm or less.

  Further, in order to prevent the laser light from being transmitted through the amorphous silicon layer 330 and damaging the gate electrode 110, in the step of FIG. 10F, the amorphous silicon layer 330 is formed from the bottom surface of the amorphous silicon layer 330. It is preferable that the convex portion is formed so that the film thickness up to the upper surface of both sides of the convex portion is 10 nm or more.

  In addition, in order to prevent the laser light from being absorbed by the gate insulating layer 120, in the process of FIG. 10C, the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG. A film such as silicon oxide or silicon nitride is preferably formed as the gate insulating layer 120.

  Further, in order to prevent the laser light from being absorbed by the channel protective layer 140, in the process of FIG. 10E, the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG. A film of silicon oxide or silicon nitride is preferably formed as the channel protective layer 140.

  Note that the amorphous silicon layer 330 is irradiated with linearly focused laser light, and there are, for example, two irradiation methods as described above.

  Next, as shown in FIG. 10H, the contact layer 160 that becomes the contact layers 161 and 162 is formed so as to extend from the upper surface of the channel protective layer 140 to the flat portion of the second crystalline silicon layer 230. . Specifically, the contact is made so as to cover the upper surface and the side surface of the channel protective layer 140 and the upper surface of the convex portion of the first crystalline silicon layer 231 and the upper surface of the flat portion of the second crystalline silicon layer 230. Layer 160 is deposited.

  Next, as shown in FIG. 10I, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.

  Next, as shown in FIG. 10J, a source electrode 171 and a drain electrode 172 and contact layers 161 and 162 corresponding to the source electrode 171 and the drain electrode 172 are formed by using a photolithography method and an etching method.

  Here, from FIGS. 4A to 6C, the wavelength of the laser beam is 473 nm in the step of FIG. 10G regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, and FIG. In the step, the film thickness from the bottom surface of the amorphous silicon layer 330 to the top surfaces of the both sides of the convex portion of the amorphous silicon layer 330 is such that the bottom surface of the amorphous silicon layer 330 has a thickness of the amorphous silicon layer 330. By forming the protrusion so as to be 13 nm or more thinner than the film thickness up to the upper surface of the protrusion, the first crystalline silicon layer 231 on the protrusion of the channel layer and the second crystalline silicon layer 230 on both sides of the protrusion Can be formed.

  In other words, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, the wavelength of the laser beam is 532 nm in the step of FIG. 10G, and the non-crystallinity in the step of FIG. The film thickness from the bottom surface of the silicon layer 330 to the upper surface of both sides of the convex portion of the amorphous silicon layer 330 is a film from the bottom surface of the amorphous silicon layer 330 to the upper surface of the convex portion of the amorphous silicon layer 330. By forming the convex portion so as to be thinner than the thickness by 15 nm or more, the first crystalline silicon layer 231 on the convex portion of the channel layer and the second crystalline silicon layer 230 on both sides of the convex portion can be formed.

  In other words, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, the wavelength of the laser light is 561 nm in the step of FIG. 10G, and the non-crystalline state in the step of FIG. The film thickness from the bottom surface of the crystalline silicon layer 330 to the top surface of the both sides of the convex portion of the amorphous silicon layer 330 is from the bottom surface of the amorphous silicon layer 330 to the top surface of the convex portion of the amorphous silicon layer 330. By forming the convex portion so as to be thinner than the film thickness by 16 nm or more, the first crystalline silicon layer 231 on the convex portion of the channel layer and the second crystalline silicon layer 230 on both sides of the convex portion can be formed.

  4A to FIG. 10F, even in the case where the scan speed is constant, the laser light absorptance of the convex portion of the amorphous silicon layer 330 and the portion below the amorphous silicon layer 330, and the amorphous silicon layer By setting the difference between the absorption ratios of the laser light on both sides of the convex portion of the layer 330 to 3% or more, silicon layers having different average grain sizes of crystals can be simultaneously formed by one laser scan. The first crystalline silicon layer 231 in the convex portion and the second crystalline silicon layer 230 on both sides of the convex portion can be formed.

  As described above, according to the thin film transistor of this embodiment, the convex portion of the channel layer is formed of the first crystalline silicon layer 231 having a large average crystal grain size, and both sides of the convex portion are small in the average crystal grain size. A bicrystalline silicon layer 230 is formed. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.

  Even when the source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the underlying channel protective layer 140, the distance from the first crystalline silicon layer 231 to the source electrode 171 in the channel path, and the channel path The distance from the first crystalline silicon layer 231 to the drain electrode 172 in FIG. Therefore, the electrical characteristics can be symmetric with respect to the replacement of the source electrode and the drain electrode.

(Modification)
Next, modifications of the thin film transistor according to the first and second embodiments of the present invention will be described below. In the following, a modification of the thin film transistor according to the first embodiment will be described, but it is needless to say that the modification can be applied to the thin film transistor according to the second embodiment.

  FIG. 11 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this modification.

  In this thin film transistor, the first and second embodiments are that the gate insulating layer 120 has a two-layer structure and includes a silicon nitride layer 121 and a silicon oxide layer 122 formed on the silicon nitride layer 121. Different from form. The following description will focus on differences from the first and second embodiments.

  This thin film transistor includes a substrate 100, a gate electrode 110, a gate insulating layer 120, a crystalline silicon layer 131, an amorphous silicon layer 130, a channel protective layer 140, a source electrode 171 and a drain electrode 172, and contacts. Layers 162 and 161.

  In the gate insulating layer 120, the capacitance of the series capacitor formed by the silicon nitride layer 121 and the silicon oxide layer 122 is equal to the capacitance of the single-layer silicon oxide layer 122 having a thickness of 100 nm to 140 nm. It has such a film thickness.

  The manufacturing method of the thin film transistor of this modification is the same as the manufacturing method shown in FIG. 2, but in the step of FIG. 2C, the silicon nitride layer 121 and the silicon oxide layer formed on the silicon nitride layer 121 are used. 2 is different from the manufacturing method of FIG. 2 in that a gate insulating layer 120 composed of 122 is formed. Since the gate insulating layer 120 has a two-layer structure, the laser light of the laser annealing in FIG. 2G is easily reflected by the gate insulating layer 120, so that the laser light absorption rate of the amorphous silicon layer 130 is increased. be able to.

  Hereinafter, characteristics of the thin film transistor according to the present modification will be described with reference to FIGS.

  FIG. 12 shows the crystal of the crystalline silicon layer 131 when the absorption rate of the laser beam of the amorphous silicon layer 130 and the scan speed of the laser beam are changed in the step of FIG. It is a figure which shows the change of sex.

  Note that changing the absorptance of the amorphous silicon layer 130 is realized by changing the thickness of the amorphous silicon layer 130, that is, the thickness of the channel layer.

In the measurement of FIG. 12, the laser output is 40 kW / cm ² , the gate electrode 110 is 50 nm thick MoW, the gate insulating layer 120 is 65 nm thick silicon nitride layer 121, and the 85 nm thick silicon oxide layer 122 is A sample consisting of

  Further, “a-Si” in FIG. 12 indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon, and “SPC” indicates the average grain size of the crystalline silicon layer 131. “Ex & .SPC” indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm, and “p-Si” indicates the crystalline silicon layer. The average particle size of 131 is about 60 nm or more and 1 μm or less, and “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.

  As shown in FIG. 12, an amorphous silicon layer and a crystalline silicon layer can be formed by changing the scanning speed of laser annealing and the absorption rate of the amorphous silicon layer 130. Even when the scanning speed is fixed, the non-crystalline property of the flat portion of the channel layer is obtained by making a difference of 1% or more between the absorption ratio of the convex portion and the flat portion of the amorphous silicon layer 130. The silicon layer 130 and the convex crystalline silicon layer 131 can be formed. In addition, when this modification is applied to the thin film transistor according to the second embodiment, by making a difference of 3% or more between the absorptance of the convex portion and the absorptance of the flat portion of the amorphous silicon layer 330, The first crystalline silicon layer 231 on the convex portion of the channel layer and the second crystalline silicon layer 230 on both sides of the convex portion can be formed.

  FIG. 13A shows an amorphous silicon layer 130 when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the step of FIG. It is a contour map which shows the calculation result of the absorptivity.

  In FIG. 13A, the lower horizontal axis indicates the optical thickness of the amorphous silicon layer 130, that is, the value obtained by integrating the refractive index of the amorphous silicon layer 130 with the thickness of the amorphous silicon layer 130. The value divided by the wavelength of light is shown. The left vertical axis shows the optical thickness obtained by converting the gate insulating layer 120 composed of the silicon nitride layer 121 and the silicon oxide layer 122 by the refractive index of the silicon oxide layer 122, that is, the silicon nitride layer 121 has a thickness of silicon nitride. The sum of the value obtained by integrating the refractive index of the layer 121 and the value obtained by integrating the refractive index of the silicon oxide layer 122 with the thickness of the silicon oxide layer 122 is integrated with the refractive index of the silicon oxide layer 122 and the wavelength of the laser beam. The value divided by the value is shown. For reference, the film thickness (film thickness) of the gate insulating layer 120 is plotted with the film thickness of the amorphous silicon layer 130 when the laser beam wavelength is set to 532 nm without being normalized by the laser beam wavelength. The thickness of the 120 nm single-layer silicon oxide layer 122 is shown on the right vertical axis. Further, on the right vertical axis, the film thickness ratio of the silicon oxide layer 122 and the silicon nitride layer 121 is also indicated by “film thickness of the silicon oxide layer 122 / film thickness of the silicon nitride layer 121”.

  13A uses a model in which the gate electrode 110 is made of MoW and the channel protective layer 140 is 0 nm.

  By the way, for example, when the wavelength is 532 nm, by using the respective refractive indexes of the silicon oxide layer 122 and the silicon nitride layer 121, the silicon oxide layer 122 and the nitride that constitute the gate insulating layer 120 from the values on the vertical axis in FIG. Each film thickness of the silicon layer 121 can be calculated. 13B to 13D are diagrams illustrating examples of values obtained by converting the values on the vertical axis in FIG. 13A into the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 included in the gate insulating layer 120. FIG. 13B shows values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at a wavelength of 532 nm. Similarly, FIGS. 13C and 13D show values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at wavelengths of 561 nm and 473 nm, respectively. Here, the relative dielectric constants of the silicon oxide layer 122 and the silicon nitride layer 121 are calculated as 4.1 and 7.9, respectively. Note that C in the figure indicates the film thickness of a single silicon oxide layer corresponding to the total capacitance of the laminated film composed of the silicon oxide layer and the silicon nitride layer, and the gate insulating layer 120 is oxidized with the film thickness C. It shows that the total capacitance of the laminated film is fixed to the capacitance value in the case of a single silicon layer. For example, if C = 140 nm, it indicates that the total capacitance value of the gate insulating layer 120 is the capacitance value of a single silicon oxide layer of 140 nm. Similarly, for example, when C = 120 nm or C = 100 nm, the value of the total capacitance of the gate insulating layer 120 is the value of the capacitance of a single silicon oxide layer of 120 nm or 100 nm.

  From FIG. 12 to FIG. 13D, regardless of the material of the gate electrode 110 and the film thickness of the channel protective layer 140, in the process of FIG. The optical film thickness of the amorphous silicon layer 130, which is a value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130, The value obtained by dividing the wavelength by X is X, and the optical thickness obtained by converting the gate insulating layer 120 composed of the silicon nitride layer 121 and the silicon oxide layer 122 by the refractive index of the silicon oxide layer 122, that is, the thickness of the silicon nitride layer 121. The sum of the value obtained by integrating the refractive index of the silicon nitride layer 121 and the value obtained by integrating the refractive index of the silicon oxide layer 122 with the film thickness of the silicon oxide layer 122 is expressed as the refractive index of the silicon oxide layer 122. If the value obtained by dividing the wavelength of the laser light by the integrated value is Y, and X and Y satisfy the following (Equation 4) and (Equation 5), or (Equation 6) and (Equation 7), the maximum absorption In addition, the absorption rate of the laser light at the convex portion of the amorphous silicon layer 130 and the portion below the amorphous silicon layer 130 can be set to, for example, 50% or more. 12A shows a range where X and Y satisfy the following (formula 4) and (formula 5), and B in FIG. 12 shows that X and Y satisfy the following (formula 6) and (formula 7). The range is shown.

(Formula 4) 0.226 ≦ Y ≦ 0.26
(Formula 5) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 6) 0.340 ≦ Y ≦ 0.543
(Expression 7) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28

  As described above, according to the thin film transistor of the present modification, it is possible to achieve both excellent on characteristics and excellent off characteristics for the same reason as in the first embodiment. Further, the electrical characteristics can be made symmetrical with respect to the replacement of the source electrode and the drain electrode.

  Further, according to the thin film transistor of this modification, since the gate insulating layer 120 has a two-layer structure, it is possible to increase the absorptance of laser light at the convex portion of the amorphous silicon layer 130 and the portion below the convex portion. Therefore, for example, the on-current can be increased by increasing the average grain size of the crystal of the convex portion of the channel layer and the portion below the convex portion.

(Comparative example)
Next, comparative examples of the thin film transistors according to the first and second embodiments of the present invention will be described below.

  FIG. 14 is a cross-sectional view schematically showing a configuration of a thin film transistor according to this comparative example.

  This thin film transistor is the same as the first and second embodiments in that the crystalline silicon layer 131 is formed by irradiating the amorphous silicon layer 130 with laser light using the source electrode 171 and the drain electrode 172 as a mask. Different.

  This thin film transistor includes a substrate 100, a gate electrode 110, a gate insulating layer 120, a crystalline silicon layer 131, an amorphous silicon layer 130, a channel protective layer 140, a source electrode 171 and a drain electrode 172, and contacts. Layers 162 and 161.

  The crystalline silicon layer 131 is not formed in the entire region below the channel protective layer 140, but is formed only in a part of the region. Therefore, a part of the channel length defined by the width of the channel protective layer 140 (C and D in FIG. 14) is occupied by the high-resistance amorphous silicon layer 130. Compared to the first and second embodiments, The horizontal resistance component of the channel layer increases.

  The source electrode 171 and the drain electrode 172 are non-uniformly arranged with respect to the underlying channel protective layer 140. Accordingly, the distance from the crystalline silicon layer 131 to the source electrode 171 in the channel path (B in FIG. 14) and the distance from the crystalline silicon layer 131 to the drain electrode 172 in the channel path are unequal. As a result, when the source electrode 171 and the drain electrode 172 are switched to operate, the electrical characteristics are asymmetric with respect to the replacement of the source electrode 171 and the drain electrode 172.

  As described above, the thin film transistor according to the first and second embodiments can realize excellent on characteristics and excellent off characteristics as compared with the thin film transistor according to this comparative example, and the electrical characteristics can be switched between the source electrode and the drain electrode. It can be symmetric.

(Third embodiment)
FIG. 15 is an external view of a display device according to the third embodiment of the present invention. FIG. 16 is a partially cutaway perspective view of the organic EL panel according to the present embodiment.

  The display device 340 is a display device including an organic EL panel, and includes the thin film transistor of the first or second embodiment, and the thin film transistor drives the organic EL panel. The display device 340 includes an organic EL panel 320 using the thin film transistor of the first or second embodiment as a switching transistor or a driving transistor of an active matrix substrate.

  The organic EL panel 320 includes an active matrix substrate 321, a plurality of pixels 322 arranged in a matrix on the active matrix substrate 321, and a pixel circuit connected to the pixels 322 and arranged in an array on the active matrix substrate 321. 323, an anode 324, an organic EL layer 325, and a cathode 326 (transparent electrode) sequentially stacked on the pixel 322 and the pixel circuit 323, and a plurality of pixels that connect each pixel circuit 323 and a control circuit (not shown). A source line 327 and a gate line 328 are provided. The organic EL layer 325 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.

  FIG. 17 is a diagram illustrating a circuit configuration of the pixel 322 of the organic EL panel 320 of FIG.

  As illustrated in FIG. 17, the pixel 322 includes a drive transistor 331, a switching transistor 332, an organic EL element 333, and a capacitor 334. The drive transistor 331 is a transistor that drives the organic EL element 333, and the switching transistor 332 is a transistor for selecting the pixel 322.

  The source electrode 332S of the switching transistor 332 is connected to the source line 327, the gate electrode 332G is connected to the gate line 328, and the drain electrode 332D is connected to the capacitor 334 and the gate electrode 331G of the driving transistor 331.

  Further, the drain electrode 331 </ b> D of the driving transistor 331 is connected to the power supply line 335, and the source electrode 331 </ b> S is connected to the anode of the organic EL element 333.

  In this structure, when a gate signal is input to the gate line 328 and the switching transistor 332 is turned on, the signal voltage supplied through the source line 327 is written to the capacitor 334. Then, the holding voltage written in the capacitor 334 is held throughout one frame period. With this holding voltage, the conductance of the drive transistor 331 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 333. Thereby, the organic EL element 333 emits light and is displayed as an image.

  In this embodiment, the organic EL display device using the organic EL panel has been described. However, the thin film transistor of the first or second embodiment can also be applied to a transistor that drives the liquid crystal panel of the liquid crystal display device. In this case, the display device includes a liquid crystal panel, and includes the thin film transistor according to the first or second embodiment, and the thin film transistor drives the liquid crystal panel.

  As described above, the thin film transistor, the manufacturing method thereof, and the display device of the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

  For example, the display device of the above embodiment can be used as a flat panel display, and can be applied to an electronic device having any display unit such as a television set, a personal computer, and a mobile phone.

  The present invention can be used for a thin film transistor, a manufacturing method thereof, and a display device, and in particular, can be used for a display device such as a television set, a personal computer, and a mobile phone, or various electric devices having a thin film transistor.

100 substrate 110, 331G, 332G gate electrode 120 gate insulating layer 121 silicon nitride layer 122 silicon oxide layer 130, 330 amorphous silicon layer 131 crystalline silicon layer 140 channel protective layer 160, 161, 162 contact layer 170 source drain metal film 171, 331 S, 332 S Source electrode 172, 331 D, 332 D Drain electrode 230 Second crystalline silicon layer 231 First crystalline silicon layer 320 Organic EL panel 321 Active matrix substrate 322 Pixel 323 Pixel circuit 324 Anode 325 Organic EL layer 326 Cathode 327 Source line 328 Gate line 331 Drive transistor 332 Switching transistor 333 Organic EL element 334 Capacitor 335 Power line 340 Display device

Claims (46)

A substrate,
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A crystalline silicon layer formed on the gate insulating layer above the gate electrode;
An amorphous silicon layer formed on both sides of the crystalline silicon layer on the gate insulating layer and having a thickness smaller than that of the crystalline silicon layer;
A channel protective layer formed on the crystalline silicon layer;
The upper surface of the end portion of the channel protective layer, the side surface of the channel protective layer and the crystalline silicon layer, and the upper surface of the amorphous silicon layer are formed above one of the amorphous silicon layers. A source electrode and a drain electrode formed above the other of the amorphous silicon layer,
Thin film transistor. The average particle size of crystals contained in the crystalline silicon layer is 10 nm or more and 1 μm or less.
The thin film transistor according to claim 1. The side surface of the crystalline silicon layer and the side surface of the channel protective layer are flush with each other.
The thin film transistor according to claim 1. A substrate,
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A first crystalline silicon layer formed on the gate insulating layer above the gate electrode;
A second crystalline silicon layer formed on both sides of the first crystalline silicon layer on the gate insulating layer and having a thickness smaller than that of the first crystalline silicon layer;
A channel protective layer formed on the first crystalline silicon layer;
An upper surface of an end portion of the channel protective layer, side surfaces of the channel protective layer and the first crystalline silicon layer, and an upper surface of the second crystalline silicon layer along the upper surface of the second crystalline silicon layer. And a drain electrode formed on the other side of the second crystalline silicon layer,
An average grain size of crystals contained in the first crystalline silicon layer is larger than an average grain size of crystals contained in the second crystalline silicon layer;
Thin film transistor. The average grain size of crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less,
The average grain size of crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm,
The thin film transistor according to claim 4. The side surface of the first crystalline silicon layer and the side surface of the channel protective layer are flush with each other.
The thin film transistor according to claim 4. A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating layer on the gate electrode;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
A fifth step of forming a channel protective layer on the amorphous silicon layer;
A sixth step of processing the amorphous silicon layer and the channel protective layer to form a convex portion in which the upper layer is a channel protective layer and the lower layer is an amorphous silicon layer;
Laser light is applied to the convex portion of the amorphous silicon layer, a portion below the convex portion, and a portion on both sides of the convex portion, and the convex portion of the amorphous silicon layer and the lower portion of the convex portion. A seventh step of leaving the portion of both sides of the convex portion of the amorphous silicon layer as the amorphous silicon layer;
A source electrode is provided above one of the amorphous silicon layers along the upper surface of the end portion of the channel protective layer, the side surfaces of the channel protective layer and the crystalline silicon layer, and the upper surface of the amorphous silicon layer. And an eighth step of forming a drain electrode over the other of the non-crystalline silicon layer,
In the seventh step,
The absorptance of the amorphous silicon layer with respect to the laser light is such that the absorptance of the convex portion of the amorphous silicon layer and the portion under the convex portion corresponding to the lower portion of the channel protective layer Greater than the absorptance of the portions on both sides of the convex portion of the crystalline silicon layer,
A method for manufacturing a thin film transistor. In the seventh step,
The crystalline silicon layer containing crystals having an average particle diameter of 10 nm or more and 1 μm or less is formed by the laser light irradiation.
A method for manufacturing the thin film transistor according to claim 7. In the seventh step,
The wavelength of the laser light is 473 nm or more and 561 nm or less,
The manufacturing method of the thin-film transistor of Claim 7 or 8. A first step of preparing a substrate;
A second step of forming a gate electrode on the substrate;
A third step of forming a gate insulating layer on the gate electrode;
A fourth step of forming an amorphous silicon layer on the gate insulating layer;
A fifth step of forming a channel protective layer on the amorphous silicon layer;
A sixth step of forming a convex portion in which the upper layer is a channel protective layer and the lower layer is an amorphous silicon layer by processing the amorphous silicon layer and the channel protective layer;
Laser light is applied to the convex portion of the amorphous silicon layer, a portion below the convex portion, and a portion on both sides of the convex portion, and the convex portion of the amorphous silicon layer and the lower portion of the convex portion. A seventh crystalline silicon layer as a first crystalline silicon layer, and a portion on both sides of the convex portion of the amorphous silicon layer as a second crystalline silicon layer;
An upper surface of an end portion of the channel protective layer, side surfaces of the channel protective layer and the first crystalline silicon layer, and an upper surface of the second crystalline silicon layer along the upper surface of the second crystalline silicon layer. Forming a source electrode, and forming a drain electrode above the other of the second crystalline silicon layers,
In the seventh step,
The absorptance of the amorphous silicon layer with respect to the laser light is such that the absorptance of the convex portion of the amorphous silicon layer and the portion under the convex portion corresponding to the lower portion of the channel protective layer Greater than the absorptance of both sides of the convex part of the crystalline silicon layer,
Forming the first crystalline silicon layer including crystals having an average grain size larger than an average grain size of crystals contained in the second crystalline silicon layer;
A method for manufacturing a thin film transistor. The average grain size of crystals contained in the first crystalline silicon layer is 40 nm or more and 1 μm or less,
The average grain size of crystals contained in the second crystalline silicon layer is 10 nm or more and less than 40 nm,
The manufacturing method of the thin-film transistor of Claim 10. In the seventh step,
The wavelength of the laser light is 473 nm or more and 561 nm or less,
The method for producing a thin film transistor according to claim 10 or 11. In the seventh step,
The wavelength of the laser beam is 473 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the protrusion so as to be 13 nm or thinner than the film thickness up to the upper surface of
The manufacturing method of the thin-film transistor of Claim 12. In the seventh step,
The wavelength of the laser beam is 532 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the convex portion so as to be thinner than the film thickness up to 15 nm by 15 nm or more.
The manufacturing method of the thin-film transistor of Claim 12. In the seventh step,
The wavelength of the laser beam is 561 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the convex portion so as to be thinner than the film thickness up to 16 nm by 16 nm or more,
The manufacturing method of the thin-film transistor of Claim 12. In the seventh step,
The difference between the absorptance of the laser light at the convex portion of the amorphous silicon layer and the portion below the convex portion and the absorptance of the laser light at the portions on both sides of the convex portion of the amorphous silicon layer is as follows: 3% or more,
The manufacturing method of the thin-film transistor of any one of Claims 10-15. In the seventh step,
The wavelength of the laser beam is 473 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the protrusions so as to be 4 nm or more thinner than the film thickness up to the upper surface of
The method for producing a thin film transistor according to claim 9 or 12. In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of both sides of the convex portion of the non-crystalline silicon layer is 27 nm or less and over 0 nm, and the non-crystalline property from the bottom surface of the non-crystalline silicon layer Forming the protrusion so that the film thickness up to the upper surface of the protrusion of the silicon layer is 35 nm or more;
The manufacturing method of the thin-film transistor of Claim 17. In the seventh step,
The wavelength of the laser beam is 532 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the convex portion so as to be 5 nm or more thinner than the film thickness up to the upper surface of
The method for producing a thin film transistor according to claim 9 or 12. In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of both sides of the convex portion of the non-crystalline silicon layer is 30 nm or less and over 0 nm, and the non-crystalline property from the bottom surface of the non-crystalline silicon layer Forming the protrusion so that the film thickness up to the upper surface of the protrusion of the silicon layer is 40 nm or more;
The manufacturing method of the thin-film transistor of Claim 19. In the seventh step,
The wavelength of the laser beam is 561 nm,
In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the both sides of the convex portion of the non-crystalline silicon layer is such that the convex portion of the non-crystalline silicon layer extends from the bottom surface of the non-crystalline silicon layer. Forming the convex portion so as to be 5 nm or more thinner than the film thickness up to the upper surface of
The method for producing a thin film transistor according to claim 9 or 12. In the sixth step,
The film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of both sides of the convex portion of the non-crystalline silicon layer is 32 nm or less and over 0 nm, and the non-crystalline property from the bottom surface of the non-crystalline silicon layer Forming the protrusion so that the film thickness up to the upper surface of the protrusion of the silicon layer is 42 nm or more;
The method for producing a thin film transistor according to claim 21. In the seventh step,
The absorptivity of the laser light of the convex part and the lower part of the amorphous silicon layer is 30% or more,
The absorptance of the laser light at the portions on both sides of the convex portion of the amorphous silicon layer is 20% or less,
The manufacturing method of the thin-film transistor of any one of Claims 7-22. In the seventh step,
The non-crystalline silicon having a value obtained by integrating the refractive index of the non-crystalline silicon layer to the film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of both sides of the convex portion of the non-crystalline silicon layer The value obtained by dividing the optical film thickness of the layer by the wavelength of the laser beam is 0.286 or less,
The optical film of the non-crystalline silicon layer having a value obtained by integrating the refractive index of the non-crystalline silicon layer to the film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the convex portion of the non-crystalline silicon layer A value obtained by dividing the thickness by the wavelength of the laser beam is 0.381 or more.
The manufacturing method of the thin-film transistor of any one of Claims 7-23. In the seventh step,
Let l and m be integers starting from 0,
The optical film of the non-crystalline silicon layer having a value obtained by integrating the refractive index of the non-crystalline silicon layer to the film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the convex portion of the non-crystalline silicon layer A value obtained by dividing the thickness by the wavelength of the laser beam is X,
A value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by integrating the refractive index of the gate insulating layer with the film thickness of the gate insulating layer, is divided by the wavelength of the laser beam, and Y.
X and Y satisfy the following (formula 1) and (formula 2).
The manufacturing method of the thin-film transistor of any one of Claims 7-24.
(Formula 1) 0.50 m ≦ Y ≦ 0.40 + 0.50 m
(Formula 2) -4.00 (X-0.50 l) + 1.92 + 0.50 m≤Y≤-4.00 (X-0.50 l) + 2.68 + 0.50 m In the third step,
Forming the gate insulating layer composed of a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer;
The manufacturing method of the thin-film transistor of any one of Claims 7-24. In the gate insulating layer, the capacitance of the series capacitor formed by the silicon nitride layer and the silicon oxide layer is equal to the capacitance of a single silicon oxide layer having a thickness of 100 nm to 140 nm. Formed with different film thickness,
27. A method of manufacturing a thin film transistor according to claim 26. In the seventh step,
Let n be an integer starting from 0,
The optical film of the non-crystalline silicon layer having a value obtained by integrating the refractive index of the non-crystalline silicon layer to the film thickness from the bottom surface of the non-crystalline silicon layer to the top surface of the convex portion of the non-crystalline silicon layer A value obtained by dividing the thickness by the wavelength of the laser beam is X,
A value obtained by dividing the optical film thickness obtained by converting the gate insulating layer composed of the silicon nitride layer and the silicon oxide layer by the refractive index of the silicon oxide layer by the sum of the refractive index of the silicon oxide layer and the wavelength of the laser beam. Is Y,
X and Y satisfy the following (formula 3) and (formula 4), or (formula 5) and (formula 6).
28. A method of manufacturing a thin film transistor according to claim 26 or 27.
(Formula 3) 0.226 ≦ Y ≦ 0.26
(Formula 4) -2.90 (X-0.5n) + 1.39≤Y≤-2.90 (X-0.5n) +1.97
(Formula 5) 0.340 ≦ Y ≦ 0.543
(Expression 6) -2.90 (X-0.5n) + 1.70 ≦ Y ≦ -2.90 (X-0.5n) +2.28 In the sixth step,
The value obtained by dividing the optical thickness of the channel protective layer by the thickness of the channel protective layer and the thickness of the channel protective layer divided by the wavelength of the laser beam is Z, and k is an integer starting from 0 age,
Said Z satisfies the following (formula 7):
The manufacturing method of the thin-film transistor of any one of Claims 7-28.
(Expression 7) 0.5 × (k + 0.3) ≦ Z ≦ 0.5 × (k + 0.7) In the sixth step,
Forming the convex portion so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the convex portion of the amorphous silicon layer is 100 nm or less;
The manufacturing method of the thin-film transistor of any one of Claims 7-29. In the sixth step,
Forming the protrusions so that the film thickness from the bottom surface of the amorphous silicon layer to the upper surface of the both sides of the protrusions of the amorphous silicon layer is 10 nm or more;
The manufacturing method of the thin-film transistor of any one of Claims 7-30. In the sixth step,
Forming the convex part in which the side surface of the lower amorphous silicon layer and the side surface of the upper channel protective layer are flush with each other;
The manufacturing method of the thin-film transistor of any one of Claims 7-31. In the first step,
Preparing the substrate having an undercoat layer formed on the surface;
In the second step,
Forming the gate electrode on the undercoat layer;
The manufacturing method of the thin-film transistor of any one of Claims 7-32. In the second step,
Forming a metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal as the gate electrode;
The manufacturing method of the thin-film transistor of any one of Claims 7-33. In the third step,
A film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam is formed as the gate insulating layer.
The manufacturing method of the thin-film transistor of any one of Claims 7-34. In the third step,
Forming a silicon oxide layer as the gate insulating layer;
36. A method of manufacturing a thin film transistor according to any one of claims 7 to 35. In the third step,
Forming a silicon nitride layer as the gate insulating layer;
36. A method of manufacturing a thin film transistor according to any one of claims 7 to 35. In the fifth step,
A film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam is formed as the channel protective layer.
The manufacturing method of the thin-film transistor of any one of Claims 7-37. In the fifth step,
Forming a silicon oxide layer as a channel protective layer;
39. A method of manufacturing a thin film transistor according to claim 38. In the fifth step,
Forming a silicon nitride layer as a channel protective layer;
39. A method of manufacturing a thin film transistor according to claim 38. In the seventh step,
The laser light is light in a continuous oscillation mode or a pseudo continuous oscillation mode.
The manufacturing method of the thin-film transistor of any one of Claims 7-40. In the seventh step,
The laser light is light emitted from a solid-state laser device.
The manufacturing method of the thin-film transistor of any one of Claims 7-40. In the seventh step,
The laser light is light emitted from a laser device using a semiconductor laser element.
The manufacturing method of the thin-film transistor of any one of Claims 7-40. In the seventh step,
The variation of the irradiation energy density of the laser beam on the amorphous silicon layer is less than 5%.
The manufacturing method of the thin-film transistor of any one of Claims 7-43. In the seventh step,
Irradiating the convex part of the non-crystalline silicon layer, a part below the convex part, and a part on both sides of the convex part with a constant scanning speed with a laser beam;
The manufacturing method of the thin-film transistor of any one of Claims 7-44. A display device comprising a liquid crystal panel or an organic EL panel,
The thin film transistor according to any one of claims 1 to 6, comprising:
The thin film transistor drives the liquid crystal panel when the display device includes the liquid crystal panel, and drives the organic EL panel when the display device includes the organic EL panel.
Display device.

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