JPH09283761A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using a polycrystal silicon and a manufacture thereof which provide high drain current by improving crystallinity and reducing leakage current. SOLUTION: A polysilicon layer 14 has gate regions G1 and G2 joined to each other via a gate electrode 12 provided on an insulating substrate 11 and a gate insulating portion 13a, a source region S1 joined to a source electrode 15, and a drain region D1 joined to a drain electrode 16. The source region S1 and the drain region D1 are provided in the gate regions G1 and G2. Upon manufacturing the semiconductor device having this structure, an amorphous silicon layer is inserted between the gate insulating portion 13a and a protective insulating film 19, and the amorphous silicon layer is melted and solidified into the polycrystal silicon layer 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) semiconductor device made of polycrystalline silicon, which is used in a liquid crystal display device and the like, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A TFT used in a liquid crystal display or the like has been developed by using an amorphous silicon film so that an image quality equal to or higher than that of a CRT can be realized. Field effect mobility (cm ² / V · s) (hereinafter abbreviated as mobility)
Is small and the operation of the TFT is unstable. Therefore,
In recent years, in place of the amorphous silicon film TFT, a TFT using a polycrystalline silicon film, which has higher mobility and stable operation, is being developed. However, the polycrystalline silicon film has a narrow band gap and
Since many dangling bonds (unbonded bonds) exist at the crystal grain boundaries, and these dangling bonds act as recombination centers of carriers, the electrical characteristics are significantly inferior to those of a single crystal silicon TFT. In particular, when there is a high electric field region near the drain, the breakdown voltage of the source / drain junction is lowered and the leak current is large.

Therefore, in order to improve the electric characteristics without lowering the driving ability of the TFT, a high resistance drain region,
That is, an LDD (Light) in which a region in which impurities of the same kind as the carrier forming the channel are diffused at a low concentration is formed.
A ly doped drain structure (hereinafter, a region in which an impurity of the same kind as a channel forming carrier is diffused at a low concentration is referred to as an LDD region) is adopted, or the crystal grain size of polycrystalline silicon is increased to increase mobility. Has been done. As a method of enlarging the crystal grains, there is a method of forming polycrystalline silicon at a high temperature of about 800 ° C. to 1000 ° C. However, this method requires the use of quartz glass which is expensive and difficult to increase in size. Therefore, in recent years, research and development has been conducted on a method of manufacturing a TFT by using a boric acid glass that is inexpensive and easily upsized and forms a polycrystalline silicon film on the glass, that is, a technology of manufacturing a TFT at a low temperature. As a method of manufacturing a TFT at a low temperature, a wavelength of 308n composed of XeCl is formed on an amorphous silicon film (α-Si: H film) formed on a glass substrate by plasma CVD.
There is a method of irradiating the excimer laser beam of m to melt the amorphous silicon film and solidify it by natural cooling.

[0004]

However, when the amorphous silicon film is melted at a low temperature and is cooled and solidified to form polycrystalline silicon, in the semiconductor device 8 as shown in FIG. In the vicinity of the tapered portion 1a of the gate electrode 1 formed so as to be in contact with the substrate 3, that is, in the LDD region L in the figure, the polycrystalline silicon film 2 is thinned due to gravity and surface tension. . Further, when the taper angle of the tapered portion 1a of the gate electrode 1 is large, step breakage occurs. Therefore, a drain current (driving current) flowing between the source region S joined to the source electrode 4 and the drain region D joined to the drain electrode 5 via the channel 6 shown by the alternate long and short dash line.
Will pass through the thinned and increased resistance portion or stepped portion, resulting in the problem that the drain current becomes small or does not flow.

In general, in the natural solidification method, when the molten silicon begins to solidify, impurities existing in the solidified silicon are not ejected from the crystal and are not solidified until the end. Therefore, the final end of solidification. Impurities segregate in the area. Therefore, in the semiconductor device 8 having the inverted staggered structure in which the gate electrode 1 is in contact with the glass substrate 3 in FIG. 16, the heat transfer coefficient of the gate electrode 1 is much larger than that of the glass substrate 3, and hence the vicinity of the gate region G. The polycrystalline silicon starts to cool and solidify, and gradually cools and solidifies from the gate region G to the outside. Therefore, impurities in the molten silicon, such as heavy metals Fe, Ni, and Cr, are easily deposited on the LDD region L, the source region S, and the drain region D, which are indicated by a mesh outside the gate region 6. (Also, in the gate region G, impurities are deposited on the side opposite to the side where the channel 6 is formed (hereinafter, the side opposite to the side where the channel is formed in the gate region is referred to as the back channel side). Therefore, in the part where this impurity is formed,
Since there is a gate / source junction or a gate / drain junction, that is, a path through which the drain current flows, when a bias is applied in the reverse direction, a breakdown at a low voltage occurs at the deposited portion, Large leak current easily flows. That is, since the breakdown voltage is low, it is difficult to obtain a large drain current.

The present invention has been made in view of the above problems, and by improving the crystallinity of polycrystalline silicon and reducing the leak current, a large drain breakdown voltage and drain current can be obtained using polycrystalline silicon. It is an object of the present invention to provide a semiconductor device having excellent electric characteristics and a manufacturing method thereof.

[0007]

[Means for Solving the Problems]
According to the invention, a semiconductor layer having a gate region joined to a gate electrode through a gate insulating portion, a source region joined to a source electrode, and a drain region joined to a drain electrode is provided on an insulating substrate. In the semiconductor device in which a channel is formed on the gate insulating portion side in the gate region of the semiconductor layer, the source region and the drain region are provided in the gate region of the semiconductor layer. It is solved by a semiconductor device characterized by the above.

That is, since the source region and the drain region are provided in the gate region, the effective channel length is shortened, so that a large drain current can be obtained with a low gate voltage and a low drain voltage, and the switching characteristics are further improved. Be improved. That is, even if a thin portion or a step break occurs due to gravity or surface tension in the step portion of the semiconductor layer formed by the gate electrode portion or the gate insulating film of the semiconductor device, a drain current passage is formed in the thin portion or the step break. Since this is not done, that is, there is no influence on the path of the drain current, a large drain current can be passed. In addition, since the source region and the drain region are provided in the gate region, the drain current does not flow in the portion where the impurities in the molten silicon segregate, and therefore, when the bias is applied in the reverse direction, the drain current is low. The breakdown due to the voltage hardly occurs, and the leak current can be reduced.

Further, according to the invention of claim 8, the above-mentioned problem is that the gate region is joined to the gate electrode through the gate insulating portion, the source region is joined to the source electrode, and the drain region is joined to the drain electrode. In the method for manufacturing a semiconductor device, wherein a semiconductor layer made of polycrystalline silicon having is formed on an insulating substrate, and a channel is formed on the gate insulating portion side in the gate region of the semiconductor layer. Forming the source region and the drain region on the side of the layer opposite to the side where the channel is formed in the gate region, and melting and solidifying the polycrystalline silicon to be the semiconductor layer; And a method for manufacturing a semiconductor device.

Therefore, when the amorphous silicon is melted and solidified to form polycrystalline silicon, or when the polycrystalline silicon is melted and solidified and recrystallized, a step portion or the like of the gate electrode is subjected to surface tension or gravity. Even if breakage or narrowing occurs, the drain current flows without passing through that portion, so that a large drain current can be obtained.

Further, according to the invention of claim 10, the above-mentioned problem is solved by a gate region joined to the gate electrode through the gate insulating portion, a source region joined to the source electrode, and a drain region joined to the drain electrode. In the method for manufacturing a semiconductor device, the method comprises: forming a semiconductor layer made of polycrystalline silicon having an insulating substrate on an insulating substrate, and forming a channel on the gate insulating portion side in the gate region of the semiconductor layer. Amorphous silicon is melted in a state where the semiconductor layer forming a region is sandwiched by the gate insulating portion and a protective insulating film provided on the opposite side of the semiconductor layer from the gate insulating portion. This is solved by a method for manufacturing a semiconductor device, which comprises solidifying to form the polycrystalline silicon.

That is, since amorphous silicon is melted and solidified into polycrystalline silicon in a state of being sandwiched between the gate insulating portion and the protective insulating film, the same phenomenon as when melted and solidified by a capillary occurs. That is, it is possible to obtain a polycrystalline silicon film in which the directions of crystal grains are aligned and which is relatively close to a single crystal. Therefore, since the mobility can be increased and the drain current can be increased, a semiconductor device using polycrystalline silicon and having excellent electric characteristics can be obtained.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, by providing a source region and a drain region in a gate region, even if the semiconductor layer is thinned or stepped due to gravity or surface tension, the gate region is used. The drain current flowing through the source region and the drain region does not pass through the portion where the thinning or step break occurs, so that the drain current does not decrease. Further, since the source region and the drain region are provided on the back channel side in the gate region of the semiconductor layer, the leak current is suppressed, and therefore the drain current can be increased.

Further, a reverse bias is applied to the gate electrode by forming a low-concentration impurity layer different from the carrier forming the channel between the source region and the drain region on the back channel side. A storage layer of a different type from the channel carrier spreads from the gate side of the semiconductor layer, and the storage layer reaches a low concentration impurity layer of a different type from the carrier of the channel with a low gate bias, so that the tunnel leak current is reduced. Further, electrons or holes move from the low-concentration impurity layer different from the carrier of the channel to the semiconductor layer due to the potential difference, and the low-concentration impurity layer is charged with an electric charge opposite to that of the carrier forming the channel.
A leak current generated at the interface between the low concentration impurity layer and the semiconductor layer can be suppressed. When mobile ions existing in the protective insulating film on the back channel side are completely eliminated, a low voltage different from that of carriers forming the channel is provided between the source region and the drain region on the back channel side. Even if the intrinsic semiconductor layer is formed instead of the concentration impurity layer, the same effect can be obtained.

Further, when the source region and the drain region are formed on the back channel side in the gate region and the thickness of the source region and the drain region is a predetermined amount with respect to the thickness of the gate region, By forming the gate region other than the source region and the drain region with an impurity layer different from the carriers forming the channel or with an intrinsic semiconductor layer, the drain current is generated between the end of the source region and the end of the drain region. Flowing through a part of the channel at the shortest distance, the effective gate channel becomes short, and a large drain current can be obtained with a low gate voltage and a low drain voltage. Since mobile ions are usually present in the gate insulating portion, in order to prevent the variation of the threshold voltage V _TH due to the mobile ions, a carrier different from the carriers forming the channel is formed in the intrinsic semiconductor layer. The low-concentration impurity layer is more preferable.

Further, since the source region and the drain region are formed on the back channel side in the gate region, and the LDD region made of the same type of impurity as the channel and having a low concentration is formed in the gate region, the drain region is changed to the gate. It is possible to reduce hot carrier injection into the insulating film or the insulating substrate, and thus to stabilize the threshold voltage V _T and the transconductance G _m even when a large gate voltage is applied to the gate electrode.

Further, the gate insulating portion has a first interlayer stress buffer layer from the semiconductor layer side toward the gate electrode side,
A first metal contamination preventing layer is formed in this order, a protective insulating film is provided on the side opposite to the gate electrode with respect to the semiconductor layer, and the protective insulating film is provided on a side away from the semiconductor layer from the gate electrode. If the second interlayer stress buffer layer and the second metal contamination preventing layer are formed in this order, the first metal contamination preventing layer of the gate insulating portion and the second metal contamination preventing layer of the protective insulating film are manufactured. It is possible to prevent metal contamination of the gate region due to metal impurities during the process or after the manufacturing process. Further, by forming the first interlayer stress buffer layer of the gate insulating portion and the second interlayer stress buffer layer of the protective insulating film, the interlayer stress of the semiconductor device having the multilayer structure is relaxed to prevent the generation of leak current. can do.

Further, in the method for manufacturing a semiconductor device of the present invention, since the source region and the drain region are provided on the back channel side in the gate region to form polycrystalline silicon to be a semiconductor layer, the amorphous silicon is melted. When polycrystalline silicon is solidified to form polycrystalline silicon, or when polycrystalline silicon is melted and solidified and recrystallized, even if a step or a step is generated in the step portion on the semiconductor layer, the drain current flows to that portion. Does not flow, the drain current does not decrease or stop flowing due to an increase in resistance due to thinning or step breakage, and therefore, the drain current can be increased.

When amorphous silicon is melted and solidified to form polycrystalline silicon of a semiconductor layer, if the semiconductor layer is sandwiched between a gate insulating portion and a protective insulating film, a capillary phenomenon occurs. As a result, it is possible to obtain polycrystalline silicon in which crystal grains are oriented in the same direction, that is, polycrystalline silicon having a high mobility, a large drain breakdown voltage, and a large drain current.

Further, in the case of the inverted stagger structure, the first metal contamination preventing layer forming the gate insulating film, the first interlayer stress buffer layer, the amorphous silicon layer forming the polycrystalline silicon layer,
In order of the second interlayer stress buffer layer and the second metal contamination preventing layer forming the protective insulating film, or in the case of a stagger structure, the second metal contamination preventing layer and the second interlayer stress buffer forming the protective insulating film. Layer, an amorphous silicon layer forming a polycrystalline silicon layer,
The first interlayer stress buffer layer and the first metal contamination preventing layer forming the gate insulating film are successively deposited in this order by, for example, plasma CVD, and then the amorphous silicon layer is laser-annealed to form polycrystalline silicon. By doing so, it is possible to reduce the interlayer stress of the semiconductor device having a multi-layer structure by continuous film formation and to reduce the mixing of dust between layers, and at the same time, perform laser annealing by the first metal contamination preventing layer or the second metal contamination preventing layer to the atmosphere. Even if it is carried out in the inside, it becomes possible to prevent the contaminant from entering the polycrystalline silicon layer. Further, it is possible to prevent the problem of characteristic deterioration due to formation of the lower oxide film by laser annealing.

Further, when a structure in which electrodes (source electrode and drain electrode or gate electrode) that come into contact with the insulating substrate are provided below the semiconductor layer, that is, a so-called reverse stagger structure, the insulating substrate is used during laser annealing. Since the electrode has better thermal conductivity than that of the electrode, amorphous silicon in the semiconductor layer melts and solidifies from the side closer to the electrode to form polycrystalline silicon, and the amorphous part is melted to the end. Impurities such as metals that were present in the high quality silicon are segregated (a so-called floating zone purification method is performed). In the present invention, since the source region and the drain region are provided in the gate region, the drain current does not flow in the portion where the impurities are segregated, and the breakdown at the low voltage does not easily occur even when the reverse bias is applied. Can be reduced. Therefore, a large drain current can be obtained with a large drain breakdown voltage. Further, if the electrode in contact with the insulating substrate is provided so as to be continuous with the other electrode in contact with the insulating substrate, the molten silicon is solidified from the side closer to the electrode as described above. Since such impurities are segregated and solidified in areas other than the effective TFT region, it is possible to prevent a decrease in breakdown voltage, an increase in leak current, a decrease in drain current, and the like.

[0022]

Embodiments of the semiconductor device and the manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1A shows a semiconductor device according to a first embodiment of the present invention, which is generally designated by 10, and has a known inverted staggered structure, ie made of metal, for example. A gate electrode 12 made of molybdenum / tantalum (Mo / Ta) is formed on an insulating substrate 11 made of, for example, translucent borate glass. Gate electrode 1
An insulating film 13 is deposited on the upper surface of 2 so as to cover the upper surfaces of the gate electrode 12 and the insulating substrate 11. The insulating film 13 includes a first metal contamination preventing layer 17 made of, for example, a SiN (silicon nitride) film. , A first interlayer stress buffer layer 18 made of, for example, a SiO ₂ (silicon oxide) film. Further, on the insulating film 13, a polycrystalline silicon layer 14 which is a semiconductor layer is formed.
The gate region G1 is formed in the polycrystalline silicon layer 14 and is joined to the polycrystalline silicon layer 14 via the gate insulating portion 13a located on the gate electrode 12 of the insulating film 13.
(Shown as the inside of the broken line) is provided, and further, a source region S1 that is joined to the source electrode 15 and a drain region D1 that is joined to the drain electrode 16 are provided. Further, the protective insulating film 19 is provided on the upper portion of the polycrystalline silicon layer 14 so as to face the gate insulating portion 13a. In the present embodiment, this is provided from the side closer to the polycrystalline silicon layer 14, for example, The second interlayer stress buffer layer 21 made of SiO ₂ and the second metal contamination prevention layer 22 made of SiN.

In this embodiment, the source region S1 and the drain region D1 are formed on the uppermost part of the polycrystalline silicon layer 14, and the right end S1a of the source region S1 and the left end D1a of the drain region D1 are the gate. It is provided in the area G1. That is, it is formed on the side opposite to the side where the channel 20 shown by the alternate long and short dash line is formed (this is formed on the gate insulating portion 13a side as is well known), that is, on the back channel side of the polycrystalline silicon layer 14. There is. The polycrystalline silicon layer 14 below the source region S1 and the drain region D1 has an LDD region L
1 is formed, that is, a part of this LDD region L1 is also formed in the gate region G1. The LDD region L1 is a region of the same kind as the channel and having a low concentration of impurities, and is provided to weaken the maximum electric field in the drain direction of the drain junction, and the LDD region L1 and the gate oxide film 13a from the drain region D1. Hot carrier injection into the insulating substrate 11 is reduced, and the threshold voltage V _T and the transconductance G _m are stabilized.

The semiconductor device 10 of this embodiment has a channel type MOS structure, which is one of the MIS structures, and the carriers of the channel 20 are conduction electrons, so that the source region S1 and the drain region D1 are impurities of conduction electrons. N-type semiconductor layer having a (hereinafter referred to as N ⁺ layer) are made of, LDD region, a low concentration N-type semiconductor layer of the impurities (hereinafter, N ^- referred to as layers) consists, gate Source region S1, drain region D1 and LDD of region G1
The gate region inside G1a other than the region L1 is composed of an intrinsic semiconductor layer (I layer) in this embodiment. It is to be noted that the inside of the gate region G1a is not the I layer but the channel 20.
If it is formed of a low-concentration impurity layer different from the impurities forming the layer, that is, a P-type semiconductor layer (hereinafter referred to as a P ⁻ layer), it is caused by mobile ions of Na ⁺ and K ^{+ in} the gate oxide film 13a. It is possible to more reliably prevent the variation of the threshold value V _TH and reduce the leak current.

Next, the semiconductor device 1 according to the first embodiment of the present invention.
A manufacturing method of 0 will be described with reference to FIGS.

First, on the insulating substrate 11, Mo / Ta
To a thickness of, for example, about 300 nm, a film is formed by sputtering, and a photolithography process is performed on the film, that is, positive resist coating, mask exposure, development,
After post-baking, dry etching is performed with CF ₄ , and resist stripping is performed with an RA stripper (HNO ₃ + NO ₂ cleaning solution). As shown in FIG. The gate electrode 12 is formed.
Here, Mo / Ta is used for lowering resistance and improving heat resistance. In order to relieve the concentration of stress in the thin film and improve the breakdown voltage, the end portion of the gate electrode 12 is preferably tapered as indicated by the alternate long and short dash line in FIG.
-30 ° is suitable.

Next, the insulating substrate 11 having the gate electrode 12 formed thereon is heated to, for example, about 300.degree.
2D, continuous film formation as shown in FIG. 2B is performed on the insulating substrate 11. That is, a SiN film forming the first metal contamination preventing layer 17 is grown so as to cover the insulating substrate 11 and the gate electrode 12 with SiH ₄ , NH ₃ , and N ₂ as reaction gases to a thickness of about 200 nm, Next, by switching the gas, Si that constitutes the first interlayer stress buffer layer 18
The O ₂ film is treated with SiH ₄ and O ₂ as reaction gases, for example, 20
It is grown to a thickness of about 0 nm. Amorphous silicon (α-S, which becomes a semiconductor layer, uses SiH ₄ as a reaction gas.
i: H) layer 14 ′ is formed to a thickness of 50 nm, and an SiO ₂ film forming the second interlayer stress buffer layer 21 is formed on the S:
S that constitutes the second metal contamination preventing layer 22 is grown by using iH ₄ and O ₂ as reaction gases to a thickness of, for example, about 50 nm.
The iN film is grown to a thickness of, for example, about 50 nm using SiH ₄ , NH ₃ , and N ₂ as reaction gases. At this time, the insulating film 13 may be thickened in order to increase the gate withstand voltage, but since the protective insulating film 19 irradiates the laser beam through this as will be described later, from the viewpoint of optical energy loss, The thickness should be thin. Since this continuous film formation is performed without opening the chamber to atmospheric pressure, it is possible to prevent contaminants from being mixed between the films and to reduce the stress between layers during film formation as much as possible. Can be made.

Next, a low concentration region L1 'is formed by using a resist R1 which is considerably narrower than the width of the gate electrode 12 as shown in FIG. 2C. First, photolithography is performed to form a resist R1. That is, a positive resist coat is applied to the upper surface of the second metal contamination preventing layer 22 formed on the uppermost portion by continuous film formation, and overexposure, that is, self-alignment exposure of the gate is performed from the back surface of the insulating substrate 11, and development is performed. Bake the gate electrode 12
Forming a resist R1 having a width considerably narrower than the width. Next, the second metal contamination preventing layer 22 is etched by, for example, dry etching of CF ₄ , and the second interlayer stress buffer layer 21 is etched by, for example, wet etching using a solution of HF: H ₂ O = 1: 5. Then, the second metal contamination preventing layer 22 and the interlayer stress buffer layer 21, which are the protective insulating film 19, are formed to have the same width as the resist R1, that is, a width considerably narrower than the width of the gate electrode 12. In the state shown in FIG. 2C, using the resist R1 and the protective insulating film 19 as a mask, for example, 10 ¹² to 10 ¹³ cm ^{−2 in the} amorphous silicon layer 14 ′.
The degree of low concentration phosphorus (P ^-) ion doping as indicated by the arrow E, then, the resist R which serves as a mask
1 is stripped with a solution of, for example, H ₂ SO ₄ : H ₂ O ₂ = 5: 1. At this time, the portion of the amorphous silicon layer not doped with P ⁻ ions remains as the I layer, and this becomes the gate region inside G1a as shown in FIG. 3B. In order to obtain a large drain current at a low gate voltage, when it is desired to narrow the distance between the source region S1 and the drain region D1, mask exposure is performed instead of self-alignment exposure of the gate electrode, and a resist of, for example, 1 to 2 μm is used. Form.

Next, as shown in FIG. 3A, laser light is drawn from above in the figure in a state where the protective insulating film 19 is provided on a part of the amorphous silicon layer 14 'to be the semiconductor layer. Laser irradiation is performed in the atmosphere by irradiation as indicated by arrow Q in FIG. In this case, as the laser light, for example, an excimer laser light made of XeCl and having a wavelength of 308 nm is used, and crystallization is performed at a dose of about 250 to 300 mJ / cm ₂ , that is, the amorphous silicon layer 14 ′ is melted and solidified to obtain a large amount. The crystalline silicon layer 14 is formed. At the same time, ions doped with C in FIG. 2 are activated in the amorphous silicon layer 14 'to form a low concentration region L1'. A part of the low concentration region L1 'is located in the gate region G1. It is provided. At the beginning of irradiation with laser light, energy lower than the melting energy is applied to expel hydrogen in the amorphous silicon layer 14 'and then melt and solidify.

In the present invention, the insulating film 13 and the protective insulating film 1
9 and the amorphous silicon layer 14 ′ are sandwiched between them and solidified to form the polycrystalline silicon layer 14,
When solidifying, silicon crystals (due to capillarity)
The polycrystalline silicon layer 14 is thinly squeezed and the crystal grains are aligned in a direction close to a single crystal. Therefore, the amount of defects at the crystal interface is reduced, and the polycrystalline silicon having a high mobility, that is, the polycrystalline silicon layer 14 having excellent electric characteristics can be obtained. That is, at this time, the protective insulating film 19 functions as an anti-reflection film for the excimer laser, reduces energy loss during laser annealing, reduces thermal diffusion of the melted silicon, and aligns the crystal grain directions by a capillary phenomenon. A large polycrystalline silicon layer is obtained.

Further, in this embodiment, the gate electrode 12 is provided so as to contact the insulating substrate 11, and the thermal conductivity of the gate electrode 12 is larger than that of the insulating substrate 11,
The gate electrode 12 functions as a forced cooling body, and in this embodiment, the right side of the gate electrode 12 shown in FIG. 5A is another gate electrode 12 not shown (which is also in contact with the insulating substrate 11). ), The solidified portion is solidified from the right side to the left side in FIG. 5A, and the molten portion is driven away as indicated by an arrow H and solidified at the end portion. That is, the melted portion in which impurities such as metal are segregated is solidified in a region other than the effective TFT region.
Further, also in the cross section of B of FIG. 5, since it is solidified from the side close to the gate electrode 12, impurities such as metal are likely to be segregated in the portion of the low concentration region L1 ′ indicated by the mesh J in the figure. In this portion, a gate region G1 / L formed later is formed.
There is no junction between the DD region L1 / source region S1 and the junction between the gate region G1 / LDD region L1 / drain region D1 (in FIG. 5B, these regions have not been formed yet, and therefore are indicated by a chain line). That is, since impurities such as metals do not segregate in the path K through which the drain current flows after manufacturing, breakdown does not easily occur at low voltage even when a reverse bias is applied, and the leak current can be reduced. With a large drain breakdown voltage,
A large current can be obtained. Further, at this time, even if the polycrystalline silicon layer 14 is thinned or stepped as shown in FIG. 5B, the drain current does not flow here, so the drain current does not decrease. .

Furthermore, since laser annealing is used when forming the polycrystalline silicon layer 14, variations in thermal efficiency, temperature distribution, etc. are suppressed, the TFT characteristics become uniform, and further, dehydrogenation of amorphous silicon is performed. Then, crystallization of polycrystalline silicon and activation of phosphorus (P) ions doped in the low concentration region L1 ′ can be performed at the same time, and productivity can be improved.

After forming the polycrystalline silicon layer 14 by this laser annealing, the polycrystalline silicon layer 14 of FIG. 3B is formed.
In the low-concentration region L1 ′ of, for example, 10 ¹⁴ to 10 ¹⁵ cm ⁻²
By doping phosphorus (P ⁺ ) ions as shown by arrow F at a high concentration, the RTA (Rapid Th
emal Annealing), for example, about 1000 ° C
Annealing is performed within 30 seconds before and after. Then, as shown by C in FIG. 3, the LDD is formed below the low concentration region L1 ′.
The region L1 has a source region S1 and a drain region D on top.
1 and 1 are formed. That is, the source region S1 and the drain region D1 are formed above, but the source region S1 and the drain region D1 are formed because part of the low-concentration region L1 ′ is provided and formed in the gate region G1.
, A right end S1a of the source region S1 and a left end D1a of the drain region D1 are provided in the gate region G1. In the present embodiment, RTA was used when forming the source region S1 and the drain region D1.
The ion-doped diffusion layer hardly diffuses during annealing, and the source region S1 and the drain region D1 can be formed as designed. Therefore, it is necessary to prevent the P ⁺ ions ion-doped to form the source region S1 and the drain region D1 from reaching the insulating film 13, that is, when the ion-doped P ⁺ ions reach the insulating film 13, Since it is not formed, it can be surely prevented.

Next, as shown in FIG. 4A, PSG (Phospho-silicate Gl) is formed on the polycrystalline silicon layer 14 so as to cover the protective insulating film 19 as well.
ass; silicon oxide containing phosphorus) 23 and its PS
The SiN layer 24 is formed on the G layer 23 by atmospheric pressure CVD. The PSG layer 23 is made of, for example, SiH ₄ , PH.
It is formed to have a thickness of, for example, about 300 nm so that phosphorus is contained in the PSG layer 23 at a concentration of about several percent using ₃ , O ₂ as a reaction gas. The SiN layer 24 is made of SiH ₄ ,
It is formed with a thickness of, for example, about 200 nm using HN ₃ and N ₂ as reaction gases.

Then, in this state, for example, in a forming gas (a gas obtained by adding a few% of H ₂ to an inert gas such as Ar or N ₂ ) at about 400 ° C. for about 3 to 4 hours for hydrogenation annealing treatment. Do. Thereby, the polycrystalline silicon layer 1
The dangling bond in 4 is cut to improve the mobility, suppress the generation of leak current, and improve the TFT characteristics. At this time, the PSG film 23 works so that hydrogen easily enters the polycrystalline silicon layer 14 due to its hygroscopicity, and the SiN film 24 works so as to contain hydrogen and prevent it from escaping to the outside, that is, PSG. Membrane 23 and S
The iN film 24 is for efficiently performing this hydrogenation annealing treatment.

Next, the source electrode 15 and the drain electrode 1
First, as shown in FIG. 4B, the SiN film 24 is dry-etched using CF ₄ , and the PSG film 23 is HF: HN ₄ F = 12: 10.
Wet etching with a solution of
A window is formed at a predetermined position of the film 24 and the PSG film 23 in alignment with each other by a technique such as photolithography and etching. After that, aluminum containing 1% of silicon (A
l) is formed by sputtering to a thickness of about 1 μm. And, for example, H ₃ PO ₄ : CH ₃ COOH: H
Al is etched by wet etching using a solution of NO ₃ = 70: 10: 3 to form the source electrode 15 and the drain electrode 16 as shown in C of FIG. And
The resist provided for etching Al is changed to R
Clean with A tripper (HNO ₃ + NO ₂ cleaning solution). Finally, in order to improve the contact characteristics between the source electrode 15 and the source region S1 and between the drain electrode 16 and the drain region D1, Al sintering is performed in a forming gas at about 350 ° C. for about 1 hour, for example.

Thus, the semiconductor device 10 shown in FIG. 1A is formed. In this embodiment, the source region S1 and the drain region D1 are formed on the back channel side in the gate region G1. Therefore, when the amorphous silicon layer 14 ′ is melted and solidified to form the polycrystalline silicon layer 14, the polycrystalline silicon layer 14 is thinned or stepped at the end of the gate electrode 12 due to gravity and surface tension. Even so, the drain current does not pass through this narrowing or step,
The drain current does not become small or stop flowing.

Further, in the present embodiment, the polycrystalline silicon layer 1 is formed from the portion contacting the gate electrode which is a large heat dissipation cooling body.
As 4 solidifies, the melted portion of the amorphous silicon layer 14 ′ containing impurities such as metal gathers in areas other than the effective TFT area, and finally the impurities segregated in the melted area in areas other than the effective TFT area. Is solidified, impurities such as metal are not deposited in the path through which the drain current flows, so that the leak current can be reduced and the breakdown voltage can be prevented from lowering.

In the present embodiment, the amorphous silicon layer 14 'is melted and solidified to form the polycrystalline silicon 14 in a state of being sandwiched between the gate insulating portion 13 and the protective insulating film 19, so that the polycrystalline silicon 14 is formed. As the crystalline silicon layer 14, polycrystalline silicon having a large crystal grain in which the crystal grains are aligned in a direction close to a single crystal due to a capillary phenomenon can be obtained. Therefore, it is possible to obtain a polycrystalline silicon TFT having a large mobility and a large drain breakdown voltage / drain current.

Further, in the present embodiment, since the drain current is made to flow through the LDD region L1, the electric field can be relaxed and the hot carrier effect can be reduced, that is, a large drain voltage can be applied.

The inside G of the gate region of the semiconductor device 10
When 1a is formed not by the I layer but by the low-concentration impurity layer (P-type semiconductor layer in this embodiment) opposite to the carrier of the channel as described above, in the continuous film formation using the plasma CVD described above, SiH ₄ and alpha-Si was formed as a reaction gas: in place of the amorphous silicon layer 14 'consisting of H, an SiH ₄ plus several ppm of B ₂ H _6, for example, as reactive gases, boron (B) Amorphous silicon (P ^- α-Si) mixed with a small amount may be formed and the above procedure may be performed. However, when forming the LDD region, the source region, and the drain region, it is necessary to increase the phosphorus concentration by the boron concentration as compared with the case where the inside G1a of the gate region is the I layer.

Next, the second embodiment of the present invention will be described with reference to FIG.
B of FIG. 6 and FIGS. 6 to 10, the same parts as those in the above embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1B, the semiconductor device 30 of this embodiment has an inverted stagger type N, as in the first embodiment.
The source region S1 and the drain region are formed in the gate region G2 on the side opposite to the gate insulating portion 13a side where the channel 20 of the polycrystalline silicon layer 14 serving as the semiconductor layer is formed, that is, on the back channel side, which has the channel MOS structure. D1 is formed, but between the source region S1 and the drain region D1, a diffusion layer 31 containing a low concentration impurity different from that of the channel 20 is formed. The diffusion layer 31 is formed of a P ⁻ layer containing holes as impurities because the semiconductor device 30 of the present embodiment has an N channel MOS structure similar to that of the above embodiment.

[0045] In this embodiment, P to the back channel side ^-
Since the diffusion layer 31 of the type is formed, when a positive bias is applied to the gate electrode 12, as shown in A of FIG. Portion surrounded by the one-dot chain line) is formed, and when a positive bias is further applied,
Electrons move from the diffusion layer 31 into the inside G1a of the gate region due to the potential difference, as indicated by an arrow M, so that a drain current also flows on the back channel side. When a negative bias is applied to the gate electrode 12, holes are accumulated and spread on the side of the gate electrode 12 and reach the diffusion layer 31 with a low gate bias, as shown in B of FIG. Diffusion layer 31 and polycrystalline silicon layer 1 which is a semiconductor layer
The leak current generated at the interface with 4 is cut off. The diffusion layer 31 is provided between the source region S1 and the drain region D1.
Since is provided, here in a row, N ⁺ (source region S1) -P - ^(diffusion layer 31) -N ⁺ (drain region D1) and the joining portion, i.e., the transistor is formed However, since the diffusion layer 31 is floating and is not biased, the drain current does not flow there. Therefore, the leak current can be suppressed low.

Next, the semiconductor device 3 according to the second embodiment of the present invention.
The manufacturing method of 0 will be described with reference to FIGS.

First, in the same manner as in the first embodiment, A in FIG.
, The gate electrode 12 is formed on the insulating substrate 11.
After the formation of the plasma, plasma C is also formed in the same manner as in the first embodiment.
By VD, the first metal contamination preventing layer 17 made of SiN of the insulating film 13 and the first interlayer stress buffer layer 1 made of SiO _{2 are formed.}
8, amorphous silicon layer 14 ′, Si of protective insulating film 19
A second interlayer stress buffer layer 21 made of O ₂ and a second metal contamination prevention layer 22 made of SiN are continuously formed. The reaction gas used for the continuous film formation of this example is the same as that of the first example, and the formed film thickness is also about the same.

Next, by photolithography of backside exposure, that is, after positive resist coating, exposure, development and post-baking to form resist R1, dry etching using CF _{4 is performed} to contaminate the second metal of SiN. Prevention layer 22
And a second interlayer stress buffer layer 21 made of SiO ₂ is etched by wet etching using a solution of HF: H ₂ O = 1: 5. Then, in the state shown in FIG. 7B, that is, using the resist R1 and the protective insulating film 19 having a width considerably smaller than the width of the gate electrode 12 as a mask,
Similar to the first embodiment, the amorphous silicon layer 14 'is doped with a low concentration P ^- ion of about 10 ¹² to 10 ¹³ / cm as shown by an arrow E', and the resist R1 is changed to H, for example. Strip with a solution of ₂ SO ₄ : H ₂ O ₂ = 5: 1. Then, the state becomes as shown by A in FIG.

In the state shown in FIG. 8A, laser annealing (indicated by the dashed line arrow Q ') is applied to perform laser annealing in the atmosphere, as in the first embodiment. In this case, as the laser light, for example, an excimer laser light having a wavelength of 308 nm made of XeCl is used, and about 250
Crystallization, that is, the polycrystalline silicon layer 14 is formed at an irradiation dose of 300 mJ / cm ₂ . At the beginning of irradiating the laser light, energy lower than the melting energy is applied to expel hydrogen in the amorphous silicon layer 14 ′ and then melt and solidify it to form the polycrystalline silicon layer 14. As a result, similar to the first embodiment, the ions doped in B of FIG. 7 are activated to form the low concentration region L1 ′ and a gate region inside G1a which are partially formed in the gate region G1. Then, the protective insulating film 19
The second metal contamination preventing layer 22 made of SiN and the second interlayer stress buffer layer 21 made of SiO ₂ are respectively dry-etched with CF ₄ gas and wet-etched with a solution of HF: H ₂ O = 1: 5. Peel off.

After the protective insulating film 19 is peeled off, plasma CVD is carried out at about 300 ° C., and as shown in FIG. 8B, BSG (Boro-silicate Glass).
s; silicon oxide containing boron) 32 is formed on the polycrystalline silicon layer 14 to a thickness of, for example, about 100 nm. At this time, SiH ₄ and B ₂ H ₆ gases are used as reaction gases.

Next, positive resist coating, mask exposure,
After development and post-baking, a resist R2 is formed with the same width as the gate region inside G2a, and the BSG film 32 is aligned with the resist R2 with this width so that the BSG film 32 is HF: H ₂ O = 1: 5.
Wet etching is performed using the above solution to obtain the state shown in FIG. 8C. In this state, for example, 10 ¹⁴ -1
After doping P ⁺ ions of about 0 ¹⁵ cm ⁻² from above as shown by the arrow F ′ and annealing the resist R2 for a short time at a high temperature, for example, at about 1000 ° C. for 30 seconds or less.
Perform TA annealing. Then, as shown in FIG. 9A, the LDD region L1 is formed below the low-concentration region L1 ′, the source region S1 and the drain region D1 are formed above the LDD region L1, and the boron (B) in the BSG film 32 is further formed. Are diffused and implanted into the central upper surface of the gate region G2, that is, a diffusion layer 31 made of P ⁻ impurity is formed between the source region S1 and the drain region D1. In this example, RTA annealing was used when forming the source region S1 and the drain region D1, so that the ion-doped diffusion layer can form the source region S1 and the drain region D1 as designed, and Not only the source region S1 and the drain region D1 are formed, but also the diffusion layer 31 is formed at the same time, which contributes to improvement in productivity.

After the source region S1, the drain region D1 and the diffusion layer 31 are formed, as shown in FIG. 9B, the effect of hydrogenation annealing is better performed as in the first embodiment. PSG film 23 and SiN film 2 for
4 is formed so as to cover the polycrystalline silicon layer 14 and the BSG film 32. Then, the same hydrogenation anneal as in the first embodiment is performed to cut the dangling bonds in the polycrystalline silicon layer 14, improve the mobility, suppress the generation of leak current, and improve the TFT characteristics. Let

Next, the source electrode 15 and the drain electrode 16
However, since this is formed by the same method as that of the above-mentioned embodiment, the description thereof will be omitted. And the source electrode 1
5, the resist used for forming the drain electrode 16 is stripped by an RA stripper, and finally, the semiconductor device having the shape of C in FIG. 9 is subjected to Al cinder, and B in FIG.
The semiconductor device 30 shown by is completed.

In the above embodiment, the low density region L
After 1'is formed, the LDD region L1 is formed below the LDD region L1 and the source region S1 and the drain region D1 are formed above the LDD region L1, so that the end of the LDD region L1 and the end of the source region S1 and the end of the drain region D1 are formed. It is consistent with the department. However, they may be provided without alignment as shown in FIG. However, aligning the end of the LDD region L1 with the end of the source region S1 and the end of the drain region D1 is more effective in relaxing the electric field, and the drain breakdown voltage can be further improved. In addition, the end of the LDD region, the end of the source region S1, and the drain region D
In the case like A of FIG. 10 where the end of 1 is not aligned,
A resist corresponding to the size of the LDD region must be provided to perform ion doping.
When the edge of the source region S1 and the edge of the drain region D1 are aligned, that is, since the low-concentration region L1 ′ is only divided into the upper and lower regions, the size of the LDD region is smaller than that of the protective insulating film 13. It is determined by the width, that is, since it is sufficient to dope the ions using the protective insulating film 13 as a mask, it is not necessary to separately provide a resist, and the LDD region can be formed without trouble. In the above embodiment, L
Although the DD region L1 is provided, it may not be provided as shown in FIG. 10B. For example, the thickness of the source region S1 ′ and the drain region D1 ′ is smaller than that of the polycrystalline silicon layer 14 ″. If the thickness is a predetermined amount, the gate insulating film 13
The source region S is formed through the electron storage layer formed on the a side.
Since the drain current flows between the right end S1a ′ of 1 ′ and the left end D1a ′ of the drain region D1 ′, a large drain current can be made to flow at a low drain voltage. In this case, if the polycrystalline silicon layer is formed of an impurity different from the carrier forming the channel, that is, a P ⁻ layer, V due to mobile ions existing in the insulating film 13 is used.
It is possible to prevent variations in _TH .

Next, a third embodiment of the present invention will be described with reference to FIG.
Through the description with reference to FIG. 15, the same parts as those in the above-described embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor device of the third embodiment is shown in FIG. 11, which is indicated by 40 as a whole, which is different from the above-mentioned embodiment in that it abuts on the insulating substrate 11 and the gate electrode 12 'is formed. It is a stagger type that is not formed. A layer 22 ′ made of, for example, SiN is formed as a protective insulating film on the insulating substrate 11, and a polycrystalline silicon layer 44 is formed on the layer 22 ′. In the polycrystalline silicon layer 44, a gate region G3 (this is a region shown by the inside of a broken line) that joins via the gate electrode 12 'made of, for example, Al and the gate insulating portion 13a', and a source electrode made of, for example, Al. A source region S3 joined to 15 and a drain region D3 joined to a drain electrode 16 made of, for example, Al are formed. The source region S3 and the drain region D3 have a shape in which two layers having different widths are overlapped with each other, and a first source region S31 and a first drain region D31 having a long width are respectively provided in a direction closer to the insulating substrate 11. A second source region S32 and a second drain region D32 are formed thereon, respectively. Therefore, the first source region S31
The right end S31a and the left end D31a of the first drain region D31 are formed in the gate region G3. LDD regions L3 are formed on the right side of the second source region S32 and the left side of the second drain region D32. The gate insulating portion 13a 'is composed of a first interlayer stress buffer layer 18' made of SiO ₂ and a first metal contamination prevention layer 17 'made of SiN.

Since this embodiment is also the semiconductor device 40 having the N-channel MOS structure as in the above-mentioned embodiment, the carriers of the channel formed on the gate insulating portion 13a 'side are conduction electrons and therefore the source region. S3 and the drain region D3 are formed of N ⁺ , and the LDD region L3 is also N
^- it is formed in. In this embodiment, the source region S
3, the gate region G3a other than the drain region D3 and the LDD region L3 is formed of the I layer.

With such a structure, that is, since the source region S3, the drain region D1 and the LDD region L3 are formed in the gate region G3, the effective channel length becomes short, and the low gate voltage and the low drain voltage are obtained. It is possible to obtain a large drain current and further improve the switching characteristics. In the embodiment, since the end portions of the first source region S31 and the first drain region D31 in the gate region G3 are tapered, it is possible to prevent the polycrystalline silicon layer 44 'from being thinned or broken.

Next, a method of manufacturing the semiconductor device 40 of this embodiment will be described with reference to FIGS.

The insulating substrate 11 is heated to about 600 ° C.,
As shown in FIG. 13A, a layer 22 ′ made of SiN, which is a protective insulating film, and a polycrystalline silicon (N ⁺ polycrystalline silicon) layer 43 containing a small amount of phosphorus are formed on the insulating substrate 11.
And are formed by continuous film formation by low pressure CVD. Layer 2 at this time
2'is formed using SiH ₄ , N ₂ , and H ₂ as a reaction gas to a thickness of, for example, about 300 nm, and the polycrystalline silicon layer 43 uses SiH ₄ and PH ₃ as a reaction gas, for example. It is formed with a thickness of about 20 nm.

Next, as shown in FIG. 13B, the polycrystalline silicon layer 43 is etched by photolithography,
A first source region S31 and a first drain region D31 are formed. That is, after performing positive resist coating, mask exposure, development, and post-baking, dry etching is performed with, for example, CCl ₄ to remove the resist. At this time, the etched portions of the first source region S31 and the first drain region D31 are formed to have a taper of about 10 to 30 ° in order to prevent the polycrystalline silicon layer 44 'from being thinned or broken.

Again, the insulating substrate 11 is heated to about 600 ° C., and as shown in FIG. 13C, the insulating substrate 11 is covered with the layer 22 ′, the first source region S 31 and the first drain region D 31 in a multi-layered manner. The crystalline silicon layer 44 'and the SiO ₂ film 45 are continuously formed by low pressure CVD. This polycrystalline silicon layer 4
4 ′ is, for example, about 30 nm when the reaction gas is SiH _4.
The SiO ₂ film 45 is formed of SiH ₄
It is formed with a thickness of about 100 nm using O ₂ as a reaction gas. The SiO ₂ film 45 is a film for preventing contaminants from being mixed into the polycrystalline silicon layer 44 ′ when forming the inside G3a of the gate region.

Next, positive resist coating, mask exposure,
A photolithography process including development and post-baking is performed to form a resist R5 as shown in A of FIG. The resist R5 is formed on the first source region S.
The right end portion S31a of the first drain region D31 and the left end portion D31a of the first drain region D31 are formed. And H
The SiO ₂ film 45 is wet-etched with an F-based etching solution so as to be aligned with the resist R5. In the state shown in FIG. 14A, the resist R5 and the SiO ₂
Using the film 45 as a mask, P ⁻ ions are added to about 10 ¹² to 10 ¹³
/ Cm ² and doping as indicated by the arrow E ″, that is, G of the polycrystalline silicon layer 44 ′ in the figure.
3a is not doped with ions, which will later become the gate region inside G3a. And further, B of FIG.
As shown in, the LDD region L3 is formed on the outer periphery of the resist R5.
The resist R6 for determining the magnitude is formed by photolithography, a P ⁺ ion, from about 10 ¹⁵ ~10 ¹⁶ / c
Doping as indicated by arrow F ″ at about m ² .
Therefore, in B of FIG. 14, the portion indicated by X is a low concentration of P.
^- ions are doped, the portion indicated by Y high concentration P ⁺ ions are doped. Then, the resists R5 and R6 and the SiO ₂ film 45 are stripped using, for example, an HF-based etching solution and an RA stripper.

After removing the resists R5, R6 and the SiO ₂ 45, as shown in FIG. 14C, RTA at a high temperature for a short time (for example, 1 to 2 minutes at about 1000 ° C.) or 20 at about 600 ° C. Perform low temperature annealing for ~ 25 hours,
The polycrystalline silicon layer 44 having larger crystal grains is recrystallized. At the same time, is performed to activate the doped ions, P ⁺ ions are doped from the portion (which is indicated by Y) second source region S32, the second drain region D32 is, P ^- ions are doped The LDD region L3 is formed from the portion (indicated by X).

Then, the gate insulating portion 13a 'as shown in FIG. 15A is formed. First, an insulating film is formed on the entire surface by low pressure CVD at about 600.degree. This insulating film is
First interlayer stress buffer layer 18 'made of SiO ₂ and SiN
And a first metal pollution prevention layer 17 'composed of, for example, SiH ₄ , O ₂ and Si, respectively.
Approximately 50 n each using H ₄ , N ₂ and H ₂ as reaction gases
The thickness is about 100 nm. Then, the first interlayer stress buffer layers 18 'and S made of SiO ₂ and S
The first metal contamination preventing layer 17 ′ made of iN is set to H
Wet etching using an F-based etching solution and C
Etching is performed by dry etching using Cl ₄ to form a gate insulating portion 13a ′ as shown in A of FIG.

Next, as shown in FIG. 15B, about 6
The PSG film 23 and the SiN film 24 are formed by low pressure CVD at 00 ° C., and hydrogenation annealing is performed as in the above-mentioned embodiment.
Then, the PSG film 23 and the SiN film 24 are etched to form electrodes, but in this embodiment, unlike the above-described embodiment, the gate electrode 12 'is provided above the polycrystalline silicon layer 44 via the gate insulating film 13a'. Since the stagger structure is provided as a window, a window is also formed in a portion where the gate electrode 12 'is formed. Then, similarly to the above-described embodiment, Al containing 1% of silicon is sputtered to form the gate electrode 12 ′, the source electrode 15 and the drain electrode 16, and the shape shown in C of FIG. Similar to the embodiment, Al cinder is performed to complete the semiconductor device 40.

In this embodiment, the protective insulating film 13 'is also used.
Is formed of a SiN film 22 '. It is formed of two layers, that is, a second interlayer stress buffer layer made of, for example, a SiO ₂ film and a second metal contamination layer made of, for example, a SiN film. Good. In this case, not only can metal contamination be prevented during or after the manufacturing process, but also interlayer stress when the multilayer structure is formed can be reduced.

Further, in this embodiment, the gate region inside G3 is
Although a is formed of the I layer, when forming the polycrystalline silicon layer 44 by low pressure CVD, not only SiH ₄ but also SiH ₄
The gate region G3a may be formed of polycrystalline silicon (P ⁻ polycrystalline silicon) containing holes as impurities by adding a few ppm of B ₂ H ₆ as a reaction gas.
However, in this case, the concentration of phosphorus ions doped when forming the LDD region L3, the second source region S32, and the second drain region D32 is slightly increased.

Further, in this embodiment, the diffusion layer is not formed on the back channel side, but as shown in FIG.
Diffusion layers 41 and 41 'may be formed on the back channel side. In this case, the diffusion layer 41 has the effect described in the second embodiment, that is, when a negative bias is applied to the gate electrode 12. , 41 'and the polycrystalline silicon layer 44, which is a semiconductor layer, are blocked from leaking current, and no current flows through the diffusion layers 41 and 41'. It is possible to achieve the effect that it is possible. In addition, in FIG. 12A,
SiH ₄ , B ₂ H ₆ was used as a reaction gas between the layer 22 ′ made of SiN of the third embodiment and the polycrystalline silicon layer 43 to be the first source region S 31 and the first drain region D 31. When the BSG film 42 is formed and the polycrystalline silicon layer 44 ′ is recrystallized, RTA annealing or low temperature annealing is used to diffuse boron from the BSG film 42 to the gate region G3 ′, thereby forming the source region S3 and the drain region D3. And the diffusion layer 41 is formed between them. Further, in FIG. 12B, several ppm of B ₂ H ₆ is provided between the layer 22 ′ made of SiN of the third embodiment and the polycrystalline silicon layer 43 made of the first source region S31 and the first drain region D31. SiH ₄ containing P is used as a reaction gas, and a polycrystalline silicon (P ⁻ polycrystalline silicon) layer 46 containing holes as impurities
On top of it by using SiH ₄ and O ₂ as reaction gases.
An SiO ₂ film 47 is continuously formed by low pressure CVD to form SiO 2.
_{The second} film 47 is etched so that the polycrystalline silicon layer 46 faces the gate region G3, and when this portion is recrystallized to form the polycrystalline silicon layer 44, it is activated by RTA annealing or low temperature annealing. The diffusion layer 41 ′ may be used. Note that, in FIG. 12, the right end S31a of the first source region S31 and the left end D31a of the first drain region D31 are not tapered, but unlike the third embodiment, the polycrystalline silicon layer 44 'is used. It is more preferable to provide a taper in order to prevent thinning and step breakage.

The embodiments of the semiconductor device and the method of manufacturing the same according to the present invention have been described above. However, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention. Is.

For example, in the above-mentioned embodiment, the so-called double LDD structure is provided in which the LDD regions are provided on both sides of the gate electrode, but a so-called single LDD structure in which the LDD regions are provided only between the gate and the drain may be adopted. Further, in the above-mentioned embodiment, the semiconductor device which forms a channel having conduction electrons as carriers, that is, the semiconductor device made of N-channel MOS type polycrystalline silicon has been described. Of course, the P channel which forms a channel having holes as carriers is described. Even in a semiconductor device made of MOS-type polycrystalline silicon, if the conductivity type in ion doping or CVD is changed and applied, the same effect can be obtained, and other MISs can be obtained.
It can be applied to a semiconductor device having a structure.

Further, in the above embodiment, laser annealing by irradiation of excimer laser light was used when melting and solidifying to form a polycrystalline silicon layer having large crystal grains, but the invention is not limited to this. Alternatively, for example, laser annealing may be performed by argon laser light irradiation, low temperature annealing (600 ° C., 20 to 30 hours), RTA 650 ° C. to 700 ° C., 0.5 to
You may use annealing treatment etc. for about 1.0 hour. With this, as described above, polycrystalline silicon having large crystal grains can be obtained without heating at high temperature, that is, it is not necessary to use quartz glass that is expensive and is not suitable for upsizing, so cost can be reduced and upsizing can be achieved. Will be easier.

[0073]

As described above, the semiconductor device and the method of manufacturing the same according to the present invention have the following effects.

Since the source region and the drain region are provided in the gate region, even if the semiconductor layer made of polycrystalline silicon is thinned or stepped, the drain current can pass through the thinned or stepped portion having a large resistance. Since the drain current does not exist, the drain current does not decrease or the current does not stop flowing. And since the effective gate length can be shortened, low gate voltage,
A large drain current can be obtained with a low drain voltage.

When the electrode is provided so as to abut on the insulating substrate, that is, in the case of the inverted stagger structure, the electrode acts as a forced cooling body and silicon is solidified from the vicinity of the electrode, The portion other than the effective TFT region is solidified lastly, and the impurities existing in the silicon are segregated and finally solidified, that is, the effective T
Since the impurities are segregated in a portion other than the FT region, breakdown at a low voltage when reverse biasing is less likely to occur, a leak current can be reduced, and thus a large drain voltage can be applied and a large drain current can be generated. can get.

Further, since amorphous silicon is melted and solidified to form polycrystalline silicon to be a semiconductor layer in a state of being sandwiched between the gate insulating portion and the protective insulating film, a phenomenon as seen in a capillary tube, That is, since the phenomenon that the directions of the crystals are aligned occurs, the mobility, the drain breakdown voltage, and the drain current can be increased.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device having an inverted stagger structure of the present invention, in which A is a semiconductor device according to a first embodiment and B is a semiconductor device.
Shows a semiconductor device according to the second embodiment.

FIG. 2 is a schematic sectional view (No. 1) for explaining the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a schematic sectional view (No. 2) for explaining the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view (3) explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

5A and 5B are schematic diagrams showing in detail the middle of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, in which A is a plan view and B is a [B]-[B] line direction in A of FIG. FIG.

FIG. 6 is a cross-sectional view illustrating the operation of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view (No. 1) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view (No. 2) for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view (3) explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a modified example of the inverted stagger structure of the first and second embodiments of the present invention, in which A indicates that the source and drain regions and the LDD region are provided without alignment. A semiconductor device is shown, and B shows a semiconductor device in which an LDD region is not formed.

FIG. 11 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a modification of the semiconductor device of the third embodiment of the present invention.

FIG. 13 is a schematic sectional view (No. 1) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 14 is a schematic sectional view (No. 2) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view (3) explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

10 ... Semiconductor device, 11 ... Insulating substrate, 12, 1
2 '... gate electrode, 13a ... gate insulating part, 14 ...
... polycrystalline silicon layer, 15 ... source electrode, 16 ... drain electrode, 19 protective insulating film, 20 ... channel,
30 ... Semiconductor device, 31 ... Diffusion layer, 40 ... Semiconductor device, 41, 41 '... Diffusion layer, 44 ... Polycrystalline silicon layer, D1, D3 ... Source region, D1a, D31a ...
... left end, G1, G2, G3 ... gate region, L1,
L3 ... LDD region, S1, S3 ... Source region, S1
a, S31a ... right end.

Claims (15)

[Claims] 1. A semiconductor layer having a gate region joined to a gate electrode via a gate insulating portion, a source region joined to a source electrode, and a drain region joined to a drain electrode is formed on an insulating substrate. In the semiconductor device in which a channel is formed on the gate insulating portion side in the gate region of the semiconductor layer, the source region and the drain region are provided in the gate region of the semiconductor layer. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the source region and the drain region are provided in the gate region on the side opposite to the side where the channel is formed. 3. A low-concentration impurity layer different from the carrier forming the channel or an intrinsic semiconductor layer is formed between the source region and the drain region. The semiconductor device according to. 4. The semiconductor layer in the gate region other than the drain region and the source region is formed of a low concentration impurity layer different from the carrier forming the channel or an intrinsic semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 5. The semiconductor device according to claim 1, wherein an LDD region made of an impurity of the same type as the channel and having a low concentration is formed in the gate region. 6. The semiconductor device according to claim 1, wherein the semiconductor layer is made of polycrystalline silicon. 7. The gate insulating portion includes a first interlayer stress buffer layer and a first interlayer stress buffer layer from the semiconductor layer side toward the gate electrode side.
A metal contamination prevention layer is formed in this order, and a protective insulating film is provided on the side opposite to the gate electrode with respect to the semiconductor layer, and the protective insulating film extends from the semiconductor layer toward the side away from the gate electrode. 7. The semiconductor device according to claim 1, wherein a second interlayer stress buffer layer and a second metal contamination preventing layer are formed in this order. 8. A semiconductor layer made of polycrystalline silicon having a gate region joined to a gate electrode through a gate insulating portion, a source region joined to a source electrode, and a drain region joined to a drain electrode is insulated. In a method of manufacturing a semiconductor device, which is formed on a substrate, wherein a channel is formed on the gate insulating portion side of the semiconductor layer in the gate region, a side of the semiconductor layer on which the channel is formed in the gate region. A method of manufacturing a semiconductor device, characterized in that the source region and the drain region are provided on the opposite side to, and the polycrystalline silicon to be the semiconductor layer is melted and solidified. 9. The semiconductor layer forming the gate region is sandwiched between the gate insulating portion and a protective insulating film provided on the opposite side of the semiconductor layer from the gate insulating portion. 9. The method for manufacturing a device according to claim 8, wherein the polycrystalline silicon is formed by melting and solidifying amorphous silicon. 10. A semiconductor layer made of polycrystalline silicon having a gate region joined to a gate electrode through a gate insulating portion, a source region joined to a source electrode, and a drain region joined to a drain electrode is insulated. In a method of manufacturing a semiconductor device, which is formed on a substrate, wherein a channel is formed on the gate insulating portion side in the gate region of the semiconductor layer, the semiconductor layer forming the gate region is the gate insulating portion. Characterized in that the amorphous silicon is melted and solidified to form the polycrystalline silicon in a state of being sandwiched by a protective insulating film provided on the side opposite to the gate insulating portion with respect to the semiconductor layer. Of manufacturing a semiconductor device. 11. The polycrystalline silicon which becomes the gate region is formed by laser annealing, low temperature annealing or RTA annealing.
0. The method for manufacturing a semiconductor according to 0. 12. A first metal contamination preventing layer forming the gate insulating film, a first interlayer stress buffer layer, an amorphous silicon layer forming the polycrystalline silicon layer, and the protective insulating film. The second interlayer stress buffer layer and the second metal contamination preventing layer in this order, or the second metal contamination preventing layer, the second interlayer stress buffer layer, the amorphous silicon layer for forming the polycrystalline silicon layer, and the first layer. 10. The interlayer stress buffer layer and the first metal contamination preventing layer are successively formed in this order, and then the amorphous silicon layer is laser-annealed to form the polycrystalline silicon layer. Item 12. The semiconductor device according to any one of items 11. 13. The method of manufacturing a semiconductor according to claim 8, wherein the source region and the drain region are ion-doped and then formed by RTA annealing. 14. The source electrode and the drain electrode, which contact the insulating substrate below the semiconductor layer,
Alternatively, the semiconductor device according to claim 8, which has a structure in which the gate electrode is provided. 15. The source electrode and the drain electrode, which are in contact with the insulating substrate, or the gate electrode, and the other source electrode and drain electrode, which are in contact with the insulating substrate, and the gate electrode. 15. The semiconductor device according to claim 14, wherein the semiconductor devices are arranged in series.