JPH06120505A - Thin film transistor - Google Patents

Abstract

PURPOSE:To suppress the back channel leakage current affected by the positive charge in a passivation film in the thin film transistor using an amorphous silicon. CONSTITUTION:The thin film transistor ia an inverse stagger type TFT wherein a P type doped amorphous silicon layer 19 is provided on the interface between a passivation film 18 and an island layer 13. At this time, the carrier electron density is low in the P type amorphous silicon layer 19. Thus, the electron density induced by the positive charge on the interface between the passivation film 18 and the P type amorphous silicon layer 19 is also lowered not to lower the resistance so much in this part. Accordingly, the leakage current flowing in such a part can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor using amorphous silicon, and more particularly to an active matrix driving thin film transistor used in a liquid crystal display or the like.

[0002]

2. Description of the Related Art A conventional thin film transistor of this type is shown in FIG.
As shown in FIG. 3, a metal gate electrode 32 of aluminum, chromium, tantalum, or the like is provided on a glass substrate 31, a gate insulating film 34 of amorphous silicon nitride or the like, and a semiconductor layer obtained by processing amorphous silicon into islands (hereinafter 33), an ohmic contact layer 35 using phosphorus-doped n-type amorphous silicon, a source electrode 36 and a drain electrode 37 using aluminum, chromium, etc., and amorphous silicon nitride, etc. It was composed of the passivation film 38.

The operation of this thin film transistor will be briefly described with reference to the drawings. FIG. 6 shows the state of the energy band near the interface between the semiconductor layer and the gate insulating film that serves as the channel portion of this thin film transistor. FIG. 6A shows an ON operation state. A positive voltage is applied to the gate electrode, negative charges are induced at the interface between the gate insulating film and the amorphous silicon layer (island layer), the band in the channel portion bends downward, and becomes a carrier storage layer. For this reason, the resistance of this portion decreases. FIG. 6B shows an off operation state. A negative voltage is applied to the gate electrode, the band of the channel portion is bent upward, and a depletion layer of carrier electrons is formed. Therefore, the resistance of this portion becomes high.

[0004]

In this conventional thin film transistor, the interface between the island layer and the passivation film (hereinafter referred to as the back channel interface) is similar to the above-described gate insulating film and the island layer interface (hereinafter referred to as the channel interface). Has become. That is, there are insulating layers on both sides of the island layer and they are the same. Therefore, when positive ions or the like are contained in the passivation film or there are positive charge trap levels or the like, the electric field effect generated by these causes the electric field effect shown in FIG.
As shown in, there is a problem that the conduction band at the back channel interface bends toward the Fermi level and the leak current flowing during the off operation increases.

[0005]

The present invention provides a gate electrode, a gate insulating film, an island-shaped semiconductor layer on an insulating substrate,
Ohmic contact layer, source and drain electrodes,
An inverted staggered thin film transistor formed by sequentially laminating a passivation film is characterized by having a P-type doped semiconductor layer in at least a part of an interface between the island-shaped semiconductor layer and the passivation film.

[0006]

When a P-type semiconductor layer is provided at the interface between the semiconductor layer and the passivation film, the carrier electron density in this portion decreases, so that even if positive charges are generated in the passivation film as shown in FIG. 7B. , The conduction band bend becomes far from the Fermi level, and the leak current does not increase.

[0007]

The present invention will be described below with reference to the drawings. 1 is a vertical sectional view of a thin film transistor according to a first embodiment of the present invention. On the glass substrate 11 having a thickness of about 1 mm, metal chrome 1000 angstrom is formed into a film by a sputtering method, and this is patterned by photolithography and wet etching method to form the gate electrode 12. Next, the gate insulating film 14 made of a silicon nitride film is formed by the plasma CVD method. An amorphous silicon film (a-Si film) and a phosphorus-doped amorphous silicon film (n ⁺ -a-Si film) are grown on this to 2000 angstroms and 500 angstroms, respectively.
The film and the n ⁺ -a-Si film are processed into an island shape in a predetermined shape on the gate electrode by photolithography and dry etching to form the island layer 13 and the ohmic contact layer 15.
To form. On top of this, a metal chromium film 150 is used as an electrode
A film of 0 angstrom is formed by a sputtering method, and a source electrode 16 and a drain electrode 17 having a predetermined shape are formed by photolithography and dry etching. Next, the n ⁺ -a-S of the portion not covered by the source and drain electrodes
The i film is removed by dry etching to separate the source and drain electrodes. Then, a P-type amorphous silicon film doped with boron is formed to a thickness of 200 angstroms on this, and is patterned by photolithography and dry etching so as not to contact the source and drain electrodes, and P-type Si is formed at the center of the channel. Form layer 19. Then, a silicon nitride film having a thickness of 4000 Å is formed on the entire surface, and portions such as electrode pads are removed by photolithography and dry etching to form a passivation film 18. Finally, the whole is annealed in an inert gas atmosphere at 250 ° C. for about 2 hours to complete the thin film transistor.

FIG. 2 is a vertical sectional view of the second embodiment of the present invention. In this embodiment, a shallow P-type amorphous silicon region 20 is formed by ion implantation on the surface of the island layer 13 after the source electrode 16 and the drain electrode 17 are formed.
This embodiment has the advantage that the photolithography and etching steps are unnecessary for forming the P-type amorphous silicon region.

FIG. 3 is a sectional view of a TFT which constitutes an active matrix LCD showing a third embodiment of the present invention. 4A and 4B are cross-sectional views of the TFT substrate showing an intermediate step for obtaining the TFT structure shown in FIG. The gate electrode 22 is formed on the glass substrate 21, and the gate insulating film 23 and the a-Si film 24 are provided thereon. This a-Si
The film 24 has a p-type or n-type impurity concentration of 10 ¹⁰ cm ^-2 or less in order to exhibit the characteristics of an intrinsic semiconductor. Next, by plasma CVD, monosilane (SiH ₄ ) and diborane (B ₂ H ₆ ) as an impurity supply source are used to form a P-type S.
The i layer 25 is obtained. Further, a silicon nitride film 26 used as a stopper during etching is deposited (FIG. 4A).

Here, it is desirable that the P-type Si layer 25 be made thin so as not to affect the potential distribution of the channel portion and thus the channel current, and not give an unnecessary P-type impurity concentration. Therefore, the P-type Si layer 25 is at least aS
It is desirable that the thickness is 1/5 or less of that of the i film 24. Further, it is sufficient that the impurity concentration is on the order of 10 ¹¹ cm ^-2 .

Next, the silicon nitride film 26 and the P-type Si layer 25 are patterned by photolithography and etching processes (FIG. 4B). It is desirable that the thickness of the P-type Si layer 25 is thin in order to reduce the pattern conversion due to overetching when the P-type Si layer 25 is etched. The subsequent steps as in the conventional TFT process, n ⁺ -
a-Si film 27, source electrode 28, drain electrode 29,
By repeating the deposition and patterning of the passivation film 30, the TFT structure of this embodiment shown in FIG. 3 is obtained.

In the above embodiment, the plasma CV is applied to the P-type Si layer.
Although formed by the D method, B may be ion-implanted into the a-Si film. This method has the advantage that the P-type impurity ion-implanted layer depth and the P-type impurity concentration can be controlled more reproducibly than the plasma CVD method because of the good controllability of the ion implantation method.

FIG. 8 is a graph showing a comparison of the gate voltage-current characteristics of the thin film transistor according to the present invention and the conventional thin film transistor. As can be seen from this figure, the thin film transistor of the present invention has a low leak current.

[0014]

As described above, according to the present invention, by providing a P-type semiconductor layer at the interface between the semiconductor layer and the passivation film of the inverted stagger type thin film transistor or at the interface between the semiconductor layer and the silicon nitride film, the P-type semiconductor layer enters the passivation film. Further, it has an effect of suppressing the leak current which increases due to the electric field effect due to positive ions, positive charge traps and the like.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a third embodiment of the present invention.

4A and 4B are cross-sectional views showing a manufacturing process in the middle of the third embodiment.

FIG. 5 is a cross-sectional view of a conventional thin film transistor.

6A and 6B are diagrams showing a basic operation principle of a thin film transistor.

7 (a) and 7 (b) are views for explaining the problems of the prior art and the problems of the present invention.

FIG. 8 is a gate voltage-current characteristic curve diagram of a thin film transistor showing the effect of the present invention.

[Explanation of symbols]

11, 21, 31 Glass substrate 12, 22, 32 Gate electrode 13, 33 Island layer 14, 23, 34 Gate insulating film 15, 35 Ohmic contact layer 18, 28, 36 Source electrode 17, 29, 37 Drain electrode 18, 30 , 38 passivation film 19, 25 P-type Si layer 20 P-type Si region 24 a-Si film 26 silicon nitride film 27 n ⁺ -a-Si film

Claims (2)

[Claims] 1. An inverted staggered thin film transistor formed by sequentially stacking a gate electrode, a gate insulating film, an island-shaped semiconductor layer, an ohmic contact layer, source and drain electrodes, and a passivation film on an insulating substrate, A thin film transistor having a P-type doped semiconductor layer on at least a part of an interface between a semiconductor layer processed into an island shape and a passivation film. 2. An inverted staggered thin film transistor formed by sequentially stacking a gate electrode, a gate insulating film, an amorphous Si film, a P-type Si layer, an ohmic contact layer, a source and drain electrode, and a passivation film on an insulating substrate. A thin film transistor, wherein the P-type or N-type impurity concentration of the amorphous Si film is 10 ¹⁰ cm ^-2 or less and the impurity concentration of the P-type Si layer is 10 ¹¹ cm ^-2 or more.